diff options
Diffstat (limited to 'deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h')
| -rw-r--r-- | deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h | 869 |
1 files changed, 629 insertions, 240 deletions
diff --git a/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h b/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h index 8461e0435fd..f24c95008c9 100644 --- a/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h +++ b/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h @@ -25,7 +25,7 @@ namespace liftoff { // 1 | return addr (ra) | // 0 | previous frame (fp)| // -----+--------------------+ <-- frame ptr (fp) -// -1 | 0xa: WASM_COMPILED | +// -1 | 0xa: WASM | // -2 | instance | // -----+--------------------+--------------------------- // -3 | slot 0 (high) | ^ @@ -46,12 +46,14 @@ constexpr int32_t kHighWordOffset = 4; // fp-4 holds the stack marker, fp-8 is the instance parameter. constexpr int kInstanceOffset = 8; -inline MemOperand GetStackSlot(int offset) { return MemOperand(fp, -offset); } +inline MemOperand GetStackSlot(int offset) { + return MemOperand(offset > 0 ? fp : sp, -offset); +} inline MemOperand GetHalfStackSlot(int offset, RegPairHalf half) { int32_t half_offset = half == kLowWord ? 0 : LiftoffAssembler::kStackSlotSize / 2; - return MemOperand(fp, -offset + half_offset); + return MemOperand(offset > 0 ? fp : sp, -offset + half_offset); } inline MemOperand GetInstanceOperand() { return GetStackSlot(kInstanceOffset); } @@ -540,37 +542,38 @@ void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg, void LiftoffAssembler::AtomicAdd(Register dst_addr, Register offset_reg, uint32_t offset_imm, LiftoffRegister value, - StoreType type) { + LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicAdd"); } void LiftoffAssembler::AtomicSub(Register dst_addr, Register offset_reg, uint32_t offset_imm, LiftoffRegister value, - StoreType type) { + LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicSub"); } void LiftoffAssembler::AtomicAnd(Register dst_addr, Register offset_reg, uint32_t offset_imm, LiftoffRegister value, - StoreType type) { + LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicAnd"); } void LiftoffAssembler::AtomicOr(Register dst_addr, Register offset_reg, uint32_t offset_imm, LiftoffRegister value, - StoreType type) { + LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicOr"); } void LiftoffAssembler::AtomicXor(Register dst_addr, Register offset_reg, uint32_t offset_imm, LiftoffRegister value, - StoreType type) { + LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicXor"); } void LiftoffAssembler::AtomicExchange(Register dst_addr, Register offset_reg, uint32_t offset_imm, - LiftoffRegister value, StoreType type) { + LiftoffRegister value, + LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicExchange"); } @@ -590,6 +593,13 @@ void LiftoffAssembler::LoadCallerFrameSlot(LiftoffRegister dst, liftoff::Load(this, dst, fp, offset, type); } +void LiftoffAssembler::StoreCallerFrameSlot(LiftoffRegister src, + uint32_t caller_slot_idx, + ValueType type) { + int32_t offset = kSystemPointerSize * (caller_slot_idx + 1); + liftoff::Store(this, fp, offset, src, type); +} + void LiftoffAssembler::MoveStackValue(uint32_t dst_offset, uint32_t src_offset, ValueType type) { DCHECK_NE(dst_offset, src_offset); @@ -768,10 +778,10 @@ I32_BINOP(xor, xor_) #undef I32_BINOP -#define I32_BINOP_I(name, instruction) \ - void LiftoffAssembler::emit_i32_##name(Register dst, Register lhs, \ - int32_t imm) { \ - instruction(dst, lhs, Operand(imm)); \ +#define I32_BINOP_I(name, instruction) \ + void LiftoffAssembler::emit_i32_##name##i(Register dst, Register lhs, \ + int32_t imm) { \ + instruction(dst, lhs, Operand(imm)); \ } // clang-format off @@ -801,12 +811,12 @@ bool LiftoffAssembler::emit_i32_popcnt(Register dst, Register src) { Register amount) { \ instruction(dst, src, amount); \ } -#define I32_SHIFTOP_I(name, instruction) \ - I32_SHIFTOP(name, instruction##v) \ - void LiftoffAssembler::emit_i32_##name(Register dst, Register src, \ - int amount) { \ - DCHECK(is_uint5(amount)); \ - instruction(dst, src, amount); \ +#define I32_SHIFTOP_I(name, instruction) \ + I32_SHIFTOP(name, instruction##v) \ + void LiftoffAssembler::emit_i32_##name##i(Register dst, Register src, \ + int amount) { \ + DCHECK(is_uint5(amount)); \ + instruction(dst, src, amount); \ } I32_SHIFTOP_I(shl, sll) @@ -816,8 +826,8 @@ I32_SHIFTOP_I(shr, srl) #undef I32_SHIFTOP #undef I32_SHIFTOP_I -void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs, - int32_t imm) { +void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs, + int32_t imm) { TurboAssembler::AddPair(dst.low_gp(), dst.high_gp(), lhs.low_gp(), lhs.high_gp(), imm, kScratchReg, kScratchReg2); @@ -922,8 +932,8 @@ void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src, &TurboAssembler::ShlPair); } -void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src, - int32_t amount) { +void LiftoffAssembler::emit_i64_shli(LiftoffRegister dst, LiftoffRegister src, + int32_t amount) { UseScratchRegisterScope temps(this); // {src.low_gp()} will still be needed after writing {dst.high_gp()} and // {dst.low_gp()}. @@ -946,8 +956,8 @@ void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src, &TurboAssembler::SarPair); } -void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src, - int32_t amount) { +void LiftoffAssembler::emit_i64_sari(LiftoffRegister dst, LiftoffRegister src, + int32_t amount) { UseScratchRegisterScope temps(this); // {src.high_gp()} will still be needed after writing {dst.high_gp()} and // {dst.low_gp()}. @@ -965,8 +975,8 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src, &TurboAssembler::ShrPair); } -void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src, - int32_t amount) { +void LiftoffAssembler::emit_i64_shri(LiftoffRegister dst, LiftoffRegister src, + int32_t amount) { UseScratchRegisterScope temps(this); // {src.high_gp()} will still be needed after writing {dst.high_gp()} and // {dst.low_gp()}. @@ -1532,328 +1542,707 @@ void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst, bind(&cont); } +void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i8x16_splat"); +} + +void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_splat"); +} + +void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_splat"); +} + +void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i64x2_splat"); +} + +void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f32x4_splat"); +} + void LiftoffAssembler::emit_f64x2_splat(LiftoffRegister dst, LiftoffRegister src) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. bailout(kSimd, "emit_f64x2_splat"); } -void LiftoffAssembler::emit_f64x2_extract_lane(LiftoffRegister dst, - LiftoffRegister lhs, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f64x2_extract_lane"); +void LiftoffAssembler::emit_i8x16_eq(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_eq"); } -void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst, - LiftoffRegister src1, - LiftoffRegister src2, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f64x2_replace_lane"); +void LiftoffAssembler::emit_i8x16_ne(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_ne"); } -void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_i8x16_gt_s(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_gt_s"); +} + +void LiftoffAssembler::emit_i8x16_gt_u(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_gt_u"); +} + +void LiftoffAssembler::emit_i8x16_ge_s(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_ge_s"); +} + +void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_ge_u"); +} + +void LiftoffAssembler::emit_i16x8_eq(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_eq"); +} + +void LiftoffAssembler::emit_i16x8_ne(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_ne"); +} + +void LiftoffAssembler::emit_i16x8_gt_s(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_gt_s"); +} + +void LiftoffAssembler::emit_i16x8_gt_u(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_gt_u"); +} + +void LiftoffAssembler::emit_i16x8_ge_s(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_ge_s"); +} + +void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_ge_u"); +} + +void LiftoffAssembler::emit_i32x4_eq(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_eq"); +} + +void LiftoffAssembler::emit_i32x4_ne(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_ne"); +} + +void LiftoffAssembler::emit_i32x4_gt_s(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_gt_s"); +} + +void LiftoffAssembler::emit_i32x4_gt_u(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_gt_u"); +} + +void LiftoffAssembler::emit_i32x4_ge_s(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_ge_s"); +} + +void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_ge_u"); +} + +void LiftoffAssembler::emit_f32x4_eq(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_eq"); +} + +void LiftoffAssembler::emit_f32x4_ne(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_ne"); +} + +void LiftoffAssembler::emit_f32x4_lt(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_lt"); +} + +void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_le"); +} + +void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_eq"); +} + +void LiftoffAssembler::emit_f64x2_ne(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_ne"); +} + +void LiftoffAssembler::emit_f64x2_lt(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_lt"); +} + +void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_le"); +} + +void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) { + bailout(kSimd, "emit_s128_not"); +} + +void LiftoffAssembler::emit_s128_and(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_s128_and"); +} + +void LiftoffAssembler::emit_s128_or(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_s128_or"); +} + +void LiftoffAssembler::emit_s128_xor(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_s128_xor"); +} + +void LiftoffAssembler::emit_s128_and_not(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_s128_and_not"); +} + +void LiftoffAssembler::emit_s128_select(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + LiftoffRegister mask) { + bailout(kSimd, "emit_s128_select"); +} + +void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i8x16_neg"); +} + +void LiftoffAssembler::emit_i8x16_shl(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f64x2_add"); + bailout(kSimd, "emit_i8x16_shl"); } -void LiftoffAssembler::emit_f64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_i8x16_shli(LiftoffRegister dst, LiftoffRegister lhs, + int32_t rhs) { + bailout(kSimd, "emit_i8x16_shli"); +} + +void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f64x2_sub"); + bailout(kSimd, "emit_i8x16_add"); } -void LiftoffAssembler::emit_f64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_i8x16_add_saturate_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_add_saturate_s"); +} + +void LiftoffAssembler::emit_i8x16_add_saturate_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_add_saturate_u"); +} + +void LiftoffAssembler::emit_i8x16_sub(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f64x2_mul"); + bailout(kSimd, "emit_i8x16_sub"); } -void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, - LiftoffRegister src) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f32x4_splat"); +void LiftoffAssembler::emit_i8x16_sub_saturate_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_sub_saturate_s"); } -void LiftoffAssembler::emit_f32x4_extract_lane(LiftoffRegister dst, - LiftoffRegister lhs, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f32x4_extract_lane"); +void LiftoffAssembler::emit_i8x16_sub_saturate_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_sub_saturate_u"); } -void LiftoffAssembler::emit_f32x4_replace_lane(LiftoffRegister dst, - LiftoffRegister src1, - LiftoffRegister src2, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f32x4_replace_lane"); +void LiftoffAssembler::emit_i8x16_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_mul"); } -void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_i8x16_min_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_min_s"); +} + +void LiftoffAssembler::emit_i8x16_min_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_min_u"); +} + +void LiftoffAssembler::emit_i8x16_max_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_max_s"); +} + +void LiftoffAssembler::emit_i8x16_max_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_max_u"); +} + +void LiftoffAssembler::emit_i16x8_neg(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_neg"); +} + +void LiftoffAssembler::emit_i16x8_shl(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f32x4_add"); + bailout(kSimd, "emit_i16x8_shl"); } -void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_i16x8_shli(LiftoffRegister dst, LiftoffRegister lhs, + int32_t rhs) { + bailout(kSimd, "emit_i16x8_shli"); +} + +void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f32x4_sub"); + bailout(kSimd, "emit_i16x8_add"); } -void LiftoffAssembler::emit_f32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_i16x8_add_saturate_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_add_saturate_s"); +} + +void LiftoffAssembler::emit_i16x8_add_saturate_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_add_saturate_u"); +} + +void LiftoffAssembler::emit_i16x8_sub(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_f32x4_mul"); + bailout(kSimd, "emit_i16x8_sub"); } -void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst, - LiftoffRegister src) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i64x2_splat"); +void LiftoffAssembler::emit_i16x8_sub_saturate_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_sub_saturate_s"); } -void LiftoffAssembler::emit_i64x2_extract_lane(LiftoffRegister dst, - LiftoffRegister lhs, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i64x2_extract_lane"); +void LiftoffAssembler::emit_i16x8_sub_saturate_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_sub_saturate_u"); } -void LiftoffAssembler::emit_i64x2_replace_lane(LiftoffRegister dst, - LiftoffRegister src1, - LiftoffRegister src2, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i64x2_replace_lane"); +void LiftoffAssembler::emit_i16x8_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_mul"); +} + +void LiftoffAssembler::emit_i16x8_min_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_min_s"); +} + +void LiftoffAssembler::emit_i16x8_min_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_min_u"); +} + +void LiftoffAssembler::emit_i16x8_max_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_max_s"); +} + +void LiftoffAssembler::emit_i16x8_max_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_max_u"); +} + +void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_neg"); +} + +void LiftoffAssembler::emit_i32x4_shl(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_shl"); +} + +void LiftoffAssembler::emit_i32x4_shli(LiftoffRegister dst, LiftoffRegister lhs, + int32_t rhs) { + bailout(kSimd, "emit_i32x4_shli"); +} + +void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_add"); +} + +void LiftoffAssembler::emit_i32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_sub"); +} + +void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_mul"); +} + +void LiftoffAssembler::emit_i32x4_min_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_min_s"); +} + +void LiftoffAssembler::emit_i32x4_min_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_min_u"); +} + +void LiftoffAssembler::emit_i32x4_max_s(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_max_s"); +} + +void LiftoffAssembler::emit_i32x4_max_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i32x4_max_u"); +} + +void LiftoffAssembler::emit_i64x2_neg(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i64x2_neg"); +} + +void LiftoffAssembler::emit_i64x2_shl(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i64x2_shl"); +} + +void LiftoffAssembler::emit_i64x2_shli(LiftoffRegister dst, LiftoffRegister lhs, + int32_t rhs) { + bailout(kSimd, "emit_i64x2_shli"); } void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. bailout(kSimd, "emit_i64x2_add"); } void LiftoffAssembler::emit_i64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. bailout(kSimd, "emit_i64x2_sub"); } void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. bailout(kSimd, "emit_i64x2_mul"); } -void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, - LiftoffRegister src) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i32x4_splat"); +void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f32x4_abs"); } -void LiftoffAssembler::emit_i32x4_extract_lane(LiftoffRegister dst, - LiftoffRegister lhs, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i32x4_extract_lane"); +void LiftoffAssembler::emit_f32x4_neg(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f32x4_neg"); } -void LiftoffAssembler::emit_i32x4_replace_lane(LiftoffRegister dst, - LiftoffRegister src1, - LiftoffRegister src2, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i32x4_replace_lane"); +void LiftoffAssembler::emit_f32x4_sqrt(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f32x4_sqrt"); } -void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i32x4_add"); + bailout(kSimd, "emit_f32x4_add"); } -void LiftoffAssembler::emit_i32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i32x4_sub"); + bailout(kSimd, "emit_f32x4_sub"); } -void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_f32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i32x4_mul"); + bailout(kSimd, "emit_f32x4_mul"); } -void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst, - LiftoffRegister src) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_splat"); +void LiftoffAssembler::emit_f32x4_div(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_div"); } -void LiftoffAssembler::emit_i16x8_extract_lane_u(LiftoffRegister dst, - LiftoffRegister lhs, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_extract_lane_u"); +void LiftoffAssembler::emit_f32x4_min(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_min"); } -void LiftoffAssembler::emit_i16x8_extract_lane_s(LiftoffRegister dst, - LiftoffRegister lhs, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_extract_lane_s"); +void LiftoffAssembler::emit_f32x4_max(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f32x4_max"); } -void LiftoffAssembler::emit_i16x8_replace_lane(LiftoffRegister dst, - LiftoffRegister src1, - LiftoffRegister src2, - uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_replace_lane"); +void LiftoffAssembler::emit_f64x2_abs(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f64x2_abs"); } -void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_f64x2_neg(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f64x2_neg"); +} + +void LiftoffAssembler::emit_f64x2_sqrt(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_f64x2_sqrt"); +} + +void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_add"); + bailout(kSimd, "emit_f64x2_add"); } -void LiftoffAssembler::emit_i16x8_sub(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_f64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_sub"); + bailout(kSimd, "emit_f64x2_sub"); } -void LiftoffAssembler::emit_i16x8_mul(LiftoffRegister dst, LiftoffRegister lhs, +void LiftoffAssembler::emit_f64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i16x8_mul"); + bailout(kSimd, "emit_f64x2_mul"); } -void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst, - LiftoffRegister src) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i8x16_splat"); +void LiftoffAssembler::emit_f64x2_div(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_div"); +} + +void LiftoffAssembler::emit_f64x2_min(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_min"); +} + +void LiftoffAssembler::emit_f64x2_max(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_f64x2_max"); +} + +void LiftoffAssembler::emit_i8x16_sconvert_i16x8(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_sconvert_i16x8"); +} + +void LiftoffAssembler::emit_i8x16_uconvert_i16x8(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_uconvert_i16x8"); +} + +void LiftoffAssembler::emit_i16x8_sconvert_i32x4(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_sconvert_i32x4"); +} + +void LiftoffAssembler::emit_i16x8_uconvert_i32x4(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_uconvert_i32x4"); +} + +void LiftoffAssembler::emit_i16x8_sconvert_i8x16_low(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_sconvert_i8x16_low"); +} + +void LiftoffAssembler::emit_i16x8_sconvert_i8x16_high(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_sconvert_i8x16_high"); +} + +void LiftoffAssembler::emit_i16x8_uconvert_i8x16_low(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_uconvert_i8x16_low"); +} + +void LiftoffAssembler::emit_i16x8_uconvert_i8x16_high(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_uconvert_i8x16_high"); +} + +void LiftoffAssembler::emit_i32x4_sconvert_i16x8_low(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_sconvert_i16x8_low"); +} + +void LiftoffAssembler::emit_i32x4_sconvert_i16x8_high(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_sconvert_i16x8_high"); +} + +void LiftoffAssembler::emit_i32x4_uconvert_i16x8_low(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_uconvert_i16x8_low"); +} + +void LiftoffAssembler::emit_i32x4_uconvert_i16x8_high(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_uconvert_i16x8_high"); +} + +void LiftoffAssembler::emit_i8x16_rounding_average_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i8x16_rounding_average_u"); +} + +void LiftoffAssembler::emit_i16x8_rounding_average_u(LiftoffRegister dst, + LiftoffRegister lhs, + LiftoffRegister rhs) { + bailout(kSimd, "emit_i16x8_rounding_average_u"); +} + +void LiftoffAssembler::emit_i8x16_abs(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i8x16_abs"); +} + +void LiftoffAssembler::emit_i16x8_abs(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i16x8_abs"); +} + +void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst, + LiftoffRegister src) { + bailout(kSimd, "emit_i32x4_abs"); +} + +void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i8x16_extract_lane_s"); } void LiftoffAssembler::emit_i8x16_extract_lane_u(LiftoffRegister dst, LiftoffRegister lhs, uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. bailout(kSimd, "emit_i8x16_extract_lane_u"); } -void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst, +void LiftoffAssembler::emit_i16x8_extract_lane_s(LiftoffRegister dst, LiftoffRegister lhs, uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i8x16_extract_lane_s"); + bailout(kSimd, "emit_i16x8_extract_lane_s"); +} + +void LiftoffAssembler::emit_i16x8_extract_lane_u(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i16x8_extract_lane_u"); +} + +void LiftoffAssembler::emit_i32x4_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i32x4_extract_lane"); +} + +void LiftoffAssembler::emit_i64x2_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i64x2_extract_lane"); +} + +void LiftoffAssembler::emit_f32x4_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_f32x4_extract_lane"); +} + +void LiftoffAssembler::emit_f64x2_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_f64x2_extract_lane"); } void LiftoffAssembler::emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. bailout(kSimd, "emit_i8x16_replace_lane"); } -void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs, - LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i8x16_add"); +void LiftoffAssembler::emit_i16x8_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i16x8_replace_lane"); } -void LiftoffAssembler::emit_i8x16_sub(LiftoffRegister dst, LiftoffRegister lhs, - LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i8x16_sub"); +void LiftoffAssembler::emit_i32x4_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i32x4_replace_lane"); } -void LiftoffAssembler::emit_i8x16_mul(LiftoffRegister dst, LiftoffRegister lhs, - LiftoffRegister rhs) { - // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS - // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming - // 3a4000 support MSA. - bailout(kSimd, "emit_i8x16_mul"); +void LiftoffAssembler::emit_i64x2_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_i64x2_replace_lane"); +} + +void LiftoffAssembler::emit_f32x4_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_f32x4_replace_lane"); +} + +void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + bailout(kSimd, "emit_f64x2_replace_lane"); } void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { |