1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
|
// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// The original source code covered by the above license above has been
// modified significantly by Google Inc.
// Copyright 2012 the V8 project authors. All rights reserved.
// A lightweight X64 Assembler.
#ifndef V8_CODEGEN_X64_ASSEMBLER_X64_H_
#define V8_CODEGEN_X64_ASSEMBLER_X64_H_
#include <deque>
#include <map>
#include <memory>
#include <vector>
#include "src/codegen/assembler.h"
#include "src/codegen/label.h"
#include "src/codegen/x64/constants-x64.h"
#include "src/codegen/x64/fma-instr.h"
#include "src/codegen/x64/register-x64.h"
#include "src/codegen/x64/sse-instr.h"
#include "src/objects/smi.h"
#if defined(V8_OS_WIN_X64)
#include "src/diagnostics/unwinding-info-win64.h"
#endif
namespace v8 {
namespace internal {
class SafepointTableBuilder;
// Utility functions
enum Condition {
// any value < 0 is considered no_condition
no_condition = -1,
overflow = 0,
no_overflow = 1,
below = 2,
above_equal = 3,
equal = 4,
not_equal = 5,
below_equal = 6,
above = 7,
negative = 8,
positive = 9,
parity_even = 10,
parity_odd = 11,
less = 12,
greater_equal = 13,
less_equal = 14,
greater = 15,
// Fake conditions that are handled by the
// opcodes using them.
always = 16,
never = 17,
// aliases
carry = below,
not_carry = above_equal,
zero = equal,
not_zero = not_equal,
sign = negative,
not_sign = positive,
last_condition = greater
};
// Returns the equivalent of !cc.
// Negation of the default no_condition (-1) results in a non-default
// no_condition value (-2). As long as tests for no_condition check
// for condition < 0, this will work as expected.
inline Condition NegateCondition(Condition cc) {
return static_cast<Condition>(cc ^ 1);
}
enum RoundingMode {
kRoundToNearest = 0x0,
kRoundDown = 0x1,
kRoundUp = 0x2,
kRoundToZero = 0x3
};
// -----------------------------------------------------------------------------
// Machine instruction Immediates
class Immediate {
public:
explicit constexpr Immediate(int32_t value) : value_(value) {}
explicit constexpr Immediate(int32_t value, RelocInfo::Mode rmode)
: value_(value), rmode_(rmode) {}
explicit Immediate(Smi value)
: value_(static_cast<int32_t>(static_cast<intptr_t>(value.ptr()))) {
DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
}
private:
const int32_t value_;
const RelocInfo::Mode rmode_ = RelocInfo::NONE;
friend class Assembler;
};
ASSERT_TRIVIALLY_COPYABLE(Immediate);
static_assert(sizeof(Immediate) <= kSystemPointerSize,
"Immediate must be small enough to pass it by value");
class Immediate64 {
public:
explicit constexpr Immediate64(int64_t value) : value_(value) {}
explicit constexpr Immediate64(int64_t value, RelocInfo::Mode rmode)
: value_(value), rmode_(rmode) {}
explicit constexpr Immediate64(Address value, RelocInfo::Mode rmode)
: value_(static_cast<int64_t>(value)), rmode_(rmode) {}
private:
const int64_t value_;
const RelocInfo::Mode rmode_ = RelocInfo::NONE;
friend class Assembler;
};
// -----------------------------------------------------------------------------
// Machine instruction Operands
enum ScaleFactor : int8_t {
times_1 = 0,
times_2 = 1,
times_4 = 2,
times_8 = 3,
times_int_size = times_4,
times_half_system_pointer_size = times_4,
times_system_pointer_size = times_8,
times_tagged_size = (kTaggedSize == 8) ? times_8 : times_4,
};
class V8_EXPORT_PRIVATE Operand {
public:
struct Data {
byte rex = 0;
byte buf[9];
byte len = 1; // number of bytes of buf_ in use.
int8_t addend; // for rip + offset + addend.
};
// [base + disp/r]
Operand(Register base, int32_t disp);
// [base + index*scale + disp/r]
Operand(Register base, Register index, ScaleFactor scale, int32_t disp);
// [index*scale + disp/r]
Operand(Register index, ScaleFactor scale, int32_t disp);
// Offset from existing memory operand.
// Offset is added to existing displacement as 32-bit signed values and
// this must not overflow.
Operand(Operand base, int32_t offset);
// [rip + disp/r]
explicit Operand(Label* label, int addend = 0);
Operand(const Operand&) V8_NOEXCEPT = default;
// Checks whether either base or index register is the given register.
// Does not check the "reg" part of the Operand.
bool AddressUsesRegister(Register reg) const;
// Queries related to the size of the generated instruction.
// Whether the generated instruction will have a REX prefix.
bool requires_rex() const { return data_.rex != 0; }
// Size of the ModR/M, SIB and displacement parts of the generated
// instruction.
int operand_size() const { return data_.len; }
const Data& data() const { return data_; }
private:
const Data data_;
};
ASSERT_TRIVIALLY_COPYABLE(Operand);
static_assert(sizeof(Operand) <= 2 * kSystemPointerSize,
"Operand must be small enough to pass it by value");
#define ASSEMBLER_INSTRUCTION_LIST(V) \
V(add) \
V(and) \
V(cmp) \
V(cmpxchg) \
V(dec) \
V(idiv) \
V(div) \
V(imul) \
V(inc) \
V(lea) \
V(mov) \
V(movzxb) \
V(movzxw) \
V(not) \
V(or) \
V(repmovs) \
V(sbb) \
V(sub) \
V(test) \
V(xchg) \
V(xor)
// Shift instructions on operands/registers with kInt32Size and kInt64Size.
#define SHIFT_INSTRUCTION_LIST(V) \
V(rol, 0x0) \
V(ror, 0x1) \
V(rcl, 0x2) \
V(rcr, 0x3) \
V(shl, 0x4) \
V(shr, 0x5) \
V(sar, 0x7)
// Partial Constant Pool
// Different from complete constant pool (like arm does), partial constant pool
// only takes effects for shareable constants in order to reduce code size.
// Partial constant pool does not emit constant pool entries at the end of each
// code object. Instead, it keeps the first shareable constant inlined in the
// instructions and uses rip-relative memory loadings for the same constants in
// subsequent instructions. These rip-relative memory loadings will target at
// the position of the first inlined constant. For example:
//
// REX.W movq r10,0x7f9f75a32c20 ; 10 bytes
// …
// REX.W movq r10,0x7f9f75a32c20 ; 10 bytes
// …
//
// turns into
//
// REX.W movq r10,0x7f9f75a32c20 ; 10 bytes
// …
// REX.W movq r10,[rip+0xffffff96] ; 7 bytes
// …
class ConstPool {
public:
explicit ConstPool(Assembler* assm) : assm_(assm) {}
// Returns true when partial constant pool is valid for this entry.
bool TryRecordEntry(intptr_t data, RelocInfo::Mode mode);
bool IsEmpty() const { return entries_.empty(); }
void PatchEntries();
// Discard any pending pool entries.
void Clear();
private:
// Adds a shared entry to entries_. Returns true if this is not the first time
// we add this entry, false otherwise.
bool AddSharedEntry(uint64_t data, int offset);
// Check if the instruction is a rip-relative move.
bool IsMoveRipRelative(Address instr);
Assembler* assm_;
// Values, pc offsets of entries.
using EntryMap = std::multimap<uint64_t, int>;
EntryMap entries_;
// Number of bytes taken up by the displacement of rip-relative addressing.
static constexpr int kRipRelativeDispSize = 4; // 32-bit displacement.
// Distance between the address of the displacement in the rip-relative move
// instruction and the head address of the instruction.
static constexpr int kMoveRipRelativeDispOffset =
3; // REX Opcode ModRM Displacement
// Distance between the address of the imm64 in the 'movq reg, imm64'
// instruction and the head address of the instruction.
static constexpr int kMoveImm64Offset = 2; // REX Opcode imm64
// A mask for rip-relative move instruction.
static constexpr uint32_t kMoveRipRelativeMask = 0x00C7FFFB;
// The bits for a rip-relative move instruction after mask.
static constexpr uint32_t kMoveRipRelativeInstr = 0x00058B48;
};
class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
private:
// We check before assembling an instruction that there is sufficient
// space to write an instruction and its relocation information.
// The relocation writer's position must be kGap bytes above the end of
// the generated instructions. This leaves enough space for the
// longest possible x64 instruction, 15 bytes, and the longest possible
// relocation information encoding, RelocInfoWriter::kMaxLength == 16.
// (There is a 15 byte limit on x64 instruction length that rules out some
// otherwise valid instructions.)
// This allows for a single, fast space check per instruction.
static constexpr int kGap = 32;
STATIC_ASSERT(AssemblerBase::kMinimalBufferSize >= 2 * kGap);
public:
// Create an assembler. Instructions and relocation information are emitted
// into a buffer, with the instructions starting from the beginning and the
// relocation information starting from the end of the buffer. See CodeDesc
// for a detailed comment on the layout (globals.h).
//
// If the provided buffer is nullptr, the assembler allocates and grows its
// own buffer. Otherwise it takes ownership of the provided buffer.
explicit Assembler(const AssemblerOptions&,
std::unique_ptr<AssemblerBuffer> = {});
~Assembler() override = default;
// GetCode emits any pending (non-emitted) code and fills the descriptor desc.
static constexpr int kNoHandlerTable = 0;
static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr;
void GetCode(Isolate* isolate, CodeDesc* desc,
SafepointTableBuilder* safepoint_table_builder,
int handler_table_offset);
// Convenience wrapper for code without safepoint or handler tables.
void GetCode(Isolate* isolate, CodeDesc* desc) {
GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable);
}
void FinalizeJumpOptimizationInfo();
// Unused on this architecture.
void MaybeEmitOutOfLineConstantPool() {}
// Read/Modify the code target in the relative branch/call instruction at pc.
// On the x64 architecture, we use relative jumps with a 32-bit displacement
// to jump to other Code objects in the Code space in the heap.
// Jumps to C functions are done indirectly through a 64-bit register holding
// the absolute address of the target.
// These functions convert between absolute Addresses of Code objects and
// the relative displacements stored in the code.
// The isolate argument is unused (and may be nullptr) when skipping flushing.
static inline Address target_address_at(Address pc, Address constant_pool);
static inline void set_target_address_at(
Address pc, Address constant_pool, Address target,
ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED);
// This sets the branch destination (which is in the instruction on x64).
// This is for calls and branches within generated code.
inline static void deserialization_set_special_target_at(
Address instruction_payload, Code code, Address target);
// Get the size of the special target encoded at 'instruction_payload'.
inline static int deserialization_special_target_size(
Address instruction_payload);
// This sets the internal reference at the pc.
inline static void deserialization_set_target_internal_reference_at(
Address pc, Address target,
RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
inline Handle<Code> code_target_object_handle_at(Address pc);
inline Handle<HeapObject> compressed_embedded_object_handle_at(Address pc);
inline Address runtime_entry_at(Address pc);
// Number of bytes taken up by the branch target in the code.
static constexpr int kSpecialTargetSize = 4; // 32-bit displacement.
// One byte opcode for test eax,0xXXXXXXXX.
static constexpr byte kTestEaxByte = 0xA9;
// One byte opcode for test al, 0xXX.
static constexpr byte kTestAlByte = 0xA8;
// One byte opcode for nop.
static constexpr byte kNopByte = 0x90;
// One byte prefix for a short conditional jump.
static constexpr byte kJccShortPrefix = 0x70;
static constexpr byte kJncShortOpcode = kJccShortPrefix | not_carry;
static constexpr byte kJcShortOpcode = kJccShortPrefix | carry;
static constexpr byte kJnzShortOpcode = kJccShortPrefix | not_zero;
static constexpr byte kJzShortOpcode = kJccShortPrefix | zero;
// VEX prefix encodings.
enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 };
enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128, kLZ = kL128 };
enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 };
enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x3 };
// ---------------------------------------------------------------------------
// Code generation
//
// Function names correspond one-to-one to x64 instruction mnemonics.
// Unless specified otherwise, instructions operate on 64-bit operands.
//
// If we need versions of an assembly instruction that operate on different
// width arguments, we add a single-letter suffix specifying the width.
// This is done for the following instructions: mov, cmp, inc, dec,
// add, sub, and test.
// There are no versions of these instructions without the suffix.
// - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
// - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
// - Instructions on 32-bit (doubleword) operands/registers use 'l'.
// - Instructions on 64-bit (quadword) operands/registers use 'q'.
// - Instructions on operands/registers with pointer size use 'p'.
#define DECLARE_INSTRUCTION(instruction) \
template <class P1> \
void instruction##_tagged(P1 p1) { \
emit_##instruction(p1, kTaggedSize); \
} \
\
template <class P1> \
void instruction##l(P1 p1) { \
emit_##instruction(p1, kInt32Size); \
} \
\
template <class P1> \
void instruction##q(P1 p1) { \
emit_##instruction(p1, kInt64Size); \
} \
\
template <class P1, class P2> \
void instruction##_tagged(P1 p1, P2 p2) { \
emit_##instruction(p1, p2, kTaggedSize); \
} \
\
template <class P1, class P2> \
void instruction##l(P1 p1, P2 p2) { \
emit_##instruction(p1, p2, kInt32Size); \
} \
\
template <class P1, class P2> \
void instruction##q(P1 p1, P2 p2) { \
emit_##instruction(p1, p2, kInt64Size); \
} \
\
template <class P1, class P2, class P3> \
void instruction##l(P1 p1, P2 p2, P3 p3) { \
emit_##instruction(p1, p2, p3, kInt32Size); \
} \
\
template <class P1, class P2, class P3> \
void instruction##q(P1 p1, P2 p2, P3 p3) { \
emit_##instruction(p1, p2, p3, kInt64Size); \
}
ASSEMBLER_INSTRUCTION_LIST(DECLARE_INSTRUCTION)
#undef DECLARE_INSTRUCTION
// Insert the smallest number of nop instructions
// possible to align the pc offset to a multiple
// of m, where m must be a power of 2.
void Align(int m);
// Insert the smallest number of zero bytes possible to align the pc offset
// to a mulitple of m. m must be a power of 2 (>= 2).
void DataAlign(int m);
void Nop(int bytes = 1);
// Aligns code to something that's optimal for a jump target for the platform.
void CodeTargetAlign();
// Stack
void pushfq();
void popfq();
void pushq(Immediate value);
// Push a 32 bit integer, and guarantee that it is actually pushed as a
// 32 bit value, the normal push will optimize the 8 bit case.
void pushq_imm32(int32_t imm32);
void pushq(Register src);
void pushq(Operand src);
void popq(Register dst);
void popq(Operand dst);
void enter(Immediate size);
void leave();
// Moves
void movb(Register dst, Operand src);
void movb(Register dst, Immediate imm);
void movb(Operand dst, Register src);
void movb(Operand dst, Immediate imm);
// Move the low 16 bits of a 64-bit register value to a 16-bit
// memory location.
void movw(Register dst, Operand src);
void movw(Operand dst, Register src);
void movw(Operand dst, Immediate imm);
// Move the offset of the label location relative to the current
// position (after the move) to the destination.
void movl(Operand dst, Label* src);
// Load a heap number into a register.
// The heap number will not be allocated and embedded into the code right
// away. Instead, we emit the load of a dummy object. Later, when calling
// Assembler::GetCode, the heap number will be allocated and the code will be
// patched by replacing the dummy with the actual object. The RelocInfo for
// the embedded object gets already recorded correctly when emitting the dummy
// move.
void movq_heap_number(Register dst, double value);
void movq_string(Register dst, const StringConstantBase* str);
// Loads a 64-bit immediate into a register, potentially using the constant
// pool.
void movq(Register dst, int64_t value) { movq(dst, Immediate64(value)); }
void movq(Register dst, uint64_t value) {
movq(dst, Immediate64(static_cast<int64_t>(value)));
}
// Loads a 64-bit immediate into a register without using the constant pool.
void movq_imm64(Register dst, int64_t value);
void movsxbl(Register dst, Register src);
void movsxbl(Register dst, Operand src);
void movsxbq(Register dst, Register src);
void movsxbq(Register dst, Operand src);
void movsxwl(Register dst, Register src);
void movsxwl(Register dst, Operand src);
void movsxwq(Register dst, Register src);
void movsxwq(Register dst, Operand src);
void movsxlq(Register dst, Register src);
void movsxlq(Register dst, Operand src);
// Repeated moves.
void repmovsb();
void repmovsw();
void repmovsl() { emit_repmovs(kInt32Size); }
void repmovsq() { emit_repmovs(kInt64Size); }
// Repeated store of doublewords (fill (E)CX bytes at ES:[(E)DI] with EAX).
void repstosl();
// Repeated store of quadwords (fill RCX quadwords at [RDI] with RAX).
void repstosq();
// Instruction to load from an immediate 64-bit pointer into RAX.
void load_rax(Address value, RelocInfo::Mode rmode);
void load_rax(ExternalReference ext);
// Conditional moves.
void cmovq(Condition cc, Register dst, Register src);
void cmovq(Condition cc, Register dst, Operand src);
void cmovl(Condition cc, Register dst, Register src);
void cmovl(Condition cc, Register dst, Operand src);
void cmpb(Register dst, Immediate src) {
immediate_arithmetic_op_8(0x7, dst, src);
}
void cmpb_al(Immediate src);
void cmpb(Register dst, Register src) { arithmetic_op_8(0x3A, dst, src); }
void cmpb(Register dst, Operand src) { arithmetic_op_8(0x3A, dst, src); }
void cmpb(Operand dst, Register src) { arithmetic_op_8(0x38, src, dst); }
void cmpb(Operand dst, Immediate src) {
immediate_arithmetic_op_8(0x7, dst, src);
}
void cmpw(Operand dst, Immediate src) {
immediate_arithmetic_op_16(0x7, dst, src);
}
void cmpw(Register dst, Immediate src) {
immediate_arithmetic_op_16(0x7, dst, src);
}
void cmpw(Register dst, Operand src) { arithmetic_op_16(0x3B, dst, src); }
void cmpw(Register dst, Register src) { arithmetic_op_16(0x3B, dst, src); }
void cmpw(Operand dst, Register src) { arithmetic_op_16(0x39, src, dst); }
void testb(Register reg, Operand op) { testb(op, reg); }
void testw(Register reg, Operand op) { testw(op, reg); }
void andb(Register dst, Immediate src) {
immediate_arithmetic_op_8(0x4, dst, src);
}
void decb(Register dst);
void decb(Operand dst);
// Lock prefix.
void lock();
void xchgb(Register reg, Operand op);
void xchgw(Register reg, Operand op);
void xaddb(Operand dst, Register src);
void xaddw(Operand dst, Register src);
void xaddl(Operand dst, Register src);
void xaddq(Operand dst, Register src);
void negb(Register reg);
void negw(Register reg);
void negl(Register reg);
void negq(Register reg);
void negb(Operand op);
void negw(Operand op);
void negl(Operand op);
void negq(Operand op);
void cmpxchgb(Operand dst, Register src);
void cmpxchgw(Operand dst, Register src);
// Sign-extends rax into rdx:rax.
void cqo();
// Sign-extends eax into edx:eax.
void cdq();
// Multiply eax by src, put the result in edx:eax.
void mull(Register src);
void mull(Operand src);
// Multiply rax by src, put the result in rdx:rax.
void mulq(Register src);
#define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
void instruction##l(Register dst, Immediate imm8) { \
shift(dst, imm8, subcode, kInt32Size); \
} \
\
void instruction##q(Register dst, Immediate imm8) { \
shift(dst, imm8, subcode, kInt64Size); \
} \
\
void instruction##l(Operand dst, Immediate imm8) { \
shift(dst, imm8, subcode, kInt32Size); \
} \
\
void instruction##q(Operand dst, Immediate imm8) { \
shift(dst, imm8, subcode, kInt64Size); \
} \
\
void instruction##l_cl(Register dst) { shift(dst, subcode, kInt32Size); } \
\
void instruction##q_cl(Register dst) { shift(dst, subcode, kInt64Size); } \
\
void instruction##l_cl(Operand dst) { shift(dst, subcode, kInt32Size); } \
\
void instruction##q_cl(Operand dst) { shift(dst, subcode, kInt64Size); }
SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
#undef DECLARE_SHIFT_INSTRUCTION
// Shifts dst:src left by cl bits, affecting only dst.
void shld(Register dst, Register src);
// Shifts src:dst right by cl bits, affecting only dst.
void shrd(Register dst, Register src);
void store_rax(Address dst, RelocInfo::Mode mode);
void store_rax(ExternalReference ref);
void subb(Register dst, Immediate src) {
immediate_arithmetic_op_8(0x5, dst, src);
}
void sub_sp_32(uint32_t imm);
void testb(Register dst, Register src);
void testb(Register reg, Immediate mask);
void testb(Operand op, Immediate mask);
void testb(Operand op, Register reg);
void testw(Register dst, Register src);
void testw(Register reg, Immediate mask);
void testw(Operand op, Immediate mask);
void testw(Operand op, Register reg);
// Bit operations.
void bswapl(Register dst);
void bswapq(Register dst);
void btq(Operand dst, Register src);
void btsq(Operand dst, Register src);
void btsq(Register dst, Immediate imm8);
void btrq(Register dst, Immediate imm8);
void bsrq(Register dst, Register src);
void bsrq(Register dst, Operand src);
void bsrl(Register dst, Register src);
void bsrl(Register dst, Operand src);
void bsfq(Register dst, Register src);
void bsfq(Register dst, Operand src);
void bsfl(Register dst, Register src);
void bsfl(Register dst, Operand src);
// Miscellaneous
void clc();
void cld();
void cpuid();
void hlt();
void int3();
void nop();
void ret(int imm16);
void ud2();
void setcc(Condition cc, Register reg);
void pblendw(XMMRegister dst, Operand src, uint8_t mask);
void pblendw(XMMRegister dst, XMMRegister src, uint8_t mask);
void palignr(XMMRegister dst, Operand src, uint8_t mask);
void palignr(XMMRegister dst, XMMRegister src, uint8_t mask);
// Label operations & relative jumps (PPUM Appendix D)
//
// Takes a branch opcode (cc) and a label (L) and generates
// either a backward branch or a forward branch and links it
// to the label fixup chain. Usage:
//
// Label L; // unbound label
// j(cc, &L); // forward branch to unbound label
// bind(&L); // bind label to the current pc
// j(cc, &L); // backward branch to bound label
// bind(&L); // illegal: a label may be bound only once
//
// Note: The same Label can be used for forward and backward branches
// but it may be bound only once.
void bind(Label* L); // binds an unbound label L to the current code position
// Calls
// Call near relative 32-bit displacement, relative to next instruction.
void call(Label* L);
void call(Address entry, RelocInfo::Mode rmode);
// Explicitly emit a near call / near jump. The displacement is relative to
// the next instructions (which starts at {pc_offset() + kNearJmpInstrSize}).
static constexpr int kNearJmpInstrSize = 5;
void near_call(intptr_t disp, RelocInfo::Mode rmode);
void near_jmp(intptr_t disp, RelocInfo::Mode rmode);
void call(Handle<Code> target,
RelocInfo::Mode rmode = RelocInfo::CODE_TARGET);
// Call near absolute indirect, address in register
void call(Register adr);
// Jumps
// Jump short or near relative.
// Use a 32-bit signed displacement.
// Unconditional jump to L
void jmp(Label* L, Label::Distance distance = Label::kFar);
void jmp(Handle<Code> target, RelocInfo::Mode rmode);
// Jump near absolute indirect (r64)
void jmp(Register adr);
void jmp(Operand src);
// Unconditional jump relative to the current address. Low-level routine,
// use with caution!
void jmp_rel(int offset);
// Conditional jumps
void j(Condition cc, Label* L, Label::Distance distance = Label::kFar);
void j(Condition cc, Address entry, RelocInfo::Mode rmode);
void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
// Floating-point operations
void fld(int i);
void fld1();
void fldz();
void fldpi();
void fldln2();
void fld_s(Operand adr);
void fld_d(Operand adr);
void fstp_s(Operand adr);
void fstp_d(Operand adr);
void fstp(int index);
void fild_s(Operand adr);
void fild_d(Operand adr);
void fist_s(Operand adr);
void fistp_s(Operand adr);
void fistp_d(Operand adr);
void fisttp_s(Operand adr);
void fisttp_d(Operand adr);
void fabs();
void fchs();
void fadd(int i);
void fsub(int i);
void fmul(int i);
void fdiv(int i);
void fisub_s(Operand adr);
void faddp(int i = 1);
void fsubp(int i = 1);
void fsubrp(int i = 1);
void fmulp(int i = 1);
void fdivp(int i = 1);
void fprem();
void fprem1();
void fxch(int i = 1);
void fincstp();
void ffree(int i = 0);
void ftst();
void fucomp(int i);
void fucompp();
void fucomi(int i);
void fucomip();
void fcompp();
void fnstsw_ax();
void fwait();
void fnclex();
void fsin();
void fcos();
void fptan();
void fyl2x();
void f2xm1();
void fscale();
void fninit();
void frndint();
void sahf();
void ucomiss(XMMRegister dst, XMMRegister src);
void ucomiss(XMMRegister dst, Operand src);
void movaps(XMMRegister dst, XMMRegister src);
// Don't use this unless it's important to keep the
// top half of the destination register unchanged.
// Use movaps when moving float values and movd for integer
// values in xmm registers.
void movss(XMMRegister dst, XMMRegister src);
void movss(XMMRegister dst, Operand src);
void movss(Operand dst, XMMRegister src);
void shufps(XMMRegister dst, XMMRegister src, byte imm8);
void cvttss2si(Register dst, Operand src);
void cvttss2si(Register dst, XMMRegister src);
void cvtlsi2ss(XMMRegister dst, Operand src);
void cvtlsi2ss(XMMRegister dst, Register src);
void movmskps(Register dst, XMMRegister src);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
SIMDPrefix pp, LeadingOpcode m, VexW w);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
SIMDPrefix pp, LeadingOpcode m, VexW w);
// SSE instructions
void sse_instr(XMMRegister dst, XMMRegister src, byte escape, byte opcode);
void sse_instr(XMMRegister dst, Operand src, byte escape, byte opcode);
#define DECLARE_SSE_INSTRUCTION(instruction, escape, opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse_instr(dst, src, 0x##escape, 0x##opcode); \
} \
void instruction(XMMRegister dst, Operand src) { \
sse_instr(dst, src, 0x##escape, 0x##opcode); \
}
SSE_UNOP_INSTRUCTION_LIST(DECLARE_SSE_INSTRUCTION)
SSE_BINOP_INSTRUCTION_LIST(DECLARE_SSE_INSTRUCTION)
#undef DECLARE_SSE_INSTRUCTION
// SSE instructions with prefix and SSE2 instructions
void sse2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape,
byte opcode);
void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape,
byte opcode);
#define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
} \
void instruction(XMMRegister dst, Operand src) { \
sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
}
// These SSE instructions have the same encoding as the SSE2 instructions.
SSE_INSTRUCTION_LIST_SS(DECLARE_SSE2_INSTRUCTION)
SSE2_INSTRUCTION_LIST(DECLARE_SSE2_INSTRUCTION)
SSE2_INSTRUCTION_LIST_SD(DECLARE_SSE2_INSTRUCTION)
SSE2_UNOP_INSTRUCTION_LIST(DECLARE_SSE2_INSTRUCTION)
#undef DECLARE_SSE2_INSTRUCTION
void sse2_instr(XMMRegister reg, byte imm8, byte prefix, byte escape,
byte opcode, int extension) {
XMMRegister ext_reg = XMMRegister::from_code(extension);
sse2_instr(ext_reg, reg, prefix, escape, opcode);
emit(imm8);
}
#define DECLARE_SSE2_SHIFT_IMM(instruction, prefix, escape, opcode, extension) \
void instruction(XMMRegister reg, byte imm8) { \
sse2_instr(reg, imm8, 0x##prefix, 0x##escape, 0x##opcode, 0x##extension); \
}
SSE2_INSTRUCTION_LIST_SHIFT_IMM(DECLARE_SSE2_SHIFT_IMM)
#undef DECLARE_SSE2_SHIFT_IMM
#define DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
} \
void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
}
SSE2_INSTRUCTION_LIST(DECLARE_SSE2_AVX_INSTRUCTION)
#undef DECLARE_SSE2_AVX_INSTRUCTION
#define DECLARE_SSE2_UNOP_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
void v##instruction(XMMRegister dst, XMMRegister src) { \
vpd(0x##opcode, dst, xmm0, src); \
} \
void v##instruction(XMMRegister dst, Operand src) { \
vpd(0x##opcode, dst, xmm0, src); \
}
SSE2_UNOP_INSTRUCTION_LIST(DECLARE_SSE2_UNOP_AVX_INSTRUCTION)
#undef DECLARE_SSE2_UNOP_AVX_INSTRUCTION
// SSE3
void lddqu(XMMRegister dst, Operand src);
void movddup(XMMRegister dst, Operand src);
void movddup(XMMRegister dst, XMMRegister src);
// SSSE3
void ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode);
void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
#define DECLARE_SSSE3_INSTRUCTION(instruction, prefix, escape1, escape2, \
opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
} \
void instruction(XMMRegister dst, Operand src) { \
ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
SSSE3_INSTRUCTION_LIST(DECLARE_SSSE3_INSTRUCTION)
SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSSE3_INSTRUCTION)
#undef DECLARE_SSSE3_INSTRUCTION
// SSE4
void sse4_instr(Register dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode, int8_t imm8);
void sse4_instr(Operand dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode, int8_t imm8);
void sse4_instr(XMMRegister dst, Register src, byte prefix, byte escape1,
byte escape2, byte opcode, int8_t imm8);
void sse4_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode);
void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
#define DECLARE_SSE4_INSTRUCTION(instruction, prefix, escape1, escape2, \
opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
} \
void instruction(XMMRegister dst, Operand src) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
DECLARE_SSE4_INSTRUCTION(blendvpd, 66, 0F, 38, 15)
#undef DECLARE_SSE4_INSTRUCTION
#define DECLARE_SSE4_EXTRACT_INSTRUCTION(instruction, prefix, escape1, \
escape2, opcode) \
void instruction(Register dst, XMMRegister src, int8_t imm8) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
imm8); \
} \
void instruction(Operand dst, XMMRegister src, int8_t imm8) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
imm8); \
}
SSE4_EXTRACT_INSTRUCTION_LIST(DECLARE_SSE4_EXTRACT_INSTRUCTION)
#undef DECLARE_SSE4_EXTRACT_INSTRUCTION
// SSE4.2
void sse4_2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
byte escape2, byte opcode);
void sse4_2_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
#define DECLARE_SSE4_2_INSTRUCTION(instruction, prefix, escape1, escape2, \
opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse4_2_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
} \
void instruction(XMMRegister dst, Operand src) { \
sse4_2_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
SSE4_2_INSTRUCTION_LIST(DECLARE_SSE4_2_INSTRUCTION)
#undef DECLARE_SSE4_2_INSTRUCTION
#define DECLARE_SSE34_AVX_INSTRUCTION(instruction, prefix, escape1, escape2, \
opcode) \
void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
} \
void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
}
SSSE3_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
SSE4_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
SSE4_2_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
#undef DECLARE_SSE34_AVX_INSTRUCTION
#define DECLARE_SSSE3_UNOP_AVX_INSTRUCTION(instruction, prefix, escape1, \
escape2, opcode) \
void v##instruction(XMMRegister dst, XMMRegister src) { \
vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
} \
void v##instruction(XMMRegister dst, Operand src) { \
vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
}
SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSSE3_UNOP_AVX_INSTRUCTION)
#undef DECLARE_SSSE3_UNOP_AVX_INSTRUCTION
void vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2,
XMMRegister mask) {
vinstr(0x4B, dst, src1, src2, k66, k0F3A, kW0);
// The mask operand is encoded in bits[7:4] of the immediate byte.
emit(mask.code() << 4);
}
#define DECLARE_SSE4_PMOV_AVX_INSTRUCTION(instruction, prefix, escape1, \
escape2, opcode) \
void v##instruction(XMMRegister dst, XMMRegister src) { \
vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
} \
void v##instruction(XMMRegister dst, Operand src) { \
vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
}
SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION)
#undef DECLARE_SSE4_PMOV_AVX_INSTRUCTION
void movd(XMMRegister dst, Register src);
void movd(XMMRegister dst, Operand src);
void movd(Register dst, XMMRegister src);
void movq(XMMRegister dst, Register src);
void movq(XMMRegister dst, Operand src);
void movq(Register dst, XMMRegister src);
void movq(XMMRegister dst, XMMRegister src);
// Don't use this unless it's important to keep the
// top half of the destination register unchanged.
// Use movapd when moving double values and movq for integer
// values in xmm registers.
void movsd(XMMRegister dst, XMMRegister src);
void movsd(Operand dst, XMMRegister src);
void movsd(XMMRegister dst, Operand src);
void movdqa(Operand dst, XMMRegister src);
void movdqa(XMMRegister dst, Operand src);
void movdqu(Operand dst, XMMRegister src);
void movdqu(XMMRegister dst, Operand src);
void movapd(XMMRegister dst, XMMRegister src);
void movupd(XMMRegister dst, Operand src);
void movupd(Operand dst, XMMRegister src);
void cvttsd2si(Register dst, Operand src);
void cvttsd2si(Register dst, XMMRegister src);
void cvttss2siq(Register dst, XMMRegister src);
void cvttss2siq(Register dst, Operand src);
void cvttsd2siq(Register dst, XMMRegister src);
void cvttsd2siq(Register dst, Operand src);
void cvttps2dq(XMMRegister dst, Operand src);
void cvttps2dq(XMMRegister dst, XMMRegister src);
void cvtlsi2sd(XMMRegister dst, Operand src);
void cvtlsi2sd(XMMRegister dst, Register src);
void cvtqsi2ss(XMMRegister dst, Operand src);
void cvtqsi2ss(XMMRegister dst, Register src);
void cvtqsi2sd(XMMRegister dst, Operand src);
void cvtqsi2sd(XMMRegister dst, Register src);
void cvtss2sd(XMMRegister dst, XMMRegister src);
void cvtss2sd(XMMRegister dst, Operand src);
void cvtsd2si(Register dst, XMMRegister src);
void cvtsd2siq(Register dst, XMMRegister src);
void haddps(XMMRegister dst, XMMRegister src);
void haddps(XMMRegister dst, Operand src);
void ucomisd(XMMRegister dst, XMMRegister src);
void ucomisd(XMMRegister dst, Operand src);
void cmpltsd(XMMRegister dst, XMMRegister src);
void movmskpd(Register dst, XMMRegister src);
// SSE 4.1 instruction
void insertps(XMMRegister dst, XMMRegister src, byte imm8);
void insertps(XMMRegister dst, Operand src, byte imm8);
void pextrq(Register dst, XMMRegister src, int8_t imm8);
void pinsrb(XMMRegister dst, Register src, int8_t imm8);
void pinsrb(XMMRegister dst, Operand src, int8_t imm8);
void pinsrw(XMMRegister dst, Register src, int8_t imm8);
void pinsrw(XMMRegister dst, Operand src, int8_t imm8);
void pinsrd(XMMRegister dst, Register src, int8_t imm8);
void pinsrd(XMMRegister dst, Operand src, int8_t imm8);
void pinsrq(XMMRegister dst, Register src, int8_t imm8);
void pinsrq(XMMRegister dst, Operand src, int8_t imm8);
void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode);
void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
void cmpps(XMMRegister dst, Operand src, int8_t cmp);
void cmppd(XMMRegister dst, XMMRegister src, int8_t cmp);
void cmppd(XMMRegister dst, Operand src, int8_t cmp);
#define SSE_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src) { cmpps(dst, src, imm8); } \
void instr##ps(XMMRegister dst, Operand src) { cmpps(dst, src, imm8); } \
void instr##pd(XMMRegister dst, XMMRegister src) { cmppd(dst, src, imm8); } \
void instr##pd(XMMRegister dst, Operand src) { cmppd(dst, src, imm8); }
SSE_CMP_P(cmpeq, 0x0)
SSE_CMP_P(cmplt, 0x1)
SSE_CMP_P(cmple, 0x2)
SSE_CMP_P(cmpneq, 0x4)
SSE_CMP_P(cmpnlt, 0x5)
SSE_CMP_P(cmpnle, 0x6)
#undef SSE_CMP_P
void movups(XMMRegister dst, XMMRegister src);
void movups(XMMRegister dst, Operand src);
void movups(Operand dst, XMMRegister src);
void psrldq(XMMRegister dst, uint8_t shift);
void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
void pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void pshufhw(XMMRegister dst, Operand src, uint8_t shuffle);
void pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
void pshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
void movlhps(XMMRegister dst, XMMRegister src) {
sse_instr(dst, src, 0x0F, 0x16);
}
// AVX instruction
void vmovddup(XMMRegister dst, XMMRegister src);
void vmovddup(XMMRegister dst, Operand src);
void vbroadcastss(XMMRegister dst, Operand src);
void fma_instr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w);
void fma_instr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w);
#define FMA(instr, length, prefix, escape1, escape2, extension, opcode) \
void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
k##escape1##escape2, k##extension); \
} \
void instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
k##escape1##escape2, k##extension); \
}
FMA_INSTRUCTION_LIST(FMA)
#undef FMA
void vmovd(XMMRegister dst, Register src);
void vmovd(XMMRegister dst, Operand src);
void vmovd(Register dst, XMMRegister src);
void vmovq(XMMRegister dst, Register src);
void vmovq(XMMRegister dst, Operand src);
void vmovq(Register dst, XMMRegister src);
void vmovsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsd(0x10, dst, src1, src2);
}
void vmovsd(XMMRegister dst, Operand src) { vsd(0x10, dst, xmm0, src); }
void vmovsd(Operand dst, XMMRegister src) { vsd(0x11, src, xmm0, dst); }
void vmovdqu(XMMRegister dst, Operand src);
void vmovdqu(Operand dst, XMMRegister src);
#define AVX_SSE_UNOP(instr, escape, opcode) \
void v##instr(XMMRegister dst, XMMRegister src2) { \
vps(0x##opcode, dst, xmm0, src2); \
} \
void v##instr(XMMRegister dst, Operand src2) { \
vps(0x##opcode, dst, xmm0, src2); \
}
SSE_UNOP_INSTRUCTION_LIST(AVX_SSE_UNOP)
#undef AVX_SSE_UNOP
#define AVX_SSE_BINOP(instr, escape, opcode) \
void v##instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vps(0x##opcode, dst, src1, src2); \
} \
void v##instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
vps(0x##opcode, dst, src1, src2); \
}
SSE_BINOP_INSTRUCTION_LIST(AVX_SSE_BINOP)
#undef AVX_SSE_BINOP
#define AVX_3(instr, opcode, impl) \
void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
impl(opcode, dst, src1, src2); \
} \
void instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
impl(opcode, dst, src1, src2); \
}
AVX_3(vhaddps, 0x7c, vsd)
#define AVX_SCALAR(instr, prefix, escape, opcode) \
void v##instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
} \
void v##instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
}
SSE_INSTRUCTION_LIST_SS(AVX_SCALAR)
SSE2_INSTRUCTION_LIST_SD(AVX_SCALAR)
#undef AVX_SCALAR
#undef AVX_3
#define AVX_SSE2_SHIFT_IMM(instr, prefix, escape, opcode, extension) \
void v##instr(XMMRegister dst, XMMRegister src, byte imm8) { \
XMMRegister ext_reg = XMMRegister::from_code(extension); \
vinstr(0x##opcode, ext_reg, dst, src, k##prefix, k##escape, kWIG); \
emit(imm8); \
}
SSE2_INSTRUCTION_LIST_SHIFT_IMM(AVX_SSE2_SHIFT_IMM)
#undef AVX_SSE2_SHIFT_IMM
void vmovlhps(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vinstr(0x16, dst, src1, src2, kNone, k0F, kWIG);
}
void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG);
}
void vcvtss2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG);
}
void vcvttps2dq(XMMRegister dst, XMMRegister src) {
vinstr(0x5b, dst, xmm0, src, kF3, k0F, kWIG);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW0);
}
void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF2, k0F, kW0);
}
void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW0);
}
void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF3, k0F, kW0);
}
void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW1);
}
void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF3, k0F, kW1);
}
void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
XMMRegister isrc2 = XMMRegister::from_code(src2.code());
vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW1);
}
void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(0x2a, dst, src1, src2, kF2, k0F, kW1);
}
void vcvttss2si(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0);
}
void vcvttss2si(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0);
}
void vcvttsd2si(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0);
}
void vcvttsd2si(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0);
}
void vcvttss2siq(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1);
}
void vcvttss2siq(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1);
}
void vcvttsd2siq(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1);
}
void vcvttsd2siq(Register dst, Operand src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1);
}
void vcvtsd2si(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x2d, idst, xmm0, src, kF2, k0F, kW0);
}
void vucomisd(XMMRegister dst, XMMRegister src) {
vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
}
void vucomisd(XMMRegister dst, Operand src) {
vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
}
void vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2,
RoundingMode mode) {
vinstr(0x0a, dst, src1, src2, k66, k0F3A, kWIG);
emit(static_cast<byte>(mode) | 0x8); // Mask precision exception.
}
void vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2,
RoundingMode mode) {
vinstr(0x0b, dst, src1, src2, k66, k0F3A, kWIG);
emit(static_cast<byte>(mode) | 0x8); // Mask precision exception.
}
void vsd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
}
void vsd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
}
void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vss(0x10, dst, src1, src2);
}
void vmovss(XMMRegister dst, Operand src) { vss(0x10, dst, xmm0, src); }
void vmovss(Operand dst, XMMRegister src) { vss(0x11, src, xmm0, dst); }
void vucomiss(XMMRegister dst, XMMRegister src);
void vucomiss(XMMRegister dst, Operand src);
void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) {
vps(0xC6, dst, src1, src2, imm8);
}
void vmovaps(XMMRegister dst, XMMRegister src) { vps(0x28, dst, xmm0, src); }
void vmovups(XMMRegister dst, XMMRegister src) { vps(0x10, dst, xmm0, src); }
void vmovups(XMMRegister dst, Operand src) { vps(0x10, dst, xmm0, src); }
void vmovups(Operand dst, XMMRegister src) { vps(0x11, src, xmm0, dst); }
void vmovapd(XMMRegister dst, XMMRegister src) { vpd(0x28, dst, xmm0, src); }
void vmovupd(XMMRegister dst, Operand src) { vpd(0x10, dst, xmm0, src); }
void vmovupd(Operand dst, XMMRegister src) { vpd(0x11, src, xmm0, dst); }
void vmovmskps(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vps(0x50, idst, xmm0, src);
}
void vmovmskpd(Register dst, XMMRegister src) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vpd(0x50, idst, xmm0, src);
}
void vcmpps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
vps(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
vps(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmppd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
vpd(0xC2, dst, src1, src2);
emit(cmp);
}
void vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
vpd(0xC2, dst, src1, src2);
emit(cmp);
}
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##ps(XMMRegister dst, XMMRegister src1, Operand src2) { \
vcmpps(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmppd(dst, src1, src2, imm8); \
} \
void instr##pd(XMMRegister dst, XMMRegister src1, Operand src2) { \
vcmppd(dst, src1, src2, imm8); \
}
AVX_CMP_P(vcmpeq, 0x0)
AVX_CMP_P(vcmplt, 0x1)
AVX_CMP_P(vcmple, 0x2)
AVX_CMP_P(vcmpneq, 0x4)
AVX_CMP_P(vcmpnlt, 0x5)
AVX_CMP_P(vcmpnle, 0x6)
#undef AVX_CMP_P
void vlddqu(XMMRegister dst, Operand src) {
vinstr(0xF0, dst, xmm0, src, kF2, k0F, kWIG);
}
void vinsertps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
byte imm8) {
vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
emit(imm8);
}
void vinsertps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) {
vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
emit(imm8);
}
void vextractps(Register dst, XMMRegister src, int8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x17, src, xmm0, idst, k66, k0F3A, kWIG);
emit(imm8);
}
void vpextrb(Register dst, XMMRegister src, uint8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x14, src, xmm0, idst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrb(Operand dst, XMMRegister src, uint8_t imm8) {
vinstr(0x14, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrw(Register dst, XMMRegister src, uint8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0xc5, idst, xmm0, src, k66, k0F, kW0);
emit(imm8);
}
void vpextrw(Operand dst, XMMRegister src, uint8_t imm8) {
vinstr(0x15, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrd(Register dst, XMMRegister src, uint8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrd(Operand dst, XMMRegister src, uint8_t imm8) {
vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrq(Register dst, XMMRegister src, int8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW1);
emit(imm8);
}
void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
XMMRegister isrc = XMMRegister::from_code(src2.code());
vinstr(0x20, dst, src1, isrc, k66, k0F3A, kW0);
emit(imm8);
}
void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
vinstr(0x20, dst, src1, src2, k66, k0F3A, kW0);
emit(imm8);
}
void vpinsrw(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
XMMRegister isrc = XMMRegister::from_code(src2.code());
vinstr(0xc4, dst, src1, isrc, k66, k0F, kW0);
emit(imm8);
}
void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
vinstr(0xc4, dst, src1, src2, k66, k0F, kW0);
emit(imm8);
}
void vpinsrd(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
XMMRegister isrc = XMMRegister::from_code(src2.code());
vinstr(0x22, dst, src1, isrc, k66, k0F3A, kW0);
emit(imm8);
}
void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
vinstr(0x22, dst, src1, src2, k66, k0F3A, kW0);
emit(imm8);
}
void vpinsrq(XMMRegister dst, XMMRegister src1, Register src2, int8_t imm8) {
XMMRegister isrc = XMMRegister::from_code(src2.code());
vinstr(0x22, dst, src1, isrc, k66, k0F3A, kW1);
emit(imm8);
}
void vpinsrq(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8) {
vinstr(0x22, dst, src1, src2, k66, k0F3A, kW1);
emit(imm8);
}
void vpshufd(XMMRegister dst, XMMRegister src, uint8_t imm8) {
vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
emit(imm8);
}
void vpshufd(XMMRegister dst, Operand src, uint8_t imm8) {
vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
emit(imm8);
}
void vpshuflw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
emit(imm8);
}
void vpshuflw(XMMRegister dst, Operand src, uint8_t imm8) {
vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
emit(imm8);
}
void vpshufhw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
vinstr(0x70, dst, xmm0, src, kF3, k0F, kWIG);
emit(imm8);
}
void vpshufhw(XMMRegister dst, Operand src, uint8_t imm8) {
vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
emit(imm8);
}
void vpblendw(XMMRegister dst, XMMRegister src1, XMMRegister src2,
uint8_t mask) {
vinstr(0x0E, dst, src1, src2, k66, k0F3A, kWIG);
emit(mask);
}
void vpblendw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) {
vinstr(0x0E, dst, src1, src2, k66, k0F3A, kWIG);
emit(mask);
}
void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2,
uint8_t imm8) {
vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
emit(imm8);
}
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
byte imm8);
void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
// BMI instruction
void andnq(Register dst, Register src1, Register src2) {
bmi1q(0xf2, dst, src1, src2);
}
void andnq(Register dst, Register src1, Operand src2) {
bmi1q(0xf2, dst, src1, src2);
}
void andnl(Register dst, Register src1, Register src2) {
bmi1l(0xf2, dst, src1, src2);
}
void andnl(Register dst, Register src1, Operand src2) {
bmi1l(0xf2, dst, src1, src2);
}
void bextrq(Register dst, Register src1, Register src2) {
bmi1q(0xf7, dst, src2, src1);
}
void bextrq(Register dst, Operand src1, Register src2) {
bmi1q(0xf7, dst, src2, src1);
}
void bextrl(Register dst, Register src1, Register src2) {
bmi1l(0xf7, dst, src2, src1);
}
void bextrl(Register dst, Operand src1, Register src2) {
bmi1l(0xf7, dst, src2, src1);
}
void blsiq(Register dst, Register src) { bmi1q(0xf3, rbx, dst, src); }
void blsiq(Register dst, Operand src) { bmi1q(0xf3, rbx, dst, src); }
void blsil(Register dst, Register src) { bmi1l(0xf3, rbx, dst, src); }
void blsil(Register dst, Operand src) { bmi1l(0xf3, rbx, dst, src); }
void blsmskq(Register dst, Register src) { bmi1q(0xf3, rdx, dst, src); }
void blsmskq(Register dst, Operand src) { bmi1q(0xf3, rdx, dst, src); }
void blsmskl(Register dst, Register src) { bmi1l(0xf3, rdx, dst, src); }
void blsmskl(Register dst, Operand src) { bmi1l(0xf3, rdx, dst, src); }
void blsrq(Register dst, Register src) { bmi1q(0xf3, rcx, dst, src); }
void blsrq(Register dst, Operand src) { bmi1q(0xf3, rcx, dst, src); }
void blsrl(Register dst, Register src) { bmi1l(0xf3, rcx, dst, src); }
void blsrl(Register dst, Operand src) { bmi1l(0xf3, rcx, dst, src); }
void tzcntq(Register dst, Register src);
void tzcntq(Register dst, Operand src);
void tzcntl(Register dst, Register src);
void tzcntl(Register dst, Operand src);
void lzcntq(Register dst, Register src);
void lzcntq(Register dst, Operand src);
void lzcntl(Register dst, Register src);
void lzcntl(Register dst, Operand src);
void popcntq(Register dst, Register src);
void popcntq(Register dst, Operand src);
void popcntl(Register dst, Register src);
void popcntl(Register dst, Operand src);
void bzhiq(Register dst, Register src1, Register src2) {
bmi2q(kNone, 0xf5, dst, src2, src1);
}
void bzhiq(Register dst, Operand src1, Register src2) {
bmi2q(kNone, 0xf5, dst, src2, src1);
}
void bzhil(Register dst, Register src1, Register src2) {
bmi2l(kNone, 0xf5, dst, src2, src1);
}
void bzhil(Register dst, Operand src1, Register src2) {
bmi2l(kNone, 0xf5, dst, src2, src1);
}
void mulxq(Register dst1, Register dst2, Register src) {
bmi2q(kF2, 0xf6, dst1, dst2, src);
}
void mulxq(Register dst1, Register dst2, Operand src) {
bmi2q(kF2, 0xf6, dst1, dst2, src);
}
void mulxl(Register dst1, Register dst2, Register src) {
bmi2l(kF2, 0xf6, dst1, dst2, src);
}
void mulxl(Register dst1, Register dst2, Operand src) {
bmi2l(kF2, 0xf6, dst1, dst2, src);
}
void pdepq(Register dst, Register src1, Register src2) {
bmi2q(kF2, 0xf5, dst, src1, src2);
}
void pdepq(Register dst, Register src1, Operand src2) {
bmi2q(kF2, 0xf5, dst, src1, src2);
}
void pdepl(Register dst, Register src1, Register src2) {
bmi2l(kF2, 0xf5, dst, src1, src2);
}
void pdepl(Register dst, Register src1, Operand src2) {
bmi2l(kF2, 0xf5, dst, src1, src2);
}
void pextq(Register dst, Register src1, Register src2) {
bmi2q(kF3, 0xf5, dst, src1, src2);
}
void pextq(Register dst, Register src1, Operand src2) {
bmi2q(kF3, 0xf5, dst, src1, src2);
}
void pextl(Register dst, Register src1, Register src2) {
bmi2l(kF3, 0xf5, dst, src1, src2);
}
void pextl(Register dst, Register src1, Operand src2) {
bmi2l(kF3, 0xf5, dst, src1, src2);
}
void sarxq(Register dst, Register src1, Register src2) {
bmi2q(kF3, 0xf7, dst, src2, src1);
}
void sarxq(Register dst, Operand src1, Register src2) {
bmi2q(kF3, 0xf7, dst, src2, src1);
}
void sarxl(Register dst, Register src1, Register src2) {
bmi2l(kF3, 0xf7, dst, src2, src1);
}
void sarxl(Register dst, Operand src1, Register src2) {
bmi2l(kF3, 0xf7, dst, src2, src1);
}
void shlxq(Register dst, Register src1, Register src2) {
bmi2q(k66, 0xf7, dst, src2, src1);
}
void shlxq(Register dst, Operand src1, Register src2) {
bmi2q(k66, 0xf7, dst, src2, src1);
}
void shlxl(Register dst, Register src1, Register src2) {
bmi2l(k66, 0xf7, dst, src2, src1);
}
void shlxl(Register dst, Operand src1, Register src2) {
bmi2l(k66, 0xf7, dst, src2, src1);
}
void shrxq(Register dst, Register src1, Register src2) {
bmi2q(kF2, 0xf7, dst, src2, src1);
}
void shrxq(Register dst, Operand src1, Register src2) {
bmi2q(kF2, 0xf7, dst, src2, src1);
}
void shrxl(Register dst, Register src1, Register src2) {
bmi2l(kF2, 0xf7, dst, src2, src1);
}
void shrxl(Register dst, Operand src1, Register src2) {
bmi2l(kF2, 0xf7, dst, src2, src1);
}
void rorxq(Register dst, Register src, byte imm8);
void rorxq(Register dst, Operand src, byte imm8);
void rorxl(Register dst, Register src, byte imm8);
void rorxl(Register dst, Operand src, byte imm8);
void mfence();
void lfence();
void pause();
// Check the code size generated from label to here.
int SizeOfCodeGeneratedSince(Label* label) {
return pc_offset() - label->pos();
}
// Record a deoptimization reason that can be used by a log or cpu profiler.
// Use --trace-deopt to enable.
void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position,
int id);
// Writes a single word of data in the code stream.
// Used for inline tables, e.g., jump-tables.
void db(uint8_t data);
void dd(uint32_t data);
void dq(uint64_t data);
void dp(uintptr_t data) { dq(data); }
void dq(Label* label);
// Patch entries for partial constant pool.
void PatchConstPool();
// Check if use partial constant pool for this rmode.
static bool UseConstPoolFor(RelocInfo::Mode rmode);
// Check if there is less than kGap bytes available in the buffer.
// If this is the case, we need to grow the buffer before emitting
// an instruction or relocation information.
inline bool buffer_overflow() const {
return pc_ >= reloc_info_writer.pos() - kGap;
}
// Get the number of bytes available in the buffer.
inline int available_space() const {
return static_cast<int>(reloc_info_writer.pos() - pc_);
}
static bool IsNop(Address addr);
// Avoid overflows for displacements etc.
static constexpr int kMaximalBufferSize = 512 * MB;
byte byte_at(int pos) { return buffer_start_[pos]; }
void set_byte_at(int pos, byte value) { buffer_start_[pos] = value; }
#if defined(V8_OS_WIN_X64)
win64_unwindinfo::BuiltinUnwindInfo GetUnwindInfo() const;
#endif
protected:
// Call near indirect
void call(Operand operand);
private:
Address addr_at(int pos) {
return reinterpret_cast<Address>(buffer_start_ + pos);
}
uint32_t long_at(int pos) {
return ReadUnalignedValue<uint32_t>(addr_at(pos));
}
void long_at_put(int pos, uint32_t x) {
WriteUnalignedValue(addr_at(pos), x);
}
// code emission
void GrowBuffer();
void emit(byte x) { *pc_++ = x; }
inline void emitl(uint32_t x);
inline void emitq(uint64_t x);
inline void emitw(uint16_t x);
inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode);
inline void emit(Immediate x);
inline void emit(Immediate64 x);
// Emits a REX prefix that encodes a 64-bit operand size and
// the top bit of both register codes.
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
// REX.W is set.
inline void emit_rex_64(XMMRegister reg, Register rm_reg);
inline void emit_rex_64(Register reg, XMMRegister rm_reg);
inline void emit_rex_64(Register reg, Register rm_reg);
inline void emit_rex_64(XMMRegister reg, XMMRegister rm_reg);
// Emits a REX prefix that encodes a 64-bit operand size and
// the top bit of the destination, index, and base register codes.
// The high bit of reg is used for REX.R, the high bit of op's base
// register is used for REX.B, and the high bit of op's index register
// is used for REX.X. REX.W is set.
inline void emit_rex_64(Register reg, Operand op);
inline void emit_rex_64(XMMRegister reg, Operand op);
// Emits a REX prefix that encodes a 64-bit operand size and
// the top bit of the register code.
// The high bit of register is used for REX.B.
// REX.W is set and REX.R and REX.X are clear.
inline void emit_rex_64(Register rm_reg);
// Emits a REX prefix that encodes a 64-bit operand size and
// the top bit of the index and base register codes.
// The high bit of op's base register is used for REX.B, and the high
// bit of op's index register is used for REX.X.
// REX.W is set and REX.R clear.
inline void emit_rex_64(Operand op);
// Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
void emit_rex_64() { emit(0x48); }
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
// REX.W is clear.
inline void emit_rex_32(Register reg, Register rm_reg);
// The high bit of reg is used for REX.R, the high bit of op's base
// register is used for REX.B, and the high bit of op's index register
// is used for REX.X. REX.W is cleared.
inline void emit_rex_32(Register reg, Operand op);
// High bit of rm_reg goes to REX.B.
// REX.W, REX.R and REX.X are clear.
inline void emit_rex_32(Register rm_reg);
// High bit of base goes to REX.B and high bit of index to REX.X.
// REX.W and REX.R are clear.
inline void emit_rex_32(Operand op);
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
// REX.W is cleared. If no REX bits are set, no byte is emitted.
inline void emit_optional_rex_32(Register reg, Register rm_reg);
// The high bit of reg is used for REX.R, the high bit of op's base
// register is used for REX.B, and the high bit of op's index register
// is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
// is emitted.
inline void emit_optional_rex_32(Register reg, Operand op);
// As for emit_optional_rex_32(Register, Register), except that
// the registers are XMM registers.
inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
// As for emit_optional_rex_32(Register, Register), except that
// one of the registers is an XMM registers.
inline void emit_optional_rex_32(XMMRegister reg, Register base);
// As for emit_optional_rex_32(Register, Register), except that
// one of the registers is an XMM registers.
inline void emit_optional_rex_32(Register reg, XMMRegister base);
// As for emit_optional_rex_32(Register, Operand), except that
// the register is an XMM register.
inline void emit_optional_rex_32(XMMRegister reg, Operand op);
// Optionally do as emit_rex_32(Register) if the register number has
// the high bit set.
inline void emit_optional_rex_32(Register rm_reg);
inline void emit_optional_rex_32(XMMRegister rm_reg);
// Optionally do as emit_rex_32(Operand) if the operand register
// numbers have a high bit set.
inline void emit_optional_rex_32(Operand op);
// Calls emit_rex_32(Register) for all non-byte registers.
inline void emit_optional_rex_8(Register reg);
// Calls emit_rex_32(Register, Operand) for all non-byte registers, and
// emit_optional_rex_32(Register, Operand) for byte registers.
inline void emit_optional_rex_8(Register reg, Operand op);
void emit_rex(int size) {
if (size == kInt64Size) {
emit_rex_64();
} else {
DCHECK_EQ(size, kInt32Size);
}
}
template <class P1>
void emit_rex(P1 p1, int size) {
if (size == kInt64Size) {
emit_rex_64(p1);
} else {
DCHECK_EQ(size, kInt32Size);
emit_optional_rex_32(p1);
}
}
template <class P1, class P2>
void emit_rex(P1 p1, P2 p2, int size) {
if (size == kInt64Size) {
emit_rex_64(p1, p2);
} else {
DCHECK_EQ(size, kInt32Size);
emit_optional_rex_32(p1, p2);
}
}
// Emit vex prefix
void emit_vex2_byte0() { emit(0xc5); }
inline void emit_vex2_byte1(XMMRegister reg, XMMRegister v, VectorLength l,
SIMDPrefix pp);
void emit_vex3_byte0() { emit(0xc4); }
inline void emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m);
inline void emit_vex3_byte1(XMMRegister reg, Operand rm, LeadingOpcode m);
inline void emit_vex3_byte2(VexW w, XMMRegister v, VectorLength l,
SIMDPrefix pp);
inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, XMMRegister rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
inline void emit_vex_prefix(Register reg, Register v, Register rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, Operand rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
inline void emit_vex_prefix(Register reg, Register v, Operand rm,
VectorLength l, SIMDPrefix pp, LeadingOpcode m,
VexW w);
// Emit the ModR/M byte, and optionally the SIB byte and
// 1- or 4-byte offset for a memory operand. Also encodes
// the second operand of the operation, a register or operation
// subcode, into the reg field of the ModR/M byte.
void emit_operand(Register reg, Operand adr) {
emit_operand(reg.low_bits(), adr);
}
// Emit the ModR/M byte, and optionally the SIB byte and
// 1- or 4-byte offset for a memory operand. Also used to encode
// a three-bit opcode extension into the ModR/M byte.
void emit_operand(int rm, Operand adr);
// Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
void emit_modrm(Register reg, Register rm_reg) {
emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
}
// Emit a ModR/M byte with an operation subcode in the reg field and
// a register in the rm_reg field.
void emit_modrm(int code, Register rm_reg) {
DCHECK(is_uint3(code));
emit(0xC0 | code << 3 | rm_reg.low_bits());
}
// Emit the code-object-relative offset of the label's position
inline void emit_code_relative_offset(Label* label);
// The first argument is the reg field, the second argument is the r/m field.
void emit_sse_operand(XMMRegister dst, XMMRegister src);
void emit_sse_operand(XMMRegister reg, Operand adr);
void emit_sse_operand(Register reg, Operand adr);
void emit_sse_operand(XMMRegister dst, Register src);
void emit_sse_operand(Register dst, XMMRegister src);
void emit_sse_operand(XMMRegister dst);
// Emit machine code for one of the operations ADD, ADC, SUB, SBC,
// AND, OR, XOR, or CMP. The encodings of these operations are all
// similar, differing just in the opcode or in the reg field of the
// ModR/M byte.
void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
void arithmetic_op_8(byte opcode, Register reg, Operand rm_reg);
void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
void arithmetic_op_16(byte opcode, Register reg, Operand rm_reg);
// Operate on operands/registers with pointer size, 32-bit or 64-bit size.
void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
void arithmetic_op(byte opcode, Register reg, Operand rm_reg, int size);
// Operate on a byte in memory or register.
void immediate_arithmetic_op_8(byte subcode, Register dst, Immediate src);
void immediate_arithmetic_op_8(byte subcode, Operand dst, Immediate src);
// Operate on a word in memory or register.
void immediate_arithmetic_op_16(byte subcode, Register dst, Immediate src);
void immediate_arithmetic_op_16(byte subcode, Operand dst, Immediate src);
// Operate on operands/registers with pointer size, 32-bit or 64-bit size.
void immediate_arithmetic_op(byte subcode, Register dst, Immediate src,
int size);
void immediate_arithmetic_op(byte subcode, Operand dst, Immediate src,
int size);
// Emit machine code for a shift operation.
void shift(Operand dst, Immediate shift_amount, int subcode, int size);
void shift(Register dst, Immediate shift_amount, int subcode, int size);
// Shift dst by cl % 64 bits.
void shift(Register dst, int subcode, int size);
void shift(Operand dst, int subcode, int size);
void emit_farith(int b1, int b2, int i);
// labels
// void print(Label* L);
void bind_to(Label* L, int pos);
// record reloc info for current pc_
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
// Arithmetics
void emit_add(Register dst, Register src, int size) {
arithmetic_op(0x03, dst, src, size);
}
void emit_add(Register dst, Immediate src, int size) {
immediate_arithmetic_op(0x0, dst, src, size);
}
void emit_add(Register dst, Operand src, int size) {
arithmetic_op(0x03, dst, src, size);
}
void emit_add(Operand dst, Register src, int size) {
arithmetic_op(0x1, src, dst, size);
}
void emit_add(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x0, dst, src, size);
}
void emit_and(Register dst, Register src, int size) {
arithmetic_op(0x23, dst, src, size);
}
void emit_and(Register dst, Operand src, int size) {
arithmetic_op(0x23, dst, src, size);
}
void emit_and(Operand dst, Register src, int size) {
arithmetic_op(0x21, src, dst, size);
}
void emit_and(Register dst, Immediate src, int size) {
immediate_arithmetic_op(0x4, dst, src, size);
}
void emit_and(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x4, dst, src, size);
}
void emit_cmp(Register dst, Register src, int size) {
arithmetic_op(0x3B, dst, src, size);
}
void emit_cmp(Register dst, Operand src, int size) {
arithmetic_op(0x3B, dst, src, size);
}
void emit_cmp(Operand dst, Register src, int size) {
arithmetic_op(0x39, src, dst, size);
}
void emit_cmp(Register dst, Immediate src, int size) {
immediate_arithmetic_op(0x7, dst, src, size);
}
void emit_cmp(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x7, dst, src, size);
}
// Compare {al,ax,eax,rax} with src. If equal, set ZF and write dst into
// src. Otherwise clear ZF and write src into {al,ax,eax,rax}. This
// operation is only atomic if prefixed by the lock instruction.
void emit_cmpxchg(Operand dst, Register src, int size);
void emit_dec(Register dst, int size);
void emit_dec(Operand dst, int size);
// Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
// Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
// when size is 32.
void emit_idiv(Register src, int size);
void emit_div(Register src, int size);
// Signed multiply instructions.
// rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
void emit_imul(Register src, int size);
void emit_imul(Operand src, int size);
void emit_imul(Register dst, Register src, int size);
void emit_imul(Register dst, Operand src, int size);
void emit_imul(Register dst, Register src, Immediate imm, int size);
void emit_imul(Register dst, Operand src, Immediate imm, int size);
void emit_inc(Register dst, int size);
void emit_inc(Operand dst, int size);
void emit_lea(Register dst, Operand src, int size);
void emit_mov(Register dst, Operand src, int size);
void emit_mov(Register dst, Register src, int size);
void emit_mov(Operand dst, Register src, int size);
void emit_mov(Register dst, Immediate value, int size);
void emit_mov(Operand dst, Immediate value, int size);
void emit_mov(Register dst, Immediate64 value, int size);
void emit_movzxb(Register dst, Operand src, int size);
void emit_movzxb(Register dst, Register src, int size);
void emit_movzxw(Register dst, Operand src, int size);
void emit_movzxw(Register dst, Register src, int size);
void emit_neg(Register dst, int size);
void emit_neg(Operand dst, int size);
void emit_not(Register dst, int size);
void emit_not(Operand dst, int size);
void emit_or(Register dst, Register src, int size) {
arithmetic_op(0x0B, dst, src, size);
}
void emit_or(Register dst, Operand src, int size) {
arithmetic_op(0x0B, dst, src, size);
}
void emit_or(Operand dst, Register src, int size) {
arithmetic_op(0x9, src, dst, size);
}
void emit_or(Register dst, Immediate src, int size) {
immediate_arithmetic_op(0x1, dst, src, size);
}
void emit_or(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x1, dst, src, size);
}
void emit_repmovs(int size);
void emit_sbb(Register dst, Register src, int size) {
arithmetic_op(0x1b, dst, src, size);
}
void emit_sub(Register dst, Register src, int size) {
arithmetic_op(0x2B, dst, src, size);
}
void emit_sub(Register dst, Immediate src, int size) {
immediate_arithmetic_op(0x5, dst, src, size);
}
void emit_sub(Register dst, Operand src, int size) {
arithmetic_op(0x2B, dst, src, size);
}
void emit_sub(Operand dst, Register src, int size) {
arithmetic_op(0x29, src, dst, size);
}
void emit_sub(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x5, dst, src, size);
}
void emit_test(Register dst, Register src, int size);
void emit_test(Register reg, Immediate mask, int size);
void emit_test(Operand op, Register reg, int size);
void emit_test(Operand op, Immediate mask, int size);
void emit_test(Register reg, Operand op, int size) {
return emit_test(op, reg, size);
}
void emit_xchg(Register dst, Register src, int size);
void emit_xchg(Register dst, Operand src, int size);
void emit_xor(Register dst, Register src, int size) {
if (size == kInt64Size && dst.code() == src.code()) {
// 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
// there is no need to make this a 64 bit operation.
arithmetic_op(0x33, dst, src, kInt32Size);
} else {
arithmetic_op(0x33, dst, src, size);
}
}
void emit_xor(Register dst, Operand src, int size) {
arithmetic_op(0x33, dst, src, size);
}
void emit_xor(Register dst, Immediate src, int size) {
immediate_arithmetic_op(0x6, dst, src, size);
}
void emit_xor(Operand dst, Immediate src, int size) {
immediate_arithmetic_op(0x6, dst, src, size);
}
void emit_xor(Operand dst, Register src, int size) {
arithmetic_op(0x31, src, dst, size);
}
// Most BMI instructions are similar.
void bmi1q(byte op, Register reg, Register vreg, Register rm);
void bmi1q(byte op, Register reg, Register vreg, Operand rm);
void bmi1l(byte op, Register reg, Register vreg, Register rm);
void bmi1l(byte op, Register reg, Register vreg, Operand rm);
void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm);
void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm);
void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
// record the position of jmp/jcc instruction
void record_farjmp_position(Label* L, int pos);
bool is_optimizable_farjmp(int idx);
void AllocateAndInstallRequestedHeapObjects(Isolate* isolate);
int WriteCodeComments();
friend class EnsureSpace;
friend class RegExpMacroAssemblerX64;
// code generation
RelocInfoWriter reloc_info_writer;
// Internal reference positions, required for (potential) patching in
// GrowBuffer(); contains only those internal references whose labels
// are already bound.
std::deque<int> internal_reference_positions_;
// Variables for this instance of assembler
int farjmp_num_ = 0;
std::deque<int> farjmp_positions_;
std::map<Label*, std::vector<int>> label_farjmp_maps_;
ConstPool constpool_;
friend class ConstPool;
#if defined(V8_OS_WIN_X64)
std::unique_ptr<win64_unwindinfo::XdataEncoder> xdata_encoder_;
#endif
};
// Helper class that ensures that there is enough space for generating
// instructions and relocation information. The constructor makes
// sure that there is enough space and (in debug mode) the destructor
// checks that we did not generate too much.
class EnsureSpace {
public:
explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
#ifdef DEBUG
space_before_ = assembler_->available_space();
#endif
}
#ifdef DEBUG
~EnsureSpace() {
int bytes_generated = space_before_ - assembler_->available_space();
DCHECK(bytes_generated < assembler_->kGap);
}
#endif
private:
Assembler* assembler_;
#ifdef DEBUG
int space_before_;
#endif
};
} // namespace internal
} // namespace v8
#endif // V8_CODEGEN_X64_ASSEMBLER_X64_H_
|