From 7e4c0099cc84b744d3844c9811f2470c50d6dcbf Mon Sep 17 00:00:00 2001 From: Ashkan Aliabadi Date: Mon, 1 Jun 2020 18:23:11 -0700 Subject: Upstream cpuinfo updates as of XNNPACK:5d67652eb23c2e94ffeeafd3e82a41745eb3ce41 --- include/cpuinfo.h | 22 +++++++++++----------- src/api.c | 12 ++++++++---- src/arm/cache.c | 1 - src/arm/mach/init.c | 9 +++++++++ src/arm/midr.h | 6 ++++++ src/arm/uarch.c | 4 ++-- tools/cpu-info.c | 2 -- 7 files changed, 36 insertions(+), 20 deletions(-) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index e89a4c1..6c67c34 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -46,14 +46,6 @@ #endif #endif -#if CPUINFO_ARCH_X86 && defined(_MSC_VER) - #define CPUINFO_ABI __cdecl -#elif CPUINFO_ARCH_X86 && defined(__GNUC__) - #define CPUINFO_ABI __attribute__((__cdecl__)) -#else - #define CPUINFO_ABI -#endif - /* Define other architecture-specific macros as 0 */ #ifndef CPUINFO_ARCH_X86 @@ -88,6 +80,14 @@ #define CPUINFO_ARCH_WASMSIMD 0 #endif +#if CPUINFO_ARCH_X86 && defined(_MSC_VER) + #define CPUINFO_ABI __cdecl +#elif CPUINFO_ARCH_X86 && defined(__GNUC__) + #define CPUINFO_ABI __attribute__((__cdecl__)) +#else + #define CPUINFO_ABI +#endif + #define CPUINFO_CACHE_UNIFIED 0x00000001 #define CPUINFO_CACHE_INCLUSIVE 0x00000002 #define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004 @@ -415,8 +415,6 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_a75 = 0x00300375, /** ARM Cortex-A76. */ cpuinfo_uarch_cortex_a76 = 0x00300376, - /** ARM Cortex-A76AE. */ - cpuinfo_uarch_cortex_a76ae = 0x00300378, /** ARM Cortex-A77. */ cpuinfo_uarch_cortex_a77 = 0x00300377, @@ -454,7 +452,9 @@ enum cpuinfo_uarch { /** Samsung Exynos M5 (Exynos 9830 big cores). */ cpuinfo_uarch_exynos_m5 = 0x00600104, - /* Old names for Exynos. */ + /* Deprecated synonym for Cortex-A76 */ + cpuinfo_uarch_cortex_a76ae = 0x00300376, + /* Deprecated names for Exynos. */ cpuinfo_uarch_mongoose_m1 = 0x00600100, cpuinfo_uarch_mongoose_m2 = 0x00600101, cpuinfo_uarch_meerkat_m3 = 0x00600102, diff --git a/src/api.c b/src/api.c index 832b085..f91b421 100644 --- a/src/api.c +++ b/src/api.c @@ -314,7 +314,8 @@ const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void) cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_processor"); } #ifdef __linux__ - unsigned cpu; + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { return 0; } @@ -332,7 +333,8 @@ const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_core"); } #ifdef __linux__ - unsigned cpu; + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { return 0; } @@ -357,7 +359,8 @@ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void) { } /* General case */ - unsigned cpu; + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { return 0; } @@ -387,7 +390,8 @@ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t defau } /* General case */ - unsigned cpu; + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { return default_uarch_index; } diff --git a/src/arm/cache.c b/src/arm/cache.c index 666ad78..446b02b 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1115,7 +1115,6 @@ void cpuinfo_arm_decode_cache( break; } case cpuinfo_uarch_cortex_a76: - case cpuinfo_uarch_cortex_a76ae: { /* * ARM Cortex-A76 Core Technical Reference Manual diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index bd27259..058cfc2 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -347,6 +347,15 @@ void cpuinfo_arm_mach_init(void) { cpuinfo_isa.fp16arith = true; } + /* + * There does not yet seem to exist an OS mechanism to detect support for + * ARMv8.2 optional dot-product instructions, so we currently whitelist CPUs + * known to support these instruction. + */ + if (cpu_family == CPUFAMILY_ARM_LIGHTNING_THUNDER) { + cpuinfo_isa.dot = true; + } + uint32_t num_clusters = 1; for (uint32_t i = 0; i < mach_topology.cores; i++) { cores[i] = (struct cpuinfo_core) { diff --git a/src/arm/midr.h b/src/arm/midr.h index d5a28e3..34d7780 100644 --- a/src/arm/midr.h +++ b/src/arm/midr.h @@ -189,22 +189,28 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D0A0): /* Cortex-A75 */ case UINT32_C(0x4100D090): /* Cortex-A73 */ case UINT32_C(0x4100D080): /* Cortex-A72 */ +#if CPUINFO_ARCH_ARM case UINT32_C(0x4100C0F0): /* Cortex-A15 */ case UINT32_C(0x4100C0E0): /* Cortex-A17 */ case UINT32_C(0x4100C0D0): /* Rockchip RK3288 cores */ case UINT32_C(0x4100C0C0): /* Cortex-A12 */ +#endif /* CPUINFO_ARCH_ARM */ /* These cores are always in big role */ return 5; case UINT32_C(0x4100D070): /* Cortex-A57 */ /* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or in big role w.r.t. Cortex-A53 */ return 4; +#if CPUINFO_ARCH_ARM64 case UINT32_C(0x4100D060): /* Cortex-A65 */ +#endif /* CPUINFO_ARCH_ARM64 */ case UINT32_C(0x4100D050): /* Cortex-A55 */ case UINT32_C(0x4100D030): /* Cortex-A53 */ /* Cortex-A53 is usually in LITTLE role, but can be in big role w.r.t. Cortex-A35 */ return 2; case UINT32_C(0x4100D040): /* Cortex-A35 */ +#if CPUINFO_ARCH_ARM case UINT32_C(0x4100C070): /* Cortex-A7 */ +#endif /* CPUINFO_ARCH_ARM */ case UINT32_C(0x51008050): /* Kryo 485 Silver */ case UINT32_C(0x51008030): /* Kryo 385 Silver */ case UINT32_C(0x51008010): /* Kryo 260 / 280 Silver */ diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 63b1a55..55b61df 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -88,8 +88,8 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD0D: *uarch = cpuinfo_uarch_cortex_a77; break; - case 0xD0E: - *uarch = cpuinfo_uarch_cortex_a76ae; + case 0xD0E: /* Cortex-A76AE */ + *uarch = cpuinfo_uarch_cortex_a76; break; #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case 0xD4A: diff --git a/tools/cpu-info.c b/tools/cpu-info.c index 4453d88..2759068 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -181,8 +181,6 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Cortex-A75"; case cpuinfo_uarch_cortex_a76: return "Cortex-A76"; - case cpuinfo_uarch_cortex_a76ae: - return "Cortex-A76AE"; case cpuinfo_uarch_cortex_a77: return "Cortex-A77"; case cpuinfo_uarch_scorpion: -- cgit v1.2.3