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authorNorbert Braun <n.f.braun@web.de>2014-08-04 17:35:55 +0400
committerNorbert Braun <n.f.braun@web.de>2014-08-04 17:38:01 +0400
commit884924d598b7927d6d38b822da981aecfbccc4ea (patch)
tree5460ea18dfa33cca7b6598e27ebb8d32431ebdd4
parentaf3389652cce7bd911a538ece4fd1fabf34e6048 (diff)
stm32: timers: fix mixup between TIMx_CCMR1 and TIMx_CCMR2 in timer_set_oc_mode()
-rw-r--r--lib/stm32/common/timer_common_all.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c
index e4850c29..a1a43801 100644
--- a/lib/stm32/common/timer_common_all.c
+++ b/lib/stm32/common/timer_common_all.c
@@ -1035,15 +1035,15 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
}
break;
case TIM_OC3:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
+ TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
+ TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
switch (oc_mode) {
case TIM_OCM_FROZEN:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
break;
case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
+ TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
break;
case TIM_OCM_INACTIVE:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
@@ -1067,15 +1067,15 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
}
break;
case TIM_OC4:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
+ TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
+ TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK;
switch (oc_mode) {
case TIM_OCM_FROZEN:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN;
break;
case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
+ TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
break;
case TIM_OCM_INACTIVE:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE;