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-rw-r--r--include/libopencm3/sdcard/sdcard.h334
-rw-r--r--include/libopencm3/stm32/common/crypto_common_f24.h21
-rw-r--r--include/libopencm3/stm32/common/sdio_common_all.h37
-rw-r--r--include/libopencm3/stm32/common/timer_common_all.h4
-rw-r--r--include/libopencm3/stm32/f2/memorymap.h5
-rw-r--r--include/libopencm3/stm32/f2/rcc.h3
-rw-r--r--include/libopencm3/stm32/sdio.h203
-rw-r--r--include/libopencm3/usb/dwc/otg_common.h4
-rw-r--r--include/libopencm3/usb/dwc/otg_hs.h27
-rw-r--r--include/libopencm3/usb/hid.h2
-rw-r--r--include/libopencm3/usb/usbd.h4
-rw-r--r--include/libopencm3/usb/usbstd.h6
12 files changed, 632 insertions, 18 deletions
diff --git a/include/libopencm3/sdcard/sdcard.h b/include/libopencm3/sdcard/sdcard.h
new file mode 100644
index 00000000..6b42b260
--- /dev/null
+++ b/include/libopencm3/sdcard/sdcard.h
@@ -0,0 +1,334 @@
+/** @defgroup sdcard_defines SDCARD Defines
+
+@brief <b>Defined Constants and Types for the SDCARD</b>
+
+@ingroup SDCARD_defines
+
+@version 1.0.0
+
+@date 19 April 2017
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SDCARD_H
+#define SDCARD_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/sdio.h>
+
+typedef enum
+{
+/**
+ * @brief SDIO specific error defines
+ */
+ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
+ SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */
+ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
+ SD_DATA_TIMEOUT = (4), /*!< Data time out */
+ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */
+ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */
+ SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/
+ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
+ SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+ SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/
+ SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */
+ SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
+ SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+ SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
+ SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
+ SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
+ SD_CC_ERROR = (18), /*!< Internal card controller error */
+ SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */
+ SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
+ SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
+ SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
+ SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */
+ SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
+ SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+ SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
+ SD_INVALID_VOLTRANGE = (27),
+ SD_ADDR_OUT_OF_RANGE = (28),
+ SD_SWITCH_ERROR = (29),
+ SD_SDIO_DISABLED = (30),
+ SD_SDIO_FUNCTION_BUSY = (31),
+ SD_SDIO_FUNCTION_FAILED = (32),
+ SD_SDIO_UNKNOWN_FUNCTION = (33),
+
+/**
+ * @brief Standard error defines
+ */
+ SD_INTERNAL_ERROR,
+ SD_NOT_CONFIGURED,
+ SD_REQUEST_PENDING,
+ SD_REQUEST_NOT_APPLICABLE,
+ SD_INVALID_PARAMETER,
+ SD_UNSUPPORTED_FEATURE,
+ SD_UNSUPPORTED_HW,
+ SD_ERROR,
+ SD_OK = 0
+} SDCARD_Result;
+
+/**
+ * @brief SDIO Transfer state
+ */
+typedef enum
+{
+ SD_TRANSFER_OK = 0,
+ SD_TRANSFER_BUSY = 1,
+ SD_TRANSFER_ERROR
+} SDTransferState;
+
+/**
+ * @brief SD Card States
+ */
+typedef enum
+{
+ SD_CARD_READY = ((uint32_t)0x00000001),
+ SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002),
+ SD_CARD_STANDBY = ((uint32_t)0x00000003),
+ SD_CARD_TRANSFER = ((uint32_t)0x00000004),
+ SD_CARD_SENDING = ((uint32_t)0x00000005),
+ SD_CARD_RECEIVING = ((uint32_t)0x00000006),
+ SD_CARD_PROGRAMMING = ((uint32_t)0x00000007),
+ SD_CARD_DISCONNECTED = ((uint32_t)0x00000008),
+ SD_CARD_ERROR = ((uint32_t)0x000000FF)
+}SDCardState;
+
+
+/**
+ * @brief Card Specific Data: CSD Register
+ */
+typedef struct
+{
+ uint8_t CSDStruct; /*!< CSD structure */
+ uint8_t SysSpecVersion; /*!< System specification version */
+ uint8_t Reserved1; /*!< Reserved */
+ uint8_t TAAC; /*!< Data read access-time 1 */
+ uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */
+ uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ uint16_t CardComdClasses; /*!< Card command classes */
+ uint8_t RdBlockLen; /*!< Max. read data block length */
+ uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ uint8_t DSRImpl; /*!< DSR implemented */
+ uint8_t Reserved2; /*!< Reserved */
+ uint32_t DeviceSize; /*!< Device Size */
+ uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ uint8_t EraseGrSize; /*!< Erase group size */
+ uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ uint8_t WrProtectGrSize; /*!< Write protect group size */
+ uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ uint8_t WrSpeedFact; /*!< Write speed factor */
+ uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ uint8_t Reserved3; /*!< Reserded */
+ uint8_t ContentProtectAppli; /*!< Content protection application */
+ uint8_t FileFormatGrouop; /*!< File format group */
+ uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ uint8_t PermWrProtect; /*!< Permanent write protection */
+ uint8_t TempWrProtect; /*!< Temporary write protection */
+ uint8_t FileFormat; /*!< File Format */
+ uint8_t ECC; /*!< ECC code */
+ uint8_t CSD_CRC; /*!< CSD CRC */
+ uint8_t Reserved4; /*!< always 1*/
+} SD_CSD;
+
+/**
+ * @brief Card Identification Data: CID Register
+ */
+typedef struct
+{
+ uint8_t ManufacturerID; /*!< ManufacturerID */
+ uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ uint32_t ProdName1; /*!< Product Name part1 */
+ uint8_t ProdName2; /*!< Product Name part2*/
+ uint8_t ProdRev; /*!< Product Revision */
+ uint32_t ProdSN; /*!< Product Serial Number */
+ uint8_t Reserved1; /*!< Reserved1 */
+ uint16_t ManufactDate; /*!< Manufacturing Date */
+ uint8_t CID_CRC; /*!< CID CRC */
+ uint8_t Reserved2; /*!< always 1 */
+} SD_CID;
+
+/**
+* @brief SD Card Status
+*/
+typedef struct
+{
+ uint8_t DAT_BUS_WIDTH;
+ uint8_t SECURED_MODE;
+ uint16_t SD_CARD_TYPE;
+ uint32_t SIZE_OF_PROTECTED_AREA;
+ uint8_t SPEED_CLASS;
+ uint8_t PERFORMANCE_MOVE;
+ uint8_t AU_SIZE;
+ uint16_t ERASE_SIZE;
+ uint8_t ERASE_TIMEOUT;
+ uint8_t ERASE_OFFSET;
+} SD_CardStatus;
+
+/**
+* @brief SD Card information
+*/
+typedef struct
+{
+ SD_CSD SD_csd;
+ SD_CID SD_cid;
+ uint64_t CardCapacity; /*!< Card Capacity */
+ uint32_t CardBlockSize; /*!< Card Block Size */
+ uint16_t RCA;
+ uint8_t CardType;
+} SD_CardInfo;
+
+/**
+* @brief SDIO Commands Index
+*/
+#define SD_CMD_GO_IDLE_STATE ((uint8_t)0)
+#define SD_CMD_SEND_OP_COND ((uint8_t)1)
+#define SD_CMD_ALL_SEND_CID ((uint8_t)2)
+#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
+#define SD_CMD_SET_DSR ((uint8_t)4)
+#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5)
+#define SD_CMD_HS_SWITCH ((uint8_t)6)
+#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
+#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8)
+#define SD_CMD_SEND_CSD ((uint8_t)9)
+#define SD_CMD_SEND_CID ((uint8_t)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */
+#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
+#define SD_CMD_SEND_STATUS ((uint8_t)13)
+#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15)
+#define SD_CMD_SET_BLOCKLEN ((uint8_t)16)
+#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
+#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
+#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */
+#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */
+#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
+#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
+#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */
+#define SD_CMD_PROG_CSD ((uint8_t)27)
+#define SD_CMD_SET_WRITE_PROT ((uint8_t)28)
+#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29)
+#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30)
+#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write block to be erased. (For SD card only) */
+#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the continuous range to be erased. (For SD card only) */
+#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. (For MMC card only spec 3.31) */
+#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the continuous range to be erased. (For MMC card only spec 3.31) */
+#define SD_CMD_ERASE ((uint8_t)38)
+#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */
+#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */
+#define SD_CMD_LOCK_UNLOCK ((uint8_t)42)
+#define SD_CMD_APP_CMD ((uint8_t)55)
+#define SD_CMD_GEN_CMD ((uint8_t)56)
+#define SD_CMD_NO_CMD ((uint8_t)64)
+
+/**
+* @brief Following commands are SD Card Specific commands.
+* SDIO_APP_CMD should be sent before sending these commands.
+*/
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */
+#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */
+#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */
+#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */
+#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */
+
+/**
+* @brief Following commands are SD Card Specific security commands.
+* SDIO_APP_CMD should be sent before sending these commands.
+*/
+#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */
+
+/**
+* @brief SD detection on its memory slot
+*/
+#define SD_PRESENT ((uint8_t)0x01)
+#define SD_NOT_PRESENT ((uint8_t)0x00)
+
+/**
+* @brief Supported SD Memory Cards
+*/
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
+#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
+
+#define SDCARD_INIT_FREQ (uint32_t)400000
+#define GET_INIT_DIVIDER(input_freq) (uint8_t)((input_freq / SDCARD_INIT_FREQ) - 2)
+#define GET_TRANSFER_DIVIDER(input_freq, freq) (uint8_t)((input_freq / freq) - 2)
+
+BEGIN_DECLS
+
+SDCARD_Result sdcard_init(uint32_t apb_freq, uint32_t sdcard_freq);
+SDCARD_Result sdcard_power_on(void);
+SDCARD_Result sdcard_power_off(void);
+SDCARD_Result sdcard_cards_init(void);
+SDCARD_Result sdcard_get_card_info(SD_CardInfo *cardinfo);
+SDCARD_Result sdcard_select_deselect(uint64_t addr);
+SDCARD_Result sdcard_enable_wide_bus_operation(SDIO_WideBusMode mode);
+SDCARD_Result sdcard_read_block(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize);
+SDCARD_Result sdcard_write_block(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize);
+uint8_t sdcard_detect(void);
+SDCARD_Result sdcard_get_card_status(SD_CardStatus *cardstatus);
+SDCARD_Result sdcard_send_status(uint32_t *psdstatus);
+SDCARD_Result sdcard_erase(uint64_t startaddr, uint64_t endaddr);
+SDTransferState sdcard_get_status(void);
+// SDCARD_Result sdcard_wait_read_operation(void);
+// SDCARD_Result sdcard_wait_write_operation(void);
+SDCardState sdcard_get_state(void);
+
+//SDCARD_Result sdcard_read_multi_blocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+// SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+// SDTransferState SD_GetTransferState(void);
+// SD_Error SD_StopTransfer(void);
+// SD_Error SD_SendStatus(uint32_t *pcardstatus);
+// SD_Error SD_ProcessIRQSrc(void);
+// void SD_ProcessDMAIRQ(void);
+// SD_Error SD_HighSpeed(void);
+
+END_DECLS
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/common/crypto_common_f24.h b/include/libopencm3/stm32/common/crypto_common_f24.h
index eb885c8f..5c96bd58 100644
--- a/include/libopencm3/stm32/common/crypto_common_f24.h
+++ b/include/libopencm3/stm32/common/crypto_common_f24.h
@@ -138,11 +138,12 @@ specific memorymap.h header before including this header file.*/
#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C)
/* CRYP Key registers (CRYP_KxLR) x=0..3 */
-#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8)
+#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 4)
+#define CRYP_KR_COUNT 8
/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */
-#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8)
-
+#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 4)
+#define CRYP_IVR_COUNT 4
/* --- CRYP_CR values ------------------------------------------------------ */
/* ALGODIR: Algorithm direction */
@@ -150,7 +151,7 @@ specific memorymap.h header before including this header file.*/
/* ALGOMODE: Algorithm mode */
#define CRYP_CR_ALGOMODE_SHIFT 3
-#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT)
+#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT)
@@ -162,7 +163,7 @@ specific memorymap.h header before including this header file.*/
/* DATATYPE: Data type selection */
#define CRYP_CR_DATATYPE_SHIFT 6
-#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT)
+#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT)
@@ -261,6 +262,12 @@ enum crypto_keysize {
CRYPTO_KEY_192BIT,
CRYPTO_KEY_256BIT,
};
+enum key_offset
+{
+ KEY_128BIT_OFFSET = 4,
+ KEY_192BIT_OFFSET = 2,
+ KEY_256BIT_OFFSET = 0,
+};
enum crypto_datatype {
CRYPTO_DATA_32BIT = 0,
@@ -271,8 +278,8 @@ enum crypto_datatype {
BEGIN_DECLS
void crypto_wait_busy(void);
-void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]);
-void crypto_set_iv(uint64_t iv[]);
+void crypto_set_key(enum crypto_keysize keysize, uint8_t *key);
+void crypto_set_iv(uint8_t *iv);
void crypto_set_datatype(enum crypto_datatype datatype);
void crypto_set_algorithm(enum crypto_mode mode);
void crypto_start(void);
diff --git a/include/libopencm3/stm32/common/sdio_common_all.h b/include/libopencm3/stm32/common/sdio_common_all.h
new file mode 100644
index 00000000..9e013f92
--- /dev/null
+++ b/include/libopencm3/stm32/common/sdio_common_all.h
@@ -0,0 +1,37 @@
+/** @defgroup sdio_defines SDIO Defines
+ *
+ * @ingroup STM32_defines
+ *
+ * @brief Defined Constants, Types n Functions for the STM32 SDIO
+ *
+ * @version 1.0.0
+ *
+ * @date 18 April 2017
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SDIO_COMMON_ALL_H
+#define SDIO_COMMON_ALL_H
+
+#include "libopencm3/stm32/sdio.h"
+#include "libopencm3/cm3/common.h"
+
+
diff --git a/include/libopencm3/stm32/common/timer_common_all.h b/include/libopencm3/stm32/common/timer_common_all.h
index c3b8c048..4dbfcc4f 100644
--- a/include/libopencm3/stm32/common/timer_common_all.h
+++ b/include/libopencm3/stm32/common/timer_common_all.h
@@ -760,8 +760,8 @@ depending on the level of the complementary input. */
/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
* TIMx_CCER). */
#define TIM_CCMR1_CC1S_OUT (0x0 << 0)
-#define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0)
-#define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0)
+#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0)
+#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0)
#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)
#define TIM_CCMR1_CC1S_MASK (0x3 << 0)
diff --git a/include/libopencm3/stm32/f2/memorymap.h b/include/libopencm3/stm32/f2/memorymap.h
index 4f47a32f..180327f4 100644
--- a/include/libopencm3/stm32/f2/memorymap.h
+++ b/include/libopencm3/stm32/f2/memorymap.h
@@ -75,8 +75,9 @@
#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100)
+#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)
+#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)
/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)
/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h
index 923ac81e..f0c13535 100644
--- a/include/libopencm3/stm32/f2/rcc.h
+++ b/include/libopencm3/stm32/f2/rcc.h
@@ -498,6 +498,9 @@
#define RCC_BDCR_BDRST (1 << 16)
#define RCC_BDCR_RTCEN (1 << 15)
/* RCC_BDCR[9:8]: RTCSEL */
+#define RCC_BDCR_RTCSEL_0 (1 << 8)
+#define RCC_BDCR_RTCSEL_1 (1 << 9)
+
#define RCC_BDCR_LSEBYP (1 << 2)
#define RCC_BDCR_LSERDY (1 << 1)
#define RCC_BDCR_LSEON (1 << 0)
diff --git a/include/libopencm3/stm32/sdio.h b/include/libopencm3/stm32/sdio.h
index 4b7b945f..220546a1 100644
--- a/include/libopencm3/stm32/sdio.h
+++ b/include/libopencm3/stm32/sdio.h
@@ -436,10 +436,209 @@
#define SDIO_FIFOCNT_FIFOCOUNT_MASK 0xFFFFFF
-/* --- Function prototypes ------------------------------------------------- */
+/* From here Thirdpin part is started */
+/* --- SDIO registers ------------------------------------------------------ */
+#define SDIO_POWER MMIO32(SDIO_BASE + 0x00) /* SDIO power control register (SDIO_POWER) */
+#define SDIO_CLKCR MMIO32(SDIO_BASE + 0x04) /* SDIO clock control register (SDIO_CLKCR) */
+#define SDIO_ARG MMIO32(SDIO_BASE + 0x08) /* SDIO argument register (SDIO_ARG) */
+#define SDIO_CMD MMIO32(SDIO_BASE + 0x0C) /* SDIO command register (SDIO_CMD) */
+#define SDIO_RESPCMD MMIO32(SDIO_BASE + 0x10) /* SDIO command response register (SDIO_RESPCMD) */
+#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x14) /* SDIO response 1..4 register (SDIO_RESPx) */
+#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x18)
+#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x1C)
+#define SDIO_RESP4 MMIO32(SDIO_BASE + 0x20)
+#define SDIO_DTIMER MMIO32(SDIO_BASE + 0x24) /* SDIO data timer register (SDIO_DTIMER) */
+#define SDIO_DLEN MMIO32(SDIO_BASE + 0x28) /* SDIO data length register (SDIO_DLEN) */
+#define SDIO_DCTRL MMIO32(SDIO_BASE + 0x2C) /* SDIO data control register (SDIO_DCTRL) */
+#define SDIO_DCOUNT MMIO32(SDIO_BASE + 0x30) /* SDIO data counter register (SDIO_DCOUNT) */
+#define SDIO_STA MMIO32(SDIO_BASE + 0x34) /* SDIO status register (SDIO_STA) */
+#define SDIO_ICR MMIO32(SDIO_BASE + 0x38) /* SDIO interrupt clear register (SDIO_ICR) */
+#define SDIO_MASK MMIO32(SDIO_BASE + 0x3C) /* SDIO mask register (SDIO_MASK) */
+#define SDIO_FIFOCNT MMIO32(SDIO_BASE + 0x48) /* SDIO FIFO counter register (SDIO_FIFOCNT) */
+#define SDIO_FIFO MMIO32(SDIO_BASE + 0x80) /* SDIO data FIFO register (SDIO_FIFO) */
+
+/* --- SDIO_POWER values -------------------------------------------------- */
+#define SDIO_CLKCR_CLKDIV_MSK (uint32_t)(0xFF << 0)
+#define SDIO_CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+/* --- SDIO_CMD values ---------------------------------------------------- */
+#define SDIO_CMD_WAITRESP_MSK (uint32_t)(0x3 << SDIO_CMD_WAITRESP_SHIFT)
+#define SDIO_CMD_CMDINDEX_MSK (uint32_t)(0x3F << 0)
+#define SDIO_CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
-/* TODO */
+/* --- SDIO_RESPCMD values ------------------------------------------------ */
+#define SDIO_RESPCMD_MSK (uint32_t)(0x3F << 0)
+
+/* --- SDIO_DLEN values --------------------------------------------------- */
+#define SDIO_DLEN_MSK (uint32_t)0x1FFFFFF
+
+/* --- SDIO_DCTRL values -------------------------------------------------- */
+#define SDIO_DCTRL_DBLOCKSIZE_MSK ((uint32_t)(0xF << SDIO_DCTRL_DBLOCKSIZE_SHIFT))
+#define SDIO_DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- Function prototypes ------------------------------------------------- */
+typedef enum
+{
+ SDIO_CK_RISING_EDGE,
+ SDIO_CK_FALLING_EDGE,
+}SDIO_CK_Polarity;
+
+typedef enum
+{
+ WIDE_BUS_1 = (uint32_t)(0x0 << SDIO_CLKCR_WIDBUS_SHIFT),
+ WIDE_BUS_4 = (uint32_t)(0x1 << SDIO_CLKCR_WIDBUS_SHIFT),
+ WIDE_BUS_8 = (uint32_t)(0x2 << SDIO_CLKCR_WIDBUS_SHIFT),
+}SDIO_WideBusMode;
+
+typedef enum
+{
+ WAIT_NO,
+ WAIT_IT,
+ WAIT_PEND,
+}SDIO_WaitInterrupt;
+
+typedef enum
+{
+ RESPONSE_NO = (uint32_t)(0x0 << SDIO_CMD_WAITRESP_SHIFT),
+ RESPONSE_SHORT = (uint32_t)(0x1 << SDIO_CMD_WAITRESP_SHIFT),
+ RESPONSE_LONG = (uint32_t)(0x3 << SDIO_CMD_WAITRESP_SHIFT),
+}SDIO_ResponseType;
+
+typedef enum
+{
+ CONTROLLER_TO_CARD,
+ CARD_TO_CONTROLLER,
+}SDIO_TransferDirection;
+
+typedef enum
+{
+ BLOCK_DATA_TRANSFER,
+ STREAM_DATA_TRANSFER,
+}SDIO_TransferMode;
+
+typedef enum
+{
+ BLOCK_LENGTH_1_B = (uint32_t)(0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_2_B = (uint32_t)(0x1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_4_B = (uint32_t)(0x2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_8_B = (uint32_t)(0x3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_16_B = (uint32_t)(0x4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_32_B = (uint32_t)(0x5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_64_B = (uint32_t)(0x6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_128_B = (uint32_t)(0x7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_256_B = (uint32_t)(0x8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_512_B = (uint32_t)(0x9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_1024_B = (uint32_t)(0xA << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_2048_B = (uint32_t)(0xB << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_4096_B = (uint32_t)(0xC << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_8192_B = (uint32_t)(0xD << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+ BLOCK_LENGTH_16384_B = (uint32_t)(0xE << SDIO_DCTRL_DBLOCKSIZE_SHIFT),
+}SDIO_BlockSize;
+
+typedef enum
+{
+ SDIO_CEATAEND = (uint32_t)(1 << 23), //CE-ATA command completion signal received for CMD61
+ SDIO_SDIOIT = (uint32_t)(1 << 22), //SD I/O received
+ SDIO_RXDAVL = (uint32_t)(1 << 21), //Data available in receive FIFO
+ SDIO_TXDAVL = (uint32_t)(1 << 20), //Data available in transmit FIFO
+ SDIO_RXFIFOE = (uint32_t)(1 << 19), //Receive FIFO empty
+ SDIO_TXFIFOE = (uint32_t)(1 << 18), //Transmit FIFO empty
+ SDIO_RXFIFOF = (uint32_t)(1 << 17), //Receive FIFO full
+ SDIO_TXFIFOF = (uint32_t)(1 << 16), //Transmit FIFO full
+ SDIO_RXFIFOHF = (uint32_t)(1 << 15), //Receive FIFO Half Full
+ SDIO_TXFIFOHE = (uint32_t)(1 << 14), //Transmit FIFO Half Empty
+ SDIO_RXACT = (uint32_t)(1 << 13), //Data receive in progress
+ SDIO_TXACT = (uint32_t)(1 << 12), //Data transmit in progress
+ SDIO_CMDACT = (uint32_t)(1 << 11), //Command transfer in progress
+ SDIO_DBCKEND = (uint32_t)(1 << 10), //Data block sent/received (CRC check passed)
+ SDIO_STBITERR = (uint32_t)(1 << 9), //Start bit not detected on all data signals in wide bus mode
+ SDIO_DATAEND = (uint32_t)(1 << 8), //Data end (data counter, SDIDCOUNT, is zero)
+ SDIO_CMDSENT = (uint32_t)(1 << 7), //Command sent (no response required)
+ SDIO_CMDREND = (uint32_t)(1 << 6), //Command response received (CRC check passed)
+ SDIO_RXOVERR = (uint32_t)(1 << 5), //Received FIFO overrun error
+ SDIO_TXUNDERR = (uint32_t)(1 << 4), //Transmit FIFO underrun error
+ SDIO_DTIMEOUT = (uint32_t)(1 << 3), //Data timeout
+ SDIO_CTIMEOUT = (uint32_t)(1 << 2), //Command response timeout
+ SDIO_DCRCFAIL = (uint32_t)(1 << 1), //Data block sent/received (CRC check failed)
+ SDIO_CCRCFAIL = (uint32_t)(1 << 0), //Command response received (CRC check failed)
+}SDIO_Flag;
+
+typedef enum
+{
+ READ_WAIT_DATA2,
+ READ_WAIT_CLK,
+}SDIO_ReadWaitMode;
+
+typedef struct
+{
+ SDIO_CK_Polarity polarity;
+ bool bypass;
+ bool power_save;
+ SDIO_WideBusMode bus_wide;
+ bool flow_control;
+ uint8_t clock_divider;
+} SDIO_config;
+
+typedef struct
+{
+ uint8_t index;
+ uint32_t arg;
+ SDIO_ResponseType response;
+ SDIO_WaitInterrupt wait;
+ bool enable_CPSM;
+} SDIO_command;
+
+typedef struct
+{
+ uint32_t period;
+ uint32_t length;
+ SDIO_BlockSize size;
+ SDIO_TransferDirection direction;
+ SDIO_TransferMode mode;
+ bool enable;
+} SDIO_data_config;
+
+/* --- Function prototypes -------------------------------------------------------------------------- */
+BEGIN_DECLS
+void sdio_deinit(void);
+void sdio_config(SDIO_config *config);
+void sdio_ck_enable(void);
+void sdio_ck_disable(void);
+void sdio_enable(void);
+void sdio_disable(void);
+void sdio_send_command(SDIO_command *cmd);
+uint8_t sdio_get_cmd_response(void);
+uint32_t sdio_get_card_status_1(void);
+uint32_t sdio_get_card_status_2(void);
+uint32_t sdio_get_card_status_3(void);
+uint32_t sdio_get_card_status_4(void);
+void sdio_data_config(SDIO_data_config *config);
+uint32_t sdio_get_data_counter(void);
+uint32_t sdio_read_fifo_data(void);
+void sdio_write_fifo_data(uint32_t data);
+uint32_t sdio_get_fifo_counter(void);
+void sdio_read_wait_start_enable(void);
+void sdio_read_wait_start_disable(void);
+void sdio_read_wait_stop_enable(void);
+void sdio_read_wait_stop_disable(void);
+void sdio_set_read_wait_mode(SDIO_ReadWaitMode mode);
+void sdio_operation_enable(void);
+void sdio_operation_disable(void);
+void sdio_suspend_cmd_enable(void);
+void sdio_suspend_cmd_disable(void);
+void sdio_completion_cmd_enable(void);
+void sdio_completion_cmd_disable(void);
+void sdio_CEATA_interrupt_enable(void);
+void sdio_CEATA_interrupt_disable(void);
+void sdio_CEATA_cmd_enable(void);
+void sdio_CEATA_cmd_disable(void);
+void sdio_enable_dma(void);
+void sdio_disable_dma(void);
+void sdio_enable_interrupt(uint32_t interrupt);
+void sdio_disable_interrupt(uint32_t interrupt);
+bool sdio_get_flag_status(uint32_t flag);
+void sdio_clear_flag_status(uint32_t flag);
+END_DECLS
#endif
diff --git a/include/libopencm3/usb/dwc/otg_common.h b/include/libopencm3/usb/dwc/otg_common.h
index 8a703713..e85184c7 100644
--- a/include/libopencm3/usb/dwc/otg_common.h
+++ b/include/libopencm3/usb/dwc/otg_common.h
@@ -248,7 +248,9 @@
#define OTG_DCTL_RWUSIG (1 << 0)
/* OTG device configuration register (OTG_DCFG) */
-#define OTG_DCFG_DSPD 0x0003
+#define OTG_DCFG_DSPD_MASK (0b11 << 0)
+#define OTG_DCFG_DSPD_FS_INT 0x0003
+#define OTG_DCFG_DSPD OTG_DCFG_DSPD_FS_INT
#define OTG_DCFG_NZLSOHSK 0x0004
#define OTG_DCFG_DAD 0x07F0
#define OTG_DCFG_PFIVL 0x1800
diff --git a/include/libopencm3/usb/dwc/otg_hs.h b/include/libopencm3/usb/dwc/otg_hs.h
index 7b5124cd..b85d7c61 100644
--- a/include/libopencm3/usb/dwc/otg_hs.h
+++ b/include/libopencm3/usb/dwc/otg_hs.h
@@ -141,7 +141,7 @@
#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5)
#define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4)
#define OTG_DIEPEACHMSK1_TOM (1 << 3)
-/* Bit 2 - Reserved */
+/* Bit 2 - Reserved */
#define OTG_DIEPEACHMSK1_EPDM (1 << 1)
#define OTG_DIEPEACHMSK1_XFRCM (1 << 0)
@@ -170,4 +170,29 @@
#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7)
#define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0)
+/* OTG USB configuration register (OTG_GUSBCFG) */
+#define OTG_GUSBCFG_ULPIIPD (1 << 25)
+#define OTG_GUSBCFG_PTCI (1 << 24)
+#define OTG_GUSBCFG_PCCI (1 << 23)
+#define OTG_GUSBCFG_TSDPS (1 << 22)
+#define OTG_GUSBCFG_ULPIEVBUSI (1 << 21)
+#define OTG_GUSBCFG_ULPIEVBUSD (1 << 20)
+#define OTG_GUSBCFG_ULPICSM (1 << 19)
+#define OTG_GUSBCFG_ULPIAR (1 << 18)
+#define OTG_GUSBCFG_ULPIFSLS (1 << 17)
+#define OTG_GUSBCFG_PHYLPCS (1 << 15)
+
+/* OTG device configuration register (OTG_DCFG) */
+#define OTG_DCFG_DSPD_HS_EXT (0x0 << 0)
+#define OTG_DCFG_DSPD_FS_EXT (0x1 << 0)
+
+/* OTG AHB configuration register (OTG_GAHBCFG) */
+#define OTG_GAHBCFG_HBSTLEN_MASK (0xf << 1)
+#define OTG_GAHBCFG_HBSTLEN_SINGLE (0b0000 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR (0b0001 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR4 (0b0011 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR8 (0b0101 << 1)
+#define OTG_GAHBCFG_HBSTLEN_INCR16 (0b0111 << 1)
+#define OTG_GAHBCFG_DMAEN (1 << 5)
+
#endif
diff --git a/include/libopencm3/usb/hid.h b/include/libopencm3/usb/hid.h
index 87f4924d..17a64b54 100644
--- a/include/libopencm3/usb/hid.h
+++ b/include/libopencm3/usb/hid.h
@@ -53,6 +53,8 @@ struct usb_hid_descriptor {
uint8_t bNumDescriptors;
} __attribute__((packed));
+#define USB_DT_HID_SIZE sizeof(usb_hid_descriptor)
+
#endif
/**@}*/
diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h
index d2451010..1f508e85 100644
--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@@ -55,9 +55,13 @@ typedef struct _usbd_device usbd_device;
extern const usbd_driver st_usbfs_v1_usb_driver;
extern const usbd_driver stm32f107_usb_driver;
extern const usbd_driver stm32f207_usb_driver;
+extern const usbd_driver stm32_dwc_usb_driver;
+extern const usbd_driver stm32_dwc_usb_driver_ulpi;
extern const usbd_driver st_usbfs_v2_usb_driver;
#define otgfs_usb_driver stm32f107_usb_driver
#define otghs_usb_driver stm32f207_usb_driver
+#define otghs_usb_driver_dwc stm32_dwc_usb_driver
+#define otghs_usb_driver_dwc_ulpi stm32_dwc_usb_driver_ulpi
extern const usbd_driver efm32lg_usb_driver;
extern const usbd_driver efm32hg_usb_driver;
extern const usbd_driver lm4f_usb_driver;
diff --git a/include/libopencm3/usb/usbstd.h b/include/libopencm3/usb/usbstd.h
index 33bdd8b5..d2313c33 100644
--- a/include/libopencm3/usb/usbstd.h
+++ b/include/libopencm3/usb/usbstd.h
@@ -202,8 +202,8 @@ struct usb_interface_descriptor {
uint8_t iInterface;
/* Descriptor ends here. The following are used internally: */
- const struct usb_endpoint_descriptor *endpoint;
- const void *extra;
+ struct usb_endpoint_descriptor *endpoint;
+ void *extra;
int extralen;
} __attribute__((packed));
#define USB_DT_INTERFACE_SIZE 9
@@ -218,7 +218,7 @@ struct usb_endpoint_descriptor {
uint8_t bInterval;
/* Descriptor ends here. The following are used internally: */
- const void *extra;
+ void *extra;
int extralen;
} __attribute__((packed));
#define USB_DT_ENDPOINT_SIZE 7
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 12:08:19 +0300