From f344eac0b9bfbfc21dc4a4caf818c952e2957141 Mon Sep 17 00:00:00 2001 From: Ilya Stolyarov Date: Thu, 4 Jul 2019 18:58:15 +0300 Subject: FEAT: [ulpi] Registers and initialization --- include/libopencm3/usb/dwc/otg_common.h | 4 +- include/libopencm3/usb/dwc/otg_hs.h | 17 +++- include/libopencm3/usb/usbd.h | 2 + lib/stm32/f2/Makefile | 2 +- lib/stm32/f4/Makefile | 2 +- lib/usb/usb_dwc.c | 156 ++++++++++++++++++++++++++++++++ 6 files changed, 179 insertions(+), 4 deletions(-) create mode 100644 lib/usb/usb_dwc.c diff --git a/include/libopencm3/usb/dwc/otg_common.h b/include/libopencm3/usb/dwc/otg_common.h index 8a703713..366ed14d 100644 --- a/include/libopencm3/usb/dwc/otg_common.h +++ b/include/libopencm3/usb/dwc/otg_common.h @@ -248,7 +248,9 @@ #define OTG_DCTL_RWUSIG (1 << 0) /* OTG device configuration register (OTG_DCFG) */ -#define OTG_DCFG_DSPD 0x0003 +#define OTG_DCFG_DSPD_MASK (0x3 << 0) +#define OTG_DCFG_DSPD_FS_INT 0x0003 +#define OTG_DCFG_DSPD OTG_DCFG_DSPD_FS_INT #define OTG_DCFG_NZLSOHSK 0x0004 #define OTG_DCFG_DAD 0x07F0 #define OTG_DCFG_PFIVL 0x1800 diff --git a/include/libopencm3/usb/dwc/otg_hs.h b/include/libopencm3/usb/dwc/otg_hs.h index 7b5124cd..99b24a9b 100644 --- a/include/libopencm3/usb/dwc/otg_hs.h +++ b/include/libopencm3/usb/dwc/otg_hs.h @@ -141,7 +141,7 @@ #define OTG_DIEPEACHMSK1_INEPNMM (1 << 5) #define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4) #define OTG_DIEPEACHMSK1_TOM (1 << 3) -/* Bit 2 - Reserved */ +/* Bit 2 - Reserved */ #define OTG_DIEPEACHMSK1_EPDM (1 << 1) #define OTG_DIEPEACHMSK1_XFRCM (1 << 0) @@ -170,4 +170,19 @@ #define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7) #define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0) +/* OTG USB configuration register (OTG_GUSBCFG) */ +#define OTG_GUSBCFG_ULPIIPD (1 << 25) +#define OTG_GUSBCFG_PTCI (1 << 24) +#define OTG_GUSBCFG_PCCI (1 << 23) +#define OTG_GUSBCFG_TSDPS (1 << 22) +#define OTG_GUSBCFG_ULPIEVBUSI (1 << 21) +#define OTG_GUSBCFG_ULPIEVBUSD (1 << 20) +#define OTG_GUSBCFG_ULPICSM (1 << 19) +#define OTG_GUSBCFG_ULPIAR (1 << 18) +#define OTG_GUSBCFG_ULPIFSLS (1 << 17) +#define OTG_GUSBCFG_PHYLPCS (1 << 15) + +/* OTG device configuration register (OTG_DCFG) */ +#define OTG_DCFG_DSPD_FS_EXT (0x2 << 0) + #endif diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index b0ba701d..a213eeb4 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -55,9 +55,11 @@ typedef struct _usbd_device usbd_device; extern const usbd_driver st_usbfs_v1_usb_driver; extern const usbd_driver stm32f107_usb_driver; extern const usbd_driver stm32f207_usb_driver; +extern const usbd_driver stm32_dwc_usb_driver_ulpi; extern const usbd_driver st_usbfs_v2_usb_driver; #define otgfs_usb_driver stm32f107_usb_driver #define otghs_usb_driver stm32f207_usb_driver +#define otghs_usb_driver_ulpi stm32_dwc_usb_driver_ulpi extern const usbd_driver efm32lg_usb_driver; extern const usbd_driver efm32hg_usb_driver; extern const usbd_driver lm4f_usb_driver; diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 0d329513..4b143e58 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -50,7 +50,7 @@ OBJS += flash_common_idcache.o OBJS += rng_common_v1.o OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o -OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \ +OBJS += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \ usb_f107.o usb_f207.o usb_msc.o OBJS += sdio_common_all.o diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 566cd3d3..91ccf4b9 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -57,7 +57,7 @@ OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o OBJS += sdio_common_all.o -OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \ +OBJS += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \ usb_f107.o usb_f207.o usb_msc.o OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o fmc.o diff --git a/lib/usb/usb_dwc.c b/lib/usb/usb_dwc.c new file mode 100644 index 00000000..bb58baa7 --- /dev/null +++ b/lib/usb/usb_dwc.c @@ -0,0 +1,156 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include "usb_private.h" +#include "usb_dwc_common.h" + +/* Receive FIFO size in 32-bit words. */ +#define RX_FIFO_SIZE 512 + +static usbd_device *stm32_dwc_usbd_init(void); +static usbd_device *stm32_dwc_ulpi_usbd_init(void); + +static struct _usbd_device usbd_dev; + +const struct _usbd_driver stm32_dwc_usb_driver = { + .init = stm32_dwc_usbd_init, + .set_address = dwc_set_address, + .ep_setup = dwc_ep_setup, + .ep_reset = dwc_endpoints_reset, + .ep_stall_set = dwc_ep_stall_set, + .ep_stall_get = dwc_ep_stall_get, + .ep_nak_set = dwc_ep_nak_set, + .ep_write_packet = dwc_ep_write_packet, + .ep_read_packet = dwc_ep_read_packet, + .poll = dwc_poll, + .disconnect = dwc_disconnect, + .base_address = USB_OTG_HS_BASE, + .set_address_before_status = 1, + .rx_fifo_size = RX_FIFO_SIZE, +}; + +const struct _usbd_driver stm32_dwc_usb_driver_ulpi = { + .init = stm32_dwc_ulpi_usbd_init, + .set_address = dwc_set_address, + .ep_setup = dwc_ep_setup, + .ep_reset = dwc_endpoints_reset, + .ep_stall_set = dwc_ep_stall_set, + .ep_stall_get = dwc_ep_stall_get, + .ep_nak_set = dwc_ep_nak_set, + .ep_write_packet = dwc_ep_write_packet, + .ep_read_packet = dwc_ep_read_packet, + .poll = dwc_poll, + .disconnect = dwc_disconnect, + .base_address = USB_OTG_HS_BASE, + .set_address_before_status = 1, + .rx_fifo_size = RX_FIFO_SIZE, +}; + +/** Initialize the USB device controller hardware of the STM32. */ +static usbd_device *stm32_dwc_usbd_init(void) +{ + rcc_periph_clock_enable(RCC_OTGHS); + OTG_HS_GINTSTS = OTG_GINTSTS_MMIS; + + OTG_HS_GUSBCFG |= OTG_GUSBCFG_PHYSEL; + /* Enable VBUS sensing in device mode and power down the PHY. */ + OTG_HS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN; + + /* Wait for AHB idle. */ + while (!(OTG_HS_GRSTCTL & OTG_GRSTCTL_AHBIDL)); + /* Do core soft reset. */ + OTG_HS_GRSTCTL |= OTG_GRSTCTL_CSRST; + while (OTG_HS_GRSTCTL & OTG_GRSTCTL_CSRST); + + /* Force peripheral only mode. */ + OTG_HS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK; + + /* Full speed internal embedded PHY device. */ + OTG_HS_DCFG |= OTG_DCFG_DSPD; + + /* Restart the PHY clock. */ + OTG_HS_PCGCCTL = 0; + + OTG_HS_GRXFSIZ = stm32_dwc_usb_driver.rx_fifo_size; + usbd_dev.fifo_mem_top = stm32_dwc_usb_driver.rx_fifo_size; + + /* Unmask interrupts for TX and RX. */ + OTG_HS_GAHBCFG |= OTG_GAHBCFG_GINT; + OTG_HS_GINTMSK = OTG_GINTMSK_ENUMDNEM | + OTG_GINTMSK_RXFLVLM | + OTG_GINTMSK_IEPINT | + OTG_GINTMSK_USBSUSPM | + OTG_GINTMSK_WUIM; + OTG_HS_DAINTMSK = 0xF; + OTG_HS_DIEPMSK = OTG_DIEPMSK_XFRCM; + + return &usbd_dev; +} + +/** Initialize the USB device controller hardware of the STM32. ULPI variant */ +static usbd_device *stm32_dwc_ulpi_usbd_init(void) +{ + rcc_periph_clock_enable(RCC_OTGHS); + OTG_HS_GINTSTS = OTG_GINTSTS_MMIS; + + /* Disable internal PHY */ + OTG_HS_GCCFG &= ~(OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + OTG_HS_GUSBCFG &= ~(OTG_GUSBCFG_TSDPS | OTG_GUSBCFG_ULPIFSLS | OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + OTG_HS_GUSBCFG &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI); + + /* Wait for AHB idle. */ + while (!(OTG_HS_GRSTCTL & OTG_GRSTCTL_AHBIDL)); + /* Do core soft reset. */ + OTG_HS_GRSTCTL |= OTG_GRSTCTL_CSRST; + while (OTG_HS_GRSTCTL & OTG_GRSTCTL_CSRST); + + /* Force peripheral only mode. */ + OTG_HS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK; + + /* Full speed external ULPI PHY device. */ + OTG_HS_DCFG |= OTG_DCFG_DSPD_FS_EXT; + + /* Restart the PHY clock. */ + OTG_HS_PCGCCTL = 0; + + OTG_HS_GRXFSIZ = stm32_dwc_usb_driver.rx_fifo_size; + usbd_dev.fifo_mem_top = stm32_dwc_usb_driver.rx_fifo_size; + + /* Unmask interrupts for TX and RX. */ + OTG_HS_GAHBCFG |= OTG_GAHBCFG_GINT; + OTG_HS_GINTMSK = OTG_GINTMSK_ENUMDNEM | + OTG_GINTMSK_RXFLVLM | + OTG_GINTMSK_IEPINT | + OTG_GINTMSK_USBSUSPM | + OTG_GINTMSK_WUIM; + OTG_HS_DAINTMSK = 0xF; + OTG_HS_DIEPMSK = OTG_DIEPMSK_XFRCM; + + return &usbd_dev; +} -- cgit v1.2.3