From e2b67d7264b30c02dd534202dd2ff82283e76762 Mon Sep 17 00:00:00 2001 From: Jacob Rodgers Date: Sat, 29 Sep 2018 07:55:16 -0700 Subject: Set PLL source in rcc_clock_setup_pll() for STM32L0 --- lib/stm32/l0/rcc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index a6e398e2..3048bef5 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -422,6 +422,7 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) /* Set up the PLL */ rcc_set_pll_multiplier(clock->pll_mul); rcc_set_pll_divider(clock->pll_div); + rcc_set_pll_source(clock->pll_source); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); -- cgit v1.2.3 From 4b16af6e2438db22e804aee57818be2b9d719dbd Mon Sep 17 00:00:00 2001 From: Filip Moc Date: Fri, 5 Oct 2018 23:30:41 +0000 Subject: stm32: iwdg: correct calculation for all ranges. The original calculations miscalculated ranges such as 512..639 or 1024..1151 or ... or 32768..32895 Reviewed-by: Karl Palsson --- lib/stm32/common/iwdg_common_all.c | 55 +++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 28 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/iwdg_common_all.c b/lib/stm32/common/iwdg_common_all.c index f2b1c1d8..44b3b9b3 100644 --- a/lib/stm32/common/iwdg_common_all.c +++ b/lib/stm32/common/iwdg_common_all.c @@ -70,45 +70,44 @@ loading a previous value. @param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset until a system reset is issued. */ - void iwdg_set_period_ms(uint32_t period) { - uint32_t count, prescale, reload, exponent; - - /* Set the count to represent ticks of the 32kHz LSI clock */ - count = (period << 5); - - /* Strip off the first 12 bits to get the prescale value required */ - prescale = (count >> 12); - if (prescale > 256) { - exponent = IWDG_PR_DIV256; reload = COUNT_MASK; - } else if (prescale > 128) { - exponent = IWDG_PR_DIV256; reload = (count >> 8); - } else if (prescale > 64) { - exponent = IWDG_PR_DIV128; reload = (count >> 7); - } else if (prescale > 32) { - exponent = IWDG_PR_DIV64; reload = (count >> 6); - } else if (prescale > 16) { - exponent = IWDG_PR_DIV32; reload = (count >> 5); - } else if (prescale > 8) { - exponent = IWDG_PR_DIV16; reload = (count >> 4); - } else if (prescale > 4) { - exponent = IWDG_PR_DIV8; reload = (count >> 3); - } else { - exponent = IWDG_PR_DIV4; reload = (count >> 2); - } + const int PRESCALER_MAX = 6; + uint8_t prescale = 0; - /* Avoid the undefined situation of a zero count */ + /* Set the count to represent ticks of 8kHz clock (the 32kHz LSI clock + * divided by 4 = lowest prescaler setting) + */ + uint32_t count = period << 3; + + /* Prevent underflow */ if (count == 0) { count = 1; } + /* Shift count while increasing prescaler as many times as needed to + * fit into IWDG_RLR + */ + while ((count - 1) >> COUNT_LENGTH) { + count >>= 1; + prescale++; + } + + /* IWDG_RLR actually holds count - 1 */ + count--; + + /* Clamp to max possible period */ + if (prescale > PRESCALER_MAX) { + count = COUNT_MASK; + prescale = PRESCALER_MAX; + } + while (iwdg_prescaler_busy()); IWDG_KR = IWDG_KR_UNLOCK; - IWDG_PR = exponent; + IWDG_PR = prescale; while (iwdg_reload_busy()); IWDG_KR = IWDG_KR_UNLOCK; - IWDG_RLR = (reload & COUNT_MASK); + IWDG_RLR = count & COUNT_MASK; } /*---------------------------------------------------------------------------*/ -- cgit v1.2.3 From bc7e454741b74680b87a77325e9cd29ea0f0d4a1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 20 Oct 2018 11:40:38 +0000 Subject: stm32f7: include common dma code Originally reported at https://github.com/libopencm3/libopencm3/pull/978 --- lib/stm32/f7/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 8b1bdef7..8a633178 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -42,8 +42,9 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = flash_common_all.o flash_common_f.o flash_common_f24.o flash.o -OBJS += desig.o +OBJS = desig.o +OBJS += dma_common_f24.o +OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += pwr.o rcc.o -- cgit v1.2.3 From f6517f7816206f9d4509a21242f330aa59360119 Mon Sep 17 00:00:00 2001 From: mfm Date: Thu, 31 May 2018 11:14:28 +0200 Subject: stm32: adc common v2: add circular dma mode Tested only on the F3 so far. --- lib/stm32/common/adc_common_v2.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'lib') diff --git a/lib/stm32/common/adc_common_v2.c b/lib/stm32/common/adc_common_v2.c index fb22d273..5ad85c6a 100644 --- a/lib/stm32/common/adc_common_v2.c +++ b/lib/stm32/common/adc_common_v2.c @@ -389,4 +389,24 @@ void adc_start_conversion_regular(uint32_t adc) ADC_CR(adc) |= ADC_CR_ADSTART; } +/** @brief Enable circular mode for DMA transfers + * + * For this to work it needs to be ebabled on the DMA side as well. + * + * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) + */ +void adc_enable_dma_circular_mode(uint32_t adc) +{ + ADC_CFGR1(adc) |= ADC_CFGR1_DMACFG; +} + +/** @brief Disable circular mode for DMA transfers + * + * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) + */ +void adc_disable_dma_circular_mode(uint32_t adc) +{ + ADC_CFGR1(adc) &= ~ADC_CFGR1_DMACFG; +} + /**@}*/ -- cgit v1.2.3 From 2619a4506c5818b752473fee26c37a00046d192e Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 23 Oct 2018 21:20:44 +0000 Subject: stm32f7: use spi v2 peripheral. F7 indeed has v2 peripheral, not the v1. Distinguishing figure is the 8/16bit fifo. --- lib/stm32/f7/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 8a633178..bbd1e400 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -50,7 +50,7 @@ OBJS += pwr.o rcc.o OBJS += rcc_common_all.o OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += spi_common_all.o spi_common_v2.o OBJS += timer_common_all.o OBJS += usart_common_all.o usart_common_v2.o -- cgit v1.2.3 From a63d0499dec1227b139a9d2c9d7e5c7ba3d8dd61 Mon Sep 17 00:00:00 2001 From: Dmitry Rezvanov Date: Sat, 6 Oct 2018 17:17:12 +0400 Subject: msp432/e4: Add GPIO support --- lib/msp432/e4/Makefile | 2 +- lib/msp432/e4/gpio.c | 448 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 449 insertions(+), 1 deletion(-) create mode 100644 lib/msp432/e4/gpio.c (limited to 'lib') diff --git a/lib/msp432/e4/Makefile b/lib/msp432/e4/Makefile index 61abb1ab..255af4cb 100644 --- a/lib/msp432/e4/Makefile +++ b/lib/msp432/e4/Makefile @@ -40,7 +40,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = systemcontrol.o +OBJS = systemcontrol.o gpio.o VPATH += ../:../../cm3:../common diff --git a/lib/msp432/e4/gpio.c b/lib/msp432/e4/gpio.c new file mode 100644 index 00000000..d3c9f048 --- /dev/null +++ b/lib/msp432/e4/gpio.c @@ -0,0 +1,448 @@ +/** @defgroup gpio_file General-Purpose I/O + * + * @ingroup MSP432E4xx + * + * @brief libopencm3 MSP432E4xx General Purpose Input/Outputs + * + * @version 1.0.0 + * + * @date 23 September 2018 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2013 Alexandru Gagniuc + * Copyright (C) 2018 Dmitry Rezvanov + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/** @brief General Purpose Input/Outputs Set Pin Mode + * + * Sets the Pin Direction, Analog/Digital Mode and Output Pin Pull, + * for a set of GPIO pins on a given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] mode Pin mode @ref gpio_mode + * - GPIO_MODE_OUTPUT -- Configure pin as output + * - GPIO_MODE_INPUT -- Configure pin as input + * - GPIO_MODE_ANALOG -- Configure pin as analog function + * @param[in] pull_up_down Pin pull up/down configuration @ref gpio_pull_up_down + * - GPIO_PUPD_NONE -- Do not pull the pin high or low + * - GPIO_PUPD_PULLUP -- Pull the pin high + * - GPIO_PUPD_PULLDOWN -- Pull the pin low + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be set, use bitwise OR '|' to separate them. + */ +void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, + enum gpio_pull_up_down pull_up_down, uint8_t gpios) +{ + GPIO_AFSEL(gpioport) &= ~gpios; + + switch (mode) { + case GPIO_MODE_OUTPUT: + GPIO_DIR(gpioport) |= gpios; + GPIO_DEN(gpioport) |= gpios; + GPIO_AMSEL(gpioport) &= ~gpios; + break; + case GPIO_MODE_INPUT: + GPIO_DIR(gpioport) &= ~gpios; + GPIO_DEN(gpioport) |= gpios; + GPIO_AMSEL(gpioport) &= ~gpios; + break; + case GPIO_MODE_ANALOG: + GPIO_AFSEL(gpioport) |= gpios; + GPIO_DEN(gpioport) &= ~gpios; + GPIO_AMSEL(gpioport) |= gpios; + break; + default: + /* Don't do anything */ + break; + } + + /* + * Setting a bit in the GPIO_PDR register clears the corresponding bit + * in the GPIO_PUR register, and vice-versa. + */ + switch (pull_up_down) { + case GPIO_PUPD_PULLUP: + GPIO_PDR(gpioport) &= ~gpios; + GPIO_PUR(gpioport) |= gpios; + break; + case GPIO_PUPD_PULLDOWN: + GPIO_PUR(gpioport) &= ~gpios; + GPIO_PDR(gpioport) |= gpios; + break; + case GPIO_PUPD_NONE: /* Fall through */ + default: + GPIO_PUR(gpioport) &= ~gpios; + GPIO_PDR(gpioport) &= ~gpios; + break; + } +} + +/** @brief General Purpose Input/Outputs Set Output Options + * + * When the pin is set to output mode, this sets the configuration + * (open drain/push pull), drive strength, speed and slew rate control, + * for a set of GPIO pins on a given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] otype Output driver configuration @ref gpio_output_type + * - GPIO_OTYPE_PP -- Configure pin driver as push-pull \n + * - GPIO_OTYPE_OD -- Configure pin driver as open drain + * @param[in] drive Pin drive strength @ref gpio_drive_strength + * - GPIO_DRIVE_2MA -- 2mA drive \n + * - GPIO_DRIVE_4MA -- 4mA drive \n + * - GPIO_DRIVE_6MA -- 4mA drive \n + * - GPIO_DRIVE_8MA -- 8mA drive \n + * - GPIO_DRIVE_10MA -- 10mA drive \n + * - GPIO_DRIVE_12MA -- 12mA drive + * @param[in] slewctl Pin slew rate control select @ref gpio_slew_ctl + * @note Available only for 8, 10 and 12-ma drive strength. + * - GPIO_SLEW_CTL_ENABLE -- Slew rate control enable + * - GPIO_SLEW_CTL_DISABLE -- Slew rate control disable + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be set, use bitwise OR '|' to separate them. + */ +void gpio_set_output_options(uint32_t gpioport, + enum gpio_output_type otype, + enum gpio_drive_strength drive, + enum gpio_slew_ctl slewctl, + uint8_t gpios) +{ + uint8_t i; + uint8_t pin_mask; + + if (otype == GPIO_OTYPE_OD) { + GPIO_ODR(gpioport) |= gpios; + } else { + GPIO_ODR(gpioport) &= ~gpios; + } + + GPIO_PP(gpioport) |= GPIO_PP_EDE; + + for (i = 0; i < 8; i++) { + pin_mask = (1 << i); + + if (!(gpios & pin_mask)) { + continue; + } + + GPIO_PC(gpioport) &= ~GPIO_PC_EDM_MASK(i); + GPIO_PC(gpioport) |= GPIO_PC_EDM(i, GPIO_PC_EDM_FULL_RANGE); + } + + GPIO_DR4R(gpioport) &= ~gpios; + GPIO_DR8R(gpioport) &= ~gpios; + GPIO_DR12R(gpioport) &= ~gpios; + + switch (drive) { + case GPIO_DRIVE_4MA: + GPIO_DR4R(gpioport) |= gpios; + break; + case GPIO_DRIVE_6MA: + GPIO_DR8R(gpioport) |= gpios; + break; + case GPIO_DRIVE_8MA: + GPIO_DR4R(gpioport) |= gpios; + GPIO_DR8R(gpioport) |= gpios; + break; + case GPIO_DRIVE_10MA: + GPIO_DR8R(gpioport) |= gpios; + GPIO_DR12R(gpioport) |= gpios; + break; + case GPIO_DRIVE_12MA: + GPIO_DR4R(gpioport) |= gpios; + GPIO_DR8R(gpioport) |= gpios; + GPIO_DR12R(gpioport) |= gpios; + break; + case GPIO_DRIVE_2MA: /* Fall through */ + default: + /* don't anything */ + break; + } + + if ((slewctl == GPIO_SLEW_CTL_ENABLE) && + ((drive == GPIO_DRIVE_8MA) || (drive == GPIO_DRIVE_10MA) || + (drive == GPIO_DRIVE_12MA))) { + GPIO_SLR(gpioport) |= gpios; + } else { + GPIO_SLR(gpioport) &= ~gpios; + } +} + +/** @brief General Purpose Input/Outputs Set Alternate Function Selection + * + * Mux the pin or group of pins to the given alternate function. Note that a + * number of pins may be set but only with a single AF number. + * + * Because AF0 is not used on the MSP432E4, + * passing GPIO_AF_DISABLE as the alt_func_num parameter will disable + * the alternate function of the given pins. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] alt_func_num Pin alternate function number or GPIO_AF_DISABLE to + * disable the alternate function multiplexing. + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be set, use bitwise OR '|' to separate them. + */ +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios) +{ + uint32_t pctl32; + uint8_t pin_mask; + uint8_t i; + + /* Did we mean to disable the alternate function? */ + if (alt_func_num == 0) { + GPIO_AFSEL(gpioport) &= ~gpios; + return; + } + + /* Enable the alternate function */ + GPIO_AFSEL(gpioport) |= gpios; + + /* Now take care of the actual multiplexing */ + pctl32 = GPIO_PCTL(gpioport); + for (i = 0; i < 8; i++) { + pin_mask = (1 << i); + + if (!(gpios & pin_mask)) { + continue; + } + + pctl32 &= ~GPIO_PCTL_MASK(i); + pctl32 |= GPIO_PCTL_AF(i, (alt_func_num & 0xf)); + } + + GPIO_PCTL(gpioport) = pctl32; +} + +/** @brief General Purpose Input/Outputs Configure Interrupt Trigger + * + * Sets the trigger level/edge, for a set of GPIO pins on a given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] trigger Trigger configuration @ref gpio_trigger + * - GPIO_TRIG_LVL_LOW -- Trigger on low level + * - GPIO_TRIG_LVL_HIGH -- Trigger on high level + * - GPIO_TRIG_EDGE_FALL -- Trigger on falling edges + * - GPIO_TRIG_EDGE_RISE -- Trigger on rising edges + * - GPIO_TRIG_EDGE_BOTH -- Trigger on all edges + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be configure, use bitwise OR '|' to separate them. + */ +void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, + uint8_t gpios) +{ + switch (trigger) { + case GPIO_TRIG_LVL_LOW: + GPIO_IS(gpioport) |= gpios; + GPIO_IEV(gpioport) &= ~gpios; + break; + case GPIO_TRIG_LVL_HIGH: + GPIO_IS(gpioport) |= gpios; + GPIO_IEV(gpioport) |= gpios; + break; + case GPIO_TRIG_EDGE_FALL: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) &= ~gpios; + GPIO_IEV(gpioport) &= ~gpios; + break; + case GPIO_TRIG_EDGE_RISE: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) &= ~gpios; + GPIO_IEV(gpioport) |= gpios; + break; + case GPIO_TRIG_EDGE_BOTH: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) |= gpios; + break; + default: + /* Don't do anything */ + break; + } +} + +/** @brief General Purpose Input/Outputs Set a Group of Pins Atomic + * + * Set one or more pins of the given GPIO port to 1 in an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be changed, use bitwise OR '|' to separate them. + */ +void gpio_set(uint32_t gpioport, uint8_t gpios) +{ + GPIO_DATA(gpioport)[gpios] = 0xFF; +} + +/** @brief General Purpose Input/Outputs Clear a Group of Pins Atomic + * + * Clear one or more pins of the given GPIO port to 0 in an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be changed, use bitwise OR '|' to separate them. + */ +void gpio_clear(uint32_t gpioport, uint8_t gpios) +{ + GPIO_DATA(gpioport)[gpios] = 0x0; +} + +/** @brief General Purpose Input/Outputs Read a Group of Pins + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be read, use bitwise OR '|' to separate them. + * + * @return Unsigned int8 value of the pin values. The bit position of the pin + value returned corresponds to the pin number. + */ +uint8_t gpio_get(uint32_t gpioport, uint8_t gpios) +{ + return (uint8_t)GPIO_DATA(gpioport)[gpios]; +} + +/** @brief General Purpose Input/Outputs Toggle a Group of Pins + * + * Toggle one or more pins of the given GPIO port. + * The non-toggled pins are not affected. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be changed, use bitwise OR '|' to separate them. + */ +void gpio_toggle(uint32_t gpioport, uint8_t gpios) +{ + /* The mask makes sure we only toggle the GPIOs we want to */ + GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL; +} + +/** @brief General Purpose Input/Outputs Read from a Port + * + * Read the current value of the given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * + * @return Unsigned int8. The value held in the specified GPIO port. + */ +uint8_t gpio_port_read(uint32_t gpioport) +{ + return (uint8_t)GPIO_DATA(gpioport)[GPIO_ALL]; +} + +/** @brief General Purpose Input/Outputs Write to a Port + * + * Write a value to the given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] data Unsigned int8. The value to be written to the GPIO port. + */ +void gpio_port_write(uint32_t gpioport, uint8_t data) +{ + GPIO_DATA(gpioport)[GPIO_ALL] = data; +} + +/** @brief General Purpose Input/Outputs Enable Interrupts on specified pins + * + * Enable interrupts on the specified GPIO pins. + * + * @note The NVIC must be enabled and properly configured for the interrupt + * to be routed to the CPU. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base) + * @param[in] gpios Pin identifiers @ref gpio_pin_id. + * Pins whose interrupts to enable. + * If multiple pins are to be enable interrupt, + * use bitwise OR '|' to separate them. + */ +void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios) +{ + GPIO_IM(gpioport) |= gpios; +} + +/** @brief General Purpose Input/Outputs Disable interrupts on specified pins + * + * Disable interrupts on the specified GPIO pins. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. + * Pins whose interrupts to disable. + * If multiple pins are to be disable interrupt, + * use bitwise OR '|' to separate them. + */ +void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios) +{ + GPIO_IM(gpioport) &= ~gpios; +} + +/** @brief General Purpose Input/Outputs Unlock The Commit Control + * + * Unlocks the commit control of the given pin or group of pins. If a pin is a + * JTAG/SWD or NMI, the pin may then be reconfigured as a GPIO pin. If the pin + * is not locked by default, this has no effect. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. + * If multiple pins are to be unlock, + * use bitwise OR '|' to separate them. + */ +void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios) +{ + /* Unlock the GPIO_CR register */ + GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE; + /* Enable committing changes */ + GPIO_CR(gpioport) |= gpios; + /* Lock the GPIO_CR register */ + GPIO_LOCK(gpioport) = ~GPIO_LOCK_UNLOCK_CODE; +} + +/** @brief General Purpose Input/Outputs Determine if interrupt is generated + * by the given pin + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Source pin identifiers @ref gpio_pin_id. + * If multiple pins are to be check, + * use bitwise OR '|' to separate them. + * + * @return Unsigned int8. The bit position of the pin + value returned corresponds to the pin number. + */ +uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios) +{ + return GPIO_MIS(gpioport) & gpios; +} + +/** @brief General Purpose Input/Outputs Mark Interrupt as Serviced + * + * After an interrupt is services, its flag must be cleared. If the flag is not + * cleared, then execution will jump back to the start of the ISR after the ISR + * returns. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be clear interrupt flag, use bitwise OR '|' to separate them. + */ +void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios) +{ + GPIO_ICR(gpioport) |= gpios; +} -- cgit v1.2.3 From 1883a4311fa7aa0f8ce59858e3b1117083e3a832 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 23 Oct 2018 21:33:16 +0000 Subject: msp432: whitespace fixups spaces->tabs whitespace only change. --- lib/msp432/e4/gpio.c | 348 +++++++++++++++++++++--------------------- lib/msp432/e4/systemcontrol.c | 36 ++--- 2 files changed, 192 insertions(+), 192 deletions(-) (limited to 'lib') diff --git a/lib/msp432/e4/gpio.c b/lib/msp432/e4/gpio.c index d3c9f048..f4b082cf 100644 --- a/lib/msp432/e4/gpio.c +++ b/lib/msp432/e4/gpio.c @@ -53,50 +53,50 @@ * to be set, use bitwise OR '|' to separate them. */ void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, - enum gpio_pull_up_down pull_up_down, uint8_t gpios) + enum gpio_pull_up_down pull_up_down, uint8_t gpios) { - GPIO_AFSEL(gpioport) &= ~gpios; - - switch (mode) { - case GPIO_MODE_OUTPUT: - GPIO_DIR(gpioport) |= gpios; - GPIO_DEN(gpioport) |= gpios; - GPIO_AMSEL(gpioport) &= ~gpios; - break; - case GPIO_MODE_INPUT: - GPIO_DIR(gpioport) &= ~gpios; - GPIO_DEN(gpioport) |= gpios; - GPIO_AMSEL(gpioport) &= ~gpios; - break; - case GPIO_MODE_ANALOG: - GPIO_AFSEL(gpioport) |= gpios; - GPIO_DEN(gpioport) &= ~gpios; - GPIO_AMSEL(gpioport) |= gpios; - break; - default: - /* Don't do anything */ - break; - } - - /* - * Setting a bit in the GPIO_PDR register clears the corresponding bit - * in the GPIO_PUR register, and vice-versa. - */ - switch (pull_up_down) { - case GPIO_PUPD_PULLUP: - GPIO_PDR(gpioport) &= ~gpios; - GPIO_PUR(gpioport) |= gpios; - break; - case GPIO_PUPD_PULLDOWN: - GPIO_PUR(gpioport) &= ~gpios; - GPIO_PDR(gpioport) |= gpios; - break; - case GPIO_PUPD_NONE: /* Fall through */ - default: - GPIO_PUR(gpioport) &= ~gpios; - GPIO_PDR(gpioport) &= ~gpios; - break; - } + GPIO_AFSEL(gpioport) &= ~gpios; + + switch (mode) { + case GPIO_MODE_OUTPUT: + GPIO_DIR(gpioport) |= gpios; + GPIO_DEN(gpioport) |= gpios; + GPIO_AMSEL(gpioport) &= ~gpios; + break; + case GPIO_MODE_INPUT: + GPIO_DIR(gpioport) &= ~gpios; + GPIO_DEN(gpioport) |= gpios; + GPIO_AMSEL(gpioport) &= ~gpios; + break; + case GPIO_MODE_ANALOG: + GPIO_AFSEL(gpioport) |= gpios; + GPIO_DEN(gpioport) &= ~gpios; + GPIO_AMSEL(gpioport) |= gpios; + break; + default: + /* Don't do anything */ + break; + } + + /* + * Setting a bit in the GPIO_PDR register clears the corresponding bit + * in the GPIO_PUR register, and vice-versa. + */ + switch (pull_up_down) { + case GPIO_PUPD_PULLUP: + GPIO_PDR(gpioport) &= ~gpios; + GPIO_PUR(gpioport) |= gpios; + break; + case GPIO_PUPD_PULLDOWN: + GPIO_PUR(gpioport) &= ~gpios; + GPIO_PDR(gpioport) |= gpios; + break; + case GPIO_PUPD_NONE: /* Fall through */ + default: + GPIO_PUR(gpioport) &= ~gpios; + GPIO_PDR(gpioport) &= ~gpios; + break; + } } /** @brief General Purpose Input/Outputs Set Output Options @@ -124,70 +124,70 @@ void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, * to be set, use bitwise OR '|' to separate them. */ void gpio_set_output_options(uint32_t gpioport, - enum gpio_output_type otype, - enum gpio_drive_strength drive, - enum gpio_slew_ctl slewctl, - uint8_t gpios) + enum gpio_output_type otype, + enum gpio_drive_strength drive, + enum gpio_slew_ctl slewctl, + uint8_t gpios) { - uint8_t i; - uint8_t pin_mask; - - if (otype == GPIO_OTYPE_OD) { - GPIO_ODR(gpioport) |= gpios; - } else { - GPIO_ODR(gpioport) &= ~gpios; - } - - GPIO_PP(gpioport) |= GPIO_PP_EDE; - - for (i = 0; i < 8; i++) { - pin_mask = (1 << i); - - if (!(gpios & pin_mask)) { - continue; - } - - GPIO_PC(gpioport) &= ~GPIO_PC_EDM_MASK(i); - GPIO_PC(gpioport) |= GPIO_PC_EDM(i, GPIO_PC_EDM_FULL_RANGE); - } - - GPIO_DR4R(gpioport) &= ~gpios; - GPIO_DR8R(gpioport) &= ~gpios; - GPIO_DR12R(gpioport) &= ~gpios; - - switch (drive) { - case GPIO_DRIVE_4MA: - GPIO_DR4R(gpioport) |= gpios; - break; - case GPIO_DRIVE_6MA: - GPIO_DR8R(gpioport) |= gpios; - break; - case GPIO_DRIVE_8MA: - GPIO_DR4R(gpioport) |= gpios; - GPIO_DR8R(gpioport) |= gpios; - break; - case GPIO_DRIVE_10MA: - GPIO_DR8R(gpioport) |= gpios; - GPIO_DR12R(gpioport) |= gpios; - break; - case GPIO_DRIVE_12MA: - GPIO_DR4R(gpioport) |= gpios; - GPIO_DR8R(gpioport) |= gpios; - GPIO_DR12R(gpioport) |= gpios; - break; - case GPIO_DRIVE_2MA: /* Fall through */ - default: - /* don't anything */ - break; - } - - if ((slewctl == GPIO_SLEW_CTL_ENABLE) && - ((drive == GPIO_DRIVE_8MA) || (drive == GPIO_DRIVE_10MA) || - (drive == GPIO_DRIVE_12MA))) { - GPIO_SLR(gpioport) |= gpios; - } else { - GPIO_SLR(gpioport) &= ~gpios; - } + uint8_t i; + uint8_t pin_mask; + + if (otype == GPIO_OTYPE_OD) { + GPIO_ODR(gpioport) |= gpios; + } else { + GPIO_ODR(gpioport) &= ~gpios; + } + + GPIO_PP(gpioport) |= GPIO_PP_EDE; + + for (i = 0; i < 8; i++) { + pin_mask = (1 << i); + + if (!(gpios & pin_mask)) { + continue; + } + + GPIO_PC(gpioport) &= ~GPIO_PC_EDM_MASK(i); + GPIO_PC(gpioport) |= GPIO_PC_EDM(i, GPIO_PC_EDM_FULL_RANGE); + } + + GPIO_DR4R(gpioport) &= ~gpios; + GPIO_DR8R(gpioport) &= ~gpios; + GPIO_DR12R(gpioport) &= ~gpios; + + switch (drive) { + case GPIO_DRIVE_4MA: + GPIO_DR4R(gpioport) |= gpios; + break; + case GPIO_DRIVE_6MA: + GPIO_DR8R(gpioport) |= gpios; + break; + case GPIO_DRIVE_8MA: + GPIO_DR4R(gpioport) |= gpios; + GPIO_DR8R(gpioport) |= gpios; + break; + case GPIO_DRIVE_10MA: + GPIO_DR8R(gpioport) |= gpios; + GPIO_DR12R(gpioport) |= gpios; + break; + case GPIO_DRIVE_12MA: + GPIO_DR4R(gpioport) |= gpios; + GPIO_DR8R(gpioport) |= gpios; + GPIO_DR12R(gpioport) |= gpios; + break; + case GPIO_DRIVE_2MA: /* Fall through */ + default: + /* don't anything */ + break; + } + + if ((slewctl == GPIO_SLEW_CTL_ENABLE) && + ((drive == GPIO_DRIVE_8MA) || (drive == GPIO_DRIVE_10MA) || + (drive == GPIO_DRIVE_12MA))) { + GPIO_SLR(gpioport) |= gpios; + } else { + GPIO_SLR(gpioport) &= ~gpios; + } } /** @brief General Purpose Input/Outputs Set Alternate Function Selection @@ -207,33 +207,33 @@ void gpio_set_output_options(uint32_t gpioport, */ void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios) { - uint32_t pctl32; - uint8_t pin_mask; - uint8_t i; + uint32_t pctl32; + uint8_t pin_mask; + uint8_t i; - /* Did we mean to disable the alternate function? */ - if (alt_func_num == 0) { - GPIO_AFSEL(gpioport) &= ~gpios; - return; - } + /* Did we mean to disable the alternate function? */ + if (alt_func_num == 0) { + GPIO_AFSEL(gpioport) &= ~gpios; + return; + } - /* Enable the alternate function */ - GPIO_AFSEL(gpioport) |= gpios; + /* Enable the alternate function */ + GPIO_AFSEL(gpioport) |= gpios; - /* Now take care of the actual multiplexing */ - pctl32 = GPIO_PCTL(gpioport); - for (i = 0; i < 8; i++) { - pin_mask = (1 << i); + /* Now take care of the actual multiplexing */ + pctl32 = GPIO_PCTL(gpioport); + for (i = 0; i < 8; i++) { + pin_mask = (1 << i); - if (!(gpios & pin_mask)) { - continue; - } + if (!(gpios & pin_mask)) { + continue; + } - pctl32 &= ~GPIO_PCTL_MASK(i); - pctl32 |= GPIO_PCTL_AF(i, (alt_func_num & 0xf)); - } + pctl32 &= ~GPIO_PCTL_MASK(i); + pctl32 |= GPIO_PCTL_AF(i, (alt_func_num & 0xf)); + } - GPIO_PCTL(gpioport) = pctl32; + GPIO_PCTL(gpioport) = pctl32; } /** @brief General Purpose Input/Outputs Configure Interrupt Trigger @@ -251,35 +251,35 @@ void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios) * to be configure, use bitwise OR '|' to separate them. */ void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, - uint8_t gpios) + uint8_t gpios) { - switch (trigger) { - case GPIO_TRIG_LVL_LOW: - GPIO_IS(gpioport) |= gpios; - GPIO_IEV(gpioport) &= ~gpios; - break; - case GPIO_TRIG_LVL_HIGH: - GPIO_IS(gpioport) |= gpios; - GPIO_IEV(gpioport) |= gpios; - break; - case GPIO_TRIG_EDGE_FALL: - GPIO_IS(gpioport) &= ~gpios; - GPIO_IBE(gpioport) &= ~gpios; - GPIO_IEV(gpioport) &= ~gpios; - break; - case GPIO_TRIG_EDGE_RISE: - GPIO_IS(gpioport) &= ~gpios; - GPIO_IBE(gpioport) &= ~gpios; - GPIO_IEV(gpioport) |= gpios; - break; - case GPIO_TRIG_EDGE_BOTH: - GPIO_IS(gpioport) &= ~gpios; - GPIO_IBE(gpioport) |= gpios; - break; - default: - /* Don't do anything */ - break; - } + switch (trigger) { + case GPIO_TRIG_LVL_LOW: + GPIO_IS(gpioport) |= gpios; + GPIO_IEV(gpioport) &= ~gpios; + break; + case GPIO_TRIG_LVL_HIGH: + GPIO_IS(gpioport) |= gpios; + GPIO_IEV(gpioport) |= gpios; + break; + case GPIO_TRIG_EDGE_FALL: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) &= ~gpios; + GPIO_IEV(gpioport) &= ~gpios; + break; + case GPIO_TRIG_EDGE_RISE: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) &= ~gpios; + GPIO_IEV(gpioport) |= gpios; + break; + case GPIO_TRIG_EDGE_BOTH: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) |= gpios; + break; + default: + /* Don't do anything */ + break; + } } /** @brief General Purpose Input/Outputs Set a Group of Pins Atomic @@ -292,7 +292,7 @@ void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, */ void gpio_set(uint32_t gpioport, uint8_t gpios) { - GPIO_DATA(gpioport)[gpios] = 0xFF; + GPIO_DATA(gpioport)[gpios] = 0xFF; } /** @brief General Purpose Input/Outputs Clear a Group of Pins Atomic @@ -305,7 +305,7 @@ void gpio_set(uint32_t gpioport, uint8_t gpios) */ void gpio_clear(uint32_t gpioport, uint8_t gpios) { - GPIO_DATA(gpioport)[gpios] = 0x0; + GPIO_DATA(gpioport)[gpios] = 0x0; } /** @brief General Purpose Input/Outputs Read a Group of Pins @@ -315,11 +315,11 @@ void gpio_clear(uint32_t gpioport, uint8_t gpios) * to be read, use bitwise OR '|' to separate them. * * @return Unsigned int8 value of the pin values. The bit position of the pin - value returned corresponds to the pin number. + value returned corresponds to the pin number. */ uint8_t gpio_get(uint32_t gpioport, uint8_t gpios) { - return (uint8_t)GPIO_DATA(gpioport)[gpios]; + return (uint8_t)GPIO_DATA(gpioport)[gpios]; } /** @brief General Purpose Input/Outputs Toggle a Group of Pins @@ -333,8 +333,8 @@ uint8_t gpio_get(uint32_t gpioport, uint8_t gpios) */ void gpio_toggle(uint32_t gpioport, uint8_t gpios) { - /* The mask makes sure we only toggle the GPIOs we want to */ - GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL; + /* The mask makes sure we only toggle the GPIOs we want to */ + GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL; } /** @brief General Purpose Input/Outputs Read from a Port @@ -347,7 +347,7 @@ void gpio_toggle(uint32_t gpioport, uint8_t gpios) */ uint8_t gpio_port_read(uint32_t gpioport) { - return (uint8_t)GPIO_DATA(gpioport)[GPIO_ALL]; + return (uint8_t)GPIO_DATA(gpioport)[GPIO_ALL]; } /** @brief General Purpose Input/Outputs Write to a Port @@ -359,7 +359,7 @@ uint8_t gpio_port_read(uint32_t gpioport) */ void gpio_port_write(uint32_t gpioport, uint8_t data) { - GPIO_DATA(gpioport)[GPIO_ALL] = data; + GPIO_DATA(gpioport)[GPIO_ALL] = data; } /** @brief General Purpose Input/Outputs Enable Interrupts on specified pins @@ -377,7 +377,7 @@ void gpio_port_write(uint32_t gpioport, uint8_t data) */ void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios) { - GPIO_IM(gpioport) |= gpios; + GPIO_IM(gpioport) |= gpios; } /** @brief General Purpose Input/Outputs Disable interrupts on specified pins @@ -392,7 +392,7 @@ void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios) */ void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios) { - GPIO_IM(gpioport) &= ~gpios; + GPIO_IM(gpioport) &= ~gpios; } /** @brief General Purpose Input/Outputs Unlock The Commit Control @@ -408,12 +408,12 @@ void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios) */ void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios) { - /* Unlock the GPIO_CR register */ - GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE; - /* Enable committing changes */ - GPIO_CR(gpioport) |= gpios; - /* Lock the GPIO_CR register */ - GPIO_LOCK(gpioport) = ~GPIO_LOCK_UNLOCK_CODE; + /* Unlock the GPIO_CR register */ + GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE; + /* Enable committing changes */ + GPIO_CR(gpioport) |= gpios; + /* Lock the GPIO_CR register */ + GPIO_LOCK(gpioport) = ~GPIO_LOCK_UNLOCK_CODE; } /** @brief General Purpose Input/Outputs Determine if interrupt is generated @@ -425,11 +425,11 @@ void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios) * use bitwise OR '|' to separate them. * * @return Unsigned int8. The bit position of the pin - value returned corresponds to the pin number. + value returned corresponds to the pin number. */ uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios) { - return GPIO_MIS(gpioport) & gpios; + return GPIO_MIS(gpioport) & gpios; } /** @brief General Purpose Input/Outputs Mark Interrupt as Serviced @@ -444,5 +444,5 @@ uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios) */ void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios) { - GPIO_ICR(gpioport) |= gpios; + GPIO_ICR(gpioport) |= gpios; } diff --git a/lib/msp432/e4/systemcontrol.c b/lib/msp432/e4/systemcontrol.c index 8a441175..01a20739 100644 --- a/lib/msp432/e4/systemcontrol.c +++ b/lib/msp432/e4/systemcontrol.c @@ -44,9 +44,9 @@ * @param[in] periph ::msp432_periph Peripheral block */ void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, - enum msp432_periph periph) + enum msp432_periph periph) { - _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph); + _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -56,9 +56,9 @@ void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, * @param[in] periph ::msp432_periph Peripheral block */ void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, - enum msp432_periph periph) + enum msp432_periph periph) { - _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph); + _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -68,7 +68,7 @@ void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, */ void sysctl_periph_reset(enum msp432_periph periph) { - _SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph); + _SYSCTL_REG((uint32_t) &SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -78,7 +78,7 @@ void sysctl_periph_reset(enum msp432_periph periph) */ void sysctl_periph_clear_reset(enum msp432_periph periph) { - _SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph); + _SYSCTL_REG((uint32_t) &SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -88,10 +88,10 @@ void sysctl_periph_clear_reset(enum msp432_periph periph) */ bool sysctl_periph_is_present(enum msp432_periph periph) { - uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PPWD, periph); - uint32_t mask = _SYSCTL_BIT(periph); + uint32_t reg32 = _SYSCTL_REG((uint32_t) &SYSCTL_PPWD, periph); + uint32_t mask = _SYSCTL_BIT(periph); - return ((reg32 & mask) != 0); + return((reg32 & mask) != 0); } /*----------------------------------------------------------------------------*/ @@ -101,10 +101,10 @@ bool sysctl_periph_is_present(enum msp432_periph periph) */ bool sysctl_periph_is_ready(enum msp432_periph periph) { - uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PRWD, periph); - uint32_t mask = _SYSCTL_BIT(periph); + uint32_t reg32 = _SYSCTL_REG((uint32_t) &SYSCTL_PRWD, periph); + uint32_t mask = _SYSCTL_BIT(periph); - return ((reg32 & mask) != 0); + return((reg32 & mask) != 0); } /*----------------------------------------------------------------------------*/ @@ -117,13 +117,13 @@ bool sysctl_periph_is_ready(enum msp432_periph periph) * is powered and receives a clock regardless of the value of power mode. */ void sysctl_periph_set_power_state(enum msp432_power_mode power_mode, - enum msp432_periph periph) + enum msp432_periph periph) { - if(power_mode == POWER_ENABLE) { - _SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph); - } else { - _SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph); - } + if (power_mode == POWER_ENABLE) { + _SYSCTL_REG((uint32_t) &SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph); + } else { + _SYSCTL_REG((uint32_t) &SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph); + } } #undef _SYSCTL_REG -- cgit v1.2.3 From f0e5c73d988e5703529da207ff8ddb44fc9ff00f Mon Sep 17 00:00:00 2001 From: Alfred Klomp Date: Fri, 9 Nov 2018 18:51:57 +0100 Subject: stm32: pll: disable before configuring --- lib/stm32/f2/rcc.c | 4 ++++ lib/stm32/f4/rcc.c | 4 ++++ lib/stm32/f7/rcc.c | 4 ++++ lib/stm32/l1/rcc.c | 4 ++++ 4 files changed, 16 insertions(+) (limited to 'lib') diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index b662cebb..d01dbcc0 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -355,6 +355,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_main_pll_hse(clock->pllm, clock->plln, clock->pllp, clock->pllq); diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 5dd775d5..7e3c0da3 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -709,6 +709,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_main_pll_hse(clock->pllm, clock->plln, clock->pllp, clock->pllq, clock->pllr); diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c index ea6dcd50..186109a5 100644 --- a/lib/stm32/f7/rcc.c +++ b/lib/stm32/f7/rcc.c @@ -392,6 +392,10 @@ void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz) rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_main_pll_hse(pllm, clock->plln, clock->pllp, clock->pllq); diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index e9f7bd68..41cf1999 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -535,6 +535,10 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) flash_prefetch_enable(); flash_set_ws(clock->flash_waitstates); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div); -- cgit v1.2.3 From 1adc418f9afaa5b99c34f3eea797dc4c1155c056 Mon Sep 17 00:00:00 2001 From: Alfred Klomp Date: Mon, 12 Nov 2018 17:06:59 +0100 Subject: stm32f42/f43: rcc: add 180 MHz clock options --- lib/stm32/f4/rcc.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'lib') diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 7e3c0da3..8a92ec40 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -114,6 +114,22 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, + { /* 180MHz */ + .pllm = 8, + .plln = 360, + .pllp = 2, + .pllq = 8, + .pllr = 0, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, + }, }; const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { @@ -181,6 +197,22 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, + { /* 180MHz */ + .pllm = 12, + .plln = 360, + .pllp = 2, + .pllq = 8, + .pllr = 0, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, + }, }; const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { @@ -248,6 +280,22 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, + { /* 180MHz */ + .pllm = 16, + .plln = 360, + .pllp = 2, + .pllq = 8, + .pllr = 0, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, + }, }; const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { @@ -315,6 +363,22 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, + { /* 180MHz */ + .pllm = 25, + .plln = 360, + .pllp = 2, + .pllq = 8, + .pllr = 0, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, + }, }; void rcc_osc_ready_int_clear(enum rcc_osc osc) -- cgit v1.2.3 From 7e1d3daa113e1ae21f308759e50be2f89361d90f Mon Sep 17 00:00:00 2001 From: Patrick Yeon Date: Thu, 6 Dec 2018 18:40:30 -0800 Subject: stm32f0: adc: API call to clear EOS flag --- lib/stm32/f0/adc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'lib') diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c index 2302582a..3f03a8c0 100644 --- a/lib/stm32/f0/adc.c +++ b/lib/stm32/f0/adc.c @@ -277,6 +277,16 @@ bool adc_get_eoc_sequence_flag(uint32_t adc) return ADC_ISR(adc) & ADC_ISR_EOSEQ; } +/*---------------------------------------------------------------------------*/ +/** @ brief ADC Clear Regular End-Of-Conversion Sequence Flag + * + * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) + */ + +void adc_clear_eoc_sequence_flag(uint32_t adc) +{ + ADC_ISR(adc) = ADC_ISR_EOSEQ; +} /**@}*/ -- cgit v1.2.3 From 72e449f529f8196722298cd7bdf903d63d0ed9d6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 10 Jan 2019 14:42:54 +0000 Subject: stm32f3: rcc: fix typo in PLL clocks for APB1 Reported by jabjoe on irc, fixed by zyp --- lib/stm32/f3/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c index 0fdb9a48..7908878f 100644 --- a/lib/stm32/f3/rcc.c +++ b/lib/stm32/f3/rcc.c @@ -80,7 +80,7 @@ const struct rcc_clock_scale rcc_hse8mhz_configs[] = { .ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ahb_frequency = 72e6, - .apb1_frequency = 32e6, + .apb1_frequency = 36e6, .apb2_frequency = 72e6, } }; -- cgit v1.2.3 From 74f460feac2e0eabb20de306bb2935011dffce5c Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 21 Jan 2019 18:41:42 +0100 Subject: stm32f0: adc: fix doc. --- lib/stm32/f0/adc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c index 3f03a8c0..30e1595c 100644 --- a/lib/stm32/f0/adc.c +++ b/lib/stm32/f0/adc.c @@ -278,7 +278,7 @@ bool adc_get_eoc_sequence_flag(uint32_t adc) } /*---------------------------------------------------------------------------*/ -/** @ brief ADC Clear Regular End-Of-Conversion Sequence Flag +/** @brief ADC Clear Regular End-Of-Conversion Sequence Flag * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ @@ -301,12 +301,12 @@ void adc_clear_eoc_sequence_flag(uint32_t adc) *@{*/ /*---------------------------------------------------------------------------*/ -/** @brief ADC Set Clock Prescale +/** @brief ADC Set Clock Source * * The ADC clock taken from the many sources. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) - * @param[in] prescale Unsigned int32. Prescale value (@ref adc_api_clksource) + * @param[in] source Unsigned int32. Source (@ref adc_api_clksource) */ void adc_set_clk_source(uint32_t adc, uint32_t source) -- cgit v1.2.3 From 7afd86db3093044ecbd9d90ffafd4fd8da31f306 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 8 Jan 2019 14:26:38 +0100 Subject: stm32l[01]: flash common: add flash_unlock_acr, allowing to unlock FLASH_ACR RUN_PD bit. flash_unlock_acr allows to unlock RUN_PD bit from FLASH_ACR register. Relock is done automatically when writing 0 to RUN_PD, so no flash_lock_acr method. --- lib/stm32/common/flash_common_l01.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'lib') diff --git a/lib/stm32/common/flash_common_l01.c b/lib/stm32/common/flash_common_l01.c index 9eceb45f..9fb1212b 100644 --- a/lib/stm32/common/flash_common_l01.c +++ b/lib/stm32/common/flash_common_l01.c @@ -89,6 +89,14 @@ void flash_lock(void) flash_lock_pecr(); } +/** @brief Unlock RUN_PD bit from FLASH_ACR register. + */ +void flash_unlock_acr(void) +{ + FLASH_PDKEYR = FLASH_PDKEYR_PDKEY1; + FLASH_PDKEYR = FLASH_PDKEYR_PDKEY2; +} + /** @brief Write a word to eeprom * * @param address assumed to be in the eeprom space, no checking -- cgit v1.2.3 From b98dd8eee02147abbd92f9b31f59ddedcba0e177 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 11 Jan 2019 18:34:46 +0100 Subject: stm32: exti: exti_select_source: rework and use EXTI_EXTICR. EXTICR on stm32g0 is in exti registers range. Previous chips used to have that gpio port exti mux configuration accessible via AFIO_EXTICR or SYSCFG_EXTICR. Also, the new chip now use 8 bits coded value instead of previously 4 for the extcr mux selection value (see AFIO/SYSCFG/EXTI_EXTICR_FIELDSIZE) Let's define two helpers: EXTICR_SELECTION_REG (to get proper AFIO/SYSCFG/ EXTI_EXTICR register) and EXTICR_SELECTION_FIELDSIZE (to get proper AFIO/SYSCFG/ EXTI_EXTICR_FIELDSIZE value), and use it them exti_select_source to determine exticr mux selection bits shift and mask. --- lib/stm32/common/exti_common_all.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index d2135f29..4ba64b02 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -25,8 +25,17 @@ #include #include -#if !defined(AFIO_BASE) -# include + +#if defined(EXTI_EXTICR) + #define EXTICR_SELECTION_FIELDSIZE EXTI_EXTICR_FIELDSIZE + #define EXTICR_SELECTION_REG(x) EXTI_EXTICR(x) +#elif defined(AFIO_EXTICR) + #define EXTICR_SELECTION_FIELDSIZE AFIO_EXTICR_FIELDSIZE + #define EXTICR_SELECTION_REG(x) AFIO_EXTICR(x) +#else + #include + #define EXTICR_SELECTION_FIELDSIZE SYSCFG_EXTICR_FIELDSIZE + #define EXTICR_SELECTION_REG(x) SYSCFG_EXTICR(x) #endif void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig) @@ -96,7 +105,7 @@ void exti_select_source(uint32_t exti, uint32_t gpioport) continue; } - uint32_t bits = 0, mask = 0x0F; + uint32_t bits = 0; switch (gpioport) { case GPIOA: @@ -148,16 +157,11 @@ void exti_select_source(uint32_t exti, uint32_t gpioport) #endif } - uint8_t shift = (uint8_t)(4 * (line % 4)); + uint8_t shift = (uint8_t)(EXTICR_SELECTION_FIELDSIZE * (line % 4)); + uint32_t mask = ((1 << EXTICR_SELECTION_FIELDSIZE) - 1) << shift; uint32_t reg = line / 4; - bits <<= shift; - mask <<= shift; -#if defined(AFIO_BASE) - AFIO_EXTICR(reg) = (AFIO_EXTICR(reg) & ~mask) | bits; -#else - SYSCFG_EXTICR(reg) = (SYSCFG_EXTICR(reg) & ~mask) | bits; -#endif + EXTICR_SELECTION_REG(reg) = (EXTICR_SELECTION_REG(reg) & ~mask) | (bits << shift); }; } /**@}*/ -- cgit v1.2.3 From c4c0d14ea4ef81601de95d811a7093976f1e47f1 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 23 Jan 2019 18:54:19 +0100 Subject: stm32: exti: stm32g0 have enhanced EXTI_[FR]PR regs instead of EXTIR_PR, use them if defined. Make exti_get_flag_status and exti_reset_request use EXTI_RPR and EXTI_FPR if present instead of EXTI_PR. This is less precise than offered by the RPR/FPR registers, but makes for a consistent experience in the common API. Reviewed-by: Karl Palsson --- lib/stm32/common/exti_common_all.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'lib') diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index 4ba64b02..5a88b232 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -80,7 +80,12 @@ void exti_disable_request(uint32_t extis) */ void exti_reset_request(uint32_t extis) { +#if defined(EXTI_RPR1) && defined(EXTI_FPR1) + EXTI_RPR1 = extis; + EXTI_FPR1 = extis; +#else EXTI_PR = extis; +#endif } /* @@ -88,7 +93,11 @@ void exti_reset_request(uint32_t extis) * */ uint32_t exti_get_flag_status(uint32_t exti) { +#if defined(EXTI_RPR1) && defined(EXTI_FPR1) + return (EXTI_RPR1 & exti) | (EXTI_FPR1 & exti); +#else return EXTI_PR & exti; +#endif } /* -- cgit v1.2.3 From 0fd4f74ee301af5de4e9b036f391bf17c5a52f02 Mon Sep 17 00:00:00 2001 From: Mike Szczys Date: Sat, 9 Feb 2019 16:37:23 -0600 Subject: stm32f1: adc: fixed deprecated/broken example code --- lib/stm32/f1/adc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index 24e79c51..3ff12bf7 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -59,11 +59,11 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent adc_set_dual_mode(ADC_CR1_DUALMOD_IND); adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); - adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); - adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); + adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_1DOT5CYC); + adc_enable_external_trigger_regular(ADC1, ADC_CR2_EXTSEL_SWSTART); adc_power_on(ADC1); adc_reset_calibration(ADC1); - adc_calibration(ADC1); + adc_calibrate(ADC1); adc_start_conversion_regular(ADC1); while (! adc_eoc(ADC1)); reg16 = adc_read_regular(ADC1); -- cgit v1.2.3 From 330d5fd5be46afa8417babd95357e90e78557b1e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 30 Jan 2019 01:14:06 +0800 Subject: gd32: add new chip series f1x0 GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng Reviewed-by: Karl Palsson gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future. --- lib/dispatch/vector_nvic.c | 3 + lib/gd32/f1x0/Makefile | 47 ++++ lib/gd32/f1x0/flash.c | 153 +++++++++++ lib/gd32/f1x0/rcc.c | 654 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 857 insertions(+) create mode 100755 lib/gd32/f1x0/Makefile create mode 100644 lib/gd32/f1x0/flash.c create mode 100644 lib/gd32/f1x0/rcc.c (limited to 'lib') diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 3c12350d..0f0d4062 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -17,6 +17,9 @@ #elif defined(STM32L4) # include "../stm32/l4/vector_nvic.c" +#elif defined(GD32F1X0) +# include "../gd32/f1x0/vector_nvic.c" + #elif defined(EFM32TG) # include "../efm32/tg/vector_nvic.c" #elif defined(EFM32G) diff --git a/lib/gd32/f1x0/Makefile b/lib/gd32/f1x0/Makefile new file mode 100755 index 00000000..72bb1598 --- /dev/null +++ b/lib/gd32/f1x0/Makefile @@ -0,0 +1,47 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Icenowy Zheng +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_gd32f1x0 +SRCLIBDIR ?= ../.. + +PREFIX ?= arm-none-eabi + +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DGD32F1X0 +TGT_CFLAGS += $(DEBUG_FLAGS) +# ARFLAGS = rcsv +ARFLAGS = rcs + +OBJS = rcc.o flash.o + +OBJS += \ + gpio_common_all.o gpio_common_f0234.o \ + rcc_common_all.o \ + flash_common_all.o flash_common_f.o flash_common_f01.o + +VPATH += ../:../../cm3:../common:../../stm32/common + +include ../../Makefile.include diff --git a/lib/gd32/f1x0/flash.c b/lib/gd32/f1x0/flash.c new file mode 100644 index 00000000..ad7cb054 --- /dev/null +++ b/lib/gd32/f1x0/flash.c @@ -0,0 +1,153 @@ +/** @defgroup flash_file FLASH + * + * @ingroup GD32F1x0 + * + * @brief libopencm3 GD32F1x0 FLASH + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 14 January 2014 + * + * FLASH memory may be used for data storage as well as code, and may be + * programmatically modified. Note that for firmware upload the GD32F1x0 + * provides a built-in bootloader in system memory that can be entered from a + * running program. + * + * FLASH must first be unlocked before programming. In this module a write to + * FLASH is a blocking operation until the end-of-operation flag is asserted. + * + * @note: don't forget to lock it again when all operations are complete. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/*---------------------------------------------------------------------------*/ +/** @brief Clear All Status Flags + +Program error, end of operation, write protect error, busy. +*/ + +void flash_clear_status_flags(void) +{ + flash_clear_pgerr_flag(); + flash_clear_eop_flag(); + flash_clear_wrprterr_flag(); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Read All Status Flags + +The programming error, end of operation, write protect error and busy flags +are returned in the order of appearance in the status register. + +@returns uint32_t. bit 0: busy, bit 2: programming error, bit 4: write protect +error, bit 5: end of operation. +*/ + +uint32_t flash_get_status_flags(void) +{ + return FLASH_SR & (FLASH_SR_PGERR | + FLASH_SR_EOP | + FLASH_SR_WRPRTERR | + FLASH_SR_BSY); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Program a Half Word to FLASH + +This performs all operations necessary to program a 16 bit word to FLASH memory. +The program error flag should be checked separately for the event that memory +was not properly erased. + +Status bit polling is used to detect end of operation. + +@param[in] address Full address of flash half word to be programmed. +@param[in] data half word to write +*/ + +void flash_program_half_word(uint32_t address, uint16_t data) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_PG; + + MMIO16(address) = data; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_CR_PG; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Erase a Page of FLASH + +This performs all operations necessary to erase a page in FLASH memory. +The page should be checked to ensure that it was properly erased. A page must +first be fully erased before attempting to program it. + +Note that the page sizes differ between devices. See the reference manual or +the FLASH programming manual for details. + +@param[in] page_address Full address of flash page to be erased. +*/ + +void flash_erase_page(uint32_t page_address) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_PER; + FLASH_AR = page_address; + FLASH_CR |= FLASH_CR_STRT; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_CR_PER; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Erase All FLASH + +This performs all operations necessary to erase all user pages in the FLASH +memory. The information block is unaffected. +*/ + +void flash_erase_all_pages(void) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */ + FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */ + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */ + +} + +/**@}*/ + diff --git a/lib/gd32/f1x0/rcc.c b/lib/gd32/f1x0/rcc.c new file mode 100644 index 00000000..118b64be --- /dev/null +++ b/lib/gd32/f1x0/rcc.c @@ -0,0 +1,654 @@ +/** @defgroup GD32F1x0-rcc-file RCC + +@ingroup GD32F1x0 + +@brief libopencm3 GD32F1x0 Reset and Clock Control + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 +Federico Ruiz-Ugalde \ +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +This library supports the Reset and Clock Control System in the GD32F1x0 +series of ARM Cortex Microcontrollers by GigaDevice. + +@note Full support for F170 and F190 devices is not yet provided. + +Clock settings and resets for many peripherals are given here rather than in +the corresponding peripheral library. + +The library also provides a number of common configurations for the processor +system clock. Not all possible configurations are included. + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include +#include +#include + +/** Set the default clock frequencies */ +uint32_t rcc_apb1_frequency = 8000000; +uint32_t rcc_apb2_frequency = 8000000; +uint32_t rcc_ahb_frequency = 8000000; + +const struct rcc_clock_scale rcc_hsi_configs[] = { + { /* 48MHz */ + .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL12, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .use_hse = false, + .ahb_frequency = 48000000, + .apb1_frequency = 24000000, + .apb2_frequency = 48000000, + }, + { /* 64MHz */ + .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL16, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .use_hse = false, + .ahb_frequency = 64000000, + .apb1_frequency = 32000000, + .apb2_frequency = 64000000, + } +}; + +const struct rcc_clock_scale rcc_hse8_configs[] = { + { /* 72MHz */ + .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL9, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .usbpre = RCC_CFGR_USBPRE_PLL_CLK_DIV1_5, + .use_hse = true, + .pll_hse_prediv = RCC_CFGR2_PREDIV_NODIV, + .ahb_frequency = 72000000, + .apb1_frequency = 36000000, + .apb2_frequency = 72000000, + }, +}; + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Clear the Oscillator Ready Interrupt Flag + +Clear the interrupt flag that was set when a clock oscillator became ready to +use. + +@param[in] osc enum ::osc_t. Oscillator ID +*/ + +void rcc_osc_ready_int_clear(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case RCC_HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case RCC_HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case RCC_LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case RCC_LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Enable the Oscillator Ready Interrupt + +@param[in] osc enum ::osc_t. Oscillator ID +*/ + +void rcc_osc_ready_int_enable(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case RCC_HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case RCC_HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case RCC_LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case RCC_LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Disable the Oscillator Ready Interrupt + +@param[in] osc enum ::osc_t. Oscillator ID +*/ + +void rcc_osc_ready_int_disable(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case RCC_HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case RCC_HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case RCC_LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case RCC_LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Read the Oscillator Ready Interrupt Flag + +@param[in] osc enum ::osc_t. Oscillator ID +@returns int. Boolean value for flag set. +*/ + +int rcc_osc_ready_int_flag(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case RCC_HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case RCC_HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case RCC_LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case RCC_LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + } + + cm3_assert_not_reached(); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Clear the Clock Security System Interrupt Flag + +*/ + +void rcc_css_int_clear(void) +{ + RCC_CIR |= RCC_CIR_CSSC; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Read the Clock Security System Interrupt Flag + +@returns int. Boolean value for flag set. +*/ + +int rcc_css_int_flag(void) +{ + return ((RCC_CIR & RCC_CIR_CSSF) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Wait for Oscillator Ready. + +@param[in] osc enum ::osc_t. Oscillator ID +*/ + +void rcc_wait_for_osc_ready(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case RCC_HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case RCC_HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case RCC_LSE: + while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); + break; + case RCC_LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Turn on an Oscillator. + +Enable an oscillator and power on. Each oscillator requires an amount of time +to settle to a usable state. Refer to datasheets for time delay information. A +status flag is available to indicate when the oscillator becomes ready (see +@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready). + +@note The LSE clock is in the backup domain and cannot be enabled until the +backup domain write protection has been removed (see @ref +pwr_disable_backup_domain_write_protect). + +@param[in] osc enum ::osc_t. Oscillator ID +*/ + +void rcc_osc_on(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR |= RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Turn off an Oscillator. + +Disable an oscillator and power off. + +@note An oscillator cannot be turned off if it is selected as the system clock. +@note The LSE clock is in the backup domain and cannot be disabled until the +backup domain write protection has been removed (see +@ref pwr_disable_backup_domain_write_protect) or the backup domain has been +(see reset @ref rcc_backupdomain_reset). + +@param[in] osc enum ::osc_t. Oscillator ID +*/ + +void rcc_osc_off(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Enable the Clock Security System. + +*/ + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Disable the Clock Security System. + +*/ + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the Source for the System Clock. + +@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs +*/ + +void rcc_set_sysclk_source(uint32_t clk) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | + (clk << RCC_CFGR_SW_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the PLL Multiplication Factor. + +@note This only has effect when the PLL is disabled. + +@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf +*/ + +void rcc_set_pll_multiplication_factor(uint32_t mul) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLMUL_0_3 & ~RCC_CFGR_PLLMUL_4) | + ((mul & 0xf) << RCC_CFGR_PLLMUL_0_3_SHIFT) | + ((!!(mul & 0x10)) << RCC_CFGR_PLLMUL_4_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the PLL Clock Source. + +@note This only has effect when the PLL is disabled. + +@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs +*/ + +void rcc_set_pll_source(uint32_t pllsrc) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLSRC) | + (pllsrc << 16); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source. + +@note This only has effect when the PLL is disabled. + +@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre +*/ + +void rcc_set_pllxtpre(uint32_t pllxtpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLXTPRE) | + (pllxtpre << 17); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC RTC Clock Enabled Flag + +@returns uint32_t. Nonzero if the RTC Clock is enabled. +*/ + +uint32_t rcc_rtc_clock_enabled_flag(void) +{ + return RCC_BDCR & RCC_BDCR_RTCEN; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Enable the RTC clock + +*/ + +void rcc_enable_rtc_clock(void) +{ + RCC_BDCR |= RCC_BDCR_RTCEN; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the Source for the RTC clock + +@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI. +*/ + +void rcc_set_rtc_clock_source(enum rcc_osc clock_source) +{ + uint32_t reg32; + + switch (clock_source) { + case RCC_LSE: + /* Turn the LSE on and wait while it stabilises. */ + RCC_BDCR |= RCC_BDCR_LSEON; + while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0); + + /* Choose LSE as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 8); + break; + case RCC_LSI: + /* Turn the LSI on and wait while it stabilises. */ + RCC_CSR |= RCC_CSR_LSION; + while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0); + + /* Choose LSI as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 9); + break; + case RCC_HSE: + /* Turn the HSE on and wait while it stabilises. */ + RCC_CR |= RCC_CR_HSEON; + while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0); + + /* Choose HSE as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 9) | (1 << 8); + break; + case RCC_PLL: + case RCC_HSI: + /* Unusable clock source, here to prevent warnings. */ + /* Turn off clock sources to RTC. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Setup the A/D Clock + +The ADC's have a common clock prescale setting. + +@param[in] adcpre uint32_t. Prescale divider taken from @ref rcc_cfgr_adcpre +*/ + +void rcc_set_adcpre(uint32_t adcpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_ADCPRE) | + (adcpre << RCC_CFGR_ADCPRE_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the APB2 Prescale Factor. + +@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre +*/ + +void rcc_set_ppre2(uint32_t ppre2) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE2) | + (ppre2 << RCC_CFGR_PPRE2_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the APB1 Prescale Factor. + +@note The APB1 clock frequency must not exceed 36MHz. + +@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre +*/ + +void rcc_set_ppre1(uint32_t ppre1) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE1) | + (ppre1 << RCC_CFGR_PPRE1_SHIFT); + +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the AHB Prescale Factor. + +@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre +*/ + +void rcc_set_hpre(uint32_t hpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_HPRE) | + (hpre << RCC_CFGR_HPRE_SHIFT); + +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the USB Prescale Factor. + +The prescale factor can be set to 1 (no prescale) for use when the PLL clock is +48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock. + +@note This bit cannot be reset while the USB clock is enabled. + +@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre +*/ + +void rcc_set_usbpre(uint32_t usbpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_USBPRE) | usbpre; +} + +void rcc_set_prediv(uint32_t prediv) +{ + RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Get the System Clock Source. + +@returns Unsigned int32. System clock source: +@li 00 indicates HSE +@li 01 indicates LSE +@li 02 indicates PLL +*/ + +uint32_t rcc_system_clock_source(void) +{ + /* Return the clock source which is used as system clock. */ + return (RCC_CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_SHIFT; +} + +/*---------------------------------------------------------------------------*/ +/* + * These functions are setting up the whole clock system for the most common + * input clock and output clock configurations. + */ +/*---------------------------------------------------------------------------*/ +/** + * Setup clocks to run from PLL. + * The arguments provide the pll source, multipliers, dividers, all that's + * needed to establish a system clock. + * @param clock clock information structure + */ +void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) +{ + if (clock->use_hse) { + /* Enable external high-speed oscillator. */ + rcc_osc_on(RCC_HSE); + rcc_wait_for_osc_ready(RCC_HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); + } else { + /* Enable internal high-speed oscillator. */ + rcc_osc_on(RCC_HSI); + rcc_wait_for_osc_ready(RCC_HSI); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + } + + /* + * Set prescalers for AHB, ADC, APB1, APB2 and USB. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(clock->hpre); + rcc_set_ppre1(clock->ppre1); + rcc_set_ppre2(clock->ppre2); + + rcc_set_adcpre(clock->adcpre); + if (clock->use_hse) + rcc_set_usbpre(clock->usbpre); + + /* Set the PLL multiplication factor. */ + rcc_set_pll_multiplication_factor(clock->pllmul); + + if (clock->use_hse) { + /* Select HSE as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); + + /* + * External frequency undivided before entering PLL + * (only valid/needed for HSE). + */ + rcc_set_prediv(clock->pll_hse_prediv); + } else { + /* Select HSI/2 as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); + } + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(RCC_PLL); + rcc_wait_for_osc_ready(RCC_PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ahb_frequency = clock->ahb_frequency; + rcc_apb1_frequency = clock->apb1_frequency; + rcc_apb2_frequency = clock->apb2_frequency; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Reset the Backup Domain + +The backup domain registers are reset to disable RTC controls and clear user +data. +*/ + +void rcc_backupdomain_reset(void) +{ + /* Set the backup domain software reset. */ + RCC_BDCR |= RCC_BDCR_BDRST; + + /* Clear the backup domain software reset. */ + RCC_BDCR &= ~RCC_BDCR_BDRST; +} + +/**@}*/ + -- cgit v1.2.3 From 4db40e08394fdc6742f9117f3098d23a5de2bd95 Mon Sep 17 00:00:00 2001 From: Ross Schlaikjer Date: Thu, 4 Apr 2019 11:06:03 -0400 Subject: stm32f7: Include i2c_common_v2 With the addition of a define for I2C4, the existing common i2c functions seem to work out of the box on the F7 (tested on an STM32F750). --- lib/stm32/f7/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index bbd1e400..be9739c4 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -46,8 +46,8 @@ OBJS = desig.o OBJS += dma_common_f24.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o OBJS += pwr.o rcc.o - OBJS += rcc_common_all.o OBJS += rng_common_v1.o OBJS += spi_common_all.o spi_common_v2.o -- cgit v1.2.3 From 0173ecec9ca5f1c79d181764e5c2d1678f474d3e Mon Sep 17 00:00:00 2001 From: Ross Schlaikjer Date: Thu, 11 Apr 2019 10:54:19 -0400 Subject: stm32f7: enable existing IWDG support --- lib/stm32/f7/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index be9739c4..0f90d3d7 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -47,6 +47,7 @@ OBJS += dma_common_f24.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o OBJS += pwr.o rcc.o OBJS += rcc_common_all.o OBJS += rng_common_v1.o -- cgit v1.2.3 From a92a44a7c20946625c5d68aadc6866e23147a3f7 Mon Sep 17 00:00:00 2001 From: Ross Schlaikjer Date: Thu, 11 Apr 2019 10:57:13 -0400 Subject: stm32f7: enable existing CRC support --- lib/stm32/f7/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 0f90d3d7..37bfc2b4 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -44,6 +44,7 @@ ARFLAGS = rcs OBJS = desig.o OBJS += dma_common_f24.o +OBJS += crc_common_all.o crc_v2.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o -- cgit v1.2.3 From 1290e3129dda12506de7acdf65f8b57f7af579f9 Mon Sep 17 00:00:00 2001 From: Ross Schlaikjer Date: Thu, 11 Apr 2019 11:01:02 -0400 Subject: stm32f7: enable existing CAN library --- lib/stm32/f7/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 37bfc2b4..b8bb8751 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -44,6 +44,7 @@ ARFLAGS = rcs OBJS = desig.o OBJS += dma_common_f24.o +OBJS += can.o OBJS += crc_common_all.o crc_v2.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o -- cgit v1.2.3 From 4fb67d891f0ceadc8640fe1bff36372c26191634 Mon Sep 17 00:00:00 2001 From: Ross Schlaikjer Date: Thu, 11 Apr 2019 11:06:18 -0400 Subject: stm32f7: enable existing ethernet libraries --- lib/stm32/f7/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index b8bb8751..e877749c 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -57,6 +57,9 @@ OBJS += spi_common_all.o spi_common_v2.o OBJS += timer_common_all.o OBJS += usart_common_all.o usart_common_v2.o +# Ethernet +OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o + VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet -- cgit v1.2.3 From f5d2d8f10998415f9937e45729493357b1471026 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 15 Apr 2019 13:12:31 +0000 Subject: stm32f7: sort makefile object list alphabetically --- lib/stm32/f7/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index e877749c..e92fac5b 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -42,10 +42,10 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = desig.o -OBJS += dma_common_f24.o OBJS += can.o OBJS += crc_common_all.o crc_v2.o +OBJS += desig.o +OBJS += dma_common_f24.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o -- cgit v1.2.3 From fc8a6aa7a2dc1009f762a5c2c5711863a50a8f79 Mon Sep 17 00:00:00 2001 From: M J Oldfield Date: Sat, 27 Apr 2019 22:21:56 +0100 Subject: stm32: adc-v2: set _only_ the ADC calibration bit In adc_calibrate_async() we should only set the ADCAL bit and leave the rest alone. While in the past there were only "rs" bits in this register, this is no longer the case. Reviewed-by: Karl Palsson --- lib/stm32/common/adc_common_v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/common/adc_common_v2.c b/lib/stm32/common/adc_common_v2.c index 5ad85c6a..7fd26476 100644 --- a/lib/stm32/common/adc_common_v2.c +++ b/lib/stm32/common/adc_common_v2.c @@ -155,7 +155,7 @@ void adc_power_off(uint32_t adc) */ void adc_calibrate_async(uint32_t adc) { - ADC_CR(adc) = ADC_CR_ADCAL; + ADC_CR(adc) |= ADC_CR_ADCAL; } /** -- cgit v1.2.3 From e50ce6a876ae41f9bb27276c3b872d64a5e39f89 Mon Sep 17 00:00:00 2001 From: Marek Koza Date: Tue, 30 Apr 2019 20:47:14 +0200 Subject: stm32l4: Correct memorymap and add the existing CAN library --- lib/stm32/l4/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index a2748535..e0bed7c5 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -38,7 +38,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs # Specific objs -OBJS = adc.o flash.o pwr.o rcc.o +OBJS = adc.o flash.o pwr.o rcc.o can.o # common/shared objs OBJS += rcc_common_all.o -- cgit v1.2.3 From 5dbdb255d873bf016c66c62376ec70fa12635cd3 Mon Sep 17 00:00:00 2001 From: vector Date: Mon, 6 May 2019 21:48:00 +0200 Subject: STM32F7: dac: include in build. Based on F4. --- lib/stm32/f7/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index e92fac5b..6689143f 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -44,6 +44,7 @@ ARFLAGS = rcs OBJS += can.o OBJS += crc_common_all.o crc_v2.o +OBJS += dac_common_all.o OBJS += desig.o OBJS += dma_common_f24.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o -- cgit v1.2.3 From 6703abf5e3331bc912037530c7c29be565f2c521 Mon Sep 17 00:00:00 2001 From: Matthew Lai Date: Mon, 29 Apr 2019 00:29:56 +0100 Subject: Added F7 ADC support (almost the same as F4) --- lib/stm32/common/adc_common_v3.c | 448 +++++++++++++++++++++++++++++++++++++++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/adc.c | 448 --------------------------------------- lib/stm32/f7/Makefile | 1 + 4 files changed, 450 insertions(+), 449 deletions(-) create mode 100644 lib/stm32/common/adc_common_v3.c delete mode 100644 lib/stm32/f4/adc.c (limited to 'lib') diff --git a/lib/stm32/common/adc_common_v3.c b/lib/stm32/common/adc_common_v3.c new file mode 100644 index 00000000..020db884 --- /dev/null +++ b/lib/stm32/common/adc_common_v3.c @@ -0,0 +1,448 @@ +/** @addtogroup adc_file ADC peripheral API +@ingroup peripheral_apis + +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +@date 30 August 2012 + +This library supports the A/D Converter Control System in the STM32 series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to three A/D converters each with their own set of +registers. However all the A/D converters share a common clock which is +prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum +of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. + +Each A/D converter has up to 19 channels: +@li On ADC1 the analog channels 16 is internally connected to the temperature +sensor, channel 17 to VREFINT, and channel 18 to VBAT. +@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. + +The conversions can occur as a one-off conversion whereby the process stops +once conversion is complete. The conversions can also be continuous wherein a +new conversion starts immediately the previous conversion has ended. + +Conversion can occur as a single channel conversion or a scan of a group of +channels in either continuous or one-off mode. If more than one channel is +converted in a scan group, DMA must be used to transfer the data as there is +only one result register available. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. + +A discontinuous mode allows a subgroup of group of a channels to be converted +in bursts of a given length. + +Injected conversions allow a second group of channels to be converted +separately from the regular group. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. + +@section adc_f4_api_ex Basic ADC Handling API. + +Example 1: Simple single channel conversion polled. Enable the peripheral clock +and ADC, reset ADC and set the prescaler divider. Set the sample time to a +minimum of 3 cycles. Set multiple mode to independent. + +@code +gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); +rcc_periph_clock_enable(RCC_ADC1); +adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2); +adc_disable_scan_mode(ADC1); +adc_set_single_conversion_mode(ADC1); +adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_3CYC); +uint8_t channels[] = ADC_CHANNEL0; +adc_set_regular_sequence(ADC1, 1, channels); +adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); +adc_power_on(ADC1); +adc_start_conversion_regular(ADC1); +while (!adc_eoc(ADC1)); +reg16 = adc_read_regular(ADC1); +@endcode + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for a Single Channel + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ + +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) +{ + uint32_t reg32; + + if (channel < 10) { + reg32 = ADC_SMPR2(adc); + reg32 &= ~(0x7 << (channel * 3)); + reg32 |= (time << (channel * 3)); + ADC_SMPR2(adc) = reg32; + } else { + reg32 = ADC_SMPR1(adc); + reg32 &= ~(0x7 << ((channel - 10) * 3)); + reg32 |= (time << ((channel - 10) * 3)); + ADC_SMPR1(adc) = reg32; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for All Channels + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ + +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) +{ + uint8_t i; + uint32_t reg32 = 0; + + for (i = 0; i <= 9; i++) { + reg32 |= (time << (i * 3)); + } + ADC_SMPR2(adc) = reg32; + + for (i = 10; i <= 17; i++) { + reg32 |= (time << ((i - 10) * 3)); + } + ADC_SMPR1(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Power On + +If the ADC is in power-down mode then it is powered up. The application needs +to wait a time of about 3 microseconds for stabilization before using the ADC. +If the ADC is already on this function call will have no effect. + * NOTE Common with L1 and F2 + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_power_on(uint32_t adc) +{ + ADC_CR2(adc) |= ADC_CR2_ADON; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Clock Prescale + +The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. + +@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref +adc_ccr_adcpre +*/ + +void adc_set_clk_prescale(uint32_t prescale) +{ + uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale); + ADC_CCR = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Dual/Triple Mode + +The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave +arrangement. This setting is applied to ADC1 only. + +The various modes possible are described in the reference manual. + +@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode +*/ + +void adc_set_multi_mode(uint32_t mode) +{ + ADC_CCR |= mode; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable an External Trigger for Regular Channels + +This enables an external trigger for set of defined regular channels, and sets +the polarity of the trigger event: rising or falling edge or both. Note that if +the trigger polarity is zero, triggering is disabled. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_regular +*/ + +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity) +{ + uint32_t reg32 = ADC_CR2(adc); + + reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); + reg32 |= (trigger | polarity); + ADC_CR2(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable an External Trigger for Regular Channels + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_external_trigger_regular(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable an External Trigger for Injected Channels + +This enables an external trigger for set of defined injected channels, and sets +the polarity of the trigger event: rising or falling edge or both. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_injected +*/ + +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity) +{ + uint32_t reg32 = ADC_CR2(adc); + + reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); + reg32 |= (trigger | polarity); + ADC_CR2(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable an External Trigger for Injected Channels + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_external_trigger_injected(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Resolution + +ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a +corresponding reduction in conversion time (resolution + 3 ADC clock cycles). + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] resolution Unsigned int32. Resolution value @ref adc_cr1_res +*/ + +void adc_set_resolution(uint32_t adc, uint32_t resolution) +{ + uint32_t reg32 = ADC_CR1(adc); + + reg32 &= ~ADC_CR1_RES_MASK; + reg32 |= resolution; + ADC_CR1(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable the Overrun Interrupt + +The overrun interrupt is generated when data is not read from a result register +before the next conversion is written. If DMA is enabled, all transfers are +terminated and any conversion sequence is aborted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_overrun_interrupt(uint32_t adc) +{ + ADC_CR1(adc) |= ADC_CR1_OVRIE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable the Overrun Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_overrun_interrupt(uint32_t adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_OVRIE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Read the Overrun Flag + +The overrun flag is set when data is not read from a result register before the +next conversion is written. If DMA is enabled, all transfers are terminated and +any conversion sequence is aborted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +bool adc_get_overrun_flag(uint32_t adc) +{ + return ADC_SR(adc) & ADC_SR_OVR; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Clear Overrun Flags + +The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. +The flag must be cleared and the DMA stream and ADC reinitialised to resume +conversions (see the reference manual). + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +void adc_clear_overrun_flag(uint32_t adc) +{ +/* need to write zero to clear this */ + ADC_SR(adc) &= ~ADC_SR_OVR; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable an EOC for Each Conversion + +The EOC is set after each conversion in a sequence rather than at the end of the +sequence. Overrun detection is enabled only if DMA is enabled. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_eoc_after_each(uint32_t adc) +{ + ADC_CR2(adc) |= ADC_CR2_EOCS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable the EOC for Each Conversion + +The EOC is set at the end of each sequence rather than after each conversion in +the sequence. Overrun detection is enabled always. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_eoc_after_group(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EOCS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set DMA to Continue + +This must be set to allow DMA to continue to operate after the last conversion +in the DMA sequence. This allows DMA to be used in continuous circular mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_dma_continue(uint32_t adc) +{ + ADC_CR2(adc) |= ADC_CR2_DDS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set DMA to Terminate + +This must be set to allow DMA to terminate after the last conversion in the DMA +sequence. This can avoid overrun errors. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_dma_terminate(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_DDS; +} +/*---------------------------------------------------------------------------*/ +/** @brief ADC Read the Analog Watchdog Flag + +This flag is set when the converted voltage crosses the high or low thresholds. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. AWD flag. +*/ + +bool adc_awd(uint32_t adc) +{ + return ADC_SR(adc) & ADC_SR_AWD; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable The Temperature Sensor + +This enables both the sensor and the reference voltage measurements on ADC1 +channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is +connected to ADC1 channel 18, the same as VBat. If both are enabled, only the +VBat conversion is performed. +*/ + +void adc_enable_temperature_sensor(void) +{ + ADC_CCR |= ADC_CCR_TSVREFE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable The Temperature Sensor + +Disabling this will reduce power consumption from the sensor and the reference +voltage measurements. +*/ + +void adc_disable_temperature_sensor(void) +{ + ADC_CCR &= ~ADC_CCR_TSVREFE; +} + +/** Enable The VBat Sensor. + * This enables the battery voltage measurements on ADC1 channel 18. On + * STM32F42x and STM32F43x, this must be disabled when the temperature sensor + * is enabled. If both are enabled, only the VBat conversion is performed. + */ +void adc_enable_vbat_sensor(void) +{ + ADC_CCR |= ADC_CCR_VBATE; +} + +/** Disable The VBat Sensor. + * Disabling this will reduce power consumption from the battery voltage + * measurement. + */ +void adc_disable_vbat_sensor(void) +{ + ADC_CCR &= ~ADC_CCR_VBATE; +} + +/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index aac2502c..45428ab7 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -39,7 +39,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \ +OBJS = adc_common_v3.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \ rtc.o crypto.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ diff --git a/lib/stm32/f4/adc.c b/lib/stm32/f4/adc.c deleted file mode 100644 index 020db884..00000000 --- a/lib/stm32/f4/adc.c +++ /dev/null @@ -1,448 +0,0 @@ -/** @addtogroup adc_file ADC peripheral API -@ingroup peripheral_apis - -@author @htmlonly © @endhtmlonly 2012 -Ken Sarkies - -@date 30 August 2012 - -This library supports the A/D Converter Control System in the STM32 series -of ARM Cortex Microcontrollers by ST Microelectronics. - -Devices can have up to three A/D converters each with their own set of -registers. However all the A/D converters share a common clock which is -prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum -of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. - -Each A/D converter has up to 19 channels: -@li On ADC1 the analog channels 16 is internally connected to the temperature -sensor, channel 17 to VREFINT, and channel 18 to VBAT. -@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. - -The conversions can occur as a one-off conversion whereby the process stops -once conversion is complete. The conversions can also be continuous wherein a -new conversion starts immediately the previous conversion has ended. - -Conversion can occur as a single channel conversion or a scan of a group of -channels in either continuous or one-off mode. If more than one channel is -converted in a scan group, DMA must be used to transfer the data as there is -only one result register available. An interrupt can be set to occur at the end -of conversion, which occurs after all channels have been scanned. - -A discontinuous mode allows a subgroup of group of a channels to be converted -in bursts of a given length. - -Injected conversions allow a second group of channels to be converted -separately from the regular group. An interrupt can be set to occur at the end -of conversion, which occurs after all channels have been scanned. - -@section adc_f4_api_ex Basic ADC Handling API. - -Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set the sample time to a -minimum of 3 cycles. Set multiple mode to independent. - -@code -gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); -rcc_periph_clock_enable(RCC_ADC1); -adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2); -adc_disable_scan_mode(ADC1); -adc_set_single_conversion_mode(ADC1); -adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_3CYC); -uint8_t channels[] = ADC_CHANNEL0; -adc_set_regular_sequence(ADC1, 1, channels); -adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); -adc_power_on(ADC1); -adc_start_conversion_regular(ADC1); -while (!adc_eoc(ADC1)); -reg16 = adc_read_regular(ADC1); -@endcode - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -/**@{*/ - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for a Single Channel - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref -adc_channel -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) -{ - uint32_t reg32; - - if (channel < 10) { - reg32 = ADC_SMPR2(adc); - reg32 &= ~(0x7 << (channel * 3)); - reg32 |= (time << (channel * 3)); - ADC_SMPR2(adc) = reg32; - } else { - reg32 = ADC_SMPR1(adc); - reg32 &= ~(0x7 << ((channel - 10) * 3)); - reg32 |= (time << ((channel - 10) * 3)); - ADC_SMPR1(adc) = reg32; - } -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for All Channels - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same -for all channels. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) -{ - uint8_t i; - uint32_t reg32 = 0; - - for (i = 0; i <= 9; i++) { - reg32 |= (time << (i * 3)); - } - ADC_SMPR2(adc) = reg32; - - for (i = 10; i <= 17; i++) { - reg32 |= (time << ((i - 10) * 3)); - } - ADC_SMPR1(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Power On - -If the ADC is in power-down mode then it is powered up. The application needs -to wait a time of about 3 microseconds for stabilization before using the ADC. -If the ADC is already on this function call will have no effect. - * NOTE Common with L1 and F2 - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_power_on(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_ADON; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Clock Prescale - -The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. - -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref -adc_ccr_adcpre -*/ - -void adc_set_clk_prescale(uint32_t prescale) -{ - uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale); - ADC_CCR = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Dual/Triple Mode - -The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave -arrangement. This setting is applied to ADC1 only. - -The various modes possible are described in the reference manual. - -@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode -*/ - -void adc_set_multi_mode(uint32_t mode) -{ - ADC_CCR |= mode; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Regular Channels - -This enables an external trigger for set of defined regular channels, and sets -the polarity of the trigger event: rising or falling edge or both. Note that if -the trigger polarity is zero, triggering is disabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_regular -*/ - -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Regular Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_external_trigger_regular(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Injected Channels - -This enables an external trigger for set of defined injected channels, and sets -the polarity of the trigger event: rising or falling edge or both. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_injected -*/ - -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Injected Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_external_trigger_injected(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Resolution - -ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a -corresponding reduction in conversion time (resolution + 3 ADC clock cycles). - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] resolution Unsigned int32. Resolution value @ref adc_cr1_res -*/ - -void adc_set_resolution(uint32_t adc, uint32_t resolution) -{ - uint32_t reg32 = ADC_CR1(adc); - - reg32 &= ~ADC_CR1_RES_MASK; - reg32 |= resolution; - ADC_CR1(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable the Overrun Interrupt - -The overrun interrupt is generated when data is not read from a result register -before the next conversion is written. If DMA is enabled, all transfers are -terminated and any conversion sequence is aborted. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_enable_overrun_interrupt(uint32_t adc) -{ - ADC_CR1(adc) |= ADC_CR1_OVRIE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable the Overrun Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_overrun_interrupt(uint32_t adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_OVRIE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Read the Overrun Flag - -The overrun flag is set when data is not read from a result register before the -next conversion is written. If DMA is enabled, all transfers are terminated and -any conversion sequence is aborted. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns Unsigned int32 conversion result. -*/ - -bool adc_get_overrun_flag(uint32_t adc) -{ - return ADC_SR(adc) & ADC_SR_OVR; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Clear Overrun Flags - -The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. -The flag must be cleared and the DMA stream and ADC reinitialised to resume -conversions (see the reference manual). - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns Unsigned int32 conversion result. -*/ - -void adc_clear_overrun_flag(uint32_t adc) -{ -/* need to write zero to clear this */ - ADC_SR(adc) &= ~ADC_SR_OVR; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an EOC for Each Conversion - -The EOC is set after each conversion in a sequence rather than at the end of the -sequence. Overrun detection is enabled only if DMA is enabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_eoc_after_each(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_EOCS; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable the EOC for Each Conversion - -The EOC is set at the end of each sequence rather than after each conversion in -the sequence. Overrun detection is enabled always. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_eoc_after_group(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EOCS; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set DMA to Continue - -This must be set to allow DMA to continue to operate after the last conversion -in the DMA sequence. This allows DMA to be used in continuous circular mode. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_set_dma_continue(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_DDS; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set DMA to Terminate - -This must be set to allow DMA to terminate after the last conversion in the DMA -sequence. This can avoid overrun errors. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_set_dma_terminate(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_DDS; -} -/*---------------------------------------------------------------------------*/ -/** @brief ADC Read the Analog Watchdog Flag - -This flag is set when the converted voltage crosses the high or low thresholds. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns bool. AWD flag. -*/ - -bool adc_awd(uint32_t adc) -{ - return ADC_SR(adc) & ADC_SR_AWD; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable The Temperature Sensor - -This enables both the sensor and the reference voltage measurements on ADC1 -channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is -connected to ADC1 channel 18, the same as VBat. If both are enabled, only the -VBat conversion is performed. -*/ - -void adc_enable_temperature_sensor(void) -{ - ADC_CCR |= ADC_CCR_TSVREFE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable The Temperature Sensor - -Disabling this will reduce power consumption from the sensor and the reference -voltage measurements. -*/ - -void adc_disable_temperature_sensor(void) -{ - ADC_CCR &= ~ADC_CCR_TSVREFE; -} - -/** Enable The VBat Sensor. - * This enables the battery voltage measurements on ADC1 channel 18. On - * STM32F42x and STM32F43x, this must be disabled when the temperature sensor - * is enabled. If both are enabled, only the VBat conversion is performed. - */ -void adc_enable_vbat_sensor(void) -{ - ADC_CCR |= ADC_CCR_VBATE; -} - -/** Disable The VBat Sensor. - * Disabling this will reduce power consumption from the battery voltage - * measurement. - */ -void adc_disable_vbat_sensor(void) -{ - ADC_CCR &= ~ADC_CCR_VBATE; -} - -/**@}*/ diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 6689143f..ce7ad334 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -42,6 +42,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs +OBJS += adc_common_v1.o adc_common_v3.o OBJS += can.o OBJS += crc_common_all.o crc_v2.o OBJS += dac_common_all.o -- cgit v1.2.3 From 0a3e1cc0e6c966c257d9ae9a61c369dd43485192 Mon Sep 17 00:00:00 2001 From: Matthew Lai Date: Sun, 5 May 2019 11:32:51 +0100 Subject: Renamed adc_common_v3 to adc_common_v1_multi --- lib/stm32/common/adc_common_v1_multi.c | 448 +++++++++++++++++++++++++++++++++ lib/stm32/common/adc_common_v3.c | 448 --------------------------------- lib/stm32/f4/Makefile | 2 +- lib/stm32/f7/Makefile | 2 +- 4 files changed, 450 insertions(+), 450 deletions(-) create mode 100644 lib/stm32/common/adc_common_v1_multi.c delete mode 100644 lib/stm32/common/adc_common_v3.c (limited to 'lib') diff --git a/lib/stm32/common/adc_common_v1_multi.c b/lib/stm32/common/adc_common_v1_multi.c new file mode 100644 index 00000000..020db884 --- /dev/null +++ b/lib/stm32/common/adc_common_v1_multi.c @@ -0,0 +1,448 @@ +/** @addtogroup adc_file ADC peripheral API +@ingroup peripheral_apis + +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +@date 30 August 2012 + +This library supports the A/D Converter Control System in the STM32 series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to three A/D converters each with their own set of +registers. However all the A/D converters share a common clock which is +prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum +of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. + +Each A/D converter has up to 19 channels: +@li On ADC1 the analog channels 16 is internally connected to the temperature +sensor, channel 17 to VREFINT, and channel 18 to VBAT. +@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. + +The conversions can occur as a one-off conversion whereby the process stops +once conversion is complete. The conversions can also be continuous wherein a +new conversion starts immediately the previous conversion has ended. + +Conversion can occur as a single channel conversion or a scan of a group of +channels in either continuous or one-off mode. If more than one channel is +converted in a scan group, DMA must be used to transfer the data as there is +only one result register available. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. + +A discontinuous mode allows a subgroup of group of a channels to be converted +in bursts of a given length. + +Injected conversions allow a second group of channels to be converted +separately from the regular group. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. + +@section adc_f4_api_ex Basic ADC Handling API. + +Example 1: Simple single channel conversion polled. Enable the peripheral clock +and ADC, reset ADC and set the prescaler divider. Set the sample time to a +minimum of 3 cycles. Set multiple mode to independent. + +@code +gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); +rcc_periph_clock_enable(RCC_ADC1); +adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2); +adc_disable_scan_mode(ADC1); +adc_set_single_conversion_mode(ADC1); +adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_3CYC); +uint8_t channels[] = ADC_CHANNEL0; +adc_set_regular_sequence(ADC1, 1, channels); +adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); +adc_power_on(ADC1); +adc_start_conversion_regular(ADC1); +while (!adc_eoc(ADC1)); +reg16 = adc_read_regular(ADC1); +@endcode + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for a Single Channel + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ + +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) +{ + uint32_t reg32; + + if (channel < 10) { + reg32 = ADC_SMPR2(adc); + reg32 &= ~(0x7 << (channel * 3)); + reg32 |= (time << (channel * 3)); + ADC_SMPR2(adc) = reg32; + } else { + reg32 = ADC_SMPR1(adc); + reg32 &= ~(0x7 << ((channel - 10) * 3)); + reg32 |= (time << ((channel - 10) * 3)); + ADC_SMPR1(adc) = reg32; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for All Channels + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ + +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) +{ + uint8_t i; + uint32_t reg32 = 0; + + for (i = 0; i <= 9; i++) { + reg32 |= (time << (i * 3)); + } + ADC_SMPR2(adc) = reg32; + + for (i = 10; i <= 17; i++) { + reg32 |= (time << ((i - 10) * 3)); + } + ADC_SMPR1(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Power On + +If the ADC is in power-down mode then it is powered up. The application needs +to wait a time of about 3 microseconds for stabilization before using the ADC. +If the ADC is already on this function call will have no effect. + * NOTE Common with L1 and F2 + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_power_on(uint32_t adc) +{ + ADC_CR2(adc) |= ADC_CR2_ADON; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Clock Prescale + +The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. + +@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref +adc_ccr_adcpre +*/ + +void adc_set_clk_prescale(uint32_t prescale) +{ + uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale); + ADC_CCR = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Dual/Triple Mode + +The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave +arrangement. This setting is applied to ADC1 only. + +The various modes possible are described in the reference manual. + +@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode +*/ + +void adc_set_multi_mode(uint32_t mode) +{ + ADC_CCR |= mode; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable an External Trigger for Regular Channels + +This enables an external trigger for set of defined regular channels, and sets +the polarity of the trigger event: rising or falling edge or both. Note that if +the trigger polarity is zero, triggering is disabled. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_regular +*/ + +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity) +{ + uint32_t reg32 = ADC_CR2(adc); + + reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); + reg32 |= (trigger | polarity); + ADC_CR2(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable an External Trigger for Regular Channels + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_external_trigger_regular(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable an External Trigger for Injected Channels + +This enables an external trigger for set of defined injected channels, and sets +the polarity of the trigger event: rising or falling edge or both. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_injected +*/ + +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity) +{ + uint32_t reg32 = ADC_CR2(adc); + + reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); + reg32 |= (trigger | polarity); + ADC_CR2(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable an External Trigger for Injected Channels + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_external_trigger_injected(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Resolution + +ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a +corresponding reduction in conversion time (resolution + 3 ADC clock cycles). + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] resolution Unsigned int32. Resolution value @ref adc_cr1_res +*/ + +void adc_set_resolution(uint32_t adc, uint32_t resolution) +{ + uint32_t reg32 = ADC_CR1(adc); + + reg32 &= ~ADC_CR1_RES_MASK; + reg32 |= resolution; + ADC_CR1(adc) = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable the Overrun Interrupt + +The overrun interrupt is generated when data is not read from a result register +before the next conversion is written. If DMA is enabled, all transfers are +terminated and any conversion sequence is aborted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_enable_overrun_interrupt(uint32_t adc) +{ + ADC_CR1(adc) |= ADC_CR1_OVRIE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable the Overrun Interrupt + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_disable_overrun_interrupt(uint32_t adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_OVRIE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Read the Overrun Flag + +The overrun flag is set when data is not read from a result register before the +next conversion is written. If DMA is enabled, all transfers are terminated and +any conversion sequence is aborted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +bool adc_get_overrun_flag(uint32_t adc) +{ + return ADC_SR(adc) & ADC_SR_OVR; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Clear Overrun Flags + +The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. +The flag must be cleared and the DMA stream and ADC reinitialised to resume +conversions (see the reference manual). + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +void adc_clear_overrun_flag(uint32_t adc) +{ +/* need to write zero to clear this */ + ADC_SR(adc) &= ~ADC_SR_OVR; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable an EOC for Each Conversion + +The EOC is set after each conversion in a sequence rather than at the end of the +sequence. Overrun detection is enabled only if DMA is enabled. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_eoc_after_each(uint32_t adc) +{ + ADC_CR2(adc) |= ADC_CR2_EOCS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable the EOC for Each Conversion + +The EOC is set at the end of each sequence rather than after each conversion in +the sequence. Overrun detection is enabled always. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_eoc_after_group(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EOCS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set DMA to Continue + +This must be set to allow DMA to continue to operate after the last conversion +in the DMA sequence. This allows DMA to be used in continuous circular mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_dma_continue(uint32_t adc) +{ + ADC_CR2(adc) |= ADC_CR2_DDS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set DMA to Terminate + +This must be set to allow DMA to terminate after the last conversion in the DMA +sequence. This can avoid overrun errors. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_set_dma_terminate(uint32_t adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_DDS; +} +/*---------------------------------------------------------------------------*/ +/** @brief ADC Read the Analog Watchdog Flag + +This flag is set when the converted voltage crosses the high or low thresholds. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. AWD flag. +*/ + +bool adc_awd(uint32_t adc) +{ + return ADC_SR(adc) & ADC_SR_AWD; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Enable The Temperature Sensor + +This enables both the sensor and the reference voltage measurements on ADC1 +channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is +connected to ADC1 channel 18, the same as VBat. If both are enabled, only the +VBat conversion is performed. +*/ + +void adc_enable_temperature_sensor(void) +{ + ADC_CCR |= ADC_CCR_TSVREFE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Disable The Temperature Sensor + +Disabling this will reduce power consumption from the sensor and the reference +voltage measurements. +*/ + +void adc_disable_temperature_sensor(void) +{ + ADC_CCR &= ~ADC_CCR_TSVREFE; +} + +/** Enable The VBat Sensor. + * This enables the battery voltage measurements on ADC1 channel 18. On + * STM32F42x and STM32F43x, this must be disabled when the temperature sensor + * is enabled. If both are enabled, only the VBat conversion is performed. + */ +void adc_enable_vbat_sensor(void) +{ + ADC_CCR |= ADC_CCR_VBATE; +} + +/** Disable The VBat Sensor. + * Disabling this will reduce power consumption from the battery voltage + * measurement. + */ +void adc_disable_vbat_sensor(void) +{ + ADC_CCR &= ~ADC_CCR_VBATE; +} + +/**@}*/ diff --git a/lib/stm32/common/adc_common_v3.c b/lib/stm32/common/adc_common_v3.c deleted file mode 100644 index 020db884..00000000 --- a/lib/stm32/common/adc_common_v3.c +++ /dev/null @@ -1,448 +0,0 @@ -/** @addtogroup adc_file ADC peripheral API -@ingroup peripheral_apis - -@author @htmlonly © @endhtmlonly 2012 -Ken Sarkies - -@date 30 August 2012 - -This library supports the A/D Converter Control System in the STM32 series -of ARM Cortex Microcontrollers by ST Microelectronics. - -Devices can have up to three A/D converters each with their own set of -registers. However all the A/D converters share a common clock which is -prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum -of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. - -Each A/D converter has up to 19 channels: -@li On ADC1 the analog channels 16 is internally connected to the temperature -sensor, channel 17 to VREFINT, and channel 18 to VBAT. -@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. - -The conversions can occur as a one-off conversion whereby the process stops -once conversion is complete. The conversions can also be continuous wherein a -new conversion starts immediately the previous conversion has ended. - -Conversion can occur as a single channel conversion or a scan of a group of -channels in either continuous or one-off mode. If more than one channel is -converted in a scan group, DMA must be used to transfer the data as there is -only one result register available. An interrupt can be set to occur at the end -of conversion, which occurs after all channels have been scanned. - -A discontinuous mode allows a subgroup of group of a channels to be converted -in bursts of a given length. - -Injected conversions allow a second group of channels to be converted -separately from the regular group. An interrupt can be set to occur at the end -of conversion, which occurs after all channels have been scanned. - -@section adc_f4_api_ex Basic ADC Handling API. - -Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set the sample time to a -minimum of 3 cycles. Set multiple mode to independent. - -@code -gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); -rcc_periph_clock_enable(RCC_ADC1); -adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2); -adc_disable_scan_mode(ADC1); -adc_set_single_conversion_mode(ADC1); -adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_3CYC); -uint8_t channels[] = ADC_CHANNEL0; -adc_set_regular_sequence(ADC1, 1, channels); -adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); -adc_power_on(ADC1); -adc_start_conversion_regular(ADC1); -while (!adc_eoc(ADC1)); -reg16 = adc_read_regular(ADC1); -@endcode - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -/**@{*/ - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for a Single Channel - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref -adc_channel -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) -{ - uint32_t reg32; - - if (channel < 10) { - reg32 = ADC_SMPR2(adc); - reg32 &= ~(0x7 << (channel * 3)); - reg32 |= (time << (channel * 3)); - ADC_SMPR2(adc) = reg32; - } else { - reg32 = ADC_SMPR1(adc); - reg32 &= ~(0x7 << ((channel - 10) * 3)); - reg32 |= (time << ((channel - 10) * 3)); - ADC_SMPR1(adc) = reg32; - } -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for All Channels - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same -for all channels. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) -{ - uint8_t i; - uint32_t reg32 = 0; - - for (i = 0; i <= 9; i++) { - reg32 |= (time << (i * 3)); - } - ADC_SMPR2(adc) = reg32; - - for (i = 10; i <= 17; i++) { - reg32 |= (time << ((i - 10) * 3)); - } - ADC_SMPR1(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Power On - -If the ADC is in power-down mode then it is powered up. The application needs -to wait a time of about 3 microseconds for stabilization before using the ADC. -If the ADC is already on this function call will have no effect. - * NOTE Common with L1 and F2 - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_power_on(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_ADON; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Clock Prescale - -The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. - -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref -adc_ccr_adcpre -*/ - -void adc_set_clk_prescale(uint32_t prescale) -{ - uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale); - ADC_CCR = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Dual/Triple Mode - -The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave -arrangement. This setting is applied to ADC1 only. - -The various modes possible are described in the reference manual. - -@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode -*/ - -void adc_set_multi_mode(uint32_t mode) -{ - ADC_CCR |= mode; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Regular Channels - -This enables an external trigger for set of defined regular channels, and sets -the polarity of the trigger event: rising or falling edge or both. Note that if -the trigger polarity is zero, triggering is disabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_regular -*/ - -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Regular Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_external_trigger_regular(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Injected Channels - -This enables an external trigger for set of defined injected channels, and sets -the polarity of the trigger event: rising or falling edge or both. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_injected -*/ - -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Injected Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_external_trigger_injected(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Resolution - -ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a -corresponding reduction in conversion time (resolution + 3 ADC clock cycles). - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] resolution Unsigned int32. Resolution value @ref adc_cr1_res -*/ - -void adc_set_resolution(uint32_t adc, uint32_t resolution) -{ - uint32_t reg32 = ADC_CR1(adc); - - reg32 &= ~ADC_CR1_RES_MASK; - reg32 |= resolution; - ADC_CR1(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable the Overrun Interrupt - -The overrun interrupt is generated when data is not read from a result register -before the next conversion is written. If DMA is enabled, all transfers are -terminated and any conversion sequence is aborted. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_enable_overrun_interrupt(uint32_t adc) -{ - ADC_CR1(adc) |= ADC_CR1_OVRIE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable the Overrun Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_overrun_interrupt(uint32_t adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_OVRIE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Read the Overrun Flag - -The overrun flag is set when data is not read from a result register before the -next conversion is written. If DMA is enabled, all transfers are terminated and -any conversion sequence is aborted. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns Unsigned int32 conversion result. -*/ - -bool adc_get_overrun_flag(uint32_t adc) -{ - return ADC_SR(adc) & ADC_SR_OVR; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Clear Overrun Flags - -The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. -The flag must be cleared and the DMA stream and ADC reinitialised to resume -conversions (see the reference manual). - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns Unsigned int32 conversion result. -*/ - -void adc_clear_overrun_flag(uint32_t adc) -{ -/* need to write zero to clear this */ - ADC_SR(adc) &= ~ADC_SR_OVR; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an EOC for Each Conversion - -The EOC is set after each conversion in a sequence rather than at the end of the -sequence. Overrun detection is enabled only if DMA is enabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_eoc_after_each(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_EOCS; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable the EOC for Each Conversion - -The EOC is set at the end of each sequence rather than after each conversion in -the sequence. Overrun detection is enabled always. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_eoc_after_group(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EOCS; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set DMA to Continue - -This must be set to allow DMA to continue to operate after the last conversion -in the DMA sequence. This allows DMA to be used in continuous circular mode. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_set_dma_continue(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_DDS; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set DMA to Terminate - -This must be set to allow DMA to terminate after the last conversion in the DMA -sequence. This can avoid overrun errors. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_set_dma_terminate(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_DDS; -} -/*---------------------------------------------------------------------------*/ -/** @brief ADC Read the Analog Watchdog Flag - -This flag is set when the converted voltage crosses the high or low thresholds. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns bool. AWD flag. -*/ - -bool adc_awd(uint32_t adc) -{ - return ADC_SR(adc) & ADC_SR_AWD; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable The Temperature Sensor - -This enables both the sensor and the reference voltage measurements on ADC1 -channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is -connected to ADC1 channel 18, the same as VBat. If both are enabled, only the -VBat conversion is performed. -*/ - -void adc_enable_temperature_sensor(void) -{ - ADC_CCR |= ADC_CCR_TSVREFE; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Disable The Temperature Sensor - -Disabling this will reduce power consumption from the sensor and the reference -voltage measurements. -*/ - -void adc_disable_temperature_sensor(void) -{ - ADC_CCR &= ~ADC_CCR_TSVREFE; -} - -/** Enable The VBat Sensor. - * This enables the battery voltage measurements on ADC1 channel 18. On - * STM32F42x and STM32F43x, this must be disabled when the temperature sensor - * is enabled. If both are enabled, only the VBat conversion is performed. - */ -void adc_enable_vbat_sensor(void) -{ - ADC_CCR |= ADC_CCR_VBATE; -} - -/** Disable The VBat Sensor. - * Disabling this will reduce power consumption from the battery voltage - * measurement. - */ -void adc_disable_vbat_sensor(void) -{ - ADC_CCR &= ~ADC_CCR_VBATE; -} - -/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 45428ab7..68411e96 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -39,7 +39,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc_common_v3.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \ +OBJS = adc_common_v1_multi.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \ rtc.o crypto.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index ce7ad334..a67e07e8 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -42,7 +42,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS += adc_common_v1.o adc_common_v3.o +OBJS += adc_common_v1.o adc_common_v1_multi.o OBJS += can.o OBJS += crc_common_all.o crc_v2.o OBJS += dac_common_all.o -- cgit v1.2.3 From f1340df003a2b3acfc67af9dfb403e77e4b15dee Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 9 May 2019 12:00:40 +0000 Subject: stm32f4: sort makefile objects --- lib/stm32/f4/Makefile | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 68411e96..ca298a25 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -39,28 +39,34 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc_common_v1_multi.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \ - rtc.o crypto.o - -OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ - gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \ - iwdg_common_all.o pwr_common_v1.o rtc_common_l1f024.o \ - timer_common_all.o \ - timer_common_f0234.o timer_common_f24.o usart_common_all.o \ - usart_common_f124.o \ - hash_common_f24.o crypto_common_f24.o exti_common_all.o \ - rcc_common_all.o +OBJS = adc_common_v1.o adc_common_v1_multi.o +OBJS += can.o +OBJS += crc_common_all.o +OBJS += crypto_common_f24.o crypto.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += exti_common_all.o OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o OBJS += flash_common_idcache.o +OBJS += fmc.o +OBJS += gpio_common_all.o gpio_common_f0234.o gpio.o +OBJS += hash_common_f24.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += ltdc.o +OBJS += pwr_common_v1.o pwr.o +OBJS += rcc_common_all.o rcc.o OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o rtc.o OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o - +OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o +OBJS += usart_common_all.o usart_common_f124.o + OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \ usb_f107.o usb_f207.o usb_msc.o -OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o fmc.o - -OBJS += ltdc.o +OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet -- cgit v1.2.3 From 8d9b455ac6d683b345030918eb50c40e8a349719 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 10 May 2019 22:40:55 +0000 Subject: stm32: adc-v1m: pull out f4/f7 specifics Sampling time and sequence length, along with the vbat channel are specific to the f4/f7, and can't be shared with the l1 and friends. Pull them out to their own common file. --- lib/stm32/common/adc_common_f47.c | 124 +++++++++++++++++++++++++++++++++ lib/stm32/common/adc_common_v1_multi.c | 88 ----------------------- lib/stm32/f4/Makefile | 2 +- lib/stm32/f7/Makefile | 2 +- 4 files changed, 126 insertions(+), 90 deletions(-) create mode 100644 lib/stm32/common/adc_common_f47.c (limited to 'lib') diff --git a/lib/stm32/common/adc_common_f47.c b/lib/stm32/common/adc_common_f47.c new file mode 100644 index 00000000..50abf2b2 --- /dev/null +++ b/lib/stm32/common/adc_common_f47.c @@ -0,0 +1,124 @@ +/** @addtogroup adc_file ADC peripheral API +@ingroup peripheral_apis + +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +@date 30 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for a Single Channel + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) +{ + uint32_t reg32; + + if (channel < 10) { + reg32 = ADC_SMPR2(adc); + reg32 &= ~(0x7 << (channel * 3)); + reg32 |= (time << (channel * 3)); + ADC_SMPR2(adc) = reg32; + } else { + reg32 = ADC_SMPR1(adc); + reg32 &= ~(0x7 << ((channel - 10) * 3)); + reg32 |= (time << ((channel - 10) * 3)); + ADC_SMPR1(adc) = reg32; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for All Channels + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) +{ + uint8_t i; + uint32_t reg32 = 0; + + for (i = 0; i <= 9; i++) { + reg32 |= (time << (i * 3)); + } + ADC_SMPR2(adc) = reg32; + + for (i = 10; i <= 17; i++) { + reg32 |= (time << ((i - 10) * 3)); + } + ADC_SMPR1(adc) = reg32; +} + + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Dual/Triple Mode + +The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave +arrangement. This setting is applied to ADC1 only. + +The various modes possible are described in the reference manual. + +@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode +*/ +void adc_set_multi_mode(uint32_t mode) +{ + ADC_CCR |= mode; +} + + +/** Enable The VBat Sensor. + * This enables the battery voltage measurements on ADC1 channel 18. On + * STM32F42x and STM32F43x, this must be disabled when the temperature sensor + * is enabled. If both are enabled, only the VBat conversion is performed. + */ +void adc_enable_vbat_sensor(void) +{ + ADC_CCR |= ADC_CCR_VBATE; +} + +/** Disable The VBat Sensor. + * Disabling this will reduce power consumption from the battery voltage + * measurement. + */ +void adc_disable_vbat_sensor(void) +{ + ADC_CCR &= ~ADC_CCR_VBATE; +} + +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/common/adc_common_v1_multi.c b/lib/stm32/common/adc_common_v1_multi.c index 020db884..8cca4387 100644 --- a/lib/stm32/common/adc_common_v1_multi.c +++ b/lib/stm32/common/adc_common_v1_multi.c @@ -83,61 +83,6 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for a Single Channel - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref -adc_channel -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) -{ - uint32_t reg32; - - if (channel < 10) { - reg32 = ADC_SMPR2(adc); - reg32 &= ~(0x7 << (channel * 3)); - reg32 |= (time << (channel * 3)); - ADC_SMPR2(adc) = reg32; - } else { - reg32 = ADC_SMPR1(adc); - reg32 &= ~(0x7 << ((channel - 10) * 3)); - reg32 |= (time << ((channel - 10) * 3)); - ADC_SMPR1(adc) = reg32; - } -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for All Channels - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same -for all channels. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) -{ - uint8_t i; - uint32_t reg32 = 0; - - for (i = 0; i <= 9; i++) { - reg32 |= (time << (i * 3)); - } - ADC_SMPR2(adc) = reg32; - - for (i = 10; i <= 17; i++) { - reg32 |= (time << ((i - 10) * 3)); - } - ADC_SMPR1(adc) = reg32; -} /*---------------------------------------------------------------------------*/ /** @brief ADC Power On @@ -170,22 +115,6 @@ void adc_set_clk_prescale(uint32_t prescale) ADC_CCR = reg32; } -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set Dual/Triple Mode - -The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave -arrangement. This setting is applied to ADC1 only. - -The various modes possible are described in the reference manual. - -@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode -*/ - -void adc_set_multi_mode(uint32_t mode) -{ - ADC_CCR |= mode; -} - /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels @@ -426,23 +355,6 @@ void adc_disable_temperature_sensor(void) ADC_CCR &= ~ADC_CCR_TSVREFE; } -/** Enable The VBat Sensor. - * This enables the battery voltage measurements on ADC1 channel 18. On - * STM32F42x and STM32F43x, this must be disabled when the temperature sensor - * is enabled. If both are enabled, only the VBat conversion is performed. - */ -void adc_enable_vbat_sensor(void) -{ - ADC_CCR |= ADC_CCR_VBATE; -} -/** Disable The VBat Sensor. - * Disabling this will reduce power consumption from the battery voltage - * measurement. - */ -void adc_disable_vbat_sensor(void) -{ - ADC_CCR &= ~ADC_CCR_VBATE; -} /**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index ca298a25..3d101568 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -39,7 +39,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc_common_v1.o adc_common_v1_multi.o +OBJS = adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o OBJS += can.o OBJS += crc_common_all.o OBJS += crypto_common_f24.o crypto.o diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index a67e07e8..dc5b0ad2 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -42,7 +42,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS += adc_common_v1.o adc_common_v1_multi.o +OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o OBJS += can.o OBJS += crc_common_all.o crc_v2.o OBJS += dac_common_all.o -- cgit v1.2.3 From 13d46e81df71f0b8ed4fa10a24c3ab3839b65c2a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 10 May 2019 22:42:44 +0000 Subject: stm32l1: adc: use v1-m shared code. Drops all the l1 copies of this code, and automatically gains all the following apis that weren't even available before: void adc_set_clk_prescale(uint32_t prescaler); void adc_set_resolution(uint32_t adc, uint32_t resolution); void adc_enable_overrun_interrupt(uint32_t adc); void adc_disable_overrun_interrupt(uint32_t adc); bool adc_get_overrun_flag(uint32_t adc); void adc_clear_overrun_flag(uint32_t adc); bool adc_awd(uint32_t adc); void adc_eoc_after_each(uint32_t adc); void adc_eoc_after_group(uint32_t adc); void adc_set_dma_continue(uint32_t adc); void adc_set_dma_terminate(uint32_t adc); --- lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/adc.c | 108 -------------------------------------------------- 2 files changed, 1 insertion(+), 109 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index ec1ea928..db8f3bf8 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -47,7 +47,7 @@ OBJS += timer_common_all.o OBJS += usart_common_all.o usart_common_f124.o OBJS += exti_common_all.o OBJS += rcc_common_all.o -OBJS += adc.o adc_common_v1.o +OBJS += adc.o adc_common_v1.o adc_common_v1_multi.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o OBJS += st_usbfs_core.o st_usbfs_v1.o diff --git a/lib/stm32/l1/adc.c b/lib/stm32/l1/adc.c index 1768437d..e2d3e4b8 100644 --- a/lib/stm32/l1/adc.c +++ b/lib/stm32/l1/adc.c @@ -29,23 +29,6 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*---------------------------------------------------------------------------*/ -/** @brief ADC Power On - -If the ADC is in power-down mode then it is powered up. The application needs -to wait a time of about 3 microseconds for stabilization before using the ADC. -If the ADC is already on this function call will have no effect. - * NOTE Common with F4 and F2 - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_power_on(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_ADON; -} - - /*----------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel @@ -102,97 +85,6 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) ADC_SMPR3(adc) = reg32; } -/*----------------------------------------------------------------------------*/ -/** @brief ADC Enable The Temperature Sensor - -This enables both the sensor and the reference voltage measurements on channels -16 and 17. - -*/ -void adc_enable_temperature_sensor() -{ - ADC_CCR |= ADC_CCR_TSVREFE; -} - -/*----------------------------------------------------------------------------*/ -/** @brief ADC Disable The Temperature Sensor - -Disabling this will reduce power consumption from the sensor and the reference -voltage measurements. - -*/ -void adc_disable_temperature_sensor() -{ - ADC_CCR &= ~ADC_CCR_TSVREFE; -} - -/*----------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Regular Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_external_trigger_regular(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; -} - -/*----------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Injected Channels - -@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base. -*/ - -void adc_disable_external_trigger_injected(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Regular Channels - -This enables an external trigger for set of defined regular channels, and sets -the polarity of the trigger event: rising or falling edge or both. Note that if -the trigger polarity is zero, triggering is disabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_regular -*/ - -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Injected Channels - -This enables an external trigger for set of defined injected channels, and sets -the polarity of the trigger event: rising or falling edge or both. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_injected -*/ - -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - /**@}*/ -- cgit v1.2.3 From e77bc94b8cb5c52d6fad4d94321bf389db857fb8 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 10 May 2019 23:15:42 +0000 Subject: stm32: adc-v1m: doc cleanups Try and fix some of the specifics from old f4 source material. --- lib/stm32/common/adc_common_v1_multi.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/adc_common_v1_multi.c b/lib/stm32/common/adc_common_v1_multi.c index 8cca4387..eb368cde 100644 --- a/lib/stm32/common/adc_common_v1_multi.c +++ b/lib/stm32/common/adc_common_v1_multi.c @@ -14,10 +14,14 @@ registers. However all the A/D converters share a common clock which is prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. -Each A/D converter has up to 19 channels: -@li On ADC1 the analog channels 16 is internally connected to the temperature -sensor, channel 17 to VREFINT, and channel 18 to VBAT. -@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. +Each A/D converter has multiple channels, not all of which might be available +externally. Internal channels can be used for the the temperature sensor, +VBat monitoring, and the internal reference voltage VREFINT. Consult the +Reference manual for the specifics of your part. +@sa ADC_MAX_CHANNELS +@sa ADC_CHANNEL_TEMP +@sa ADC_CHANNEL_VREF +@sa ADC_CHANNEL_VBAT The conversions can occur as a one-off conversion whereby the process stops once conversion is complete. The conversions can also be continuous wherein a @@ -36,7 +40,7 @@ Injected conversions allow a second group of channels to be converted separately from the regular group. An interrupt can be set to occur at the end of conversion, which occurs after all channels have been scanned. -@section adc_f4_api_ex Basic ADC Handling API. +@section adc_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock and ADC, reset ADC and set the prescaler divider. Set the sample time to a @@ -102,11 +106,9 @@ void adc_power_on(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale - -The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. - -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref -adc_ccr_adcpre +The ADC clock can be prescaled. +The Clock sources and scaler values are part specific. +@param[in] prescale Prescale value for ADC Clock @ref adc_ccr_adcpre */ void adc_set_clk_prescale(uint32_t prescale) @@ -332,8 +334,8 @@ bool adc_awd(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor -This enables both the sensor and the reference voltage measurements on ADC1 -channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is +This enables both the sensor and the reference voltage measurements on ADC1. +On STM32F42x and STM32F43x, the temperature sensor is connected to ADC1 channel 18, the same as VBat. If both are enabled, only the VBat conversion is performed. */ @@ -355,6 +357,4 @@ void adc_disable_temperature_sensor(void) ADC_CCR &= ~ADC_CCR_TSVREFE; } - - /**@}*/ -- cgit v1.2.3 From 4fc7196463e794ee634610c13ab663574f7e90fa Mon Sep 17 00:00:00 2001 From: Oliver Meier Date: Sat, 11 May 2019 02:26:10 +0200 Subject: stm32f7: enable existing exti headers --- lib/stm32/common/exti_common_all.c | 2 +- lib/stm32/f7/Makefile | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index 5a88b232..a690ca26 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -17,7 +17,7 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * - * This provides the code for the "next gen" EXTI block provided in F2/F4/L1 + * This provides the code for the "next gen" EXTI block provided in F2/F4/F7/L1 * devices. (differences only in the source selection) */ /**@{*/ diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index dc5b0ad2..bbad11d6 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -48,6 +48,7 @@ OBJS += crc_common_all.o crc_v2.o OBJS += dac_common_all.o OBJS += desig.o OBJS += dma_common_f24.o +OBJS += exti_common_all.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o -- cgit v1.2.3 From 16cfc6d8488741f7acc6da4f04ecea59b04007c6 Mon Sep 17 00:00:00 2001 From: Oliver Meier Date: Mon, 1 Apr 2019 00:52:30 +0200 Subject: stm32f7: enable fsmc This uses the existing f4 code as a new shared common base code. --- lib/stm32/common/fmc_common_f47.c | 111 ++++++++++++++++++++++++++++++++++++++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/fmc.c | 99 ---------------------------------- lib/stm32/f7/Makefile | 1 + 4 files changed, 113 insertions(+), 100 deletions(-) create mode 100644 lib/stm32/common/fmc_common_f47.c delete mode 100644 lib/stm32/f4/fmc.c (limited to 'lib') diff --git a/lib/stm32/common/fmc_common_f47.c b/lib/stm32/common/fmc_common_f47.c new file mode 100644 index 00000000..1a5bc027 --- /dev/null +++ b/lib/stm32/common/fmc_common_f47.c @@ -0,0 +1,111 @@ +/** @addtogroup fmc_file FMC peripheral API +@ingroup peripheral_apis + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net + +This library supports the Flexible Memory Controller in the STM32F4xx and +STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. +*/ +/* + * + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Utility functions for the SDRAM component of the FMC */ + +#include +#include + +/**@{*/ + +/* + * Install various timing values into the correct place in the + * SDRAM Timing Control Register format. + * + * Note that the register is 'zero' based to save bits so 1 cycle + * is stored as '0'. This command takes actual cycles and adjusts + * by subtracting 1. + */ +uint32_t +sdram_timing(struct sdram_timing *t) { + uint32_t result; + + result = 0; + result |= ((t->trcd - 1) & 0xf) << FMC_SDTR_TRCD_SHIFT; + result |= ((t->trp - 1) & 0xf) << FMC_SDTR_TRP_SHIFT; + result |= ((t->twr - 1) & 0xf) << FMC_SDTR_TWR_SHIFT; + result |= ((t->trc - 1) & 0xf) << FMC_SDTR_TRC_SHIFT; + result |= ((t->tras - 1) & 0xf) << FMC_SDTR_TRAS_SHIFT; + result |= ((t->txsr - 1) & 0xf) << FMC_SDTR_TXSR_SHIFT; + result |= ((t->tmrd - 1) & 0xf) << FMC_SDTR_TMRD_SHIFT; + return result; +} + +/* + * Send a command to the SDRAM controller, wait until it is not + * busy before sending. This allows you to chain sending commands + * and the code will pause as needed between them. + */ +void +sdram_command(enum fmc_sdram_bank bank, + enum fmc_sdram_command cmd, int autorefresh, int modereg) { + uint32_t tmp_reg = 0; + + switch (bank) { + case SDRAM_BANK1: + tmp_reg = FMC_SDCMR_CTB1; + break; + case SDRAM_BANK2: + tmp_reg = FMC_SDCMR_CTB2; + break; + case SDRAM_BOTH_BANKS: + tmp_reg = FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; + break; + } + tmp_reg |= autorefresh << FMC_SDCMR_NRFS_SHIFT; + tmp_reg |= modereg << FMC_SDCMR_MRD_SHIFT; + switch (cmd) { + case SDRAM_CLK_CONF: + tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA; + break; + case SDRAM_AUTO_REFRESH: + tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH; + break; + case SDRAM_LOAD_MODE: + tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER; + break; + case SDRAM_PALL: + tmp_reg |= FMC_SDCMR_MODE_PALL; + break; + case SDRAM_SELF_REFRESH: + tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH; + break; + case SDRAM_POWER_DOWN: + tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN; + break; + case SDRAM_NORMAL: + default: + break; + } + + /* Wait for the next chance to talk to the controller */ + while (FMC_SDSR & FMC_SDSR_BUSY); + + /* Send the next command */ + FMC_SDCMR = tmp_reg; +} + +/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 3d101568..800d3137 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -49,7 +49,7 @@ OBJS += dma_common_f24.o OBJS += exti_common_all.o OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o OBJS += flash_common_idcache.o -OBJS += fmc.o +OBJS += fmc_common_f47.o OBJS += gpio_common_all.o gpio_common_f0234.o gpio.o OBJS += hash_common_f24.o OBJS += i2c_common_v1.o diff --git a/lib/stm32/f4/fmc.c b/lib/stm32/f4/fmc.c deleted file mode 100644 index 1c30dd67..00000000 --- a/lib/stm32/f4/fmc.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/* Utility functions for the SDRAM component of the FMC */ - -#include -#include - -/* - * Install various timing values into the correct place in the - * SDRAM Timing Control Register format. - * - * Note that the register is 'zero' based to save bits so 1 cycle - * is stored as '0'. This command takes actual cycles and adjusts - * by subtracting 1. - */ -uint32_t -sdram_timing(struct sdram_timing *t) { - uint32_t result; - - result = 0; - result |= ((t->trcd - 1) & 0xf) << FMC_SDTR_TRCD_SHIFT; - result |= ((t->trp - 1) & 0xf) << FMC_SDTR_TRP_SHIFT; - result |= ((t->twr - 1) & 0xf) << FMC_SDTR_TWR_SHIFT; - result |= ((t->trc - 1) & 0xf) << FMC_SDTR_TRC_SHIFT; - result |= ((t->tras - 1) & 0xf) << FMC_SDTR_TRAS_SHIFT; - result |= ((t->txsr - 1) & 0xf) << FMC_SDTR_TXSR_SHIFT; - result |= ((t->tmrd - 1) & 0xf) << FMC_SDTR_TMRD_SHIFT; - return result; -} - -/* - * Send a command to the SDRAM controller, wait until it is not - * busy before sending. This allows you to chain sending commands - * and the code will pause as needed between them. - */ -void -sdram_command(enum fmc_sdram_bank bank, - enum fmc_sdram_command cmd, int autorefresh, int modereg) { - uint32_t tmp_reg = 0; - - switch (bank) { - case SDRAM_BANK1: - tmp_reg = FMC_SDCMR_CTB1; - break; - case SDRAM_BANK2: - tmp_reg = FMC_SDCMR_CTB2; - break; - case SDRAM_BOTH_BANKS: - tmp_reg = FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; - break; - } - tmp_reg |= autorefresh << FMC_SDCMR_NRFS_SHIFT; - tmp_reg |= modereg << FMC_SDCMR_MRD_SHIFT; - switch (cmd) { - case SDRAM_CLK_CONF: - tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA; - break; - case SDRAM_AUTO_REFRESH: - tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH; - break; - case SDRAM_LOAD_MODE: - tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER; - break; - case SDRAM_PALL: - tmp_reg |= FMC_SDCMR_MODE_PALL; - break; - case SDRAM_SELF_REFRESH: - tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH; - break; - case SDRAM_POWER_DOWN: - tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN; - break; - case SDRAM_NORMAL: - default: - break; - } - - /* Wait for the next chance to talk to the controller */ - while (FMC_SDSR & FMC_SDSR_BUSY); - - /* Send the next command */ - FMC_SDCMR = tmp_reg; -} diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index bbad11d6..409a550f 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -50,6 +50,7 @@ OBJS += desig.o OBJS += dma_common_f24.o OBJS += exti_common_all.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o +OBJS += fmc_common_f47.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o -- cgit v1.2.3 From 5a03cfe54e8fe4af5f59c9f1f57f99f679e7fa84 Mon Sep 17 00:00:00 2001 From: Oliver Meier Date: Sun, 7 Apr 2019 21:04:01 +0200 Subject: stm32f7: enable existing ltdc This uses the existing f4 code as a new shared common base code. --- lib/stm32/common/ltdc_common_f47.c | 87 +++++++++++++++++++++++++++++++++++++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/ltdc.c | 89 -------------------------------------- lib/stm32/f7/Makefile | 1 + 4 files changed, 89 insertions(+), 90 deletions(-) create mode 100644 lib/stm32/common/ltdc_common_f47.c delete mode 100644 lib/stm32/f4/ltdc.c (limited to 'lib') diff --git a/lib/stm32/common/ltdc_common_f47.c b/lib/stm32/common/ltdc_common_f47.c new file mode 100644 index 00000000..3255f356 --- /dev/null +++ b/lib/stm32/common/ltdc_common_f47.c @@ -0,0 +1,87 @@ +/** @defgroup ltdc_file LTDC peripheral API + * + * @ingroup peripheral_apis + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2014 + * Oliver Meier + * + * @date 5 December 2014 + * + * This library supports the LCD controller (LTDC) in the STM32F4xx and + * STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Oliver Meier + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +void ltdc_set_tft_sync_timings(uint16_t sync_width, uint16_t sync_height, + uint16_t h_back_porch, uint16_t v_back_porch, + uint16_t active_width, uint16_t active_height, + uint16_t h_front_porch, uint16_t v_front_porch) +{ + /*assert((active_width <= 0x400) && (active_height <= 0x300));*/ + + uint16_t w, h; + w = sync_width - 1; + h = sync_height - 1; + /*assert((w&0xfff == w) && (h&0x7ff == h));*/ + LTDC_SSCR = (w << 16) | (h << 0); + + w += h_back_porch; + h += v_back_porch; + /*assert((w&0xfff == w) && (h&0x7ff == h));*/ + LTDC_BPCR = (w << 16) | (h << 0); + + w += active_width; + h += active_height; + /*assert((w&0xfff == w) && (h&0x7ff == h));*/ + LTDC_AWCR = (w << 16) | (h << 0); + + w += h_front_porch; + h += v_front_porch; + /*assert((w&0xfff == w) && (h&0x7ff == h));*/ + LTDC_TWCR = (w << 16) | (h << 0); +} + +void ltdc_setup_windowing(uint8_t layer_number, + uint16_t h_back_porch, uint16_t v_back_porch, + uint16_t active_width, uint16_t active_height) +{ + active_width += h_back_porch - 1; + active_height += v_back_porch - 1; + /*assert((h_back_porch & 0xfff == h_back_porch) && + (v_back_porch & 0xfff == v_back_porch) && + (active_width & 0xfff == active_width) && + (active_height & 0xfff == active_height));*/ + LTDC_LxWHPCR(layer_number) = (active_width << 16) | + (h_back_porch << 0); + LTDC_LxWVPCR(layer_number) = (active_height << 16) | + (v_back_porch << 0); +} + +/**@}*/ + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 800d3137..3fb41586 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -54,7 +54,7 @@ OBJS += gpio_common_all.o gpio_common_f0234.o gpio.o OBJS += hash_common_f24.o OBJS += i2c_common_v1.o OBJS += iwdg_common_all.o -OBJS += ltdc.o +OBJS += ltdc_common_f47.o OBJS += pwr_common_v1.o pwr.o OBJS += rcc_common_all.o rcc.o OBJS += rng_common_v1.o diff --git a/lib/stm32/f4/ltdc.c b/lib/stm32/f4/ltdc.c deleted file mode 100644 index 83a13961..00000000 --- a/lib/stm32/f4/ltdc.c +++ /dev/null @@ -1,89 +0,0 @@ -/** @defgroup ltdc_file LTDC - * - * @ingroup STM32F4xx - * - * @brief libopencm3 STM32F4xx LTDC - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Oliver Meier - * - * @date 5 December 2014 - * - * This library supports the LCD controller (LTDC) in the STM32F4 - * series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * For the STM32F4xx, LTDC is described in LCD-TFT Controller (LTDC) - * section 16 of the STM32F4xx Reference Manual (RM0090,Rev8). - * - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Oliver Meier - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - -void ltdc_set_tft_sync_timings(uint16_t sync_width, uint16_t sync_height, - uint16_t h_back_porch, uint16_t v_back_porch, - uint16_t active_width, uint16_t active_height, - uint16_t h_front_porch, uint16_t v_front_porch) -{ - /*assert((active_width <= 0x400) && (active_height <= 0x300));*/ - - uint16_t w, h; - w = sync_width - 1; - h = sync_height - 1; - /*assert((w&0xfff == w) && (h&0x7ff == h));*/ - LTDC_SSCR = (w << 16) | (h << 0); - - w += h_back_porch; - h += v_back_porch; - /*assert((w&0xfff == w) && (h&0x7ff == h));*/ - LTDC_BPCR = (w << 16) | (h << 0); - - w += active_width; - h += active_height; - /*assert((w&0xfff == w) && (h&0x7ff == h));*/ - LTDC_AWCR = (w << 16) | (h << 0); - - w += h_front_porch; - h += v_front_porch; - /*assert((w&0xfff == w) && (h&0x7ff == h));*/ - LTDC_TWCR = (w << 16) | (h << 0); -} - -void ltdc_setup_windowing(uint8_t layer_number, - uint16_t h_back_porch, uint16_t v_back_porch, - uint16_t active_width, uint16_t active_height) -{ - active_width += h_back_porch - 1; - active_height += v_back_porch - 1; - /*assert((h_back_porch & 0xfff == h_back_porch) && - (v_back_porch & 0xfff == v_back_porch) && - (active_width & 0xfff == active_width) && - (active_height & 0xfff == active_height));*/ - LTDC_LxWHPCR(layer_number) = (active_width << 16) | - (h_back_porch << 0); - LTDC_LxWVPCR(layer_number) = (active_height << 16) | - (v_back_porch << 0); -} - diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 409a550f..5e2df7ed 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -54,6 +54,7 @@ OBJS += fmc_common_f47.o OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += ltdc_common_f47.o OBJS += pwr.o rcc.o OBJS += rcc_common_all.o OBJS += rng_common_v1.o -- cgit v1.2.3 From 92a23405516f0b626ba4de654f374a1a1d4389b5 Mon Sep 17 00:00:00 2001 From: Oliver Meier Date: Sun, 12 May 2019 01:43:50 +0200 Subject: stm32f7: enable existing dsi support --- lib/stm32/common/dsi_common_f47.c | 34 ++++++++++++++++++++++++++++++++++ lib/stm32/f4/Makefile | 1 + lib/stm32/f7/Makefile | 1 + 3 files changed, 36 insertions(+) create mode 100644 lib/stm32/common/dsi_common_f47.c (limited to 'lib') diff --git a/lib/stm32/common/dsi_common_f47.c b/lib/stm32/common/dsi_common_f47.c new file mode 100644 index 00000000..17d875d7 --- /dev/null +++ b/lib/stm32/common/dsi_common_f47.c @@ -0,0 +1,34 @@ +/** @defgroup dsi_file DSI peripheral API + * + * @ingroup peripheral_apis + * + * @version 1.0.0 + * + * This library supports the Display Serial Interface Host and Wrapper in + * the STM32F4xx and STM32F7xx series of ARM Cortex Microcontrollers by + * ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 3fb41586..671effc5 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -46,6 +46,7 @@ OBJS += crypto_common_f24.o crypto.o OBJS += dac_common_all.o OBJS += desig.o OBJS += dma_common_f24.o +OBJS += dsi_common_f47.o OBJS += exti_common_all.o OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o OBJS += flash_common_idcache.o diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 5e2df7ed..fdf45b53 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -48,6 +48,7 @@ OBJS += crc_common_all.o crc_v2.o OBJS += dac_common_all.o OBJS += desig.o OBJS += dma_common_f24.o +OBJS += dsi_common_f47.o OBJS += exti_common_all.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += fmc_common_f47.o -- cgit v1.2.3 From 07868ad8b6d8086e77c0e2e1b4e2b837a54f7431 Mon Sep 17 00:00:00 2001 From: Oliver Meier Date: Sat, 11 May 2019 03:14:54 +0200 Subject: stm32f7: enable existing dma2d headers --- lib/stm32/common/dma2d_common_f47.c | 33 +++++++++++++++++++++++++++++++++ lib/stm32/f4/Makefile | 1 + lib/stm32/f7/Makefile | 1 + 3 files changed, 35 insertions(+) create mode 100644 lib/stm32/common/dma2d_common_f47.c (limited to 'lib') diff --git a/lib/stm32/common/dma2d_common_f47.c b/lib/stm32/common/dma2d_common_f47.c new file mode 100644 index 00000000..013292a0 --- /dev/null +++ b/lib/stm32/common/dma2d_common_f47.c @@ -0,0 +1,33 @@ +/** @defgroup dma2d_file DMA2D peripheral API + * + * @ingroup peripheral_apis + * + * @version 1.0.0 + * + * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx + * series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/**@{*/ + +/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 671effc5..9728e3be 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -46,6 +46,7 @@ OBJS += crypto_common_f24.o crypto.o OBJS += dac_common_all.o OBJS += desig.o OBJS += dma_common_f24.o +OBJS += dma2d_common_f47.o OBJS += dsi_common_f47.o OBJS += exti_common_all.o OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index fdf45b53..466ca351 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -48,6 +48,7 @@ OBJS += crc_common_all.o crc_v2.o OBJS += dac_common_all.o OBJS += desig.o OBJS += dma_common_f24.o +OBJS += dma2d_common_f47.o OBJS += dsi_common_f47.o OBJS += exti_common_all.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o -- cgit v1.2.3 From b8d4b037229b9f3faecd905f3ef16d3fa849ce74 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 23 Jan 2019 19:00:51 +0100 Subject: stm32g0: add base, irqs, memorymap and current devices. --- lib/dispatch/vector_nvic.c | 2 ++ lib/stm32/g0/Makefile | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 lib/stm32/g0/Makefile (limited to 'lib') diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 0f0d4062..c7221c87 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -16,6 +16,8 @@ # include "../stm32/l1/vector_nvic.c" #elif defined(STM32L4) # include "../stm32/l4/vector_nvic.c" +#elif defined(STM32G0) +# include "../stm32/g0/vector_nvic.c" #elif defined(GD32F1X0) # include "../gd32/f1x0/vector_nvic.c" diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile new file mode 100644 index 00000000..2893c262 --- /dev/null +++ b/lib/stm32/g0/Makefile @@ -0,0 +1,44 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Guillaume Revaillot +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_stm32g0 +SRCLIBDIR ?= ../.. + +PREFIX ?= arm-none-eabi + +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) \ + -ffunction-sections -fdata-sections -MD -DSTM32G0 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) + +ARFLAGS = rcs + +OBJS += + + +VPATH +=../:../../cm3:../common + +include ../../Makefile.include -- cgit v1.2.3 From c49937a09cac757d560c1d6165fb78d6512dfd83 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 10 Jan 2019 16:24:02 +0100 Subject: stm32g0: add gpio. regular peripheral. --- lib/stm32/g0/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 2893c262..a3d05553 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -36,7 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS += +OBJS = gpio_common_all.o gpio_common_f0234.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From f13a9eee5b16f8b34d22744730fead6bdd05b522 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 16 Jan 2019 17:41:42 +0100 Subject: stm32g0: add power. neither v1 nor v2... --- lib/stm32/g0/Makefile | 4 +-- lib/stm32/g0/pwr.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 lib/stm32/g0/pwr.c (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index a3d05553..fbe252a9 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -36,8 +36,8 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_f0234.o - +OBJS = gpio_common_all.o gpio_common_f0234.o +OBJS += pwr.o VPATH +=../:../../cm3:../common diff --git a/lib/stm32/g0/pwr.c b/lib/stm32/g0/pwr.c new file mode 100644 index 00000000..b366760b --- /dev/null +++ b/lib/stm32/g0/pwr.c @@ -0,0 +1,99 @@ +/** @defgroup pwr_file PWR + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot + * + * @ingroup STM32G0xx + * + * @brief libopencm3 STM32G0xx Power Control + * + * @version 1.0.0 + * + * This library supports the power control system for the + * STM32G0 series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/**@{*/ +#include + +/*---------------------------------------------------------------------------*/ +/** @brief Setup voltage scaling range. + */ +void pwr_set_vos_scale(enum pwr_vos_scale scale) +{ + uint32_t reg32; + + reg32 = PWR_CR1 & ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT); + reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT; + PWR_CR1 = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable RTC domain write protect. + */ +void pwr_disable_backup_domain_write_protect(void) +{ + PWR_CR1 |= PWR_CR1_DBP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable RTC domain write protect. + */ +void pwr_enable_backup_domain_write_protect(void) +{ + PWR_CR1 &= ~PWR_CR1_DBP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Select the low power mode used in deep sleep. + * @param lpms low power mode @ref pwr_cr1_lpms + */ +void pwr_set_low_power_mode_selection(uint32_t lpms) +{ + uint32_t reg32; + + reg32 = PWR_CR1; + reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT); + PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT)); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable Power Voltage Detector. + * @param[in] pvdr_level Power Voltage Detector Rising Threshold voltage @ref pwr_cr2_pvdrt. + * @param[in] pvdf_level Power Voltage Detector Falling Threshold voltage @ref pwr_cr2_pvdft. +*/ +void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level) +{ + uint32_t reg32; + + reg32 = PWR_CR2; + reg32 &= ~(PWR_CR2_PVDRT_MASK << PWR_CR2_PVDRT_SHIFT); + reg32 &= ~(PWR_CR2_PVDFT_MASK << PWR_CR2_PVDFT_SHIFT); + PWR_CR2 = (reg32 | (pvdf_level << PWR_CR2_PVDFT_SHIFT) | (pvdr_level << PWR_CR2_PVDRT_SHIFT) | PWR_CR2_PVDE); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable Power Voltage Detector. +*/ +void pwr_disable_power_voltage_detect(void) +{ + PWR_CR2 &= ~PWR_CR2_PVDE; +} + +/**@}*/ -- cgit v1.2.3 From cbe5425090750bb4981052b387994a301bdc2973 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 10 Jan 2019 18:41:56 +0100 Subject: stm32g0: add flash. here, it's a bit of a mess.. G0 flash controller does not really match exsting feature split. IE it has instruction cache only .. so, no flash_idcache.c as it. flash_common_f could be used, but flash_unlock would not take care of option byte ? prefetch, icache and lock is ok. I had no look at flash programming or erase yet.. --- lib/stm32/g0/Makefile | 3 +- lib/stm32/g0/flash.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 lib/stm32/g0/flash.c (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index fbe252a9..dcb34bae 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -36,7 +36,8 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_f0234.o +OBJS += flash.o flash_common_all.o +OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += pwr.o VPATH +=../:../../cm3:../common diff --git a/lib/stm32/g0/flash.c b/lib/stm32/g0/flash.c new file mode 100644 index 00000000..9096723d --- /dev/null +++ b/lib/stm32/g0/flash.c @@ -0,0 +1,83 @@ +/** @defgroup flash_file FLASH + * + * @ingroup STM32G0xx + * + * @brief libopencm3 STM32G0xx FLASH + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/* @brief Enable instruction cache */ +void flash_icache_enable(void) +{ + FLASH_ACR |= FLASH_ACR_ICEN; +} + +/* @brief Disable instruction cache */ +void flash_icache_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_ICEN; +} + +/* @brief Reset instruction cache */ +void flash_icache_reset(void) +{ + FLASH_ACR |= FLASH_ACR_ICRST; +} + +/* @brief Unlock program memory */ +void flash_unlock_progmem(void) +{ + FLASH_KEYR = FLASH_KEYR_KEY1; + FLASH_KEYR = FLASH_KEYR_KEY2; +} + +/* @brief lock program memory */ +void flash_lock_progmem(void) +{ + FLASH_CR |= FLASH_CR_LOCK; +} + +/* @brief Lock Option Byte Access */ +void flash_lock_option_bytes(void) +{ + FLASH_CR |= FLASH_CR_OPTLOCK; +} + +/* @brief Unlock all segments of flash */ +void flash_unlock(void) +{ + flash_unlock_progmem(); + flash_unlock_option_bytes(); +} + +/* @brief Lock all segments of flash */ +void flash_lock(void) +{ + flash_lock_option_bytes(); + flash_lock_progmem(); +} + -- cgit v1.2.3 From afd2db30973652ded2201df6712da41aec251121 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 10 Jan 2019 16:24:15 +0100 Subject: stm32g0: add rcc. --- lib/stm32/g0/Makefile | 1 + lib/stm32/g0/rcc.c | 549 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 550 insertions(+) create mode 100644 lib/stm32/g0/rcc.c (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index dcb34bae..18ed5bbd 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -39,6 +39,7 @@ ARFLAGS = rcs OBJS += flash.o flash_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += pwr.o +OBJS += rcc.o rcc_common_all.o VPATH +=../:../../cm3:../common diff --git a/lib/stm32/g0/rcc.c b/lib/stm32/g0/rcc.c new file mode 100644 index 00000000..e587a722 --- /dev/null +++ b/lib/stm32/g0/rcc.c @@ -0,0 +1,549 @@ +/** @defgroup rcc_file RCC + * + * @ingroup STM32G0xx + * + * @brief libopencm3 STM32G0xx Reset and Clock Control + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot + * + * @date 10 January 2019 + * + * This library supports the Reset and Clock Control System in the STM32 series + * of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include +#include +#include +#include + +/* Set the default clock frequencies after reset. */ +uint32_t rcc_ahb_frequency = 16000000; +uint32_t rcc_apb1_frequency = 16000000; + +const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { + [RCC_CLOCK_CONFIG_LSI_32KHZ] = { + /* 32khz from lsi, scale2, 0ws */ + .sysclock_source = RCC_LSI, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_0WS, + .voltage_scale = PWR_SCALE2, + .ahb_frequency = 32000, + .apb_frequency = 32000, + }, + [RCC_CLOCK_CONFIG_HSI_4MHZ] = { + /* 4mhz from hsi/4, scale2, 0ws */ + .sysclock_source = RCC_HSI, + .hsisys_div = RCC_CR_HSIDIV_DIV4, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_0WS, + .voltage_scale = PWR_SCALE2, + .ahb_frequency = 4000000, + .apb_frequency = 4000000, + }, + [RCC_CLOCK_CONFIG_HSI_16MHZ] = { + /* 16mhz from hsi, scale2, 0ws */ + .sysclock_source = RCC_HSI, + .hsisys_div = RCC_CR_HSIDIV_DIV1, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_0WS, + .voltage_scale = PWR_SCALE2, + .ahb_frequency = 16000000, + .apb_frequency = 16000000, + }, + [RCC_CLOCK_CONFIG_HSI_PLL_32MHZ] = { + /* 32mhz from hsi via pll @ 128mhz / 4, scale1, 1ws */ + .sysclock_source = RCC_PLL, + .pll_source = RCC_PLLCFGR_PLLSRC_HSI16, + .pll_div = RCC_PLLCFGR_PLLM_DIV(1), + .pll_mul = RCC_PLLCFGR_PLLN_MUL(8), + .pllp_div = RCC_PLLCFGR_PLLP_DIV(4), + .pllq_div = RCC_PLLCFGR_PLLQ_DIV(4), + .pllr_div = RCC_PLLCFGR_PLLR_DIV(4), + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_1WS, + .voltage_scale = PWR_SCALE1, + .ahb_frequency = 32000000, + .apb_frequency = 32000000, + }, + [RCC_CLOCK_CONFIG_HSI_PLL_64MHZ] = { + /* 64mhz from hsi via pll @ 128mhz / 2, scale1, 2ws */ + .sysclock_source = RCC_PLL, + .pll_source = RCC_PLLCFGR_PLLSRC_HSI16, + .pll_div = RCC_PLLCFGR_PLLM_DIV(1), + .pll_mul = RCC_PLLCFGR_PLLN_MUL(8), + .pllp_div = RCC_PLLCFGR_PLLP_DIV(2), + .pllq_div = RCC_PLLCFGR_PLLQ_DIV(2), + .pllr_div = RCC_PLLCFGR_PLLR_DIV(2), + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_2WS, + .voltage_scale = PWR_SCALE1, + .ahb_frequency = 64000000, + .apb_frequency = 64000000, + }, + [RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ] = { + /* 64mhz from hse@12mhz via pll @ 128mhz / 2, scale1, 2ws */ + .sysclock_source = RCC_PLL, + .pll_source = RCC_PLLCFGR_PLLSRC_HSE, + .pll_div = RCC_PLLCFGR_PLLM_DIV(3), + .pll_mul = RCC_PLLCFGR_PLLN_MUL(32), + .pllp_div = RCC_PLLCFGR_PLLP_DIV(2), + .pllq_div = RCC_PLLCFGR_PLLQ_DIV(2), + .pllr_div = RCC_PLLCFGR_PLLR_DIV(2), + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_2WS, + .voltage_scale = PWR_SCALE1, + .ahb_frequency = 64000000, + .apb_frequency = 64000000, + }, +}; + +void rcc_osc_on(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR |= RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + default: + cm3_assert_not_reached(); + break; + } +} + +void rcc_osc_off(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + default: + cm3_assert_not_reached(); + break; + } +} + +bool rcc_is_osc_ready(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + return RCC_CR & RCC_CR_PLLRDY; + case RCC_HSE: + return RCC_CR & RCC_CR_HSERDY; + case RCC_HSI: + return RCC_CR & RCC_CR_HSIRDY; + case RCC_LSE: + return RCC_BDCR & RCC_BDCR_LSERDY; + case RCC_LSI: + return RCC_CSR & RCC_CSR_LSIRDY; + default: + cm3_assert_not_reached(); + return 0; + } + return false; +} + +void rcc_wait_for_osc_ready(enum rcc_osc osc) +{ + while (!rcc_is_osc_ready(osc)); +} + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +void rcc_css_int_clear(void) +{ + RCC_CICR |= RCC_CICR_CSSC; +} + +int rcc_css_int_flag(void) +{ + return ((RCC_CIFR & RCC_CIFR_CSSF) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the Source for the System Clock. + * @param osc Oscillator to use. + */ +void rcc_set_sysclk_source(enum rcc_osc osc) +{ + uint32_t reg32; + uint32_t sw = 0; + + switch (osc) { + case RCC_HSI: + sw = RCC_CFGR_SW_HSISYS; + break; + case RCC_HSE: + sw = RCC_CFGR_SW_HSE; + break; + case RCC_PLL: + sw = RCC_CFGR_SW_PLLRCLK; + break; + case RCC_LSE: + sw = RCC_CFGR_SW_LSE; + break; + case RCC_LSI: + sw = RCC_CFGR_SW_LSI; + break; + default: + cm3_assert_not_reached(); + return; + } + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT); + RCC_CFGR = (reg32 | (sw << RCC_CFGR_SW_SHIFT)); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Return the clock source which is used as system clock. + * @return rcc_osc system clock source + */ +enum rcc_osc rcc_system_clock_source(void) +{ + switch ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) { + case RCC_CFGR_SW_HSISYS: + return RCC_HSI; + case RCC_CFGR_SW_HSE: + return RCC_HSE; + case RCC_CFGR_SWS_PLLRCLK: + return RCC_PLL; + case RCC_CFGR_SW_LSE: + return RCC_LSE; + case RCC_CFGR_SW_LSI: + return RCC_LSI; + default: + cm3_assert_not_reached(); + return 0; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief Wait until system clock switched to given oscillator. + * @param osc Oscillator. + */ +void rcc_wait_for_sysclk_status(enum rcc_osc osc) +{ + uint32_t sws = 0; + + switch (osc) { + case RCC_PLL: + sws = RCC_CFGR_SWS_PLLRCLK; + break; + case RCC_HSE: + sws = RCC_CFGR_SWS_HSE; + break; + case RCC_HSI: + sws = RCC_CFGR_SWS_HSISYS; + break; + case RCC_LSI: + sws = RCC_CFGR_SWS_LSI; + break; + case RCC_LSE: + sws = RCC_CFGR_SWS_LSE; + break; + default: + cm3_assert_not_reached(); + break; + } + + while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) != sws); +} + +/** + * @brief Configure pll source. + * @param[in] pllsrc pll clock source @ref rcc_pllcfgr_pllsrc + */ +void rcc_set_pll_source(uint32_t pllsrc) +{ + uint32_t reg32; + + reg32 = RCC_PLLCFGR; + reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT); + RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT)); +} + +/** + * @brief Configure pll source and output frequencies. + * @param[in] source pll clock source @ref rcc_pllcfgr_pllsrc + * @param[in] pllm pll vco division factor @ref rcc_pllcfgr_pllm + * @param[in] plln pll vco multiplation factor @ref rcc_pllcfgr_plln + * @param[in] pllp pll P clock output division factor @ref rcc_pllcfgr_pllp + * @param[in] pllq pll Q clock output division factor @ref rcc_pllcfgr_pllq + * @param[in] pllr pll R clock output (sysclock pll) division factor @ref rcc_pllcfgr_pllr + */ +void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq, uint32_t pllr) +{ + RCC_PLLCFGR = (source << RCC_PLLCFGR_PLLSRC_SHIFT) | + (pllm << RCC_PLLCFGR_PLLM_SHIFT) | + (plln << RCC_PLLCFGR_PLLN_SHIFT) | + (pllp << RCC_PLLCFGR_PLLP_SHIFT) | + (pllq << RCC_PLLCFGR_PLLQ_SHIFT) | + (pllr << RCC_PLLCFGR_PLLR_SHIFT); +} + +/** + * @brief Enable PLL P clock output. + * @param[in] enable or disable P clock output + */ +void rcc_enable_pllp(bool enable) +{ + if (enable) { + RCC_PLLCFGR |= RCC_PLLCFGR_PLLPEN; + } else { + RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLPEN; + } +} + +/** + * @brief Enable PLL Q clock output. + * @param[in] enable or disable Q clock output + */ +void rcc_enable_pllq(bool enable) +{ + if (enable) { + RCC_PLLCFGR |= RCC_PLLCFGR_PLLQEN; + } else { + RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLQEN; + } +} + +/** + * @brief Enable PLL R clock output. + * @param[in] enable or disable R clock output + */ +void rcc_enable_pllr(bool enable) +{ + if (enable) { + RCC_PLLCFGR |= RCC_PLLCFGR_PLLREN; + } else { + RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLREN; + } +} + +/** + * @brief Configure APB peripheral clock prescaler + * @param[in] APB clock prescaler value @ref rcc_cfgr_ppre + */ +void rcc_set_ppre(uint32_t ppre) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_PPRE_MASK << RCC_CFGR_PPRE_SHIFT); + RCC_CFGR = (reg32 | (ppre << RCC_CFGR_PPRE_SHIFT)); +} + +/** + * @brief Configure AHB peripheral clock prescaler + * @param[in] AHB clock prescaler value @ref rcc_cfgr_hpre + */ +void rcc_set_hpre(uint32_t hpre) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT); + RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT)); +} + +/** + * @brief Configure HSI16 clock division factor to feed SYSCLK + * @param[in] HSYSSIS clock division factor @ref rcc_cr_hsidiv + */ +void rcc_set_hsisys_div(uint32_t hsidiv) +{ + uint32_t reg32; + + reg32 = RCC_CR; + reg32 &= ~(RCC_CR_HSIDIV_MASK << RCC_CR_HSIDIV_SHIFT); + RCC_CR = (reg32 | (hsidiv << RCC_CR_HSIDIV_SHIFT)); +} + +/** + * @brief Configure mco prescaler. + * @param[in] mcore prescaler value @ref rcc_cfgr_mcopre + */ +void rcc_set_mcopre(uint32_t mcopre) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_MCOPRE_MASK << RCC_CFGR_MCOPRE_SHIFT); + RCC_CFGR = (reg32 | (mcopre << RCC_CFGR_MCOPRE_SHIFT)); +} + +/** + * @brief Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). taking care of flash/pwr and src configuration + * @param rcc_clock_scale with desired parameters + */ +void rcc_clock_setup(const struct rcc_clock_scale *clock) +{ + if (clock->sysclock_source == RCC_PLL) { + enum rcc_osc pll_source; + + if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) + pll_source = RCC_HSE; + else + pll_source = RCC_HSI; + + /* start pll src osc. */ + rcc_osc_on(pll_source); + rcc_wait_for_osc_ready(pll_source); + + /* stop pll to reconfigure it. */ + rcc_osc_off(RCC_PLL); + while (rcc_is_osc_ready(RCC_PLL)); + + rcc_set_main_pll(clock->pll_source, clock->pll_div, clock->pll_mul, clock->pllp_div, clock->pllq_div, clock->pllr_div); + + rcc_enable_pllr(true); + } else if (clock->sysclock_source == RCC_HSI) { + rcc_set_hsisys_div(clock->hsisys_div); + } + + rcc_periph_clock_enable(RCC_PWR); + pwr_set_vos_scale(clock->voltage_scale); + + flash_set_ws(clock->flash_waitstates); + + /* enable flash prefetch if we have at least 1WS */ + if (clock->flash_waitstates > FLASH_ACR_LATENCY_0WS) + flash_prefetch_enable(); + else + flash_prefetch_disable(); + + rcc_set_hpre(clock->hpre); + rcc_set_ppre(clock->ppre); + + rcc_osc_on(clock->sysclock_source); + rcc_wait_for_osc_ready(clock->sysclock_source); + + rcc_set_sysclk_source(clock->sysclock_source); + rcc_wait_for_sysclk_status(clock->sysclock_source); + + rcc_ahb_frequency = clock->ahb_frequency; + rcc_apb1_frequency = clock->apb_frequency; +} + +/** + * @brief Setup RNG Peripheral Clock Divider + * @param rng_div clock divider @ref rcc_ccipr_rngdiv + */ +void rcc_set_rng_clk_div(uint32_t rng_div) +{ + uint32_t reg32 = RCC_CCIPR & ~(RCC_CCIPR_RNGDIV_MASK << RCC_CCIPR_RNGDIV_SHIFT); + RCC_CCIPR = reg32 | (rng_div << RCC_CCIPR_RNGDIV_SHIFT); +} + +/** + * @brief Set the peripheral clock source + * @param sel periphral clock source + */ +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) +{ + uint8_t shift; + uint32_t mask; + + switch (periph) { + case ADC1_BASE: + shift = RCC_CCIPR_ADCSEL_SHIFT; + mask = RCC_CCIPR_ADCSEL_MASK; + break; + case RNG_BASE: + shift = RCC_CCIPR_RNGSEL_SHIFT; + mask = RCC_CCIPR_RNGSEL_MASK; + break; + case TIM1_BASE: + shift = RCC_CCIPR_TIM1SEL_SHIFT; + mask = RCC_CCIPR_TIM1SEL_MASK; + break; + case LPTIM1_BASE: + shift = RCC_CCIPR_LPTIM1SEL_SHIFT; + mask = RCC_CCIPR_LPTIM1SEL_MASK; + break; + case LPTIM2_BASE: + shift = RCC_CCIPR_LPTIM2SEL_SHIFT; + mask = RCC_CCIPR_LPTIM2SEL_MASK; + break; + case CEC_BASE: + shift = RCC_CCIPR_CECSEL_SHIFT; + mask = RCC_CCIPR_CECSEL_MASK; + break; + case USART2_BASE: + shift = RCC_CCIPR_USART2SEL_SHIFT; + mask = RCC_CCIPR_USART2SEL_MASK; + break; + case USART1_BASE: + shift = RCC_CCIPR_USART1SEL_SHIFT; + mask = RCC_CCIPR_USART1SEL_MASK; + break; + default: + cm3_assert_not_reached(); + return; + } + + uint32_t reg32 = RCC_CCIPR & ~(mask << shift); + RCC_CCIPR = reg32 | (sel << shift); +} + +/**@}*/ -- cgit v1.2.3 From 55121126c3a053ee79759eab731852d7fe504134 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 5 Feb 2019 19:03:39 +0100 Subject: stm32g0: add exti. Regular exti, with enhanced EXTI_[FR]PR regs instead of EXTIR_PR. --- lib/stm32/g0/Makefile | 1 + lib/stm32/g0/exti.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 lib/stm32/g0/exti.c (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 18ed5bbd..9b4719bc 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -36,6 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs +OBJS += exti.o exti_common_all.o OBJS += flash.o flash_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += pwr.o diff --git a/lib/stm32/g0/exti.c b/lib/stm32/g0/exti.c new file mode 100644 index 00000000..74b31f26 --- /dev/null +++ b/lib/stm32/g0/exti.c @@ -0,0 +1,71 @@ +/** @addtogroup exti_defines + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot + * + * @date 10 January 2019 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/* @brief Get the rising edge interrupt requestf flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +uint32_t exti_get_rising_flag_status(uint32_t exti) +{ + return (EXTI_RPR1 & exti); +} + +/* @brief Get the rising edge interrupt request flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +uint32_t exti_get_falling_flag_status(uint32_t exti) +{ + return (EXTI_FPR1 & exti); +} + +/* @brief Resets the rising edge interrupt request pending flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +void exti_reset_rising_request(uint32_t extis) +{ + EXTI_RPR1 = extis; +} + +/* @brief Resets the falling edge interrupt request pending flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +void exti_reset_falling_request(uint32_t extis) +{ + EXTI_FPR1 = extis; +} + +/**@}*/ -- cgit v1.2.3 From 709d98e0a8026ec232007c0d86424e6604e03905 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 21:44:05 +0000 Subject: doc: stm32g0: drop redundant @ingroup and close groups the group defaults to the implicit container based on location, so drop all the explicit @ingroups, less to maintain. Properly use /**@}*/ to close all groups too, even though it mostly seems to have worked anyway. Properly close all groups opened for files. --- lib/stm32/g0/flash.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/flash.c b/lib/stm32/g0/flash.c index 9096723d..78e4d7d8 100644 --- a/lib/stm32/g0/flash.c +++ b/lib/stm32/g0/flash.c @@ -81,3 +81,4 @@ void flash_lock(void) flash_lock_progmem(); } +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 4aa9e484f6b674b1fa112a3dd68349f2eba74945 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 21:46:02 +0000 Subject: stm32g0: flash: drop redundant docs Functions that are already documented in the top level common api.h file won't add any more documentation from later .c files. Keep docs for part specifics, in the .h files where they're accessible to IDEs and also the documentation generation, and drop all (including the redundant ones) from the .c file. --- lib/stm32/g0/flash.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'lib') diff --git a/lib/stm32/g0/flash.c b/lib/stm32/g0/flash.c index 78e4d7d8..3356fc9d 100644 --- a/lib/stm32/g0/flash.c +++ b/lib/stm32/g0/flash.c @@ -30,51 +30,43 @@ #include -/* @brief Enable instruction cache */ void flash_icache_enable(void) { FLASH_ACR |= FLASH_ACR_ICEN; } -/* @brief Disable instruction cache */ void flash_icache_disable(void) { FLASH_ACR &= ~FLASH_ACR_ICEN; } -/* @brief Reset instruction cache */ void flash_icache_reset(void) { FLASH_ACR |= FLASH_ACR_ICRST; } -/* @brief Unlock program memory */ void flash_unlock_progmem(void) { FLASH_KEYR = FLASH_KEYR_KEY1; FLASH_KEYR = FLASH_KEYR_KEY2; } -/* @brief lock program memory */ void flash_lock_progmem(void) { FLASH_CR |= FLASH_CR_LOCK; } -/* @brief Lock Option Byte Access */ void flash_lock_option_bytes(void) { FLASH_CR |= FLASH_CR_OPTLOCK; } -/* @brief Unlock all segments of flash */ void flash_unlock(void) { flash_unlock_progmem(); flash_unlock_option_bytes(); } -/* @brief Lock all segments of flash */ void flash_lock(void) { flash_lock_option_bytes(); -- cgit v1.2.3 From d559b5a4dbfffc30894b1972bbb1d7edd77ff507 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 21:47:43 +0000 Subject: stm32g0: doc: move flash/pwr/rcc to "peripheral_apis" Where we've been collecting things that have common/specific parts as the new style of docs. --- lib/stm32/g0/flash.c | 4 ++-- lib/stm32/g0/pwr.c | 4 ++-- lib/stm32/g0/rcc.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/stm32/g0/flash.c b/lib/stm32/g0/flash.c index 3356fc9d..74ecf5d0 100644 --- a/lib/stm32/g0/flash.c +++ b/lib/stm32/g0/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32G0xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32G0xx FLASH * diff --git a/lib/stm32/g0/pwr.c b/lib/stm32/g0/pwr.c index b366760b..a4c71ad9 100644 --- a/lib/stm32/g0/pwr.c +++ b/lib/stm32/g0/pwr.c @@ -1,8 +1,8 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file PWR peripheral APIS * * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot * - * @ingroup STM32G0xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32G0xx Power Control * diff --git a/lib/stm32/g0/rcc.c b/lib/stm32/g0/rcc.c index e587a722..adfe5b5c 100644 --- a/lib/stm32/g0/rcc.c +++ b/lib/stm32/g0/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32G0xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32G0xx Reset and Clock Control * -- cgit v1.2.3 From fe5e82a3ccb8250ab1f3b3013dcf1526538dc61d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 22:13:43 +0000 Subject: stm32: doc: dac: move to peripheral_apis. Drops all the stub dummy header files, many of which weren't even being built, and moves them to the clean peripherals_api doc section. --- lib/stm32/common/dac_common_all.c | 9 +++++---- lib/stm32/f0/Makefile | 2 +- lib/stm32/f0/dac.c | 31 ------------------------------- lib/stm32/f1/dac.c | 31 ------------------------------- lib/stm32/f2/dac.c | 31 ------------------------------- lib/stm32/f3/dac.c | 31 ------------------------------- lib/stm32/f4/dac.c | 31 ------------------------------- lib/stm32/l1/dac.c | 31 ------------------------------- 8 files changed, 6 insertions(+), 191 deletions(-) delete mode 100644 lib/stm32/f0/dac.c delete mode 100644 lib/stm32/f1/dac.c delete mode 100644 lib/stm32/f2/dac.c delete mode 100644 lib/stm32/f3/dac.c delete mode 100644 lib/stm32/f4/dac.c delete mode 100644 lib/stm32/l1/dac.c (limited to 'lib') diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c index a8a0daf8..5d1893c1 100644 --- a/lib/stm32/common/dac_common_all.c +++ b/lib/stm32/common/dac_common_all.c @@ -1,12 +1,13 @@ -/** @addtogroup dac_file +/** @addtogroup dac_file DAC peripheral API + * @ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net This library supports the Digital to Analog Conversion System in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. +STM32 series of ARM Cortex Microcontrollers by ST Microelectronics. -The DAC is present only in a limited set of devices, notably some -of the connection line, high density and XL devices. +The DAC peripheral found on many of the devices in the STM32 lineup, +sometimes with only one channel, but normally with two channels. Two DAC channels are available, however unlike the ADC channels these are separate DAC devices controlled by the same register block. diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index a5883643..816f3f81 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs OBJS = can.o flash.o rcc.o dma.o rtc.o comparator.o \ - dac.o pwr.o gpio.o timer.o adc.o desig.o + pwr.o gpio.o timer.o adc.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ diff --git a/lib/stm32/f0/dac.c b/lib/stm32/f0/dac.c deleted file mode 100644 index 55cdd62c..00000000 --- a/lib/stm32/f0/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx DAC - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f1/dac.c b/lib/stm32/f1/dac.c deleted file mode 100644 index fa599bb7..00000000 --- a/lib/stm32/f1/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - -@ingroup STM32F1xx - -@brief libopencm3 STM32F1xx DAC - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f2/dac.c b/lib/stm32/f2/dac.c deleted file mode 100644 index 635e142b..00000000 --- a/lib/stm32/f2/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - -@ingroup STM32F2xx - -@brief libopencm3 STM32F2xx DAC - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f3/dac.c b/lib/stm32/f3/dac.c deleted file mode 100644 index 2d8021e0..00000000 --- a/lib/stm32/f3/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - * - * @ingroup STM32F3xx - * - * @brief libopencm3 STM32F3xx DAC - * - * @version 1.0.0 - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f4/dac.c b/lib/stm32/f4/dac.c deleted file mode 100644 index c5397b62..00000000 --- a/lib/stm32/f4/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - -@ingroup STM32F4xx - -@brief libopencm3 STM32F4xx DAC - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/l1/dac.c b/lib/stm32/l1/dac.c deleted file mode 100644 index ed118b4d..00000000 --- a/lib/stm32/l1/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - -@ingroup STM32L1xx - -@brief libopencm3 STM32L1xx DAC - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -- cgit v1.2.3 From 1af3acdba49519f8dc0d26b2802c21480a91e8ec Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 22:21:17 +0000 Subject: stm32: doc: exti: fix missing/wrong groups and move to peripheral_api Almost all families were missing all docs for the exti apis. --- lib/stm32/common/exti_common_all.c | 3 +++ lib/stm32/g0/exti.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index a690ca26..7135a964 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -1,3 +1,6 @@ +/** @addtogroup exti_file EXTI peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * diff --git a/lib/stm32/g0/exti.c b/lib/stm32/g0/exti.c index 74b31f26..5a55583c 100644 --- a/lib/stm32/g0/exti.c +++ b/lib/stm32/g0/exti.c @@ -1,4 +1,4 @@ -/** @addtogroup exti_defines +/** @addtogroup exti_file * * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot * -- cgit v1.2.3 From d77f539013a67adf57cd3bd2754a2bfff5a8db05 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 22:23:09 +0000 Subject: stm32: doc: rng: migrate to peripheral apis Gets them all documented properly, and cleans up the language that this was just for F4. --- lib/stm32/common/rng_common_v1.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/rng_common_v1.c b/lib/stm32/common/rng_common_v1.c index 7ed1e635..3b2a45a7 100644 --- a/lib/stm32/common/rng_common_v1.c +++ b/lib/stm32/common/rng_common_v1.c @@ -1,7 +1,10 @@ -/** @addtogroup rng_file +/** @addtogroup rng_file RNG peripheral API + * @ingroup peripheral_apis * - * This library supports the random number generator peripheral (RNG) in the - * STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. + * This library supports "version 1" of the random number generator + * peripheral (RNG) in the STM32 series of ARM Cortex Microcontrollers + * by ST Microelectronics. This is a common peripheral available on multiple + * devices in the family. * * LGPL License Terms @ref lgpl_license */ -- cgit v1.2.3 From 508f8d94872b5733db61687df1603993e1f0e28a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 22:32:30 +0000 Subject: stm32: doc: gpio: move gpio to peripheral_apis Drops dummy gpio.c files that weren't even being compiled in some cases. --- lib/stm32/common/gpio_common_all.c | 3 ++- lib/stm32/f0/Makefile | 2 +- lib/stm32/f0/gpio.c | 31 ------------------------------- lib/stm32/f1/gpio.c | 4 +--- lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/gpio.c | 31 ------------------------------- lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/gpio.c | 31 ------------------------------- lib/stm32/f7/Makefile | 2 +- lib/stm32/f7/gpio.c | 31 ------------------------------- lib/stm32/l0/Makefile | 2 +- lib/stm32/l0/gpio.c | 31 ------------------------------- lib/stm32/l1/gpio.c | 31 ------------------------------- 13 files changed, 8 insertions(+), 195 deletions(-) delete mode 100644 lib/stm32/f0/gpio.c delete mode 100644 lib/stm32/f2/gpio.c delete mode 100644 lib/stm32/f4/gpio.c delete mode 100644 lib/stm32/f7/gpio.c delete mode 100644 lib/stm32/l0/gpio.c delete mode 100644 lib/stm32/l1/gpio.c (limited to 'lib') diff --git a/lib/stm32/common/gpio_common_all.c b/lib/stm32/common/gpio_common_all.c index 98d15ad4..9602a999 100644 --- a/lib/stm32/common/gpio_common_all.c +++ b/lib/stm32/common/gpio_common_all.c @@ -1,4 +1,5 @@ -/** @addtogroup gpio_file +/** @addtogroup gpio_file GPIO peripheral API + * @ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2009 Uwe Hermann diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 816f3f81..f5b439a7 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs OBJS = can.o flash.o rcc.o dma.o rtc.o comparator.o \ - pwr.o gpio.o timer.o adc.o desig.o + pwr.o timer.o adc.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ diff --git a/lib/stm32/f0/gpio.c b/lib/stm32/f0/gpio.c deleted file mode 100644 index f60b4289..00000000 --- a/lib/stm32/f0/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx General Purpose I/O - * - * @version 1.0.0 - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f1/gpio.c b/lib/stm32/f1/gpio.c index c8943fce..160c46b5 100644 --- a/lib/stm32/f1/gpio.c +++ b/lib/stm32/f1/gpio.c @@ -1,6 +1,4 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F1xx +/** @addtogroup gpio_file @brief libopencm3 STM32F1xx General Purpose I/O diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index bfad2895..2af763fd 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -36,7 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o rcc.o desig.o +OBJS = rcc.o desig.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \ diff --git a/lib/stm32/f2/gpio.c b/lib/stm32/f2/gpio.c deleted file mode 100644 index 052e306f..00000000 --- a/lib/stm32/f2/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F2xx - -@brief libopencm3 STM32F2xx General Purpose I/O - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 9728e3be..c01c26e6 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -52,7 +52,7 @@ OBJS += exti_common_all.o OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o OBJS += flash_common_idcache.o OBJS += fmc_common_f47.o -OBJS += gpio_common_all.o gpio_common_f0234.o gpio.o +OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += hash_common_f24.o OBJS += i2c_common_v1.o OBJS += iwdg_common_all.o diff --git a/lib/stm32/f4/gpio.c b/lib/stm32/f4/gpio.c deleted file mode 100644 index ea59ae79..00000000 --- a/lib/stm32/f4/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F4xx - -@brief libopencm3 STM32F4xx General Purpose I/O - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 466ca351..35d226e9 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -53,7 +53,7 @@ OBJS += dsi_common_f47.o OBJS += exti_common_all.o OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o OBJS += fmc_common_f47.o -OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o +OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o OBJS += ltdc_common_f47.o diff --git a/lib/stm32/f7/gpio.c b/lib/stm32/f7/gpio.c deleted file mode 100644 index a5fb4afc..00000000 --- a/lib/stm32/f7/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F7xx - -@brief libopencm3 STM32F7xx General Purpose I/O - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index cd3e27c3..90b88b19 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -36,7 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = gpio.o rcc.o desig.o +OBJS = rcc.o desig.o OBJS += pwr_common_v1.o pwr_common_v2.o OBJS += timer_common_all.o OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o diff --git a/lib/stm32/l0/gpio.c b/lib/stm32/l0/gpio.c deleted file mode 100644 index 9382ece2..00000000 --- a/lib/stm32/l0/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - * - * @ingroup STM32L0xx - * - * @brief libopencm3 STM32L0xx General Purpose I/O - * - * @version 1.0.0 - * - * @date 8 September 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/l1/gpio.c b/lib/stm32/l1/gpio.c deleted file mode 100644 index 46ea658a..00000000 --- a/lib/stm32/l1/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32L1xx - -@brief libopencm3 STM32L1xx General Purpose I/O - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -- cgit v1.2.3 From 9382042180975edd49c8b8ddcd7f2f97ea749dd1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 23:03:50 +0000 Subject: stm32: doc: move timer to peripheral_apis Drop all the dummy timer.c files, and _actually_ compile the L1 specific file that was dropped by accident in 5b8953124e in 2013! --- lib/stm32/common/timer_common_all.c | 3 ++- lib/stm32/f0/Makefile | 2 +- lib/stm32/f0/timer.c | 34 --------------------------------- lib/stm32/f1/timer.c | 14 +++++--------- lib/stm32/f2/timer.c | 38 ------------------------------------- lib/stm32/f3/timer.c | 33 -------------------------------- lib/stm32/f4/timer.c | 38 ------------------------------------- lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/timer.c | 10 ++++------ 9 files changed, 13 insertions(+), 161 deletions(-) delete mode 100644 lib/stm32/f0/timer.c delete mode 100644 lib/stm32/f2/timer.c delete mode 100644 lib/stm32/f3/timer.c delete mode 100644 lib/stm32/f4/timer.c (limited to 'lib') diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index 9c8b5cc6..b9512f5b 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -1,4 +1,5 @@ -/** @addtogroup timer_file +/** @addtogroup timer_file Timer peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2010 Edward Cheeseman diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index f5b439a7..858e34ad 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs OBJS = can.o flash.o rcc.o dma.o rtc.o comparator.o \ - pwr.o timer.o adc.o desig.o + pwr.o adc.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ diff --git a/lib/stm32/f0/timer.c b/lib/stm32/f0/timer.c deleted file mode 100644 index 88006834..00000000 --- a/lib/stm32/f0/timer.c +++ /dev/null @@ -1,34 +0,0 @@ -/** @defgroup timer_file Timers - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx Timers - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Edward Cheeseman - * Copyright (C) 2011 Stephen Caudle - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c index fd46742c..b04bd971 100644 --- a/lib/stm32/f1/timer.c +++ b/lib/stm32/f1/timer.c @@ -1,12 +1,5 @@ -/* This file is used for documentation purposes. It does not need -to be compiled. All source code is in the common area. -If there is any device specific code required it can be included here, -in which case this file must be added to the compile list. */ - -/** @defgroup timer_file Timers - -@ingroup STM32F1xx - +/** @defgroup timer_file +@ingroup peripheral_apis @brief libopencm3 STM32F1xx Timers @version 1.0.0 @@ -37,6 +30,8 @@ in which case this file must be added to the compile list. */ #include +/**@{*/ + /*---------------------------------------------------------------------------*/ /** @brief Set Input Polarity @@ -55,3 +50,4 @@ void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic, } } +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/f2/timer.c b/lib/stm32/f2/timer.c deleted file mode 100644 index 6600705a..00000000 --- a/lib/stm32/f2/timer.c +++ /dev/null @@ -1,38 +0,0 @@ -/* This file is used for documentation purposes. It does not need -to be compiled. All source code is in the common area. -If there is any device specific code required it can be included here, -in which case this file must be added to the compile list. */ - -/** @defgroup timer_file Timers - -@ingroup STM32F2xx - -@brief libopencm3 STM32F2xx Timers - -@version 1.0.0 - -@date 18 August 2012 - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Edward Cheeseman - * Copyright (C) 2011 Stephen Caudle - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f3/timer.c b/lib/stm32/f3/timer.c deleted file mode 100644 index 0e9ac3d4..00000000 --- a/lib/stm32/f3/timer.c +++ /dev/null @@ -1,33 +0,0 @@ -/** @defgroup timer_file TIMER - * - * @ingroup STM32F3xx - * - * @brief libopencm3 STM32F3xx Timers - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - - diff --git a/lib/stm32/f4/timer.c b/lib/stm32/f4/timer.c deleted file mode 100644 index 72ecd8df..00000000 --- a/lib/stm32/f4/timer.c +++ /dev/null @@ -1,38 +0,0 @@ -/* This file is used for documentation purposes. It does not need -to be compiled. All source code is in the common area. -If there is any device specific code required it can be included here, -in which case this file must be added to the compile list. */ - -/** @defgroup timer_file Timers - -@ingroup STM32F4xx - -@brief libopencm3 STM32F4xx Timers - -@version 1.0.0 - -@date 18 August 2012 - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Edward Cheeseman - * Copyright (C) 2011 Stephen Caudle - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index db8f3bf8..68a6b6ee 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -43,7 +43,7 @@ OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v1.o iwdg_common_all.o OBJS += pwr_common_v1.o pwr_common_v2.o rtc_common_l1f024.o OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o -OBJS += timer_common_all.o +OBJS += timer.o timer_common_all.o OBJS += usart_common_all.o usart_common_f124.o OBJS += exti_common_all.o OBJS += rcc_common_all.o diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c index ab69c622..f9ce5dd0 100644 --- a/lib/stm32/l1/timer.c +++ b/lib/stm32/l1/timer.c @@ -1,7 +1,5 @@ -/** @defgroup timer_file Timers - -@ingroup STM32L1xx - +/** @defgroup timer_file +@ingroup peripheral_apis @brief libopencm3 STM32L1xx Timers @version 1.0.0 @@ -30,10 +28,10 @@ * along with this library. If not, see . */ -/**@{*/ - #include +/**@{*/ + /*---------------------------------------------------------------------------*/ /** @brief Set Timer Option -- cgit v1.2.3 From 1001a9323b0624cadef03673b4e086f56eb9d442 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 23:27:21 +0000 Subject: stm32: doc: dma: move to peripheral_apis drops dummy .c files, and adds proper groupings to the shared files. --- lib/stm32/common/dma_common_f24.c | 3 ++- lib/stm32/common/dma_common_l1f013.c | 3 ++- lib/stm32/f0/Makefile | 2 +- lib/stm32/f0/dma.c | 31 ------------------------------- lib/stm32/f1/dma.c | 31 ------------------------------- lib/stm32/f2/dma.c | 31 ------------------------------- lib/stm32/f3/Makefile | 2 +- lib/stm32/f3/dma.c | 31 ------------------------------- lib/stm32/f4/dma.c | 31 ------------------------------- lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/dma.c | 31 ------------------------------- 11 files changed, 7 insertions(+), 191 deletions(-) delete mode 100644 lib/stm32/f0/dma.c delete mode 100644 lib/stm32/f1/dma.c delete mode 100644 lib/stm32/f2/dma.c delete mode 100644 lib/stm32/f3/dma.c delete mode 100644 lib/stm32/f4/dma.c delete mode 100644 lib/stm32/l1/dma.c (limited to 'lib') diff --git a/lib/stm32/common/dma_common_f24.c b/lib/stm32/common/dma_common_f24.c index d706674f..2c61b548 100644 --- a/lib/stm32/common/dma_common_f24.c +++ b/lib/stm32/common/dma_common_f24.c @@ -1,4 +1,5 @@ -/** @addtogroup dma_file +/** @addtogroup dma_file DMA peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Ken Sarkies diff --git a/lib/stm32/common/dma_common_l1f013.c b/lib/stm32/common/dma_common_l1f013.c index 47abfa24..2f9190a4 100644 --- a/lib/stm32/common/dma_common_l1f013.c +++ b/lib/stm32/common/dma_common_l1f013.c @@ -1,4 +1,5 @@ -/** @addtogroup dma_file +/** @addtogroup dma_file DMA peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2010 Thomas Otto diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 858e34ad..5a8333d7 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -36,7 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = can.o flash.o rcc.o dma.o rtc.o comparator.o \ +OBJS = can.o flash.o rcc.o rtc.o comparator.o \ pwr.o adc.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ diff --git a/lib/stm32/f0/dma.c b/lib/stm32/f0/dma.c deleted file mode 100644 index 8f158a81..00000000 --- a/lib/stm32/f0/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx DMA - * - * @version 1.0.0 - * - * @date 10 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f1/dma.c b/lib/stm32/f1/dma.c deleted file mode 100644 index 70193659..00000000 --- a/lib/stm32/f1/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - -@ingroup STM32F1xx - -@brief libopencm3 STM32F1xx DMA - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f2/dma.c b/lib/stm32/f2/dma.c deleted file mode 100644 index 285f1fe7..00000000 --- a/lib/stm32/f2/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - -@ingroup STM32F2xx - -@brief libopencm3 STM32F2xx DMA - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index 1c098e81..010e14df 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = rcc.o adc.o can.o pwr.o dma.o flash.o desig.o +OBJS = rcc.o adc.o can.o pwr.o flash.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o \ dac_common_all.o crc_common_all.o crc_v2.o \ diff --git a/lib/stm32/f3/dma.c b/lib/stm32/f3/dma.c deleted file mode 100644 index c5d82b13..00000000 --- a/lib/stm32/f3/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - * - * @ingroup STM32F3xx - * - * @brief libopencm3 STM32F3xx Direct Memory Access - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f4/dma.c b/lib/stm32/f4/dma.c deleted file mode 100644 index 6616621a..00000000 --- a/lib/stm32/f4/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - -@ingroup STM32F4xx - -@brief libopencm3 STM32F4xx DMA - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 68a6b6ee..cd614593 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -35,7 +35,7 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = desig.o flash.o rcc.o dma.o lcd.o +OBJS = desig.o flash.o rcc.o lcd.o OBJS += crc_common_all.o dac_common_all.o OBJS += dma_common_l1f013.o OBJS += flash_common_all.o flash_common_l01.o diff --git a/lib/stm32/l1/dma.c b/lib/stm32/l1/dma.c deleted file mode 100644 index 6f4622d2..00000000 --- a/lib/stm32/l1/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - * - * @ingroup STM32L1xx - * - * @brief libopencm3 STM32L1xx DMA - * - * @version 1.0.0 - * - * @date 10 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -- cgit v1.2.3 From da76279bc692e5bc1b1ee0ed9d44b088769df821 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 21 May 2019 23:41:21 +0000 Subject: stm32: flash: move to peripheral_apis Change the groupings and headings to make them all consistent. --- lib/stm32/common/flash_common_all.c | 4 ++-- lib/stm32/f0/flash.c | 4 ++-- lib/stm32/f1/flash.c | 4 ++-- lib/stm32/f2/flash.c | 4 ++-- lib/stm32/f3/flash.c | 4 ++-- lib/stm32/f4/flash.c | 4 ++-- lib/stm32/f7/flash.c | 3 ++- lib/stm32/g0/flash.c | 2 +- lib/stm32/l0/Makefile | 2 +- lib/stm32/l0/flash.c | 27 --------------------------- lib/stm32/l1/flash.c | 4 ++-- lib/stm32/l4/flash.c | 4 ++-- 12 files changed, 20 insertions(+), 46 deletions(-) delete mode 100644 lib/stm32/l0/flash.c (limited to 'lib') diff --git a/lib/stm32/common/flash_common_all.c b/lib/stm32/common/flash_common_all.c index 98821796..b369d903 100644 --- a/lib/stm32/common/flash_common_all.c +++ b/lib/stm32/common/flash_common_all.c @@ -1,5 +1,5 @@ -/** @addtogroup flash_file - * +/** @addtogroup flash_file FLASH peripheral API + * @ingroup peripheral_apis */ /* diff --git a/lib/stm32/f0/flash.c b/lib/stm32/f0/flash.c index 433b7b53..9e7ebc33 100644 --- a/lib/stm32/f0/flash.c +++ b/lib/stm32/f0/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32F0xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F05x FLASH * diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c index 68606a9a..8c8c6e5f 100644 --- a/lib/stm32/f1/flash.c +++ b/lib/stm32/f1/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32F1xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F1xx FLASH Memory * diff --git a/lib/stm32/f2/flash.c b/lib/stm32/f2/flash.c index c2a0b3ba..0744ba5b 100644 --- a/lib/stm32/f2/flash.c +++ b/lib/stm32/f2/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32F2xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F2xx FLASH * diff --git a/lib/stm32/f3/flash.c b/lib/stm32/f3/flash.c index da8dfb68..e987d374 100644 --- a/lib/stm32/f3/flash.c +++ b/lib/stm32/f3/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32F3xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F3xx FLASH * diff --git a/lib/stm32/f4/flash.c b/lib/stm32/f4/flash.c index 8891be6e..75407d0d 100644 --- a/lib/stm32/f4/flash.c +++ b/lib/stm32/f4/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F4xx FLASH * diff --git a/lib/stm32/f7/flash.c b/lib/stm32/f7/flash.c index 9ec3e219..341a32f2 100644 --- a/lib/stm32/f7/flash.c +++ b/lib/stm32/f7/flash.c @@ -1,5 +1,6 @@ -/** @addtogroup flash_file +/** @defgroup flash_file * + * @ingroup peripheral_apis */ /* diff --git a/lib/stm32/g0/flash.c b/lib/stm32/g0/flash.c index 74ecf5d0..bb19d598 100644 --- a/lib/stm32/g0/flash.c +++ b/lib/stm32/g0/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file FLASH peripheral API +/** @defgroup flash_file * * @ingroup peripheral_apis * diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index 90b88b19..baa19d3e 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -46,7 +46,7 @@ OBJS += adc_common_v2.o OBJS += crs_common_all.o OBJS += dma_common_l1f013.o OBJS += exti_common_all.o -OBJS += flash.o flash_common_all.o flash_common_l01.o +OBJS += flash_common_all.o flash_common_l01.o OBJS += i2c_common_v2.o OBJS += rng_common_v1.o OBJS += usart_common_all.o usart_common_v2.o diff --git a/lib/stm32/l0/flash.c b/lib/stm32/l0/flash.c deleted file mode 100644 index b1ba6420..00000000 --- a/lib/stm32/l0/flash.c +++ /dev/null @@ -1,27 +0,0 @@ -/** @defgroup gpio_file GPIO - * - * @ingroup STM32L0xx - * - * @brief libopencm3 STM32L0xx General Purpose I/O - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c index 5e176b05..416b4efc 100644 --- a/lib/stm32/l1/flash.c +++ b/lib/stm32/l1/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32L1xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32L1xx FLASH * diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c index 58374b29..cb45081a 100644 --- a/lib/stm32/l4/flash.c +++ b/lib/stm32/l4/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file * - * @ingroup STM32L4xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32L4xx FLASH * -- cgit v1.2.3 From 0aef9c2ec68c089624f67c2bdfd5816dad81424c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 22 May 2019 00:10:39 +0000 Subject: stm32: doc: pwr: move to peripheral_api Some families had partially moved to peripheral api, and others were only documenting common code, but not specific code. Delete dummy .c files, and check that all specific apis are also being documented, not just common apis. --- lib/stm32/common/pwr_common_v1.c | 3 ++- lib/stm32/common/pwr_common_v2.c | 3 ++- lib/stm32/f0/Makefile | 2 +- lib/stm32/f0/pwr.c | 38 ----------------------------------- lib/stm32/f1/pwr.c | 43 ---------------------------------------- lib/stm32/f2/pwr.c | 39 ------------------------------------ lib/stm32/f3/Makefile | 2 +- lib/stm32/f3/pwr.c | 40 ------------------------------------- lib/stm32/f4/pwr.c | 8 ++++++-- lib/stm32/f7/pwr.c | 8 ++++++-- lib/stm32/g0/pwr.c | 3 ++- lib/stm32/l4/pwr.c | 4 ++-- 12 files changed, 22 insertions(+), 171 deletions(-) delete mode 100644 lib/stm32/f0/pwr.c delete mode 100644 lib/stm32/f1/pwr.c delete mode 100644 lib/stm32/f2/pwr.c delete mode 100644 lib/stm32/f3/pwr.c (limited to 'lib') diff --git a/lib/stm32/common/pwr_common_v1.c b/lib/stm32/common/pwr_common_v1.c index 820dfcab..d4c44b3d 100644 --- a/lib/stm32/common/pwr_common_v1.c +++ b/lib/stm32/common/pwr_common_v1.c @@ -1,4 +1,5 @@ -/** @addtogroup pwr_file +/** @addtogroup pwr_file PWR peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Ken Sarkies diff --git a/lib/stm32/common/pwr_common_v2.c b/lib/stm32/common/pwr_common_v2.c index b895e7d0..940b29e5 100644 --- a/lib/stm32/common/pwr_common_v2.c +++ b/lib/stm32/common/pwr_common_v2.c @@ -1,4 +1,5 @@ -/** @addtogroup pwr_file +/** @addtogroup pwr_file PWR peripheral API + * @ingroup peripheral_apis * * @author @htmlonly © @endhtmlonly 2012 Karl Palsson */ diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 5a8333d7..326baac0 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs OBJS = can.o flash.o rcc.o rtc.o comparator.o \ - pwr.o adc.o desig.o + adc.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ diff --git a/lib/stm32/f0/pwr.c b/lib/stm32/f0/pwr.c deleted file mode 100644 index 8a3ffd2e..00000000 --- a/lib/stm32/f0/pwr.c +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup pwr_file PWR - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx Power Control - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * This library supports the power control system for the - * STM32F0 series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -/**@}*/ - diff --git a/lib/stm32/f1/pwr.c b/lib/stm32/f1/pwr.c deleted file mode 100644 index 167f920d..00000000 --- a/lib/stm32/f1/pwr.c +++ /dev/null @@ -1,43 +0,0 @@ -/** @defgroup pwr_file PWR - * - * @ingroup STM32F1xx - * - * @brief libopencm3 STM32F1xx Power Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2012 - * Ken Sarkies - * - * @date 18 August 2012 - * - * This library supports the power control system for the - * STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -/**@}*/ - diff --git a/lib/stm32/f2/pwr.c b/lib/stm32/f2/pwr.c deleted file mode 100644 index 0e5641eb..00000000 --- a/lib/stm32/f2/pwr.c +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup pwr_file PWR - * - * @ingroup STM32F2xx - * - * @brief libopencm3 STM32F2xx Power Control - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies - * - * @date 13 January 2014 - * - * This library supports the power control system for the - * STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index 010e14df..362e0cd0 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = rcc.o adc.o can.o pwr.o flash.o desig.o +OBJS = rcc.o adc.o can.o flash.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o \ dac_common_all.o crc_common_all.o crc_v2.o \ diff --git a/lib/stm32/f3/pwr.c b/lib/stm32/f3/pwr.c deleted file mode 100644 index 3c1a84bd..00000000 --- a/lib/stm32/f3/pwr.c +++ /dev/null @@ -1,40 +0,0 @@ -/** @defgroup pwr_file PWR - * - * @ingroup STM32F3xx - * - * @brief libopencm3 STM32F3xx Power Control - * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies - * - * @date 13 January 2014 - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - - diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c index 58d9bd19..9bd2f8da 100644 --- a/lib/stm32/f4/pwr.c +++ b/lib/stm32/f4/pwr.c @@ -1,6 +1,6 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F4xx Power Control * @@ -36,6 +36,8 @@ #include +/**@{*/ + void pwr_set_vos_scale(enum pwr_vos_scale scale) { uint32_t reg32; @@ -43,3 +45,5 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale) reg32 |= (scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_SHIFT; PWR_CR = reg32; } + +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/f7/pwr.c b/lib/stm32/f7/pwr.c index 93bb845d..cb19bb6a 100644 --- a/lib/stm32/f7/pwr.c +++ b/lib/stm32/f7/pwr.c @@ -1,6 +1,6 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file PWR peripheral API * - * @ingroup STM32F7xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F7xx Power Control * @@ -38,6 +38,8 @@ #include +/**@{*/ + void pwr_set_vos_scale(enum pwr_vos_scale scale) { PWR_CR1 &= ~PWR_CR1_VOS_MASK; @@ -64,3 +66,5 @@ void pwr_disable_overdrive(void) PWR_CR1 &= ~(PWR_CR1_ODEN | PWR_CR1_ODSWEN); while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY)); } + +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/g0/pwr.c b/lib/stm32/g0/pwr.c index a4c71ad9..32cd535a 100644 --- a/lib/stm32/g0/pwr.c +++ b/lib/stm32/g0/pwr.c @@ -1,4 +1,5 @@ -/** @defgroup pwr_file PWR peripheral APIS +/** @defgroup pwr_file PWR peripheral API + * @ingroup peripheral_apis * * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot * diff --git a/lib/stm32/l4/pwr.c b/lib/stm32/l4/pwr.c index 7bfc8361..e6f71296 100644 --- a/lib/stm32/l4/pwr.c +++ b/lib/stm32/l4/pwr.c @@ -1,6 +1,6 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file PWR peripheral API * - * @ingroup STM32L4xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32L4xx Power Control * -- cgit v1.2.3 From f2a9980638a0f52368a0c76fe12ef88e9ecb07c5 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 22 May 2019 00:16:40 +0000 Subject: stm32: doc: rtc: move to peripheral apis Drop some dummy.c files, add some missing groupings and make sure all specifics are included in the generated output. --- lib/stm32/common/rtc_common_l1f024.c | 3 ++- lib/stm32/f0/Makefile | 2 +- lib/stm32/f0/rtc.c | 31 ----------------------------- lib/stm32/f1/rtc.c | 4 ++-- lib/stm32/f2/rtc.c | 31 ----------------------------- lib/stm32/f3/rtc.c | 38 ------------------------------------ lib/stm32/f4/rtc.c | 7 +++++-- lib/stm32/l1/rtc.c | 31 ----------------------------- 8 files changed, 10 insertions(+), 137 deletions(-) delete mode 100644 lib/stm32/f0/rtc.c delete mode 100644 lib/stm32/f2/rtc.c delete mode 100644 lib/stm32/f3/rtc.c delete mode 100644 lib/stm32/l1/rtc.c (limited to 'lib') diff --git a/lib/stm32/common/rtc_common_l1f024.c b/lib/stm32/common/rtc_common_l1f024.c index 7579dfdc..2d529449 100644 --- a/lib/stm32/common/rtc_common_l1f024.c +++ b/lib/stm32/common/rtc_common_l1f024.c @@ -1,4 +1,5 @@ -/** @addtogroup rtc_file +/** @addtogroup rtc_file RTC peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Karl Palsson diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 326baac0..efe25563 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -36,7 +36,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = can.o flash.o rcc.o rtc.o comparator.o \ +OBJS = can.o flash.o rcc.o comparator.o \ adc.o desig.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ diff --git a/lib/stm32/f0/rtc.c b/lib/stm32/f0/rtc.c deleted file mode 100644 index 6d55cc71..00000000 --- a/lib/stm32/f0/rtc.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup rtc_file RTC - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx RTC - * - * @version 1.0.0 - * - * @date 10 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c index 2743eed9..e32424f4 100644 --- a/lib/stm32/f1/rtc.c +++ b/lib/stm32/f1/rtc.c @@ -1,6 +1,6 @@ -/** @defgroup rtc_file RTC +/** @defgroup rtc_file RTC peripheral API * - * @ingroup STM32F1xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F1xx RTC * diff --git a/lib/stm32/f2/rtc.c b/lib/stm32/f2/rtc.c deleted file mode 100644 index 06666ab1..00000000 --- a/lib/stm32/f2/rtc.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup rtc_file RTC - * - * @ingroup STM32F2xx - * - * @brief libopencm3 STM32F2xx RTC - * - * @version 1.0.0 - * - * @date 4 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f3/rtc.c b/lib/stm32/f3/rtc.c deleted file mode 100644 index f332765a..00000000 --- a/lib/stm32/f3/rtc.c +++ /dev/null @@ -1,38 +0,0 @@ -/** @defgroup rtc_file RTC - * - * @ingroup STM32F3xx - * - * @brief libopencm3 STM32F3xx Real Time Clock - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include - - diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c index f08ac2bc..4d1008c1 100644 --- a/lib/stm32/f4/rtc.c +++ b/lib/stm32/f4/rtc.c @@ -1,6 +1,6 @@ -/** @defgroup rtc_file RTC +/** @defgroup rtc_file * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F4xx RTC * @@ -32,6 +32,7 @@ #include #include +/**@{*/ /*---------------------------------------------------------------------------*/ /** @brief Enable the wakeup timer @@ -95,3 +96,5 @@ void rtc_disable_wakeup_timer_interrupt(void) /* 3. Disable RTC wakeup timer event. */ RTC_CR &= ~RTC_CR_WUTIE; } + +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/l1/rtc.c b/lib/stm32/l1/rtc.c deleted file mode 100644 index 5628aa7e..00000000 --- a/lib/stm32/l1/rtc.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup rtc_file RTC - * - * @ingroup STM32L1xx - * - * @brief libopencm3 STM32L1xx RTC - * - * @version 1.0.0 - * - * @date 4 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -- cgit v1.2.3 From ca6dcfbea137bd2145b4a7fbf24379f565f8280d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Mon, 8 Apr 2019 23:58:54 +0200 Subject: stm32f4: rcc: support hsi pll source --- lib/stm32/f4/rcc.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 8a92ec40..aecbea69 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -56,6 +56,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 2, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -72,6 +73,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -88,6 +90,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 5, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -104,6 +107,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -120,6 +124,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -139,6 +144,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 2, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -155,6 +161,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -171,6 +178,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 5, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -187,6 +195,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -203,6 +212,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -222,6 +232,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 2, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -238,6 +249,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -254,6 +266,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 5, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -270,6 +283,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -286,6 +300,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -305,6 +320,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 2, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -321,6 +337,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -337,6 +354,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 5, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -353,6 +371,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -369,6 +388,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .pllp = 2, .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -748,7 +768,15 @@ uint32_t rcc_system_clock_source(void) return (RCC_CFGR & 0x000c) >> 2; } -void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) +/** + * Setup clocks to run from PLL. + * + * The arguments provide the pll source, multipliers, dividers, all that's + * needed to establish a system clock. + * + * @param clock clock information structure. + */ +void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { /* Enable internal high-speed oscillator (HSI). */ rcc_osc_on(RCC_HSI); @@ -758,8 +786,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* Enable external high-speed oscillator (HSE). */ - rcc_osc_on(RCC_HSE); - rcc_wait_for_osc_ready(RCC_HSE); + if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { + rcc_osc_on(RCC_HSE); + rcc_wait_for_osc_ready(RCC_HSE); + } /* Set the VOS scale mode */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_PWR); @@ -777,8 +807,13 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_osc_off(RCC_PLL); /* Configure the PLL oscillator. */ - rcc_set_main_pll_hse(clock->pllm, clock->plln, - clock->pllp, clock->pllq, clock->pllr); + if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { + rcc_set_main_pll_hse(clock->pllm, clock->plln, + clock->pllp, clock->pllq, clock->pllr); + } else { + rcc_set_main_pll_hsi(clock->pllm, clock->plln, + clock->pllp, clock->pllq, clock->pllr); + } /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); @@ -809,7 +844,19 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_apb2_frequency = clock->apb2_frequency; /* Disable internal high-speed oscillator. */ - rcc_osc_off(RCC_HSI); + if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { + rcc_osc_off(RCC_HSI); + } +} + +/** + * Setup clocks with the HSE. + * + * @deprecated Use `rcc_clock_setup_pll` instead. + */ +void __attribute__((deprecated)) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) +{ + rcc_clock_setup_pll(clock); } /**@}*/ -- cgit v1.2.3 From 1d68c299e8804d47f407a2f9f3c1274d3c892273 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Tue, 9 Apr 2019 00:46:15 +0200 Subject: stm32f4: add HSI clock configurations --- lib/stm32/f4/rcc.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) (limited to 'lib') diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index aecbea69..515693e4 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -49,6 +49,94 @@ uint32_t rcc_ahb_frequency = 16000000; uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; +const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { + { /* 48MHz */ + .pllm = 16, + .plln = 96, + .pllp = 2, + .pllq = 2, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_1WS, + .ahb_frequency = 48000000, + .apb1_frequency = 12000000, + .apb2_frequency = 24000000, + }, + { /* 84MHz */ + .pllm = 16, + .plln = 336, + .pllp = 4, + .pllq = 7, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_2WS, + .ahb_frequency = 84000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, + { /* 120MHz */ + .pllm = 16, + .plln = 240, + .pllp = 2, + .pllq = 5, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_3WS, + .ahb_frequency = 120000000, + .apb1_frequency = 30000000, + .apb2_frequency = 60000000, + }, + { /* 168MHz */ + .pllm = 16, + .plln = 336, + .pllp = 2, + .pllq = 7, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 168000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, + { /* 180MHz */ + .pllm = 16, + .plln = 360, + .pllp = 2, + .pllq = 8, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, + }, +}; + const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 8, -- cgit v1.2.3 From a9dde2832eb8039b9e0d21a50b9b991ddbfc4e2d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 2 Jun 2019 10:50:10 +0000 Subject: stm32f4: rcc: drop 48 & 120 MHz configs 48Mhz has no purpose other than to be a naiive method of haivng working USB. 120MHz never had any purpose, other than to match the f2 code it was copied from. Drop them both. Remaining configs are all max speeds for various F4 parts. Lower speeds are all custom --- lib/stm32/f4/rcc.c | 170 ----------------------------------------------------- 1 file changed, 170 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 515693e4..d86421ec 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -50,23 +50,6 @@ uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 16, - .plln = 96, - .pllp = 2, - .pllq = 2, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, { /* 84MHz */ .pllm = 16, .plln = 336, @@ -84,23 +67,6 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 16, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 16, .plln = 336, @@ -138,23 +104,6 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { }; const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 8, - .plln = 96, - .pllp = 2, - .pllq = 2, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, { /* 84MHz */ .pllm = 8, .plln = 336, @@ -172,23 +121,6 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 8, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 8, .plln = 336, @@ -226,23 +158,6 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { }; const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 12, - .plln = 96, - .pllp = 2, - .pllq = 2, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, { /* 84MHz */ .pllm = 12, .plln = 336, @@ -260,23 +175,6 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 12, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 12, .plln = 336, @@ -314,23 +212,6 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { }; const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 16, - .plln = 96, - .pllp = 2, - .pllq = 2, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, { /* 84MHz */ .pllm = 16, .plln = 336, @@ -348,23 +229,6 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 16, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 16, .plln = 336, @@ -402,23 +266,6 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { }; const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 25, - .plln = 96, - .pllp = 2, - .pllq = 2, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, { /* 84MHz */ .pllm = 25, .plln = 336, @@ -436,23 +283,6 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 25, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 25, .plln = 336, -- cgit v1.2.3 From f9900304404fc97deef5cda3b1549bb456faf621 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 2 Jun 2019 12:50:34 +0000 Subject: stm32f4: rcc: move deprecated attribute to header This makes it actually generate deprecated warnings. The deprecated doxygen stays with the .c file as before. --- lib/stm32/f4/rcc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index d86421ec..a20ce865 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -770,9 +770,11 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) /** * Setup clocks with the HSE. * - * @deprecated Use `rcc_clock_setup_pll` instead. + * @deprecated replaced by rcc_clock_setup_pll as a drop in replacement. + * @see rcc_clock_setup_pll which supports HSI as well as HSE, using the same + * clock structures. */ -void __attribute__((deprecated)) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) +void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) { rcc_clock_setup_pll(clock); } -- cgit v1.2.3 From a1ffdc59f0c75d29db00d12f827f7d9fd7e1df18 Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Fri, 22 Dec 2017 12:39:58 +0000 Subject: stm32:l4: flash: Program in double words According to RM0351 and RM0394 flash needs to be programmed by double words. Also fix flash_program() which was wrong anyways. Reviewed-by: Karl Palsson --- lib/stm32/l4/flash.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c index cb45081a..6381197b 100644 --- a/lib/stm32/l4/flash.c +++ b/lib/stm32/l4/flash.c @@ -108,15 +108,16 @@ void flash_lock_option_bytes(void) FLASH_CR |= FLASH_CR_OPTLOCK; } -/** @brief Program a 32 bit Word to FLASH - * This performs all operations necessary to program a 32 bit word to FLASH - * memory. The program error flag should be checked separately for the event - * that memory was not properly erased. +/** @brief Program a 64 bit word to FLASH + * + * This performs all operations necessary to program a 64 bit word to FLASH memory. + * The program error flag should be checked separately for the event that memory + * was not properly erased. * * @param[in] address Starting address in Flash. - * @param[in] data word to write + * @param[in] data Double word to write */ -void flash_program_word(uint32_t address, uint32_t data) +void flash_program_double_word(uint32_t address, uint64_t data) { /* Ensure that all flash operations are complete. */ flash_wait_for_last_operation(); @@ -124,8 +125,9 @@ void flash_program_word(uint32_t address, uint32_t data) /* Enable writes to flash. */ FLASH_CR |= FLASH_CR_PG; - /* Program the word. */ - MMIO32(address) = data; + /* Program the each word separately. */ + MMIO32(address) = (uint32_t)data; + MMIO32(address+4) = (uint32_t)(data >> 32); /* Wait for the write to complete. */ flash_wait_for_last_operation(); @@ -140,16 +142,12 @@ void flash_program_word(uint32_t address, uint32_t data) * memory was not properly erased. * @param[in] address Starting address in Flash. * @param[in] data Pointer to start of data block. - * @param[in] len Length of data block. + * @param[in] len Length of data block in bytes (multiple of 8). */ void flash_program(uint32_t address, uint8_t *data, uint32_t len) { - /* TODO: Use dword and word size program operations where possible for - * turbo speed. - */ - uint32_t i; - for (i = 0; i < len; i++) { - flash_program_word(address+i, data[i]); + for (uint32_t i = 0; i < len; i += 8) { + flash_program_double_word(address+i, *(uint64_t*)(data + i)); } } -- cgit v1.2.3 From fe722d46436afe502ddf1cc023a24b348e809293 Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Thu, 28 Dec 2017 13:32:29 +0000 Subject: stm32:l4: rcc: Add helper functions Add functions for PLL output and 48MHz clock source selection --- lib/stm32/l4/rcc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'lib') diff --git a/lib/stm32/l4/rcc.c b/lib/stm32/l4/rcc.c index d1fb0c48..86631254 100644 --- a/lib/stm32/l4/rcc.c +++ b/lib/stm32/l4/rcc.c @@ -369,4 +369,33 @@ void rcc_set_msi_range_standby(uint32_t msi_range) RCC_CSR = reg; } +/** Enable PLL Output + * + * - P (RCC_PLLCFGR_PLLPEN) + * - Q (RCC_PLLCFGR_PLLQEN) + * - R (RCC_PLLCFGR_PLLREN) + * + * @param pllout One or more of the definitions above + */ +void rcc_pll_output_enable(uint32_t pllout) +{ + RCC_PLLCFGR |= pllout; +} + +/** Set clock source for 48MHz clock + * + * The 48 MHz clock is derived from one of the four following sources: + * - main PLL VCO (RCC_CCIPR_CLK48SEL_PLL) + * - PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q) + * - MSI clock (RCC_CCIPR_CLK48SEL_MSI) + * - HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48) + * + * @param clksel One of the definitions above + */ +void rcc_set_clock48_source(uint32_t clksel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT); + RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT); +} + /**@}*/ -- cgit v1.2.3 From 2c1823f7bbae19f9322770e855555da08f8bcea8 Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Fri, 5 Jan 2018 13:36:05 +0000 Subject: stm32:l4: pwr: Add en/disable_backup_domain_write_protect() --- lib/stm32/l4/pwr.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'lib') diff --git a/lib/stm32/l4/pwr.c b/lib/stm32/l4/pwr.c index e6f71296..e6bd877a 100644 --- a/lib/stm32/l4/pwr.c +++ b/lib/stm32/l4/pwr.c @@ -52,4 +52,24 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale) } PWR_CR1 = reg32; } + +/** Disable Backup Domain Write Protection + * + * This allows backup domain registers to be changed. These registers are write + * protected after a reset. + */ +void pwr_disable_backup_domain_write_protect(void) +{ + PWR_CR1 |= PWR_CR1_DBP; +} + +/** Re-enable Backup Domain Write Protection + * + * This protects backup domain registers from inadvertent change. + */ +void pwr_enable_backup_domain_write_protect(void) +{ + PWR_CR1 &= ~PWR_CR1_DBP; +} + /**@}*/ -- cgit v1.2.3 From b8424263e8e13a2c6a225a76f242f6af042dab73 Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Fri, 5 Jan 2018 13:36:59 +0000 Subject: stm32:l4: rcc: Add RTC clock functions --- lib/stm32/l4/rcc.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'lib') diff --git a/lib/stm32/l4/rcc.c b/lib/stm32/l4/rcc.c index 86631254..f44cfca1 100644 --- a/lib/stm32/l4/rcc.c +++ b/lib/stm32/l4/rcc.c @@ -398,4 +398,40 @@ void rcc_set_clock48_source(uint32_t clksel) RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT); } + +/** Enable the RTC clock */ +void rcc_enable_rtc_clock(void) +{ + RCC_BDCR |= RCC_BDCR_RTCEN; +} + +/** Disable the RTC clock */ +void rcc_disable_rtc_clock(void) +{ + RCC_BDCR &= ~RCC_BDCR_RTCEN; +} + +/** Set the source for the RTC clock + * @param[in] clk ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI. + */ +void rcc_set_rtc_clock_source(enum rcc_osc clk) +{ + RCC_BDCR &= ~(RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT); + + switch (clk) { + case RCC_HSE: + RCC_BDCR |= (RCC_BDCR_RTCSEL_HSEDIV32 << RCC_BDCR_RTCSEL_SHIFT); + break; + case RCC_LSE: + RCC_BDCR |= (RCC_BDCR_RTCSEL_LSE << RCC_BDCR_RTCSEL_SHIFT); + break; + case RCC_LSI: + RCC_BDCR |= (RCC_BDCR_RTCSEL_LSI << RCC_BDCR_RTCSEL_SHIFT); + break; + default: + /* none selected */ + break; + } +} + /**@}*/ -- cgit v1.2.3 From 833ddd9b0a6c8ddfc6003cf49b80a1661f2def3e Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Wed, 5 Sep 2018 15:09:38 +0100 Subject: stm32: rtc: clear wakeup clock selection Clear wakeup clock selection before setting the desired bits, so no old bits can stay set Reviewed-by: Karl Palsson --- lib/stm32/common/rtc_common_l1f024.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/common/rtc_common_l1f024.c b/lib/stm32/common/rtc_common_l1f024.c index 2d529449..d7825a7c 100644 --- a/lib/stm32/common/rtc_common_l1f024.c +++ b/lib/stm32/common/rtc_common_l1f024.c @@ -107,6 +107,7 @@ void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel) * down-counting. */ RTC_WUTR = wkup_time; + RTC_CR &= ~(RTC_CR_WUCLKSEL_MASK << RTC_CR_WUCLKSEL_SHIFT); RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT); RTC_CR |= RTC_CR_WUTE; } -- cgit v1.2.3 From 53ce5aa3ddf17e588b245f0ab29e18073505684b Mon Sep 17 00:00:00 2001 From: Bruno Randolf Date: Thu, 20 Sep 2018 16:38:14 +0100 Subject: stm32:l4:flash: Fix option bytes programming FLASH_CR_OPTSTRT needs to be written to FLASH_CR, and there is no reason to mask the last two data bits. Signed-off-by: Bruno Randolf Reviewed-by: Karl Palsson (original code appeared to be badly copied from the flash_common_f24 codebase) --- lib/stm32/l4/flash.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c index 6381197b..2aff56a6 100644 --- a/lib/stm32/l4/flash.c +++ b/lib/stm32/l4/flash.c @@ -196,8 +196,8 @@ void flash_program_option_bytes(uint32_t data) flash_unlock_option_bytes(); } - FLASH_OPTR = data & ~0x3; - FLASH_OPTR |= FLASH_CR_OPTSTRT; + FLASH_OPTR = data; + FLASH_CR |= FLASH_CR_OPTSTRT; flash_wait_for_last_operation(); } /**@}*/ -- cgit v1.2.3 From b805db04444f5a2bc4cde919121eab80a3b17297 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 10 May 2018 14:59:50 -0700 Subject: efm32: cmu: support switching HFCLK to USHFRCODIV2 Allow for the high frequency clock that controlls things such as the main CPU to be switched over to USHFRCODIV2. This is a 24 MHz PLL that is trimmed using clock recovery from the USB signal, and is accurate to within 1% of 24 MHz. Signed-off-by: Sean Cross --- lib/efm32/hg/cmu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'lib') diff --git a/lib/efm32/hg/cmu.c b/lib/efm32/hg/cmu.c index db28680d..f7de65e7 100644 --- a/lib/efm32/hg/cmu.c +++ b/lib/efm32/hg/cmu.c @@ -105,6 +105,9 @@ void cmu_osc_on(enum cmu_osc osc) case AUXHFRCO: CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN; break; + default: + /* not applicable */ + break; } } @@ -133,6 +136,9 @@ void cmu_osc_off(enum cmu_osc osc) case AUXHFRCO: CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS; break; + default: + /* not applicable */ + break; } } @@ -163,6 +169,9 @@ bool cmu_osc_ready_flag(enum cmu_osc osc) case AUXHFRCO: return (CMU_STATUS & CMU_STATUS_AUXHFRCORDY) != 0; break; + default: + /* not applicable */ + break; } return false; @@ -193,6 +202,9 @@ void cmu_wait_for_osc_ready(enum cmu_osc osc) case AUXHFRCO: while ((CMU_STATUS & CMU_STATUS_AUXHFRCORDY) == 0); break; + default: + /* not applicable */ + break; } } @@ -218,6 +230,9 @@ void cmu_set_hfclk_source(enum cmu_osc osc) case LFRCO: CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO; break; + case USHFRCODIV2: + CMU_CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; + break; default: /* not applicable */ return; @@ -239,6 +254,8 @@ enum cmu_osc cmu_get_hfclk_source(void) return HFXO; } else if (status & CMU_STATUS_HFRCOSEL) { return HFRCO; + } else if (status & CMU_STATUS_USHFRCODIV2SEL) { + return USHFRCODIV2; } /* never reached */ -- cgit v1.2.3 From 6953138a280bfab54464a780e5491e8bd6e1753e Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 30 Jan 2019 14:53:20 +0100 Subject: stm32l0: add rcc_set_msi_range. --- lib/stm32/l0/rcc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'lib') diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index 3048bef5..90d6b437 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -391,6 +391,17 @@ void rcc_set_hpre(uint32_t hpre) RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT); } +/*---------------------------------------------------------------------------*/ +/** @brief Set the range of the MSI oscillator +* + * @param range desired range @ref rcc_icscr_msirange + */ +void rcc_set_msi_range(uint32_t msi_range) +{ + uint32_t reg32 = RCC_ICSCR & ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT); + RCC_ICSCR = reg32 | (msi_range << RCC_ICSCR_MSIRANGE_SHIFT); +} + /** * Set up sysclock with PLL from HSI16 * @param clock full struct with desired parameters -- cgit v1.2.3 From 8668f9198b48dfd6bdba55baa834c52f20710884 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 30 Jan 2019 14:55:18 +0100 Subject: stm32l0: rcc: add peripherals clock source selection helpers. --- lib/stm32/l0/rcc.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'lib') diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index 90d6b437..7605e6ae 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -402,6 +402,50 @@ void rcc_set_msi_range(uint32_t msi_range) RCC_ICSCR = reg32 | (msi_range << RCC_ICSCR_MSIRANGE_SHIFT); } +/*---------------------------------------------------------------------------*/ +/** @brief Set the LPTIM1 clock source +* + * @param lptim1_sel peripheral clock source @ref rcc_ccpipr_lptim1sel + */ +void rcc_set_lptim1_sel(uint32_t lptim1_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_LPTIM1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT); + RCC_CCIPR |= (lptim1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT); +} + + +/*---------------------------------------------------------------------------*/ +/** @brief Set the LPUART1 clock source +* + * @param lpuart1_sel periphral clock source @ref rcc_ccpipr_lpuart1sel + */ +void rcc_set_lpuart1_sel(uint32_t lpuart1_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_LPUART1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT); + RCC_CCIPR |= (lpuart1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the USART1 clock source +* + * @param usart1_sel periphral clock source @ref rcc_ccpipr_usart1sel + */ +void rcc_set_usart1_sel(uint32_t usart1_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT); + RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT); +} +/*---------------------------------------------------------------------------*/ +/** @brief Set the USART2 clock source +* + * @param usart2_sel periphral clock source @ref rcc_ccpipr_usartxsel + */ +void rcc_set_usart2_sel(uint32_t usart2_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_USART2SEL_MASK << RCC_CCIPR_USART2SEL_SHIFT); + RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT); +} + /** * Set up sysclock with PLL from HSI16 * @param clock full struct with desired parameters -- cgit v1.2.3 From a65285653376717390cff0e0377a732835b782b1 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 5 Feb 2019 15:33:55 +0100 Subject: stm32l0: rcc: add rcc_set_peripheral_clk_sel(periph, sel) --- lib/stm32/l0/rcc.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'lib') diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index 7605e6ae..4f902f87 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -435,6 +435,7 @@ void rcc_set_usart1_sel(uint32_t usart1_sel) RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT); RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT); } + /*---------------------------------------------------------------------------*/ /** @brief Set the USART2 clock source * @@ -446,6 +447,55 @@ void rcc_set_usart2_sel(uint32_t usart2_sel) RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT); } +/*---------------------------------------------------------------------------*/ +/** @brief Set the peripheral clock source +* + * @param sel periphral clock source + */ +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) +{ + uint8_t shift; + uint32_t mask; + + switch (periph) { + case LPTIM1_BASE: + shift = RCC_CCIPR_LPTIM1SEL_SHIFT; + mask = RCC_CCIPR_LPTIM1SEL_MASK; + break; + + case I2C3_BASE: + shift = RCC_CCIPR_I2C3SEL_SHIFT; + mask = RCC_CCIPR_I2C3SEL_MASK; + break; + + case I2C1_BASE: + shift = RCC_CCIPR_I2C1SEL_SHIFT; + mask = RCC_CCIPR_I2C1SEL_MASK; + break; + + case LPUART1_BASE: + shift = RCC_CCIPR_LPUART1SEL_SHIFT; + mask = RCC_CCIPR_LPUART1SEL_MASK; + break; + + case USART2_BASE: + shift = RCC_CCIPR_USART2SEL_SHIFT; + mask = RCC_CCIPR_USART2SEL_MASK; + break; + + case USART1_BASE: + shift = RCC_CCIPR_USART1SEL_SHIFT; + mask = RCC_CCIPR_USART1SEL_MASK; + break; + + default: + return; + } + + uint32_t reg32 = RCC_CCIPR & ~(mask << shift); + RCC_CCIPR = reg32 | (sel << shift); +} + /** * Set up sysclock with PLL from HSI16 * @param clock full struct with desired parameters -- cgit v1.2.3 From 54eff24e7c0fe3e0eba69f414452033ebc90fb9b Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 19 Feb 2019 01:25:12 +0800 Subject: swm050: new MCU family SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals are GPIO, Timer and WDT. There's only two parts in this series, with either TSSOP-8 or SSOP-16 packages. This commit introduces the interrupt vector and GPIO support for them. Signed-off-by: Icenowy Zheng --- lib/dispatch/vector_nvic.c | 3 + lib/swm050/Makefile | 41 ++++++++++ lib/swm050/gpio.c | 190 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 lib/swm050/Makefile create mode 100644 lib/swm050/gpio.c (limited to 'lib') diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index c7221c87..0d4dd519 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -71,6 +71,9 @@ #elif defined(MSP432E4) # include "../msp432/e4/vector_nvic.c" +#elif defined(SWM050) +# include "../swm050/vector_nvic.c" + #else # warning "no interrupts defined for chipset;"\ "not allocating space in the vector table" diff --git a/lib/swm050/Makefile b/lib/swm050/Makefile new file mode 100644 index 00000000..ccbf14a7 --- /dev/null +++ b/lib/swm050/Makefile @@ -0,0 +1,41 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Icenowy Zheng +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_swm050 +SRCLIBDIR ?= .. + +PREFIX ?= arm-none-eabi + +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../include -fno-common \ + -mcpu=cortex-m0 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSWM050 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) +ARFLAGS = rcs +OBJS = gpio.o + +VPATH += ../cm3 + +include ../Makefile.include diff --git a/lib/swm050/gpio.c b/lib/swm050/gpio.c new file mode 100644 index 00000000..31ee3969 --- /dev/null +++ b/lib/swm050/gpio.c @@ -0,0 +1,190 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/*---------------------------------------------------------------------------*/ +/** @brief Set a Group of Pins + +Set one or more pins of GPIO to 1. Please note that this chip doesn't support +atomic pin setting. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_set(uint16_t gpios) +{ + GPIO_DATA |= gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Clear a Group of Pins + +Set one or more pins of GPIO to 0. Please note that this chip doesn't support +atomic pin setting. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_clear(uint16_t gpios) +{ + GPIO_DATA &= ~gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Read a Group of Pins. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be read, use bitwise OR '|' to separate + them. +@return Unsigned int16 value of the pin values. The bit position of the pin + value returned corresponds to the pin number. +*/ +uint16_t gpio_get(uint16_t gpios) +{ + return GPIO_EXT & gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Toggle a Group of Pins + +Toggle one or more pins of GPIO. The non-toggled pins are not affected. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_toggle(uint16_t gpios) +{ + uint32_t curr_status = GPIO_DATA & gpios; + GPIO_DATA = (GPIO_DATA & (~gpios)) | (~curr_status); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the direction of a Group of Pins to Input + +Set the direction of one or more pins of GPIO to input. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_input(uint16_t gpios) +{ + GPIO_DIR &= ~gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the direction of a Group of Pins to Output + +Set the direction of one or more pins of GPIO to output. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_output(uint16_t gpios) +{ + GPIO_DIR |= gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Select the alternative function of a Group of Pins + +Select the alternative function of one or more pins of GPIO. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +@param[in] af_en Bool. Whether alternative function is selected +*/ +void gpio_sel_af(uint16_t gpios, bool af_en) +{ + if (gpios & GPIO0) { + GPIO_SEL = (GPIO_SEL & (~0x3)) | (af_en ? 0x1 : 0x0); + } + if (gpios & GPIO1) { + GPIO_SEL = (GPIO_SEL & (~0xc)) | (af_en ? 0x4 : 0x0); + } + if (gpios & GPIO2) { + GPIO_SEL = (GPIO_SEL & (~0x30)) | (af_en ? 0x10 : 0x0); + } + if (gpios & GPIO7) { + GPIO_SEL = (GPIO_SEL & (~0xc000)) | (af_en ? 0x4000 : 0x0); + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the internal pull-up of a Group of Pins + +Enable or disable the internal pull-up of one or more pins of GPIO. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +@param[in] en Bool. Whether pull-up is enabled +*/ +void gpio_pullup(uint16_t gpios, bool en) +{ + if (en) { + GPIO_PULLUP |= gpios; + } else { + GPIO_PULLUP &= ~gpios; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the input function of a Group of Pins + +Enable or disable the input function of one or more pins of GPIO. Disabling +the input function of pins can decrease the power usage of the MCU. + +@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +@param[in] en Bool. Whether input function is enabled +*/ +void gpio_in_en(uint16_t gpios, bool en) +{ + if (en) { + GPIO_INEN &= ~gpios; + } else { + GPIO_INEN |= gpios; + } +} + + +/*---------------------------------------------------------------------------*/ +/** @brief Select the SWD function of GPIO 1/2 + +Enable or disable the SWD debugging port at GPIO 1/2. When SWD debugging port +is enabled, GPIO and AF of the SWD pins will be both unavailable. + +@param[in] en Bool. Whether SWD is enabled +*/ +void gpio_sel_swd(bool en) +{ + if (en) { + SWD_SEL = 1; + } else { + SWD_SEL = 0; + } +} -- cgit v1.2.3 From 1e3741cb202e14134874991496f6e008d8375c30 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 5 Jun 2019 21:31:56 +0000 Subject: swm050: doxygen fixups * Include the doc-swm050.h core file that defines the base groups. * Fix/tweak groupings to make things consistent with other targets. * Drop redundant type information. That's all included from the function signatures automatically by doxygen. * Added register descriptions from datasheet. --- lib/swm050/gpio.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) (limited to 'lib') diff --git a/lib/swm050/gpio.c b/lib/swm050/gpio.c index 31ee3969..fdf50996 100644 --- a/lib/swm050/gpio.c +++ b/lib/swm050/gpio.c @@ -1,3 +1,6 @@ +/** @addtogroup gpio_file GPIO peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,13 +22,15 @@ #include +/**@{*/ + /*---------------------------------------------------------------------------*/ /** @brief Set a Group of Pins Set one or more pins of GPIO to 1. Please note that this chip doesn't support atomic pin setting. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. */ @@ -40,7 +45,7 @@ void gpio_set(uint16_t gpios) Set one or more pins of GPIO to 0. Please note that this chip doesn't support atomic pin setting. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. */ @@ -52,10 +57,10 @@ void gpio_clear(uint16_t gpios) /*---------------------------------------------------------------------------*/ /** @brief Read a Group of Pins. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be read, use bitwise OR '|' to separate them. -@return Unsigned int16 value of the pin values. The bit position of the pin +@return The pin values as a bitfield. The bit position of the pin value returned corresponds to the pin number. */ uint16_t gpio_get(uint16_t gpios) @@ -68,7 +73,7 @@ uint16_t gpio_get(uint16_t gpios) Toggle one or more pins of GPIO. The non-toggled pins are not affected. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. */ @@ -83,7 +88,7 @@ void gpio_toggle(uint16_t gpios) Set the direction of one or more pins of GPIO to input. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. */ @@ -97,7 +102,7 @@ void gpio_input(uint16_t gpios) Set the direction of one or more pins of GPIO to output. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. */ @@ -111,10 +116,10 @@ void gpio_output(uint16_t gpios) Select the alternative function of one or more pins of GPIO. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. -@param[in] af_en Bool. Whether alternative function is selected +@param[in] af_en Whether alternative function is selected */ void gpio_sel_af(uint16_t gpios, bool af_en) { @@ -137,7 +142,7 @@ void gpio_sel_af(uint16_t gpios, bool af_en) Enable or disable the internal pull-up of one or more pins of GPIO. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. @param[in] en Bool. Whether pull-up is enabled @@ -155,12 +160,12 @@ void gpio_pullup(uint16_t gpios, bool en) /** @brief Enable the input function of a Group of Pins Enable or disable the input function of one or more pins of GPIO. Disabling -the input function of pins can decrease the power usage of the MCU. +the input function of pins decreases the power usage of the MCU. -@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id +@param[in] gpios Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use bitwise OR '|' to separate them. -@param[in] en Bool. Whether input function is enabled +@param[in] en true to enable input function. */ void gpio_in_en(uint16_t gpios, bool en) { @@ -178,7 +183,7 @@ void gpio_in_en(uint16_t gpios, bool en) Enable or disable the SWD debugging port at GPIO 1/2. When SWD debugging port is enabled, GPIO and AF of the SWD pins will be both unavailable. -@param[in] en Bool. Whether SWD is enabled +@param[in] en true to enable SWD. */ void gpio_sel_swd(bool en) { @@ -188,3 +193,5 @@ void gpio_sel_swd(bool en) SWD_SEL = 0; } } + +/**@}*/ -- cgit v1.2.3 From 7be50a5e75ed2d163d38a6759347c5e778ac02ab Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 7 Jun 2019 21:25:46 +0000 Subject: make: use $(PREFIX)gcc instead of $(PREFIX)-gcc The leading - makes it rather inconsistent with the majority of other projects around the world. Use the form everyone else uses. To solve this, properly pass prefix to inner makes as was always intended. Fixes: https://github.com/libopencm3/libopencm3/issues/1058 --- lib/efm32/ezr32wg/Makefile | 6 ++---- lib/efm32/g/Makefile | 6 ++---- lib/efm32/gg/Makefile | 6 ++---- lib/efm32/hg/Makefile | 6 ++---- lib/efm32/lg/Makefile | 6 ++---- lib/efm32/tg/Makefile | 6 ++---- lib/efm32/wg/Makefile | 6 ++---- lib/gd32/f1x0/Makefile | 6 ++---- lib/lm3s/Makefile | 6 ++---- lib/lm4f/Makefile | 6 ++---- lib/lpc13xx/Makefile | 6 ++---- lib/lpc17xx/Makefile | 6 ++---- lib/lpc43xx/m0/Makefile | 6 ++---- lib/lpc43xx/m4/Makefile | 6 ++---- lib/msp432/e4/Makefile | 6 ++---- lib/sam/3a/Makefile | 6 ++---- lib/sam/3n/Makefile | 6 ++---- lib/sam/3s/Makefile | 6 ++---- lib/sam/3u/Makefile | 6 ++---- lib/sam/3x/Makefile | 6 ++---- lib/sam/4l/Makefile | 6 ++---- lib/sam/d/Makefile | 6 ++---- lib/stm32/f0/Makefile | 6 ++---- lib/stm32/f1/Makefile | 6 ++---- lib/stm32/f2/Makefile | 6 ++---- lib/stm32/f3/Makefile | 6 ++---- lib/stm32/f4/Makefile | 6 ++---- lib/stm32/f7/Makefile | 6 ++---- lib/stm32/g0/Makefile | 6 ++---- lib/stm32/l0/Makefile | 6 ++---- lib/stm32/l1/Makefile | 6 ++---- lib/stm32/l4/Makefile | 6 ++---- lib/swm050/Makefile | 6 ++---- lib/vf6xx/Makefile | 6 ++---- 34 files changed, 68 insertions(+), 136 deletions(-) (limited to 'lib') diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 70b1a252..1a8f2a08 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -24,10 +24,8 @@ SRCLIBDIR ?= ../.. FAMILY = EZR32WG FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/g/Makefile b/lib/efm32/g/Makefile index 1aace7c6..f1f3568b 100644 --- a/lib/efm32/g/Makefile +++ b/lib/efm32/g/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_efm32g SRCLIBDIR ?= ../.. FAMILY = EFM32G -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/gg/Makefile b/lib/efm32/gg/Makefile index a96b3df8..231cec2c 100644 --- a/lib/efm32/gg/Makefile +++ b/lib/efm32/gg/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_efm32gg SRCLIBDIR ?= ../.. FAMILY = EFM32GG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/hg/Makefile b/lib/efm32/hg/Makefile index f5b897d8..fe59d9b9 100644 --- a/lib/efm32/hg/Makefile +++ b/lib/efm32/hg/Makefile @@ -24,10 +24,8 @@ LIBNAME = libopencm3_efm32hg SRCLIBDIR ?= ../.. FAMILY = EFM32HG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index a0163677..a5010169 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -23,10 +23,8 @@ LIBNAME = libopencm3_efm32lg SRCLIBDIR ?= ../.. FAMILY = EFM32LG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/tg/Makefile b/lib/efm32/tg/Makefile index 43ab711c..d29ade3e 100644 --- a/lib/efm32/tg/Makefile +++ b/lib/efm32/tg/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_efm32tg SRCLIBDIR ?= ../.. FAMILY = EFM32TG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index f2a767c5..4909c24e 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -24,10 +24,8 @@ SRCLIBDIR ?= ../.. FAMILY = EFM32WG FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/gd32/f1x0/Makefile b/lib/gd32/f1x0/Makefile index 72bb1598..9c605133 100755 --- a/lib/gd32/f1x0/Makefile +++ b/lib/gd32/f1x0/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_gd32f1x0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index 7bce6313..8c6338a7 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_lm3s SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/lm4f/Makefile b/lib/lm4f/Makefile index 2cb3853a..bc50bdc2 100644 --- a/lib/lm4f/Makefile +++ b/lib/lm4f/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_lm4f SRCLIBDIR ?= .. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 5b6ec485..35f27a3f 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_lpc13xx SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile index 5a34606e..c970bea1 100644 --- a/lib/lpc17xx/Makefile +++ b/lib/lpc17xx/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_lpc17xx SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/lpc43xx/m0/Makefile b/lib/lpc43xx/m0/Makefile index e05b799c..6f36574b 100644 --- a/lib/lpc43xx/m0/Makefile +++ b/lib/lpc43xx/m0/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_lpc43xx_m0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -O2 -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m0 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLPC43XX -DLPC43XX_M0 diff --git a/lib/lpc43xx/m4/Makefile b/lib/lpc43xx/m4/Makefile index 4c022f92..e9ca7eaf 100644 --- a/lib/lpc43xx/m4/Makefile +++ b/lib/lpc43xx/m4/Makefile @@ -24,10 +24,8 @@ LIBNAME = libopencm3_lpc43xx SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -O2 \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/msp432/e4/Makefile b/lib/msp432/e4/Makefile index 255af4cb..d4a40a78 100644 --- a/lib/msp432/e4/Makefile +++ b/lib/msp432/e4/Makefile @@ -23,10 +23,8 @@ LIBNAME = libopencm3_msp432e4 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/sam/3a/Makefile b/lib/sam/3a/Makefile index 5b9293d7..b77d12a2 100644 --- a/lib/sam/3a/Makefile +++ b/lib/sam/3a/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_sam3a SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3A diff --git a/lib/sam/3n/Makefile b/lib/sam/3n/Makefile index 2baa2ee2..e5c9e249 100644 --- a/lib/sam/3n/Makefile +++ b/lib/sam/3n/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_sam3n SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3N diff --git a/lib/sam/3s/Makefile b/lib/sam/3s/Makefile index 4ec0b12b..4fb973b4 100644 --- a/lib/sam/3s/Makefile +++ b/lib/sam/3s/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_sam3s SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3S diff --git a/lib/sam/3u/Makefile b/lib/sam/3u/Makefile index 4b0ab0ce..7424c842 100644 --- a/lib/sam/3u/Makefile +++ b/lib/sam/3u/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_sam3u SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3U diff --git a/lib/sam/3x/Makefile b/lib/sam/3x/Makefile index c3dbc02d..5234fb76 100644 --- a/lib/sam/3x/Makefile +++ b/lib/sam/3x/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_sam3x SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3X diff --git a/lib/sam/4l/Makefile b/lib/sam/4l/Makefile index 42a507f0..24144dd9 100644 --- a/lib/sam/4l/Makefile +++ b/lib/sam/4l/Makefile @@ -18,11 +18,9 @@ LIBNAME = libopencm3_sam4l SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi FP_FLAGS ?= -msoft-float - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM4L diff --git a/lib/sam/d/Makefile b/lib/sam/d/Makefile index 0a2a5c89..380ade30 100644 --- a/lib/sam/d/Makefile +++ b/lib/sam/d/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_samd SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAMD diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index efe25563..4480ff2f 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32f0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index c61f737b..de6082b5 100755 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32f1 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 2af763fd..0b5c8c82 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32f2 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index 362e0cd0..3a37b34d 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_stm32f3 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index c01c26e6..b80d6a65 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_stm32f4 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 35d226e9..fed0a274 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_stm32f7 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar # STM32F7 only supports single precision FPU FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv5-sp-d16 diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 9b4719bc..ffdd6fbf 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32g0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index baa19d3e..facaa8dd 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32l0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index cd614593..a9382cb5 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32l1 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index e0bed7c5..1de6e320 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_stm32l4 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/swm050/Makefile b/lib/swm050/Makefile index ccbf14a7..fc2f89d1 100644 --- a/lib/swm050/Makefile +++ b/lib/swm050/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_swm050 SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/vf6xx/Makefile b/lib/vf6xx/Makefile index d87247be..f24d2e9b 100644 --- a/lib/vf6xx/Makefile +++ b/lib/vf6xx/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_vf6xx SRCLIBDIR ?= .. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -- cgit v1.2.3 From d88d6fde123a8e614bb576bdfce0e1234b1146b2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 8 Jun 2019 11:46:30 +0000 Subject: cm3 systick: fix doxygen syntax Makes links works, avoids warnings. --- lib/cm3/systick.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c index a99593b6..d775dd06 100644 --- a/lib/cm3/systick.c +++ b/lib/cm3/systick.c @@ -48,7 +48,7 @@ * * @note The systick counter value might be undefined upon startup. To get * predictable behavior, it is a good idea to set or clear the counter after - * set reload. @seealso systick_clear + * set reload. @sa systick_clear * * @param[in] value uint32_t. 24 bit reload value. */ -- cgit v1.2.3 From b4b2a2101cc7f252c0ffab92cffc1aebf68a8108 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 10 Jun 2019 11:17:41 +0000 Subject: doc: nvic: generate a discoverable link name The nvic_ functions all had a broken link to an f1 list of irqs. Change the header generator to generate a fixed name, and link to them. Because of their scoping, this ok, they find the correct family's irq definitions. --- lib/cm3/nvic.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'lib') diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c index 6c2188a8..7b20941f 100644 --- a/lib/cm3/nvic.c +++ b/lib/cm3/nvic.c @@ -51,7 +51,7 @@ * * Enables a user interrupt. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_enable_irq(uint8_t irqn) @@ -64,7 +64,7 @@ void nvic_enable_irq(uint8_t irqn) * * Disables a user interrupt. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_disable_irq(uint8_t irqn) @@ -77,7 +77,7 @@ void nvic_disable_irq(uint8_t irqn) * * True if the interrupt has occurred and is waiting for service. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @return Boolean. Interrupt pending. */ @@ -92,7 +92,7 @@ uint8_t nvic_get_pending_irq(uint8_t irqn) * Force a user interrupt to a pending state. This has no effect if the * interrupt is already pending. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_set_pending_irq(uint8_t irqn) @@ -106,7 +106,7 @@ void nvic_set_pending_irq(uint8_t irqn) * Force remove a user interrupt from a pending state. This has no effect if * the interrupt is actively being serviced. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_clear_pending_irq(uint8_t irqn) @@ -119,7 +119,7 @@ void nvic_clear_pending_irq(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Enabled Interrupt * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @return Boolean. Interrupt enabled. */ @@ -144,7 +144,7 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn) * There are 4 priority levels only, given by the upper two bits of the * priority byte, as required by ARM standards. No grouping available. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of * 16) */ @@ -170,7 +170,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority) * * Interrupt has occurred and is currently being serviced. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @return Boolean. Interrupt active. */ -- cgit v1.2.3 From c9d45e0e2c47c68bf52a44af3dff8488c7b057f6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 10 Jun 2019 12:53:14 +0000 Subject: doc: stm32: move RCC to peripheral api style For f7, it was completely missing doc markers --- lib/stm32/common/rcc_common_all.c | 3 +++ lib/stm32/f0/rcc.c | 4 ++-- lib/stm32/f1/rcc.c | 4 ++-- lib/stm32/f2/rcc.c | 4 ++-- lib/stm32/f3/rcc.c | 4 ++-- lib/stm32/f4/rcc.c | 4 ++-- lib/stm32/f7/rcc.c | 13 +++++++++++++ lib/stm32/l0/rcc.c | 4 ++-- lib/stm32/l1/rcc.c | 4 ++-- lib/stm32/l4/rcc.c | 4 ++-- 10 files changed, 32 insertions(+), 16 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/rcc_common_all.c b/lib/stm32/common/rcc_common_all.c index e338dcea..5852b675 100644 --- a/lib/stm32/common/rcc_common_all.c +++ b/lib/stm32/common/rcc_common_all.c @@ -1,3 +1,6 @@ +/** @addtogroup rcc_file RCC peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index d4b79e5d..e0758c0a 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32F0xx-rcc-file RCC +/** @defgroup rcc_file RCC Peripheral API * - * @ingroup STM32F0xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F0xx Reset and Clock Control * diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 69041d7c..f09fbc0f 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32F1xx-rcc-file RCC +/** @defgroup rcc_file RCC Peripheral API -@ingroup STM32F1xx +@ingroup peripheral_apis @brief libopencm3 STM32F1xx Reset and Clock Control diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index d01dbcc0..3b3c73f6 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC Peripheral API * - * @ingroup STM32F2xx + * @ingroup peripheral_apis * * @section rcc_f2_api_ex Reset and Clock Control API. * diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c index 7908878f..2a3d2150 100644 --- a/lib/stm32/f3/rcc.c +++ b/lib/stm32/f3/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC Peripheral API * - * @ingroup STM32F3xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32F3xx Reset and Clock Control * diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index a20ce865..74778410 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC Peripheral API * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @section rcc_f4_api_ex Reset and Clock Control API. * diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c index 186109a5..64b27427 100644 --- a/lib/stm32/f7/rcc.c +++ b/lib/stm32/f7/rcc.c @@ -1,8 +1,19 @@ +/** @defgroup rcc_file RCC Peripheral API + * + * @ingroup peripheral_apis + * This library supports the Reset and Clock Control System in the STM32 series + * of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + #include #include #include #include +/**@{*/ + uint32_t rcc_ahb_frequency = 16000000; uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; @@ -472,3 +483,5 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock) rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; } + +/**@}*/ \ No newline at end of file diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index 4f902f87..a2a1b3c0 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32L0xx-rcc-file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32L0xx + * @ingroup peripheral_apis * * @brief libopencm3 STM32L0xx Reset and Clock Control * diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index 41cf1999..6d4ddfa7 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32L1xx-rcc-file RCC +/** @defgroup rcc_file RCC Peripheral API -@ingroup STM32L1xx +@ingroup peripheral_apis @brief libopencm3 STM32L1xx Reset and Clock Control diff --git a/lib/stm32/l4/rcc.c b/lib/stm32/l4/rcc.c index f44cfca1..1d3e3472 100644 --- a/lib/stm32/l4/rcc.c +++ b/lib/stm32/l4/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32L4xx + * @ingroup peripheral_apis * * @section rcc_l4_api_ex Reset and Clock Control API. * -- cgit v1.2.3 From 020d8833385b911fa56608c76aa2c3fdba1737d6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 11 Jun 2019 19:00:38 +0000 Subject: doc: stm32: flash: fix missing doxygen trailer --- lib/stm32/common/flash_common_f.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/common/flash_common_f.c b/lib/stm32/common/flash_common_f.c index 291fad9b..0b867def 100644 --- a/lib/stm32/common/flash_common_f.c +++ b/lib/stm32/common/flash_common_f.c @@ -43,3 +43,4 @@ void flash_clear_eop_flag(void) FLASH_SR |= FLASH_SR_EOP; } +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From e8f03b46151b76ee603ac4d4ec8de79e865df0a6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 11 Jun 2019 20:56:38 +0000 Subject: doc: usbd: Add missing / incorrect parameters. Just basic documentation to clear up errors for starters. --- lib/stm32/common/st_usbfs_core.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/common/st_usbfs_core.c b/lib/stm32/common/st_usbfs_core.c index a4ab414a..0dba875b 100644 --- a/lib/stm32/common/st_usbfs_core.c +++ b/lib/stm32/common/st_usbfs_core.c @@ -40,6 +40,7 @@ void st_usbfs_set_address(usbd_device *dev, uint8_t addr) /** * Set the receive buffer size for a given USB endpoint. * + * @param dev the usb device handle returned from @ref usbd_init * @param ep Index of endpoint to configure. * @param size Size in bytes of the RX buffer. Legal sizes : {2,4,6...62}; {64,96,128...992}. * @returns (uint16) Actual size set -- cgit v1.2.3 From cfdb9b78563bf3a7a4666fba3bb47b5cc90c962c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 11 Jun 2019 21:04:08 +0000 Subject: doc: stm32f0: rcc: add groups and tags for bus prescalers --- lib/stm32/f0/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index e0758c0a..a0e859b5 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -467,7 +467,7 @@ void rcc_set_pllxtpre(uint32_t pllxtpre) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB Prescale Factor. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre + * @param[in] ppre Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre(uint32_t ppre) -- cgit v1.2.3 From 9a53dc3a897a298217308e71455b460f55a9d9ee Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 11 Jun 2019 21:13:26 +0000 Subject: doc: stm32f0: adc: fix missing param (trivial) --- lib/stm32/f0/adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c index 30e1595c..663099dd 100644 --- a/lib/stm32/f0/adc.c +++ b/lib/stm32/f0/adc.c @@ -117,7 +117,7 @@ void adc_disable_discontinuous_mode(uint32_t adc) * @par * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) - * @param[in] adc ::adc_opmode. ADC operation mode (@ref adc_opmode) + * @param[in] opmode ADC operation mode */ void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode) -- cgit v1.2.3 From a143e5644e1c94d2e7fc4626b2e9fb2469aa37e7 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 11 Jun 2019 21:42:55 +0000 Subject: doc: stm32f1:rtc: fix trivial param typos --- lib/stm32/f1/rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c index e32424f4..ec2711ad 100644 --- a/lib/stm32/f1/rtc.c +++ b/lib/stm32/f1/rtc.c @@ -241,7 +241,7 @@ uint32_t rtc_get_alarm_val(void) /*---------------------------------------------------------------------------*/ /** @brief RTC set the Counter -@param[in] uint32_t counter_val: 32 bit time setting for the counter. +@param[in] counter_val 32 bit time setting for the counter. */ void rtc_set_counter_val(uint32_t counter_val) -- cgit v1.2.3 From b287bbd3220cd1843996015808cfb3729af6d034 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 11 Jun 2019 21:56:01 +0000 Subject: stm32: hash: move to peripherals API docs Drop redundant .c files and add groupings and labels. Eliminates warnings from doxygen --- lib/stm32/common/hash_common_f24.c | 5 +++-- lib/stm32/f2/hash.c | 31 ------------------------------- lib/stm32/f4/hash.c | 31 ------------------------------- 3 files changed, 3 insertions(+), 64 deletions(-) delete mode 100644 lib/stm32/f2/hash.c delete mode 100644 lib/stm32/f4/hash.c (limited to 'lib') diff --git a/lib/stm32/common/hash_common_f24.c b/lib/stm32/common/hash_common_f24.c index 24d489c1..b5046dd8 100644 --- a/lib/stm32/common/hash_common_f24.c +++ b/lib/stm32/common/hash_common_f24.c @@ -1,4 +1,6 @@ -/** @addtogroup hash_file +/** @addtogroup hash_file HASH Peripheral API + * + * @ingroup peripheral_apis * * @author @htmlonly © @endhtmlonly 2013 * Mikhail Avkhimenia @@ -145,7 +147,6 @@ void hash_digest() Makes a copy of the resulting hash. @param[out] data unsigned int32. Hash 4\5 words long depending on the algorithm. -@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm */ void hash_get_result(uint32_t *data) diff --git a/lib/stm32/f2/hash.c b/lib/stm32/f2/hash.c deleted file mode 100644 index ca48d8bb..00000000 --- a/lib/stm32/f2/hash.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup hash_file HASH - * - * @ingroup STM32F2xx - * - * @brief libopencm3 STM32F2xx Hash Processor - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include diff --git a/lib/stm32/f4/hash.c b/lib/stm32/f4/hash.c deleted file mode 100644 index cd791bff..00000000 --- a/lib/stm32/f4/hash.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup hash_file HASH - * - * @ingroup STM32F4xx - * - * @brief libopencm3 STM32F4xx Hash Processor - * - * @version 1.0.0 - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -- cgit v1.2.3 From f38c6f4f918a8c273a1280432860ca4107360e2f Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 8 Oct 2018 18:03:19 +0200 Subject: stm32l0: rcc: doc: fix rcc_clock_setup_pll brief. rcc_clock_setup_pll allows to use HSE or HSI as PLL source, comment is misleading. --- lib/stm32/l0/rcc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index a2a1b3c0..2429459d 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -496,9 +496,10 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) RCC_CCIPR = reg32 | (sel << shift); } -/** - * Set up sysclock with PLL from HSI16 - * @param clock full struct with desired parameters +/** @brief RCC Setup PLL and use it as Sysclk source. + * + * @param[in] clock full struct with desired parameters + * */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { -- cgit v1.2.3 From 9904f9803e3e0d36fc4a3aa6d75038df1535c3d9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 10 Jun 2019 11:20:57 +0000 Subject: doc: stm32: unify "peripheral API" titles doxygen really wants the @defgroup _and_ the @addtogroup to both have the full name, matching identically, to avoid all warnings. Standardize on the "CAPS_PERIPH peripheral API" style. --- lib/stm32/common/timer_common_all.c | 2 +- lib/stm32/f0/flash.c | 2 +- lib/stm32/f0/rcc.c | 2 +- lib/stm32/f1/flash.c | 2 +- lib/stm32/f1/rcc.c | 2 +- lib/stm32/f1/timer.c | 2 +- lib/stm32/f2/flash.c | 2 +- lib/stm32/f2/rcc.c | 2 +- lib/stm32/f3/flash.c | 2 +- lib/stm32/f3/rcc.c | 2 +- lib/stm32/f4/flash.c | 2 +- lib/stm32/f4/pwr.c | 2 +- lib/stm32/f4/rcc.c | 2 +- lib/stm32/f4/rtc.c | 2 +- lib/stm32/f7/flash.c | 2 +- lib/stm32/f7/rcc.c | 2 +- lib/stm32/g0/flash.c | 2 +- lib/stm32/l1/flash.c | 2 +- lib/stm32/l1/rcc.c | 2 +- lib/stm32/l1/timer.c | 2 +- lib/stm32/l4/flash.c | 2 +- 21 files changed, 21 insertions(+), 21 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index b9512f5b..64701836 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -1,4 +1,4 @@ -/** @addtogroup timer_file Timer peripheral API +/** @addtogroup timer_file TIMER peripheral API @ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2010 diff --git a/lib/stm32/f0/flash.c b/lib/stm32/f0/flash.c index 9e7ebc33..d594a5e6 100644 --- a/lib/stm32/f0/flash.c +++ b/lib/stm32/f0/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index a0e859b5..cc52fad3 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c index 8c8c6e5f..c990b1e6 100644 --- a/lib/stm32/f1/flash.c +++ b/lib/stm32/f1/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index f09fbc0f..9d01881a 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API @ingroup peripheral_apis diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c index b04bd971..6640d6f3 100644 --- a/lib/stm32/f1/timer.c +++ b/lib/stm32/f1/timer.c @@ -1,4 +1,4 @@ -/** @defgroup timer_file +/** @defgroup timer_file TIMER peripheral API @ingroup peripheral_apis @brief libopencm3 STM32F1xx Timers diff --git a/lib/stm32/f2/flash.c b/lib/stm32/f2/flash.c index 0744ba5b..958e62a9 100644 --- a/lib/stm32/f2/flash.c +++ b/lib/stm32/f2/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index 3b3c73f6..e530de47 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f3/flash.c b/lib/stm32/f3/flash.c index e987d374..7d73ce62 100644 --- a/lib/stm32/f3/flash.c +++ b/lib/stm32/f3/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c index 2a3d2150..3e1852bf 100644 --- a/lib/stm32/f3/rcc.c +++ b/lib/stm32/f3/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f4/flash.c b/lib/stm32/f4/flash.c index 75407d0d..93cef9f3 100644 --- a/lib/stm32/f4/flash.c +++ b/lib/stm32/f4/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c index 9bd2f8da..0d0c2d2d 100644 --- a/lib/stm32/f4/pwr.c +++ b/lib/stm32/f4/pwr.c @@ -1,4 +1,4 @@ -/** @defgroup pwr_file +/** @defgroup pwr_file PWR peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 74778410..66c3d4a1 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c index 4d1008c1..847fb55b 100644 --- a/lib/stm32/f4/rtc.c +++ b/lib/stm32/f4/rtc.c @@ -1,4 +1,4 @@ -/** @defgroup rtc_file +/** @defgroup rtc_file RTC peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/f7/flash.c b/lib/stm32/f7/flash.c index 341a32f2..82dcf4f3 100644 --- a/lib/stm32/f7/flash.c +++ b/lib/stm32/f7/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis */ diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c index 64b27427..7abdd770 100644 --- a/lib/stm32/f7/rcc.c +++ b/lib/stm32/f7/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API * * @ingroup peripheral_apis * This library supports the Reset and Clock Control System in the STM32 series diff --git a/lib/stm32/g0/flash.c b/lib/stm32/g0/flash.c index bb19d598..74ecf5d0 100644 --- a/lib/stm32/g0/flash.c +++ b/lib/stm32/g0/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c index 416b4efc..dfd90d25 100644 --- a/lib/stm32/l1/flash.c +++ b/lib/stm32/l1/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index 6d4ddfa7..44eac07b 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -1,4 +1,4 @@ -/** @defgroup rcc_file RCC Peripheral API +/** @defgroup rcc_file RCC peripheral API @ingroup peripheral_apis diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c index f9ce5dd0..fa701dd1 100644 --- a/lib/stm32/l1/timer.c +++ b/lib/stm32/l1/timer.c @@ -1,4 +1,4 @@ -/** @defgroup timer_file +/** @defgroup timer_file TIMER peripheral API @ingroup peripheral_apis @brief libopencm3 STM32L1xx Timers diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c index 2aff56a6..16007ee6 100644 --- a/lib/stm32/l4/flash.c +++ b/lib/stm32/l4/flash.c @@ -1,4 +1,4 @@ -/** @defgroup flash_file +/** @defgroup flash_file FLASH peripheral API * * @ingroup peripheral_apis * -- cgit v1.2.3 From 4533b1be68d61b615ae3466ee133e89742e85fe9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 12 Jun 2019 21:44:49 +0000 Subject: doc: fix some trivial parameter name style problems Just gets them out of the way so we can do bigger item changes. --- lib/ethernet/mac_stm32fxx7.c | 2 +- lib/stm32/can.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/ethernet/mac_stm32fxx7.c b/lib/ethernet/mac_stm32fxx7.c index 2a404b61..525f6229 100644 --- a/lib/ethernet/mac_stm32fxx7.c +++ b/lib/ethernet/mac_stm32fxx7.c @@ -371,7 +371,7 @@ void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits) * * @param[in] phy uint8_t ID of the PHY (defaults to 1) * @param[in] reg uint8_t Register address - * @param[in] bits uint16_t Bits that have to be set (or'ed) + * @param[in] setbits uint16_t Bits that have to be set (or'ed) */ void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits) { diff --git a/lib/stm32/can.c b/lib/stm32/can.c index 37599c9b..f404a4a7 100644 --- a/lib/stm32/can.c +++ b/lib/stm32/can.c @@ -464,7 +464,7 @@ void can_fifo_release(uint32_t canport, uint8_t fifo) @param[out] fmi Unsigned int8 pointer. ID of the matched filter. @param[out] length Unsigned int8 pointer. Length of message payload. @param[out] data Unsigned int8[]. Message payload data. -@param[out] timestamp. Pointer to store the message timestamp. +@param[out] timestamp Pointer to store the message timestamp. Only valid on time triggered CAN. Use NULL to ignore. */ void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, -- cgit v1.2.3 From 5eefc214f6be9a78433d3dd81a1f3ee91d010d41 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 12 Jun 2019 21:48:49 +0000 Subject: doc: stm32: fix "osc" incorrect linkages Was copied around a lot, was always wrong. --- lib/stm32/f0/rcc.c | 22 +++++++++++----------- lib/stm32/f1/rcc.c | 14 +++++++------- lib/stm32/l0/rcc.c | 11 +++++------ 3 files changed, 23 insertions(+), 24 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index cc52fad3..182bdd28 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -51,7 +51,7 @@ uint32_t rcc_apb1_frequency = 8000000; /* 8MHz after reset */ * Clear the interrupt flag that was set when a clock oscillator became ready * to use. * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) @@ -84,7 +84,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) @@ -117,7 +117,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) @@ -150,7 +150,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID * @returns int. Boolean value for flag set. */ @@ -238,7 +238,7 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc) * becomes ready (see @ref rcc_osc_ready_int_flag and @ref * rcc_wait_for_osc_ready). * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_on(enum rcc_osc osc) @@ -276,7 +276,7 @@ void rcc_osc_on(enum rcc_osc osc) * @note An oscillator cannot be turned off if it is selected as the system * clock. * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_off(enum rcc_osc osc) @@ -327,7 +327,7 @@ void rcc_css_disable(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. * - * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, LSE and PLL have + * @param clk Oscillator ID. Only HSE, LSE and PLL have * effect. */ @@ -357,7 +357,7 @@ void rcc_set_sysclk_source(enum rcc_osc clk) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the USB Clock. * - * @param[in] osc enum ::osc_t. Oscillator ID. Only HSI48 or PLL have + * @param clk Oscillator ID. Only HSI48 or PLL have * effect. */ void rcc_set_usbclk_source(enum rcc_osc clk) @@ -402,7 +402,7 @@ void rcc_disable_rtc_clock(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the RTC clock -@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI. +@param[in] clk RTC clock source. Only HSE/32, LSE and LSI. */ void rcc_set_rtc_clock_source(enum rcc_osc clk) @@ -501,7 +501,7 @@ void rcc_set_prediv(uint32_t prediv) /*---------------------------------------------------------------------------*/ /** @brief RCC Get the System Clock Source. * - * @returns ::osc_t System clock source: + * @returns current system clock source */ enum rcc_osc rcc_system_clock_source(void) @@ -543,7 +543,7 @@ uint32_t rcc_get_i2c_clocks(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Get the USB Clock Source. * - * @returns ::osc_t USB clock source: + * @returns Currently selected USB clock source */ enum rcc_osc rcc_usb_clock_source(void) diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 9d01881a..6d1c252a 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -64,7 +64,7 @@ uint32_t rcc_ahb_frequency = 8000000; Clear the interrupt flag that was set when a clock oscillator became ready to use. -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) @@ -97,7 +97,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt -@param[in] osc enum ::osc_t. Oscillator ID +@param osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) @@ -130,7 +130,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) @@ -163,7 +163,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID @returns int. Boolean value for flag set. */ @@ -255,7 +255,7 @@ status flag is available to indicate when the oscillator becomes ready (see backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_on(enum rcc_osc osc) @@ -296,7 +296,7 @@ backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect) or the backup domain has been (see reset @ref rcc_backupdomain_reset). -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_off(enum rcc_osc osc) @@ -452,7 +452,7 @@ void rcc_enable_rtc_clock(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the RTC clock -@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI. +@param[in] clock_source RTC clock source. Only HSE/128, LSE and LSI. */ void rcc_set_rtc_clock_source(enum rcc_osc clock_source) diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index 2429459d..e1401924 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -105,7 +105,7 @@ void rcc_osc_off(enum rcc_osc osc) * Clear the interrupt flag that was set when a clock oscillator became ready * to use. * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) { @@ -137,7 +137,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) { @@ -169,7 +169,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) { @@ -201,7 +201,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID * @returns int. Boolean value for flag set. */ int rcc_osc_ready_int_flag(enum rcc_osc osc) @@ -279,8 +279,7 @@ void rcc_set_hsi48_source_pll(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. * - * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, HSI16, MSI and PLL have - * effect. + * @param[in] osc Oscillator ID. Only HSE, HSI16, MSI and PLL have effect. */ void rcc_set_sysclk_source(enum rcc_osc osc) -- cgit v1.2.3 From 55c899c93bbe9e4aa506d4a5f8d9fdf839e0bdd5 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 12 Jun 2019 22:14:22 +0000 Subject: doc: stm32l0: rcc: add groups requested by existing docs And cleanse the arguments to all match the docs. --- lib/stm32/l0/rcc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index e1401924..39bdaff7 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -309,7 +309,7 @@ void rcc_set_sysclk_source(enum rcc_osc osc) * * @note This only has effect when the PLL is disabled. * - * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf + * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll_multiplier(uint32_t factor) @@ -325,7 +325,7 @@ void rcc_set_pll_multiplier(uint32_t factor) * * @note This only has effect when the PLL is disabled. * - * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf + * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pdf */ void rcc_set_pll_divider(uint32_t factor) @@ -353,7 +353,7 @@ void rcc_set_pll_source(uint32_t pllsrc) * * @note The APB1 clock frequency must not exceed 32MHz. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre + * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre1(uint32_t ppre) @@ -368,7 +368,7 @@ void rcc_set_ppre1(uint32_t ppre) * * @note The APB2 clock frequency must not exceed 32MHz. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre + * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb2pre */ void rcc_set_ppre2(uint32_t ppre) @@ -393,7 +393,7 @@ void rcc_set_hpre(uint32_t hpre) /*---------------------------------------------------------------------------*/ /** @brief Set the range of the MSI oscillator * - * @param range desired range @ref rcc_icscr_msirange + * @param msi_range desired range @ref rcc_icscr_msirange */ void rcc_set_msi_range(uint32_t msi_range) { @@ -448,8 +448,8 @@ void rcc_set_usart2_sel(uint32_t usart2_sel) /*---------------------------------------------------------------------------*/ /** @brief Set the peripheral clock source -* - * @param sel periphral clock source + * @param periph peripheral of desire, eg XXX_BASE + * @param sel peripheral clock source */ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) { -- cgit v1.2.3 From 9f58ad439348f6fa225c9786b29b7316a34c1b78 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 12 Jun 2019 23:16:58 +0000 Subject: doc: fix trivial missing trailers or typos --- lib/stm32/common/flash_common_idcache.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/common/flash_common_idcache.c b/lib/stm32/common/flash_common_idcache.c index ebfdd0ad..c7da2066 100644 --- a/lib/stm32/common/flash_common_idcache.c +++ b/lib/stm32/common/flash_common_idcache.c @@ -55,4 +55,5 @@ void flash_icache_reset(void) FLASH_ACR |= FLASH_ACR_ICRST; } +/**@}*/ -- cgit v1.2.3 From 209dea96e7b45a1266b070bf1157a4e4a7a49800 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 12 Jun 2019 23:20:59 +0000 Subject: doc: stm32g0: rcc: fix missing/typod param names --- lib/stm32/g0/rcc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'lib') diff --git a/lib/stm32/g0/rcc.c b/lib/stm32/g0/rcc.c index adfe5b5c..c3f157ab 100644 --- a/lib/stm32/g0/rcc.c +++ b/lib/stm32/g0/rcc.c @@ -382,7 +382,7 @@ void rcc_enable_pllr(bool enable) /** * @brief Configure APB peripheral clock prescaler - * @param[in] APB clock prescaler value @ref rcc_cfgr_ppre + * @param[in] ppre APB clock prescaler value @ref rcc_cfgr_ppre */ void rcc_set_ppre(uint32_t ppre) { @@ -395,7 +395,7 @@ void rcc_set_ppre(uint32_t ppre) /** * @brief Configure AHB peripheral clock prescaler - * @param[in] AHB clock prescaler value @ref rcc_cfgr_hpre + * @param[in] hpre AHB clock prescaler value @ref rcc_cfgr_hpre */ void rcc_set_hpre(uint32_t hpre) { @@ -408,7 +408,7 @@ void rcc_set_hpre(uint32_t hpre) /** * @brief Configure HSI16 clock division factor to feed SYSCLK - * @param[in] HSYSSIS clock division factor @ref rcc_cr_hsidiv + * @param[in] hsidiv HSYSSIS clock division factor @ref rcc_cr_hsidiv */ void rcc_set_hsisys_div(uint32_t hsidiv) { @@ -421,7 +421,7 @@ void rcc_set_hsisys_div(uint32_t hsidiv) /** * @brief Configure mco prescaler. - * @param[in] mcore prescaler value @ref rcc_cfgr_mcopre + * @param[in] mcopre prescaler value @ref rcc_cfgr_mcopre */ void rcc_set_mcopre(uint32_t mcopre) { @@ -434,7 +434,7 @@ void rcc_set_mcopre(uint32_t mcopre) /** * @brief Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). taking care of flash/pwr and src configuration - * @param rcc_clock_scale with desired parameters + * @param clock rcc_clock_scale with desired parameters */ void rcc_clock_setup(const struct rcc_clock_scale *clock) { @@ -497,6 +497,7 @@ void rcc_set_rng_clk_div(uint32_t rng_div) /** * @brief Set the peripheral clock source + * @param periph peripheral of choice, eg XXX_BASE * @param sel periphral clock source */ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) -- cgit v1.2.3 From 3d422a930fde20bf1de177d663d93eb532c9a117 Mon Sep 17 00:00:00 2001 From: Eric Van Albert Date: Mon, 10 Jun 2019 23:06:33 -0400 Subject: stm32l4: add common DAC support Replace the DAC1_BASE style, only used on l4 with the standard DAC_BASE used on all other targets. Reviewed-by: Karl Palsson --- lib/stm32/l4/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index 1de6e320..43f4c831 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -54,6 +54,7 @@ OBJS += dma_common_l1f013.o OBJS += iwdg_common_all.o OBJS += rtc_common_l1f024.o OBJS += spi_common_all.o spi_common_v2.o +OBJS += dac_common_all.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o OBJS += st_usbfs_core.o st_usbfs_v2.o -- cgit v1.2.3 From bb98d0755cc64298c781c45c95607c4f0fd49dc5 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 17 Jan 2019 18:10:47 +0100 Subject: stm32g0: add iwdg. regular v2 iwdg. --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index ffdd6fbf..23fff3e2 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -39,6 +39,7 @@ OBJS += flash.o flash_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o +OBJS += iwdg_common_all.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From a51ecb4719995a3de117922d756e8b5634a2fa76 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 21 Jan 2019 15:20:46 +0100 Subject: stm32g0: add usart. --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 23fff3e2..8d2f05b0 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -40,6 +40,7 @@ OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += iwdg_common_all.o +OBJS += usart_common_all.o usart_common_v2.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From ba3b50a4ad68c3c94f1d1c45a97e7fbd32f6a4cf Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 21 Jan 2019 12:07:43 +0100 Subject: stm32g0: add spi. classic "common" spi + frf bit spi peripheral. As for i2c, i could only check signals on scope, no spi slave to check, but looks ok. --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 8d2f05b0..d7964259 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -41,6 +41,7 @@ OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += iwdg_common_all.o OBJS += usart_common_all.o usart_common_v2.o +OBJS += spi_common_all.o spi_common_v1_frf.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From 5a349d3ab6762e19ece874551fa2a6cbfdc485c3 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 21 Jan 2019 15:36:56 +0100 Subject: stm32g0: add i2c. Regular i2c peripheral. Partially tested as i had no i2c slave on hand, but i can see i2c on my scope.. --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index d7964259..db3b8912 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -42,6 +42,7 @@ OBJS += rcc.o rcc_common_all.o OBJS += iwdg_common_all.o OBJS += usart_common_all.o usart_common_v2.o OBJS += spi_common_all.o spi_common_v1_frf.o +OBJS += i2c_common_v2.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From 38006c3c826bd8784a1d41d184a248eacd9fd67a Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 5 Feb 2019 18:16:54 +0100 Subject: stm32g0: add rng. Regular rng peripheral, with one additional bit : clock error detection apparently available on l4 chips). Curiously, Clock error detection is _disabled_ when bit is set, but bit is cleared by default, so peripheral / clock error detection behaves like all other chips.. NB: RNG need proper rcc_ccicr_rngsel bits set to work, no clock is set by default. Note also that on that chip fRNGCLK must be higher than fHCLK/32 --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index db3b8912..3d52362b 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -43,6 +43,7 @@ OBJS += iwdg_common_all.o OBJS += usart_common_all.o usart_common_v2.o OBJS += spi_common_all.o spi_common_v1_frf.o OBJS += i2c_common_v2.o +OBJS += rng_common_v1.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From 74526f00ccae51010550d7e90313b67a31440320 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 4 Feb 2019 13:38:19 +0100 Subject: stm32g0: add crc. Regular crc-v2 peripheral, except that CRC_IDR is now 32bit wide - but not used. --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 3d52362b..ceadfd8c 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -44,6 +44,7 @@ OBJS += usart_common_all.o usart_common_v2.o OBJS += spi_common_all.o spi_common_v1_frf.o OBJS += i2c_common_v2.o OBJS += rng_common_v1.o +OBJS += crc_common_all.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From 8173fb7249f0cd4043a088224f4f6f13d20c7b80 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 17 Jan 2019 18:27:48 +0100 Subject: stm32g0: add timer. Only tim2/3/7/14 have been really tested yet - but the others should work as well. --- lib/stm32/g0/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index ceadfd8c..c9e8f74f 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -45,6 +45,7 @@ OBJS += spi_common_all.o spi_common_v1_frf.o OBJS += i2c_common_v2.o OBJS += rng_common_v1.o OBJS += crc_common_all.o +OBJS += timer_common_all.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From ab1b0c1a5eed9c85dd1daed1e2a884b79d3f732c Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 12 Jun 2019 18:02:28 +0200 Subject: stm32g0: exti doc fixup --- lib/stm32/g0/exti.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/g0/exti.c b/lib/stm32/g0/exti.c index 5a55583c..fb5534ba 100644 --- a/lib/stm32/g0/exti.c +++ b/lib/stm32/g0/exti.c @@ -1,4 +1,5 @@ -/** @addtogroup exti_file +/** @defgroup exti_file EXTI peripheral API + * @ingroup peripheral_apis * * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot * -- cgit v1.2.3 From 6c1f54dcb7bca7dd8cd4ffd9d48612fdfc302a0f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 13 Jun 2019 21:30:06 +0000 Subject: stm32g0: sort makefiles easier to merge, easier to find things you're looking for. --- lib/stm32/g0/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index c9e8f74f..7a663b50 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -34,18 +34,18 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs +OBJS += crc_common_all.o OBJS += exti.o exti_common_all.o OBJS += flash.o flash_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o -OBJS += iwdg_common_all.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += spi_common_all.o spi_common_v1_frf.o -OBJS += i2c_common_v2.o OBJS += rng_common_v1.o -OBJS += crc_common_all.o +OBJS += spi_common_all.o spi_common_v1_frf.o OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o VPATH +=../:../../cm3:../common -- cgit v1.2.3 From 6198f2575f5c8ee17b3a6700252aa23bd33a395f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 16 Jun 2019 18:20:34 +0000 Subject: doc: efm32hg: fix missing parameter names --- lib/efm32/hg/cmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/efm32/hg/cmu.c b/lib/efm32/hg/cmu.c index f7de65e7..d5f3b4ce 100644 --- a/lib/efm32/hg/cmu.c +++ b/lib/efm32/hg/cmu.c @@ -54,7 +54,7 @@ bool cmu_get_lock_flag(void) * * Enable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -69,7 +69,7 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken) * @brief Disable Peripheral Clock in running mode. * Disable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -264,7 +264,7 @@ enum cmu_osc cmu_get_hfclk_source(void) /** * Set USBCLK clock source - * @retval enum cmu_osc Oscillator name + * @param osc Oscillator name */ void cmu_set_usbclk_source(enum cmu_osc osc) { -- cgit v1.2.3 From 7d344b187dae32c456b81f6e8b370ac0fffcef4e Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 11 Jun 2019 16:59:57 +0200 Subject: stm32: dma: add dma_set_channel_request to ease dma cselr usage. --- lib/stm32/common/dma_common_csel.c | 46 ++++++++++++++++++++++++++++++++++++++ lib/stm32/f0/Makefile | 3 ++- lib/stm32/l0/Makefile | 2 +- lib/stm32/l4/Makefile | 2 +- 4 files changed, 50 insertions(+), 3 deletions(-) create mode 100644 lib/stm32/common/dma_common_csel.c (limited to 'lib') diff --git a/lib/stm32/common/dma_common_csel.c b/lib/stm32/common/dma_common_csel.c new file mode 100644 index 00000000..4cf1fca9 --- /dev/null +++ b/lib/stm32/common/dma_common_csel.c @@ -0,0 +1,46 @@ +/** @addtogroup dma_file DMA peripheral API +@ingroup peripheral_apis + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/*---------------------------------------------------------------------------*/ +/** @brief DMA Channel Set Request Selection + +Set DMA request mapping selection for given channel. Refer to datasheet for channel +request mapping tables. + +@param[in] dma DMA controller base address: DMA1 or DMA2 +@param[in] channel Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] request DMA request mapping. +*/ + +void dma_set_channel_request(uint32_t dma, uint8_t channel, uint8_t request) +{ + uint32_t reg32 = DMA_CSELR(dma) & ~(DMA_CSELR_CxS_MASK << DMA_CSELR_CxS_SHIFT(channel)); + DMA_CSELR(dma) = reg32 | ((DMA_CSELR_CxS_MASK & request) << DMA_CSELR_CxS_SHIFT(channel)); +} + +/**@}*/ diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 4480ff2f..9aeb71e5 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -39,7 +39,8 @@ OBJS = can.o flash.o rcc.o comparator.o \ OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ - dma_common_l1f013.o exti_common_all.o \ + dma_common_l1f013.o dma_common_csel.o \ + exti_common_all.o \ dac_common_all.o \ timer_common_all.o timer_common_f0234.o rcc_common_all.o diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index facaa8dd..3cad62eb 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -42,7 +42,7 @@ OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o OBJS += gpio_common_all.o gpio_common_f0234.o rcc_common_all.o OBJS += adc_common_v2.o OBJS += crs_common_all.o -OBJS += dma_common_l1f013.o +OBJS += dma_common_l1f013.o dma_common_csel.o OBJS += exti_common_all.o OBJS += flash_common_all.o flash_common_l01.o OBJS += i2c_common_v2.o diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index 43f4c831..dd834031 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -50,7 +50,7 @@ OBJS += rng_common_v1.o OBJS += timer_common_all.o OBJS += i2c_common_v2.o OBJS += usart_common_all.o usart_common_v2.o -OBJS += dma_common_l1f013.o +OBJS += dma_common_l1f013.o dma_common_csel.o OBJS += iwdg_common_all.o OBJS += rtc_common_l1f024.o OBJS += spi_common_all.o spi_common_v2.o -- cgit v1.2.3 From c28a5a81cf17e47af2907de2c6b1146bf2afa98e Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 11:48:18 +0000 Subject: stm32: rng-v1: fix missing doxygen parameter --- lib/stm32/common/rng_common_v1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/common/rng_common_v1.c b/lib/stm32/common/rng_common_v1.c index 3b2a45a7..e26b6880 100644 --- a/lib/stm32/common/rng_common_v1.c +++ b/lib/stm32/common/rng_common_v1.c @@ -47,7 +47,7 @@ void rng_enable(void) /** Randomizes a number (non-blocking). * Can fail if a clock error or seed error is detected. Consult the Reference * Manual, but "try again", potentially after resetting the peripheral - * @param pointer to a uint32_t that will be randomized. + * @param rand_nr pointer to a uint32_t that will be randomized. * @returns true on success, pointer is only written to on success * @sa rng_get_random_blocking */ -- cgit v1.2.3 From 2d0d29d9469cdc82cda27f85879e1b9ffbd323ca Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:37:09 +0000 Subject: doc: stm32l1: timer: fix params, missing groupings --- lib/stm32/l1/timer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c index fa701dd1..43f8d541 100644 --- a/lib/stm32/l1/timer.c +++ b/lib/stm32/l1/timer.c @@ -38,8 +38,7 @@ Set timer options register on TIM2 or TIM3, used for trigger remapping. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: -@ref tim3_opt_trigger_remap. +@param[in] option Desired option @ref tim2_opt_trigger_remap and @ref tim3_opt_trigger_remap */ void timer_set_option(uint32_t timer_peripheral, uint32_t option) -- cgit v1.2.3 From 452b39555b6437500805d174ea8e91d24eb53cc1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 12:00:52 +0000 Subject: stm32f0: sort makefile object list Consistent approach, easier to find what you need, easier to merge --- lib/stm32/f0/Makefile | 41 ++++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 9aeb71e5..6d832a57 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -34,25 +34,28 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = can.o flash.o rcc.o comparator.o \ - adc.o desig.o - -OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ - pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ - dma_common_l1f013.o dma_common_csel.o \ - exti_common_all.o \ - dac_common_all.o \ - timer_common_all.o timer_common_f0234.o rcc_common_all.o - -OBJS += adc_common_v2.o -OBJS += crs_common_all.o -OBJS += flash_common_all.o flash_common_f.o flash_common_f01.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += i2c_common_v2.o -OBJS += spi_common_all.o spi_common_v2.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v2.o +OBJS += adc.o adc_common_v2.o +OBJS += can.o +OBJS += comparator.o +OBJS += crc_common_all.o crc_v2.o +OBJS += crs_common_all.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o dma_common_csel.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += iwdg_common_all.o +OBJS += i2c_common_v2.o +OBJS += pwr_common_v1.o +OBJS += rcc.o rcc_common_all.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o timer_common_f0234.o +OBJS += usart_common_all.o usart_common_v2.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v2.o VPATH += ../../usb:../:../../cm3:../common -- cgit v1.2.3 From 8002148286b57aa2ac32013fea66b55e25d04d53 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:38:27 +0000 Subject: stm32f1: Makefile: sort objects periphs, ethernet, usb. Sorted for ease of finding, ease of merging. --- lib/stm32/f1/Makefile | 40 ++++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 16 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index de6082b5..9154a5fe 100755 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -34,22 +34,30 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc.o adc_common_v1.o can.o desig.o flash.o gpio.o \ - rcc.o rtc.o timer.o -OBJS += mac.o mac_stm32fxx7.o phy.o phy_ksz80x1.o - -OBJS += crc_common_all.o dac_common_all.o dma_common_l1f013.o \ - gpio_common_all.o i2c_common_v1.o iwdg_common_all.o \ - pwr_common_v1.o \ - timer_common_all.o usart_common_all.o usart_common_f124.o \ - rcc_common_all.o exti_common_all.o - -OBJS += flash_common_all.o flash_common_f.o flash_common_f01.o -OBJS += spi_common_all.o spi_common_v1.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_dwc_common.o usb_f107.o -OBJS += st_usbfs_core.o st_usbfs_v1.o +OBJS += adc.o adc_common_v1.o +OBJS += can.o +OBJS += crc_common_all.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += gpio.o gpio_common_all.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += pwr_common_v1.o +OBJS += rcc.o rcc_common_all.o +OBJS += rtc.o +OBJS += spi_common_all.o spi_common_v1.o +OBJS += timer.o timer_common_all.o +OBJS += usart_common_all.o usart_common_f124.o + +OBJS += mac.o mac_stm32fxx7.o +OBJS += phy.o phy_ksz80x1.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_dwc_common.o usb_f107.o +OBJS += st_usbfs_core.o st_usbfs_v1.o VPATH += ../../usb:../:../../cm3:../common:../../ethernet -- cgit v1.2.3 From 17a0e30cd86a9c364b4a1d5295e585e5932706bf Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:46:15 +0000 Subject: stm32f2: Sort Makefile --- lib/stm32/f2/Makefile | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 0b5c8c82..290cc330 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -34,22 +34,26 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o desig.o +OBJS += crc_common_all.o +OBJS += crypto_common_f24.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o flash_common_idcache.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += hash_common_f24.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o +OBJS += usart_common_all.o usart_common_f124.o -OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ - gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \ - iwdg_common_all.o rtc_common_l1f024.o \ - timer_common_all.o timer_common_f0234.o \ - timer_common_f24.o usart_common_all.o usart_common_f124.o \ - hash_common_f24.o \ - crypto_common_f24.o exti_common_all.o rcc_common_all.o -OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o -OBJS += flash_common_idcache.o -OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o - -OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \ - usb_f107.o usb_f207.o usb_msc.o +OBJS += usb.o usb_standard.o usb_control.o usb_msc.o +OBJS += usb_dwc_common.o usb_f107.o usb_f207.o VPATH += ../../usb:../:../../cm3:../common -- cgit v1.2.3 From 48eb9957d66e7eb8456a163a5a597e28193492e0 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:49:44 +0000 Subject: stm32f3: sort makefile --- lib/stm32/f3/Makefile | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index 3a37b34d..c24cae90 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -35,21 +35,25 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = rcc.o adc.o can.o flash.o desig.o - -OBJS += gpio_common_all.o gpio_common_f0234.o \ - dac_common_all.o crc_common_all.o crc_v2.o \ - iwdg_common_all.o pwr_common_v1.o dma_common_l1f013.o\ - timer_common_all.o timer_common_f0234.o \ - exti_common_all.o rcc_common_all.o -OBJS += adc_common_v2.o adc_common_v2_multi.o -OBJS += flash_common_all.o flash_common_f.o -OBJS += usart_common_v2.o usart_common_all.o -OBJS += i2c_common_v2.o -OBJS += spi_common_all.o spi_common_v2.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v1.o +OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o +OBJS += can.o +OBJS += crc_common_all.o crc_v2.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += pwr_common_v1.o +OBJS += rcc.o rcc_common_all.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o timer_common_f0234.o +OBJS += usart_common_v2.o usart_common_all.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v1.o VPATH += ../../usb:../:../../cm3:../common -- cgit v1.2.3 From 00f947ec840f23fd0dc6ffb121a414b3afbed13a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:51:45 +0000 Subject: stm32f4: consistent makefile Had already been sorted, now just make it consistent format with the others. --- lib/stm32/f4/Makefile | 58 +++++++++++++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index b80d6a65..747ee549 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -37,36 +37,36 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o -OBJS += can.o -OBJS += crc_common_all.o -OBJS += crypto_common_f24.o crypto.o -OBJS += dac_common_all.o -OBJS += desig.o -OBJS += dma_common_f24.o -OBJS += dma2d_common_f47.o -OBJS += dsi_common_f47.o -OBJS += exti_common_all.o -OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o -OBJS += flash_common_idcache.o -OBJS += fmc_common_f47.o -OBJS += gpio_common_all.o gpio_common_f0234.o -OBJS += hash_common_f24.o -OBJS += i2c_common_v1.o -OBJS += iwdg_common_all.o -OBJS += ltdc_common_f47.o -OBJS += pwr_common_v1.o pwr.o -OBJS += rcc_common_all.o rcc.o -OBJS += rng_common_v1.o -OBJS += rtc_common_l1f024.o rtc.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o -OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o -OBJS += usart_common_all.o usart_common_f124.o - -OBJS += usb.o usb_standard.o usb_control.o usb_dwc_common.o \ - usb_f107.o usb_f207.o usb_msc.o +OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o +OBJS += can.o +OBJS += crc_common_all.o +OBJS += crypto_common_f24.o crypto.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += dma2d_common_f47.o +OBJS += dsi_common_f47.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o +OBJS += flash_common_idcache.o +OBJS += fmc_common_f47.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += hash_common_f24.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += ltdc_common_f47.o +OBJS += pwr_common_v1.o pwr.o +OBJS += rcc_common_all.o rcc.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o rtc.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o +OBJS += usart_common_all.o usart_common_f124.o -OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o +OBJS += usb.o usb_standard.o usb_control.o usb_msc.o +OBJS += usb_dwc_common.o usb_f107.o usb_f207.o + +OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet -- cgit v1.2.3 From 3fe8c3cf93314c1d34ca96f5512719c65274bc5f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:53:53 +0000 Subject: stm32f7: makefile consistent style Had already been sorted like f4, just use the same style as everywhere now --- lib/stm32/f7/Makefile | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index fed0a274..693bb58d 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -40,30 +40,30 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o -OBJS += can.o -OBJS += crc_common_all.o crc_v2.o -OBJS += dac_common_all.o -OBJS += desig.o -OBJS += dma_common_f24.o -OBJS += dma2d_common_f47.o -OBJS += dsi_common_f47.o -OBJS += exti_common_all.o -OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o -OBJS += fmc_common_f47.o -OBJS += gpio_common_all.o gpio_common_f0234.o -OBJS += i2c_common_v2.o -OBJS += iwdg_common_all.o -OBJS += ltdc_common_f47.o -OBJS += pwr.o rcc.o -OBJS += rcc_common_all.o -OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v2.o -OBJS += timer_common_all.o -OBJS += usart_common_all.o usart_common_v2.o +OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o +OBJS += can.o +OBJS += crc_common_all.o crc_v2.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += dma2d_common_f47.o +OBJS += dsi_common_f47.o +OBJS += exti_common_all.o +OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o +OBJS += fmc_common_f47.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += ltdc_common_f47.o +OBJS += pwr.o rcc.o +OBJS += rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o # Ethernet -OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o +OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet -- cgit v1.2.3 From 50607901335c06dc71ce37192d429af231dc7995 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 20:57:28 +0000 Subject: stm32l4: sort makefile Consistent with all others. The separation of the common and specific portions is unnecessary and misleading. --- lib/stm32/l4/Makefile | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index dd834031..514128f6 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -35,29 +35,27 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -# Specific objs -OBJS = adc.o flash.o pwr.o rcc.o can.o +OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o +OBJS += can.o +OBJS += crc_common_all.o crc_v2.o +OBJS += crs_common_all.o +OBJS += dac_common_all.o +OBJS += dma_common_l1f013.o dma_common_csel.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += pwr.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o -# common/shared objs -OBJS += rcc_common_all.o -OBJS += gpio_common_all.o gpio_common_f0234.o -OBJS += exti_common_all.o -OBJS += adc_common_v2.o adc_common_v2_multi.o -OBJS += crc_common_all.o crc_v2.o -OBJS += crs_common_all.o -OBJS += flash_common_all.o flash_common_f.o flash_common_idcache.o -OBJS += rng_common_v1.o -OBJS += timer_common_all.o -OBJS += i2c_common_v2.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += dma_common_l1f013.o dma_common_csel.o -OBJS += iwdg_common_all.o -OBJS += rtc_common_l1f024.o -OBJS += spi_common_all.o spi_common_v2.o -OBJS += dac_common_all.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v2.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v2.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet -- cgit v1.2.3 From 9165c8c56749ee784d8fc7d16b2e91408a1032b4 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:00:36 +0000 Subject: stm32l1: consistent makefile sorting and unifying specific/shared. --- lib/stm32/l1/Makefile | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index a9382cb5..b5853051 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -33,22 +33,27 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = desig.o flash.o rcc.o lcd.o -OBJS += crc_common_all.o dac_common_all.o -OBJS += dma_common_l1f013.o -OBJS += flash_common_all.o flash_common_l01.o -OBJS += gpio_common_all.o gpio_common_f0234.o -OBJS += i2c_common_v1.o iwdg_common_all.o -OBJS += pwr_common_v1.o pwr_common_v2.o rtc_common_l1f024.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o -OBJS += timer.o timer_common_all.o -OBJS += usart_common_all.o usart_common_f124.o -OBJS += exti_common_all.o -OBJS += rcc_common_all.o -OBJS += adc.o adc_common_v1.o adc_common_v1_multi.o +OBJS += adc.o adc_common_v1.o adc_common_v1_multi.o +OBJS += flash.o +OBJS += crc_common_all.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o +OBJS += exti_common_all.o +OBJS += flash_common_all.o flash_common_l01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += lcd.o +OBJS += pwr_common_v1.o pwr_common_v2.o +OBJS += rcc.o rcc_common_all.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer.o timer_common_all.o +OBJS += usart_common_all.o usart_common_f124.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v1.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v1.o VPATH += ../../usb:../:../../cm3:../common -- cgit v1.2.3 From 1cd9ca6dc25464c3808b2e18900660cfff636603 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:02:16 +0000 Subject: vf6xx: consistent makefile Hasn't seen any work for a while, but it should still be consistent with other parts of the tree --- lib/vf6xx/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/vf6xx/Makefile b/lib/vf6xx/Makefile index f24d2e9b..c8bfd2a3 100644 --- a/lib/vf6xx/Makefile +++ b/lib/vf6xx/Makefile @@ -34,7 +34,11 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = ccm.o uart.o gpio.o iomuxc.o + +OBJS += ccm.o +OBJS += gpio.o +OBJS += iomuxc.o +OBJS += uart.o VPATH += ../cm3 -- cgit v1.2.3 From 528e4865c8e9fc91724341ec82a9295aa091e482 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:06:04 +0000 Subject: sam: consistent makefile styles sorted as per style now --- lib/sam/3a/Makefile | 5 ++++- lib/sam/3n/Makefile | 5 ++++- lib/sam/3s/Makefile | 5 ++++- lib/sam/3u/Makefile | 5 ++++- lib/sam/3x/Makefile | 5 ++++- lib/sam/4l/Makefile | 7 ++++++- 6 files changed, 26 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/sam/3a/Makefile b/lib/sam/3a/Makefile index b77d12a2..61183ae4 100644 --- a/lib/sam/3a/Makefile +++ b/lib/sam/3a/Makefile @@ -29,7 +29,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3a3u3x.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/3n/Makefile b/lib/sam/3n/Makefile index e5c9e249..167e9093 100644 --- a/lib/sam/3n/Makefile +++ b/lib/sam/3n/Makefile @@ -29,7 +29,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3n3s.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3n3s.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../cm3:../common diff --git a/lib/sam/3s/Makefile b/lib/sam/3s/Makefile index 4fb973b4..e20931e2 100644 --- a/lib/sam/3s/Makefile +++ b/lib/sam/3s/Makefile @@ -30,7 +30,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3n3s.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3n3s.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/3u/Makefile b/lib/sam/3u/Makefile index 7424c842..5dce7e92 100644 --- a/lib/sam/3u/Makefile +++ b/lib/sam/3u/Makefile @@ -30,7 +30,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3a3u3x.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/3x/Makefile b/lib/sam/3x/Makefile index 5234fb76..5fa4c419 100644 --- a/lib/sam/3x/Makefile +++ b/lib/sam/3x/Makefile @@ -29,7 +29,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3a3u3x.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/4l/Makefile b/lib/sam/4l/Makefile index 24144dd9..fd8d825b 100644 --- a/lib/sam/4l/Makefile +++ b/lib/sam/4l/Makefile @@ -27,7 +27,12 @@ TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adcife.o gpio.o scif.o pm.o usart_common_all.o usart.o + +OBJS += adcife.o +OBJS += gpio.o +OBJS += pm.o +OBJS += scif.o +OBJS += usart_common_all.o usart.o VPATH += ../../usb:../../cm3:../common -- cgit v1.2.3 From 4ec81b01f53f56a994ccdca8445755c57750a5d5 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:07:31 +0000 Subject: lpc13xx/lpc17xx: consistent makefiles --- lib/lpc13xx/Makefile | 3 ++- lib/lpc17xx/Makefile | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 35f27a3f..7d12597e 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -33,7 +33,8 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o + +OBJS += gpio.o VPATH += ../cm3 diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile index c970bea1..eaaef8c8 100644 --- a/lib/lpc17xx/Makefile +++ b/lib/lpc17xx/Makefile @@ -33,7 +33,9 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o pwr.o + +OBJS += gpio.o +OBJS += pwr.o VPATH += ../cm3 -- cgit v1.2.3 From d501e606ed7970fc4263000827a78d13478ba75f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:10:16 +0000 Subject: ti lm3s/lm4f: consistent makefiles --- lib/lm3s/Makefile | 7 ++++++- lib/lm4f/Makefile | 13 ++++++++++--- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'lib') diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index 8c6338a7..287ccacc 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -33,7 +33,12 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o assert.o rcc.o usart.o + +OBJS += assert.o +OBJS += gpio.o +OBJS += rcc.o +OBJS += usart.o +OBJS += vector.o VPATH += ../cm3 diff --git a/lib/lm4f/Makefile b/lib/lm4f/Makefile index bc50bdc2..ab23f083 100644 --- a/lib/lm4f/Makefile +++ b/lib/lm4f/Makefile @@ -35,9 +35,16 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o assert.o systemcontrol.o rcc.o uart.o \ - usb_lm4f.o usb.o usb_control.o usb_standard.o -OBJS += usb_msc.o + +OBJS += assert.o +OBJS += gpio.o +OBJS += rcc.o +OBJS += systemcontrol.o +OBJS += uart.o +OBJS += vector.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_lm4f.o VPATH += ../usb:../cm3 -- cgit v1.2.3 From b063c18a0c1dba6d7b5a0fc46114461d93bee5ac Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:11:03 +0000 Subject: ti msp432: consistent makefile --- lib/msp432/e4/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/msp432/e4/Makefile b/lib/msp432/e4/Makefile index d4a40a78..53d20f78 100644 --- a/lib/msp432/e4/Makefile +++ b/lib/msp432/e4/Makefile @@ -38,7 +38,8 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = systemcontrol.o gpio.o +OBJS += gpio.o +OBJS += systemcontrol.o VPATH += ../:../../cm3:../common -- cgit v1.2.3 From 3363e18c9cfebfd697ecc29fed632f39aaea7ae6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:11:24 +0000 Subject: swm050: consistent makefile --- lib/swm050/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/swm050/Makefile b/lib/swm050/Makefile index fc2f89d1..977f5f74 100644 --- a/lib/swm050/Makefile +++ b/lib/swm050/Makefile @@ -32,7 +32,8 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = gpio.o + +OBJS += gpio.o VPATH += ../cm3 -- cgit v1.2.3 From a522f7f3fa3bdc1b75cf24ffa97013ce6d7b99e6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:12:45 +0000 Subject: gd32: consistent makefile --- lib/gd32/f1x0/Makefile | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/gd32/f1x0/Makefile b/lib/gd32/f1x0/Makefile index 9c605133..fb5cd4d6 100755 --- a/lib/gd32/f1x0/Makefile +++ b/lib/gd32/f1x0/Makefile @@ -33,12 +33,9 @@ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o flash.o - -OBJS += \ - gpio_common_all.o gpio_common_f0234.o \ - rcc_common_all.o \ - flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += rcc.o rcc_common_all.o VPATH += ../:../../cm3:../common:../../stm32/common -- cgit v1.2.3 From e97c4b39b95f2d4c6f9b4875dafd5cbca17c1519 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:17:32 +0000 Subject: efm32: consistent makefiles sorted and styled per the rest of the project --- lib/efm32/ezr32wg/Makefile | 15 +++++++++------ lib/efm32/hg/Makefile | 9 ++++++--- lib/efm32/lg/Makefile | 15 +++++++++------ lib/efm32/wg/Makefile | 15 +++++++++------ 4 files changed, 33 insertions(+), 21 deletions(-) (limited to 'lib') diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 1a8f2a08..75bd7a3f 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -36,14 +36,17 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = -OBJS = gpio_common.o cmu_common.o prs_common.o -OBJS += adc_common.o dma_common.o timer_common.o -OBJS += dac_common.o +OBJS += adc_common.o +OBJS += cmu_common.o +OBJS += dac_common.o +OBJS += dma_common.o +OBJS += gpio_common.o +OBJS += prs_common.o +OBJS += timer_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_efm32.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/efm32/hg/Makefile b/lib/efm32/hg/Makefile index fe59d9b9..c6f7ba5a 100644 --- a/lib/efm32/hg/Makefile +++ b/lib/efm32/hg/Makefile @@ -38,9 +38,12 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = cmu.o gpio_common.o timer_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o \ - usb_dwc_common.o usb_efm32hg.o +OBJS += cmu.o +OBJS += gpio_common.o +OBJS += timer_common.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_dwc_common.o usb_efm32hg.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index a5010169..7da85ca0 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -36,14 +36,17 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = -OBJS = gpio_common.o cmu_common.o prs_common.o -OBJS += adc_common.o dma_common.o timer_common.o -OBJS += dac_common.o +OBJS += adc_common.o +OBJS += cmu_common.o +OBJS += dac_common.o +OBJS += dma_common.o +OBJS += gpio_common.o +OBJS += prs_common.o +OBJS += timer_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_efm32.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index 4909c24e..e089defd 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -36,14 +36,17 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = -OBJS = gpio_common.o cmu_common.o prs_common.o -OBJS += adc_common.o dma_common.o timer_common.o -OBJS += dac_common.o +OBJS += adc_common.o +OBJS += cmu_common.o +OBJS += dac_common.o +OBJS += dma_common.o +OBJS += gpio_common.o +OBJS += prs_common.o +OBJS += timer_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_efm32.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common -- cgit v1.2.3 From 1bc8a015f7ec6c26a98012a47f391fcb1b9976e6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:54:53 +0000 Subject: doc: stm32: timer: fix trivial parameter misnaming --- lib/stm32/common/timer_common_f24.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/stm32/common/timer_common_f24.c b/lib/stm32/common/timer_common_f24.c index ce1c1e38..8368c38a 100644 --- a/lib/stm32/common/timer_common_f24.c +++ b/lib/stm32/common/timer_common_f24.c @@ -33,8 +33,7 @@ Set timer options register on TIM2 or TIM5, used for trigger remapping on TIM2, and similarly for TIM5 for oscillator calibration purposes. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5: -@ref tim5_opt_trigger_remap. +@param option flags TIM2 @ref tim2_opt_trigger_remap or TIM5 @ref tim5_opt_trigger_remap */ void timer_set_option(uint32_t timer_peripheral, uint32_t option) -- cgit v1.2.3 From 615918ffdef98d5a1b3a219b5c9e1e22bb4ef2a3 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 17 Jun 2019 21:46:39 +0200 Subject: stm32g0: compile spi_common_v1.c fix #1067 --- lib/stm32/g0/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 7a663b50..376ee203 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -43,7 +43,7 @@ OBJS += iwdg_common_all.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v1_frf.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o OBJS += timer_common_all.o OBJS += usart_common_all.o usart_common_v2.o -- cgit v1.2.3 From 05214d826ad2e0466c4f1e68e3e5fb13ebda1556 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 18 Jun 2019 13:39:02 +0200 Subject: stm32l0: consistent makefile. sorted and styled per the rest of the project --- lib/stm32/l0/Makefile | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'lib') diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index 3cad62eb..a9743caf 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -34,25 +34,25 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = rcc.o desig.o -OBJS += pwr_common_v1.o pwr_common_v2.o -OBJS += timer_common_all.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o - -OBJS += gpio_common_all.o gpio_common_f0234.o rcc_common_all.o -OBJS += adc_common_v2.o -OBJS += crs_common_all.o -OBJS += dma_common_l1f013.o dma_common_csel.o -OBJS += exti_common_all.o -OBJS += flash_common_all.o flash_common_l01.o -OBJS += i2c_common_v2.o -OBJS += rng_common_v1.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += iwdg_common_all.o -OBJS += rtc_common_l1f024.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v2.o +OBJS += adc_common_v2.o +OBJS += crs_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o dma_common_csel.o +OBJS += exti_common_all.o +OBJS += flash_common_all.o flash_common_l01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += pwr_common_v1.o pwr_common_v2.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v2.o VPATH += ../../usb:../:../../cm3:../common -- cgit v1.2.3 From a5562f27c04c05221b220d264e3c312f8a50843a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 17 Jun 2019 21:53:27 +0000 Subject: doc: efm32: fix doxygen warnings Mind you, this doesn't actually fix that most of these are _missing_ that is a subsequent commit --- lib/efm32/common/adc_common.c | 4 ++++ lib/efm32/common/cmu_common.c | 4 ++-- lib/efm32/common/dac_common.c | 16 ++++++++-------- lib/efm32/common/dma_common.c | 9 ++++----- 4 files changed, 18 insertions(+), 15 deletions(-) (limited to 'lib') diff --git a/lib/efm32/common/adc_common.c b/lib/efm32/common/adc_common.c index 980c7151..f1d14aeb 100644 --- a/lib/efm32/common/adc_common.c +++ b/lib/efm32/common/adc_common.c @@ -633,6 +633,7 @@ uint32_t adc_scan_data_peak(uint32_t adc) /** * Set ADC scan gain calibration * @param[in] adc ADC (use ADCx) + * @param scan_gain calibration of gain for internal ref */ void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain) { @@ -642,6 +643,7 @@ void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain) /** * Set ADC scan offset calibration * @param[in] adc ADC (use ADCx) + * @param scan_offset calibration of offset for internal ref */ void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset) { @@ -651,6 +653,7 @@ void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset) /** * Set ADC single gain calibration * @param[in] adc ADC (use ADCx) + * @param single_gain calibration of gain for internal ref */ void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain) { @@ -660,6 +663,7 @@ void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain) /** * Set ADC single offset calibration * @param[in] adc ADC (use ADCx) + * @param single_offset calibration of offset for internal ref */ void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset) { diff --git a/lib/efm32/common/cmu_common.c b/lib/efm32/common/cmu_common.c index 6edc42dd..c1472ed6 100644 --- a/lib/efm32/common/cmu_common.c +++ b/lib/efm32/common/cmu_common.c @@ -54,7 +54,7 @@ bool cmu_get_lock_flag(void) * * Enable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -69,7 +69,7 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken) * @brief Disable Peripheral Clock in running mode. * Disable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) diff --git a/lib/efm32/common/dac_common.c b/lib/efm32/common/dac_common.c index 8a211afc..4d5c1036 100644 --- a/lib/efm32/common/dac_common.c +++ b/lib/efm32/common/dac_common.c @@ -95,8 +95,8 @@ void dac_disable_sine(uint32_t dac) /** * Set PRS trigger source on DAC channel * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) - * @param[in] prs_ch PRS Channel (use PRS_CHx) + * @param[in] dac_chan DAC Channel (use DAC_CHx) + * @param[in] prs_chan PRS Channel (use PRS_CHx) */ void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan, enum prs_ch prs_chan) @@ -110,7 +110,7 @@ void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan, /** * Enable PRS triggerring * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_enable_prs_trigger(uint32_t dac, enum dac_ch ch) { @@ -120,7 +120,7 @@ void dac_enable_prs_trigger(uint32_t dac, enum dac_ch ch) /** * Disable PRS triggerring * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_disable_prs_trigger(uint32_t dac, enum dac_ch ch) { @@ -130,7 +130,7 @@ void dac_disable_prs_trigger(uint32_t dac, enum dac_ch ch) /** * Enable auto refresh * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_enable_auto_refresh(uint32_t dac, enum dac_ch ch) { @@ -140,7 +140,7 @@ void dac_enable_auto_refresh(uint32_t dac, enum dac_ch ch) /** * Disable auto refresh * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_disable_auto_refresh(uint32_t dac, enum dac_ch ch) { @@ -150,7 +150,7 @@ void dac_disable_auto_refresh(uint32_t dac, enum dac_ch ch) /** * Enable channel * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_enable_channel(uint32_t dac, enum dac_ch ch) { @@ -160,7 +160,7 @@ void dac_enable_channel(uint32_t dac, enum dac_ch ch) /** * Disable channel * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_disable_channel(uint32_t dac, enum dac_ch ch) { diff --git a/lib/efm32/common/dma_common.c b/lib/efm32/common/dma_common.c index e6967bfe..856bf0ab 100644 --- a/lib/efm32/common/dma_common.c +++ b/lib/efm32/common/dma_common.c @@ -563,8 +563,8 @@ static inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc, * descriptor * @param[in] ch Channel (use DMA_CHx) * @param[in] src_start Source data start address - * @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc() - * set value to calculate the src data end address from @a src_start + * this function uses @ref dma_calc_end_from_start to calculate the + * src data end address from @a src_start * @note dma_desc_set_count() should be called first. * @note dma_desc_set_src_inc() should be called first. */ @@ -586,9 +586,8 @@ void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, * descriptor * @param[in] ch Channel (use DMA_CHx) * @param[in] dest_start Destination data start address - * @param[in] this function use dma_desc_set_count() and - * dma_desc_set_dest_inc() set value to calculate the dest data end - * address from @a dest_start + * this function uses @ref dma_calc_end_from_start to calculate the + * dest data end address from @a dest_start * @note dma_desc_set_count() should be called first. * @note dma_desc_set_dest_inc() should be called first. */ -- cgit v1.2.3 From 9bc432474b1ceca6b130564da75879539c513694 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 00:53:54 +0000 Subject: doc: efm32: include gpio_common gpio_common was built, but wasn't picked up by any documentation. Use the peripheral_apis style from stm32, but try out the #pragma once style. Downside is you don't get warnings if you include an sub layer .h file. Upsides are * no ifdef/endif blocks * no /**@cond*/ /**@endcond*/ blocks * that's enough win! --- lib/efm32/common/gpio_common.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/gpio_common.c b/lib/efm32/common/gpio_common.c index 23574228..0c768ca4 100644 --- a/lib/efm32/common/gpio_common.c +++ b/lib/efm32/common/gpio_common.c @@ -1,3 +1,6 @@ +/** @addtogroup gpio_file GPIO peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include +/**@{*/ + /** * Enable GPIO registers lock. * @see gpio_disable_lock() @@ -173,3 +178,5 @@ void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios) { GPIO_P_PINLOCKN(gpio_port) = ~gpios; } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 093edfb8810c03513396abbaeab391d234d21fe9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 00:59:05 +0000 Subject: doc: efm32: cmu: move to peripheral_apis Was completely undocumented before. Just needed different tagging so it could be picked up. No attempt at this stage of sharing more code between the cmu modules. --- lib/efm32/common/cmu_common.c | 7 +++++++ lib/efm32/hg/cmu.c | 7 +++++++ 2 files changed, 14 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/cmu_common.c b/lib/efm32/common/cmu_common.c index c1472ed6..8a577516 100644 --- a/lib/efm32/common/cmu_common.c +++ b/lib/efm32/common/cmu_common.c @@ -1,3 +1,6 @@ +/** @addtogroup cmu_file CMU peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -20,6 +23,8 @@ #include #include +/**@{*/ + /** * Enable CMU registers lock. */ @@ -270,3 +275,5 @@ void cmu_clock_setup_in_hfxo_out_48mhz(void) /* wait till HFXO not selected */ while (cmu_get_hfclk_source() != HFXO); } + +/**@}*/ \ No newline at end of file diff --git a/lib/efm32/hg/cmu.c b/lib/efm32/hg/cmu.c index d5f3b4ce..3d678eeb 100644 --- a/lib/efm32/hg/cmu.c +++ b/lib/efm32/hg/cmu.c @@ -1,3 +1,6 @@ +/** @addtogroup cmu_file CMU peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -20,6 +23,8 @@ #include +/**@{*/ + /** * Enable CMU registers lock. */ @@ -305,3 +310,5 @@ void cmu_wait_for_usbclk_selected(enum cmu_osc osc) return; } } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From c8b8285446f56784b89832a2319726a5cffbb2f8 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:03:29 +0000 Subject: doc: efm32: dac: enable peripheral_apis documentation --- lib/efm32/common/dac_common.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/dac_common.c b/lib/efm32/common/dac_common.c index 4d5c1036..4d982401 100644 --- a/lib/efm32/common/dac_common.c +++ b/lib/efm32/common/dac_common.c @@ -1,3 +1,6 @@ +/** @addtogroup dac_file DAC peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -22,6 +25,8 @@ #include +/**@{*/ + /** * Set DAC refresh cycle * @param[in] dac DAC (use DACx) @@ -166,3 +171,5 @@ void dac_disable_channel(uint32_t dac, enum dac_ch ch) { DAC_CHx_CTRL(dac, ch) &= ~DAC_CH_CTRL_REFREN; } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From ae777bb9200dbcc205d4032b4bba6f906ff1860a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:04:26 +0000 Subject: doc: efm32: timer: enable peripheral_apis style --- lib/efm32/common/timer_common.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/timer_common.c b/lib/efm32/common/timer_common.c index 22664954..8f82fcfe 100644 --- a/lib/efm32/common/timer_common.c +++ b/lib/efm32/common/timer_common.c @@ -1,3 +1,6 @@ +/** @addtogroup timer_file TIMER peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include +/**@{*/ + #define HAS_DEAD_TIME_INSERTION(timer) (timer == TIMER0) /** @@ -60,3 +65,5 @@ void timer_set_top(uint32_t timer, uint32_t top) { TIMER_TOP(timer) = top; } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 0626f6f75d748acd4a689589cabf5d2151864714 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:08:22 +0000 Subject: doc: efm32: adc: enable peripheral_apis style --- lib/efm32/common/adc_common.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/adc_common.c b/lib/efm32/common/adc_common.c index f1d14aeb..4c7a1481 100644 --- a/lib/efm32/common/adc_common.c +++ b/lib/efm32/common/adc_common.c @@ -1,3 +1,6 @@ +/** @addtogroup adc_file ADC peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include +/**@{*/ + /** * Set ADC over sampling * @param[in] adc ADC (use ADCx) @@ -669,3 +674,5 @@ void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset) { ADC_CAL(adc) = (ADC_CAL(adc) & ADC_CAL_SINGLEOFF_MASK) | single_offset; } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 7861f2c2f65208d6834bf83de30dbd1c67cae41e Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:19:27 +0000 Subject: doc: efm32: prs: enable peripheral_apis style Include _basic_ description of unusual acronyms --- lib/efm32/common/prs_common.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/prs_common.c b/lib/efm32/common/prs_common.c index bcd47f7f..877c5c07 100644 --- a/lib/efm32/common/prs_common.c +++ b/lib/efm32/common/prs_common.c @@ -1,3 +1,10 @@ +/** @addtogroup prs_file PRS peripheral API + * @ingroup peripheral_apis + * @brief EFM32 Peripheral Reflex System (PRS). + * The Peripheral Reflex System (PRS) system is a network which allows the + * different peripheral modules to communicate directly with each other + * without involving the CPU. + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +26,8 @@ #include +/**@{*/ + /** * Enable PRS output to GPIO. * @param[in] ch Channel (use PRS_CHx) @@ -138,3 +147,5 @@ void prs_set_signal(enum prs_ch ch, uint32_t signal) PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK) | signal; } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 7a058016b51f62f6e472eaa4371f168b947811dd Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:20:17 +0000 Subject: doc: efm32: dma: enable peripheral_apis --- lib/efm32/common/dma_common.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib') diff --git a/lib/efm32/common/dma_common.c b/lib/efm32/common/dma_common.c index 856bf0ab..e6a18ced 100644 --- a/lib/efm32/common/dma_common.c +++ b/lib/efm32/common/dma_common.c @@ -1,3 +1,6 @@ +/** @addtogroup dma_file DMA peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include +/**@{*/ + #define CHANNEL_SUPPORT_LOOP(ch) (((ch) == DMA_CH0) || ((ch) == DMA_CH1)) /** @@ -618,3 +623,5 @@ void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode) cfg |= DMA_DESC_CH_CFG_CYCLE_CTRL(mode); DMA_DESC_CHx_CFG(desc_base, ch) = cfg; } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 7e2cd050aa1c85e4a60c244dedf32265fb8b4da2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:36:06 +0000 Subject: doc: efm32: acmp: document, and include via peripheral_apis Requires a stub .c file as it has common includes with out any common code (yet) --- lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 3 files changed, 3 insertions(+) (limited to 'lib') diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 75bd7a3f..e7fd6bdc 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -37,6 +37,7 @@ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs +OBJS += acmp_common.o OBJS += adc_common.o OBJS += cmu_common.o OBJS += dac_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 7da85ca0..7c6eb1a1 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -37,6 +37,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs +OBJS += acmp_common.o OBJS += adc_common.o OBJS += cmu_common.o OBJS += dac_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index e089defd..17c91eb9 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -37,6 +37,7 @@ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs +OBJS += acmp_common.o OBJS += adc_common.o OBJS += cmu_common.o OBJS += dac_common.o -- cgit v1.2.3 From dc3bb245f1f77c9898546817c54d5a51fc559048 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Jun 2019 01:50:23 +0000 Subject: doc: efm32: acmp: add missing file Classssssssic error. Don't git add the local file created. doh. --- lib/efm32/common/acmp_common.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 lib/efm32/common/acmp_common.c (limited to 'lib') diff --git a/lib/efm32/common/acmp_common.c b/lib/efm32/common/acmp_common.c new file mode 100644 index 00000000..1095d673 --- /dev/null +++ b/lib/efm32/common/acmp_common.c @@ -0,0 +1,15 @@ +/** @addtogroup acmp_file ACMP peripheral API + * @ingroup peripheral_apis + * @brief Analog Comparator helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + -- cgit v1.2.3 From 790d62423084a013f3f91ca483f5a9e92abafb50 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 09:35:45 +0000 Subject: doc: efm32: burtc: tag properly for doxyen includes a stub .c file until there are APIs defined. --- lib/efm32/common/burtc_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/burtc_common.c (limited to 'lib') diff --git a/lib/efm32/common/burtc_common.c b/lib/efm32/common/burtc_common.c new file mode 100644 index 00000000..e909f8cd --- /dev/null +++ b/lib/efm32/common/burtc_common.c @@ -0,0 +1,15 @@ +/** @addtogroup burtc_file BURTC peripheral API + * @ingroup peripheral_apis + * @brief Backup RTC helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index e7fd6bdc..44763d7e 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -39,6 +39,7 @@ ARFLAGS = rcs OBJS += acmp_common.o OBJS += adc_common.o +OBJS += burtc_common.o OBJS += cmu_common.o OBJS += dac_common.o OBJS += dma_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 7c6eb1a1..94ca814c 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -39,6 +39,7 @@ ARFLAGS = rcs OBJS += acmp_common.o OBJS += adc_common.o +OBJS += burtc_common.o OBJS += cmu_common.o OBJS += dac_common.o OBJS += dma_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index 17c91eb9..f2ca009f 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -39,6 +39,7 @@ ARFLAGS = rcs OBJS += acmp_common.o OBJS += adc_common.o +OBJS += burtc_common.o OBJS += cmu_common.o OBJS += dac_common.o OBJS += dma_common.o -- cgit v1.2.3 From 4c01e47aed58d7fed433b0f96bce7abe71b24505 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 10:58:19 +0000 Subject: doc: efm32: emu: tag for doxygen properly Requires a stub .c file to make the common files be included until we build some APIs. --- lib/efm32/common/emu_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/emu_common.c (limited to 'lib') diff --git a/lib/efm32/common/emu_common.c b/lib/efm32/common/emu_common.c new file mode 100644 index 00000000..1015e8e0 --- /dev/null +++ b/lib/efm32/common/emu_common.c @@ -0,0 +1,15 @@ +/** @addtogroup emu_file EMU peripheral API + * @ingroup peripheral_apis + * @brief Energy Management Unit helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 44763d7e..2ea15784 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -43,6 +43,7 @@ OBJS += burtc_common.o OBJS += cmu_common.o OBJS += dac_common.o OBJS += dma_common.o +OBJS += emu_common.o OBJS += gpio_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 94ca814c..de10765a 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -43,6 +43,7 @@ OBJS += burtc_common.o OBJS += cmu_common.o OBJS += dac_common.o OBJS += dma_common.o +OBJS += emu_common.o OBJS += gpio_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index f2ca009f..ea30bbcd 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -43,6 +43,7 @@ OBJS += burtc_common.o OBJS += cmu_common.o OBJS += dac_common.o OBJS += dma_common.o +OBJS += emu_common.o OBJS += gpio_common.o OBJS += prs_common.o OBJS += timer_common.o -- cgit v1.2.3 From 25dc3a9b4bf9077b5c78d0768de8c486e0ccbdf2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 11:03:22 +0000 Subject: doc: efm32: i2c: tag for doxygen Includes a stub .c file until there are some APIs --- lib/efm32/common/i2c_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/i2c_common.c (limited to 'lib') diff --git a/lib/efm32/common/i2c_common.c b/lib/efm32/common/i2c_common.c new file mode 100644 index 00000000..304f12e6 --- /dev/null +++ b/lib/efm32/common/i2c_common.c @@ -0,0 +1,15 @@ +/** @addtogroup i2c_file I2C peripheral API + * @ingroup peripheral_apis + * @brief I²C helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 2ea15784..3f270dbf 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -45,6 +45,7 @@ OBJS += dac_common.o OBJS += dma_common.o OBJS += emu_common.o OBJS += gpio_common.o +OBJS += i2c_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index de10765a..98572eae 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -45,6 +45,7 @@ OBJS += dac_common.o OBJS += dma_common.o OBJS += emu_common.o OBJS += gpio_common.o +OBJS += i2c_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index ea30bbcd..207be1cf 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -45,6 +45,7 @@ OBJS += dac_common.o OBJS += dma_common.o OBJS += emu_common.o OBJS += gpio_common.o +OBJS += i2c_common.o OBJS += prs_common.o OBJS += timer_common.o -- cgit v1.2.3 From c92f3dc0adb6d6502a86fd6681d7f8fb1c1a1feb Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 11:11:27 +0000 Subject: doc: efm32: letimer: include tags for doxygen Include a stub .c file to document the shared headers. --- lib/efm32/common/letimer_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/letimer_common.c (limited to 'lib') diff --git a/lib/efm32/common/letimer_common.c b/lib/efm32/common/letimer_common.c new file mode 100644 index 00000000..7c1ba9cb --- /dev/null +++ b/lib/efm32/common/letimer_common.c @@ -0,0 +1,15 @@ +/** @addtogroup letimer_file LETIMER peripheral API + * @ingroup peripheral_apis + * @brief Low Energy Timer helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 3f270dbf..fd50eafc 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -46,6 +46,7 @@ OBJS += dma_common.o OBJS += emu_common.o OBJS += gpio_common.o OBJS += i2c_common.o +OBJS += letimer_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 98572eae..07c92dde 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -46,6 +46,7 @@ OBJS += dma_common.o OBJS += emu_common.o OBJS += gpio_common.o OBJS += i2c_common.o +OBJS += letimer_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index 207be1cf..8a0d301e 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -46,6 +46,7 @@ OBJS += dma_common.o OBJS += emu_common.o OBJS += gpio_common.o OBJS += i2c_common.o +OBJS += letimer_common.o OBJS += prs_common.o OBJS += timer_common.o -- cgit v1.2.3 From 75f6cbfd9deff16769491f35aeb062c69feded43 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 11:18:44 +0000 Subject: doc: efm32: msc: tag for doxygen inclusion Includes a stub .c file to trigger common code generation --- lib/efm32/common/msc_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/msc_common.c (limited to 'lib') diff --git a/lib/efm32/common/msc_common.c b/lib/efm32/common/msc_common.c new file mode 100644 index 00000000..a542898d --- /dev/null +++ b/lib/efm32/common/msc_common.c @@ -0,0 +1,15 @@ +/** @addtogroup msc_file MSC peripheral API + * @ingroup peripheral_apis + * @brief Memory Systems Controller helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index fd50eafc..7b21f0ae 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -47,6 +47,7 @@ OBJS += emu_common.o OBJS += gpio_common.o OBJS += i2c_common.o OBJS += letimer_common.o +OBJS += msc_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 07c92dde..344a75ed 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -47,6 +47,7 @@ OBJS += emu_common.o OBJS += gpio_common.o OBJS += i2c_common.o OBJS += letimer_common.o +OBJS += msc_common.o OBJS += prs_common.o OBJS += timer_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index 8a0d301e..38a2163b 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -47,6 +47,7 @@ OBJS += emu_common.o OBJS += gpio_common.o OBJS += i2c_common.o OBJS += letimer_common.o +OBJS += msc_common.o OBJS += prs_common.o OBJS += timer_common.o -- cgit v1.2.3 From 531aa7e6b794c45f11b45b7ba203e25c7dfcc530 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 11:24:44 +0000 Subject: doc: efm32: rmu: include in doxygen generation Include a stub .c file for shared code generation --- lib/efm32/common/rmu_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/rmu_common.c (limited to 'lib') diff --git a/lib/efm32/common/rmu_common.c b/lib/efm32/common/rmu_common.c new file mode 100644 index 00000000..1b0a8cfd --- /dev/null +++ b/lib/efm32/common/rmu_common.c @@ -0,0 +1,15 @@ +/** @addtogroup rmu_file RMU peripheral API + * @ingroup peripheral_apis + * @brief Reset Management Unit helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 7b21f0ae..5c26a76f 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -49,6 +49,7 @@ OBJS += i2c_common.o OBJS += letimer_common.o OBJS += msc_common.o OBJS += prs_common.o +OBJS += rmu_common.o OBJS += timer_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 344a75ed..446c6611 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -49,6 +49,7 @@ OBJS += i2c_common.o OBJS += letimer_common.o OBJS += msc_common.o OBJS += prs_common.o +OBJS += rmu_common.o OBJS += timer_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index 38a2163b..596592b5 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -49,6 +49,7 @@ OBJS += i2c_common.o OBJS += letimer_common.o OBJS += msc_common.o OBJS += prs_common.o +OBJS += rmu_common.o OBJS += timer_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -- cgit v1.2.3 From 9b3ab933acfb067fa5f6d8d2c7b18004b463f737 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 11:35:54 +0000 Subject: doc: efm32: wdog: include stub file Tags were added, but without the stub file, common headers aren't picked up by the auto source list generation --- lib/efm32/common/wdog_common.c | 15 +++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 18 insertions(+) create mode 100644 lib/efm32/common/wdog_common.c (limited to 'lib') diff --git a/lib/efm32/common/wdog_common.c b/lib/efm32/common/wdog_common.c new file mode 100644 index 00000000..a926ab92 --- /dev/null +++ b/lib/efm32/common/wdog_common.c @@ -0,0 +1,15 @@ +/** @addtogroup wdog_file WDOG peripheral API + * @ingroup peripheral_apis + * @brief Watchdog Module helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 5c26a76f..f2c8e962 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -51,6 +51,7 @@ OBJS += msc_common.o OBJS += prs_common.o OBJS += rmu_common.o OBJS += timer_common.o +OBJS += wdog_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o OBJS += usb_efm32.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 446c6611..30c747a9 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -51,6 +51,7 @@ OBJS += msc_common.o OBJS += prs_common.o OBJS += rmu_common.o OBJS += timer_common.o +OBJS += wdog_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o OBJS += usb_efm32.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index 596592b5..d0f45a0b 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -51,6 +51,7 @@ OBJS += msc_common.o OBJS += prs_common.o OBJS += rmu_common.o OBJS += timer_common.o +OBJS += wdog_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o OBJS += usb_efm32.o -- cgit v1.2.3 From 56265ad93fe0474d1a6a2ca3095dded3ef548541 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 11:42:47 +0000 Subject: doc: efm32: rtc: tag and include in generated output Includes the sutb file ncessary to find shared headers without any apis --- lib/efm32/common/rtc_common.c | 16 ++++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 19 insertions(+) create mode 100644 lib/efm32/common/rtc_common.c (limited to 'lib') diff --git a/lib/efm32/common/rtc_common.c b/lib/efm32/common/rtc_common.c new file mode 100644 index 00000000..b7898ae6 --- /dev/null +++ b/lib/efm32/common/rtc_common.c @@ -0,0 +1,16 @@ +/** @addtogroup rtc_file RTC peripheral API + * @ingroup peripheral_apis + * @brief Real Time Clock helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @sa rtc_defines + * @copyright See @ref lgpl_license + */ + +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index f2c8e962..78ee2db1 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -50,6 +50,7 @@ OBJS += letimer_common.o OBJS += msc_common.o OBJS += prs_common.o OBJS += rmu_common.o +OBJS += rtc_common.o OBJS += timer_common.o OBJS += wdog_common.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index 30c747a9..cf1e5bc9 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -50,6 +50,7 @@ OBJS += letimer_common.o OBJS += msc_common.o OBJS += prs_common.o OBJS += rmu_common.o +OBJS += rtc_common.o OBJS += timer_common.o OBJS += wdog_common.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index d0f45a0b..ef4b264f 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -50,6 +50,7 @@ OBJS += letimer_common.o OBJS += msc_common.o OBJS += prs_common.o OBJS += rmu_common.o +OBJS += rtc_common.o OBJS += timer_common.o OBJS += wdog_common.o -- cgit v1.2.3 From 2d1277e1fae9552d11499a1573ecad39d0147d99 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 12:06:47 +0000 Subject: doc: efm32: uart/usart provide common doxygen Fix some direct includes, tag properly, include a stub file to pull in shared header documentation and re-arrange some existing documentation to make it present nicely. --- lib/efm32/common/usart_common.c | 18 ++++++++++++++++++ lib/efm32/ezr32wg/Makefile | 1 + lib/efm32/lg/Makefile | 1 + lib/efm32/wg/Makefile | 1 + 4 files changed, 21 insertions(+) create mode 100644 lib/efm32/common/usart_common.c (limited to 'lib') diff --git a/lib/efm32/common/usart_common.c b/lib/efm32/common/usart_common.c new file mode 100644 index 00000000..ef49f42c --- /dev/null +++ b/lib/efm32/common/usart_common.c @@ -0,0 +1,18 @@ +/** @addtogroup usart_file UART/USART peripheral API + * @ingroup peripheral_apis + * @brief UART/USART helper functions. + * + * NO helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @sa usart_defines + * @sa uart_defines + * @copyright See @ref lgpl_license + */ + +#include +#include + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 78ee2db1..28026b8c 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -52,6 +52,7 @@ OBJS += prs_common.o OBJS += rmu_common.o OBJS += rtc_common.o OBJS += timer_common.o +OBJS += usart_common.o OBJS += wdog_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index cf1e5bc9..da0ef81d 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -52,6 +52,7 @@ OBJS += prs_common.o OBJS += rmu_common.o OBJS += rtc_common.o OBJS += timer_common.o +OBJS += usart_common.o OBJS += wdog_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index ef4b264f..0df4b0b6 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -52,6 +52,7 @@ OBJS += prs_common.o OBJS += rmu_common.o OBJS += rtc_common.o OBJS += timer_common.o +OBJS += usart_common.o OBJS += wdog_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -- cgit v1.2.3 From 1f359e0cb803c7c1cd6591cbe43685ba4ee521c7 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 12:19:03 +0000 Subject: doc: efm32: tag USB files for doxygen generation --- lib/usb/usb_efm32.c | 10 ++++++++++ lib/usb/usb_efm32hg.c | 14 ++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'lib') diff --git a/lib/usb/usb_efm32.c b/lib/usb/usb_efm32.c index 5768947c..4f7fa254 100644 --- a/lib/usb/usb_efm32.c +++ b/lib/usb/usb_efm32.c @@ -1,3 +1,9 @@ +/** @addtogroup usb_file USB peripheral API + * @ingroup peripheral_apis + * + * @sa usb_defines + * @copyright See @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -26,6 +32,8 @@ #include #include "usb_private.h" +/**@{*/ + /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 256 @@ -424,3 +432,5 @@ const struct _usbd_driver efm32lg_usb_driver = { .set_address_before_status = 1, .rx_fifo_size = RX_FIFO_SIZE, }; + +/**@}*/ \ No newline at end of file diff --git a/lib/usb/usb_efm32hg.c b/lib/usb/usb_efm32hg.c index 96f22c1e..5459566e 100644 --- a/lib/usb/usb_efm32hg.c +++ b/lib/usb/usb_efm32hg.c @@ -1,3 +1,13 @@ +/** @addtogroup usb_file USB peripheral API + * @ingroup peripheral_apis + * + * @brief USB Peripheral for Happy Gecko + * + * The Happy Gecko uses the "standard" usb_dwc_otg core. + * + * @sa usb_defines + * @copyright See @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -28,6 +38,8 @@ #include "usb_private.h" #include "usb_dwc_common.h" +/**@{*/ + /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 256 @@ -124,3 +136,5 @@ const struct _usbd_driver efm32hg_usb_driver = { .set_address_before_status = 1, .rx_fifo_size = RX_FIFO_SIZE, }; + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From e5b5ba0f9ce15da40d9de188cd80eeb0a4553dbe Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 13:21:38 +0000 Subject: doc: cm3: dwt: include existing documentation --- lib/cm3/dwt.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'lib') diff --git a/lib/cm3/dwt.c b/lib/cm3/dwt.c index b4408b0c..91a67029 100644 --- a/lib/cm3/dwt.c +++ b/lib/cm3/dwt.c @@ -1,3 +1,29 @@ +/** @defgroup CM3_dwt_file DWT + * + * @ingroup CM3_files + * + * @brief libopencm3 Cortex-M Data Watchpoint and Trace unit + * + * The DWT provides + * * Comparators, that support + * * watch points + * * data tracing + * * signalling to ETM + * * PC value tracing + * * cycle count matching + * * extra PC sampling + * * Sampling as a result of a clock count + * * external access for sampling + * * exception trace + * * performance profiling counters. + * + * Which of these features are available is unfortunately implementation defined. + * + * @see ARMv7m Architecture Reference Manual (Chapter ARMv7-M Debug) + * + * LGPL License Terms @ref lgpl_license + * @{ + */ /* * This file is part of the libopencm3 project. * @@ -75,3 +101,5 @@ uint32_t dwt_read_cycle_counter(void) } #endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ } + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 668cfb2967c5aab4d4a24bfd11306e52e3aec074 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 13:31:50 +0000 Subject: doc: cm3: scb: add basic documentation Adds a summary page, and now we have the existing functions documented. --- lib/cm3/scb.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'lib') diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c index 8c5a2f3a..52f38e81 100644 --- a/lib/cm3/scb.c +++ b/lib/cm3/scb.c @@ -1,3 +1,23 @@ +/** @defgroup CM3_scb_file SCB + * + * @ingroup CM3_files + * + * @brief libopencm3 Cortex-M System Control Block + * + * The System Control Block (SCB) is a section of the System Control Space + * which provides status information and control features for the processor core. + * It allows, amongst other: + * * software reset control + * * exception management and grouping + * * fault information + * * power management + * * debug status information + * + * @see ARMv7m Architecture Reference Manual (Chapter B3.2.1 About the SCB) + * + * LGPL License Terms @ref lgpl_license + * @{ + */ /* * This file is part of the libopencm3 project. * @@ -45,3 +65,5 @@ void scb_set_priority_grouping(uint32_t prigroup) SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; } #endif + +/**@}*/ \ No newline at end of file -- cgit v1.2.3 From 0cd06bcc9794c58a0384097b3fa15f9824ab329c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 25 Jun 2019 14:00:53 +0000 Subject: doc: gd32/f1x0: fix missing tags, drop wrong tags Drop incorrect/redundant type information from doxygen parameters Adds groupings that are referred to. --- lib/gd32/f1x0/rcc.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'lib') diff --git a/lib/gd32/f1x0/rcc.c b/lib/gd32/f1x0/rcc.c index 118b64be..c50e2d65 100644 --- a/lib/gd32/f1x0/rcc.c +++ b/lib/gd32/f1x0/rcc.c @@ -106,7 +106,7 @@ const struct rcc_clock_scale rcc_hse8_configs[] = { Clear the interrupt flag that was set when a clock oscillator became ready to use. -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) @@ -133,7 +133,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) @@ -160,7 +160,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) @@ -187,7 +187,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID @returns int. Boolean value for flag set. */ @@ -238,7 +238,7 @@ int rcc_css_int_flag(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Wait for Oscillator Ready. -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_wait_for_osc_ready(enum rcc_osc osc) @@ -274,7 +274,7 @@ status flag is available to indicate when the oscillator becomes ready (see backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_on(enum rcc_osc osc) @@ -309,7 +309,7 @@ backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect) or the backup domain has been (see reset @ref rcc_backupdomain_reset). -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_off(enum rcc_osc osc) @@ -356,7 +356,7 @@ void rcc_css_disable(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. -@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs +@param[in] clk System Clock Selection @ref rcc_cfgr_scs */ void rcc_set_sysclk_source(uint32_t clk) @@ -370,7 +370,7 @@ void rcc_set_sysclk_source(uint32_t clk) @note This only has effect when the PLL is disabled. -@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf +@param[in] mul PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll_multiplication_factor(uint32_t mul) @@ -385,7 +385,7 @@ void rcc_set_pll_multiplication_factor(uint32_t mul) @note This only has effect when the PLL is disabled. -@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs +@param[in] pllsrc PLL clock source @ref rcc_cfgr_pcs */ void rcc_set_pll_source(uint32_t pllsrc) @@ -399,7 +399,7 @@ void rcc_set_pll_source(uint32_t pllsrc) @note This only has effect when the PLL is disabled. -@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre +@param[in] pllxtpre HSE division factor @ref rcc_cfgr_hsepre */ void rcc_set_pllxtpre(uint32_t pllxtpre) @@ -432,7 +432,7 @@ void rcc_enable_rtc_clock(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the RTC clock -@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI. +@param[in] clock_source RTC clock source. Only HSE/128, LSE and LSI. */ void rcc_set_rtc_clock_source(enum rcc_osc clock_source) @@ -481,7 +481,7 @@ void rcc_set_rtc_clock_source(enum rcc_osc clock_source) The ADC's have a common clock prescale setting. -@param[in] adcpre uint32_t. Prescale divider taken from @ref rcc_cfgr_adcpre +@param[in] adcpre Prescale divider taken from @ref rcc_cfgr_adcpre */ void rcc_set_adcpre(uint32_t adcpre) @@ -493,7 +493,7 @@ void rcc_set_adcpre(uint32_t adcpre) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB2 Prescale Factor. -@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre +@param[in] ppre2 APB2 prescale factor @ref rcc_cfgr_apb2pre */ void rcc_set_ppre2(uint32_t ppre2) @@ -507,7 +507,7 @@ void rcc_set_ppre2(uint32_t ppre2) @note The APB1 clock frequency must not exceed 36MHz. -@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre +@param[in] ppre1 APB1 prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre1(uint32_t ppre1) @@ -520,7 +520,7 @@ void rcc_set_ppre1(uint32_t ppre1) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the AHB Prescale Factor. -@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre +@param[in] hpre AHB prescale factor @ref rcc_cfgr_ahbpre */ void rcc_set_hpre(uint32_t hpre) @@ -538,7 +538,7 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is @note This bit cannot be reset while the USB clock is enabled. -@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre +@param[in] usbpre USB prescale factor @ref rcc_cfgr_usbpre */ void rcc_set_usbpre(uint32_t usbpre) -- cgit v1.2.3 From 06ee2009e812805ac828b7f2cbe31e00cee1cafb Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 26 Jun 2019 12:24:07 +0000 Subject: doc: gd32f1x0: merge flash and rcc into periperhal apis Instead of having some in peripheral_apis and some under the target itself --- lib/gd32/f1x0/flash.c | 4 ++-- lib/gd32/f1x0/rcc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'lib') diff --git a/lib/gd32/f1x0/flash.c b/lib/gd32/f1x0/flash.c index ad7cb054..4f222082 100644 --- a/lib/gd32/f1x0/flash.c +++ b/lib/gd32/f1x0/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup GD32F1x0 + * @ingroup peripheral_apis * * @brief libopencm3 GD32F1x0 FLASH * diff --git a/lib/gd32/f1x0/rcc.c b/lib/gd32/f1x0/rcc.c index c50e2d65..729a71eb 100644 --- a/lib/gd32/f1x0/rcc.c +++ b/lib/gd32/f1x0/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup GD32F1x0-rcc-file RCC +/** @defgroup rcc_file RCC peripheral API -@ingroup GD32F1x0 +@ingroup peripheral_apis @brief libopencm3 GD32F1x0 Reset and Clock Control -- cgit v1.2.3 From 9b3c813399aa85409a6fa9b2b86a3b49eef372a8 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 26 Jun 2019 12:33:57 +0000 Subject: doc: lm3s: escape email address to avoid xml interp --- lib/lm3s/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/lm3s/rcc.c b/lib/lm3s/rcc.c index 96c09504..248ff815 100644 --- a/lib/lm3s/rcc.c +++ b/lib/lm3s/rcc.c @@ -7,7 +7,7 @@ @version 1.0.0 @author @htmlonly © @endhtmlonly 2015 -Daniele Lacamera +Daniele Lacamera \ @date 21 November 2015 -- cgit v1.2.3 From 8b4d952629f9c43a89939b83290bc2fe3fd46f0f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 26 Jun 2019 12:42:34 +0000 Subject: doc: stm32f3: adc: add missing parameters Minor, link the adc peripheral parameter in a couple of places --- lib/stm32/f3/adc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'lib') diff --git a/lib/stm32/f3/adc.c b/lib/stm32/f3/adc.c index 9eb73dc2..e9a36846 100644 --- a/lib/stm32/f3/adc.c +++ b/lib/stm32/f3/adc.c @@ -587,10 +587,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) * * The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. * + * @param adc peripheral of choice @ref adc_reg_base * @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref * adc_ccr_adcpre -*/ - + */ void adc_set_clk_prescale(uint32_t adc, uint32_t prescale) { uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | prescale); @@ -605,10 +605,10 @@ void adc_set_clk_prescale(uint32_t adc, uint32_t prescale) * * The various modes possible are described in the reference manual. * + * @param adc peripheral of choice @ref adc_reg_base * @param[in] mode Unsigned int32. Multiple mode selection from @ref * adc_multi_mode -*/ - + */ void adc_set_multi_mode(uint32_t adc, uint32_t mode) { ADC_CCR(adc) |= mode; -- cgit v1.2.3 From 2035d84e550f64b9423b37bdef578be2708530c9 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 18 Jun 2019 13:33:11 +0200 Subject: stm32: lptim: add base support Add basically what's needed to have some minimal but usefull subset of function for a timer: irqs, compare, period, out polarity, enable/disable and start. --- lib/stm32/common/lptimer_common_all.c | 294 ++++++++++++++++++++++++++++++++++ lib/stm32/f4/Makefile | 1 + lib/stm32/f7/Makefile | 1 + lib/stm32/g0/Makefile | 1 + lib/stm32/l0/Makefile | 1 + lib/stm32/l4/Makefile | 1 + 6 files changed, 299 insertions(+) create mode 100644 lib/stm32/common/lptimer_common_all.c (limited to 'lib') diff --git a/lib/stm32/common/lptimer_common_all.c b/lib/stm32/common/lptimer_common_all.c new file mode 100644 index 00000000..1dc4e0ab --- /dev/null +++ b/lib/stm32/common/lptimer_common_all.c @@ -0,0 +1,294 @@ +/** @addtogroup lptimer_file LPTIM peripheral API + * @ingroup peripheral_apis + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot + * + * @date 2 July 2019 + * + * LGPL License Terms @ref lgpl_license + * + * @section lptim_api_ex Basic LPTIMER handling API. + * + * Example: LPTIM1 with 2x clock prescaler, from internal clock (LSE), irq on match and reload. + * + * @code + * + * rcc_set_peripheral_clk_sel(LPTIM1, RCC_CCIPR_LPTIM1SEL_LSE); + * + * rcc_periph_clock_enable(RCC_LPTIM1); + * + * lptimer_set_internal_clock_source(LPTIM1); + * lptimer_enable_trigger(LPTIM1, LPTIM_CFGR_TRIGEN_SW); + * lptimer_set_prescaler(LPTIM1, LPTIM_CFGR_PRESC_2); + * + * lptimer_enable(LPTIM1); + * + * lptimer_set_period(LPTIM1, 0xffff); + * lptimer_set_compare(LPTIM1, 1234); + * + * lptimer_enable_irq(LPTIM1, LPTIM_IER_ARRMIE | LPTIM_IER_CMPMIE); + * nvic_enable_irq(NVIC_LPTIM1_IRQ); + * + * lptimer_start_counter(LPTIM1, LPTIM_CR_CNTSTRT); + * + * @endcode + * + * Note: LPTIM internal clock source selection is device specific, see clock tree + * and rcc section of reference manual. + * + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/** @brief Set lptimer Counter + * + * Set the value of a lptimer counter. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] count Counter value. +*/ +void lptimer_set_counter(uint32_t lptimer_peripheral, uint16_t count) +{ + LPTIM_CNT(lptimer_peripheral) = count; +} + +/** @brief Read lptimer Counter + * + * Read back the value of lptimer counter. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @returns Counter value. + */ +uint16_t lptimer_get_counter(uint32_t lptimer_peripheral) +{ + return LPTIM_CNT(lptimer_peripheral); +} + +/** @brief Clear lptimer Status Flag. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] flag Status Register clear flag (@ref lptim_icr) + */ +void lptimer_clear_flag(uint32_t lptimer_peripheral, uint32_t flag) +{ + LPTIM_ICR(lptimer_peripheral) = flag; +} + +/** @brief Read lptimer Status Flag. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] flag Status Register flag (@ref lptim_isr) + * @returns flag set. + */ +bool lptimer_get_flag(uint32_t lptimer_peripheral, uint32_t flag) +{ + return (LPTIM_ISR(lptimer_peripheral) & flag); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable lptimer interrupts. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] irq Logical or of all interrupt enable bits to be set (@ref lptim_ier) + */ +void lptimer_enable_irq(uint32_t lptimer_peripheral, uint32_t irq) +{ + LPTIM_IER(lptimer_peripheral) |= irq; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable lptimer Interrupts. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] irq Logical or of all interrupt enable bits to be cleared (@ref lptim_ier) + */ +void lptimer_disable_irq(uint32_t lptimer_peripheral, uint32_t irq) +{ + LPTIM_IER(lptimer_peripheral) &= ~irq; +} + +/** @brief Enable lptimer. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_enable(uint32_t lptimer_peripheral) +{ + LPTIM_CR(lptimer_peripheral) |= LPTIM_CR_ENABLE; +} + +/** @brief Disable lptimer. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_disable(uint32_t lptimer_peripheral) +{ + LPTIM_CR(lptimer_peripheral) &= ~LPTIM_CR_ENABLE; +} + +/** @brief Start lptimer in a given mode. + * + * Starts the timer in specified mode - Either Single (@ref LPTIM_CR_SNGSTRT) or + * Continuous mode (@ref LPTIM_CR_CNTSTRT). In Single mode, the timer will stop at + * next match on compare or period value. + * If LPTIM_CR_SNGSTRT is set while timer is started in countious mode, it + * will stop at next match on compare or period value. + * If Software trigger is disabled, start will be delayed until programmed + * triggers is detected. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] mode lptimer start mode (@ref LPTIM_CR_SNGSTRT or @ref LPTIM_CR_CNTSTRT) + */ +void lptimer_start_counter(uint32_t lptimer_peripheral, uint32_t mode) +{ + LPTIM_CR(lptimer_peripheral) |= mode; +} + +/** @brief Set lptimer clock prescaler. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] prescaler Clock prescaler (@ref lptim_cfgr_presc) + */ +void lptimer_set_prescaler(uint32_t lptimer_peripheral, uint32_t prescaler) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_PRESC_MASK << LPTIM_CFGR_PRESC_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | prescaler; +} + +/** @brief Enable lptimer External Trigger + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel) + */ +void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_TRIGEN_MASK << LPTIM_CFGR_TRIGEN_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | trigen; +} + +/** @brief Select lptimer Trigger Source + * + * Select timer external trigger source. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel) + */ +void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_TRIGSEL_MASK << LPTIM_CFGR_TRIGSEL_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | trigger_source; +} + +/** @brief Set lptimer counter Compare Value + * + * Set the timer compare value. Must only be set with timer enabled. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] compare_value Compare value. + */ +void lptimer_set_compare(uint32_t lptimer_peripheral, uint16_t compare_value) +{ + LPTIM_CMP(lptimer_peripheral) = compare_value; +} + +/** @brief Set lptimer period + * + * Set the timer period in the auto-reload register. Must only be set with timer + * enabled. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] period_value Autoreload value. Must be greater that CMP value. + */ +void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value) +{ + LPTIM_ARR(lptimer_peripheral) = period_value; +} + +/** @brief Enable lptimer Preload mode. + * + * Enable lptimer preload mode, delaying update of period and compare registers + * to the end of current period. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_enable_preload(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_PRELOAD; +} + +/** @brief Disable lptimer Preload mode. + * + * Disable lptimer preload mode, ensureing updated period and compare registers + * values are taken in account immediatly. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_disable_preload(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_PRELOAD; +} + + +/** @brief Set lptimer Internal Clock source + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_internal_clock_source(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_CKSEL; +} + +/** @brief Set lptimer External Clock source + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_external_clock_source(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_CKSEL; +} + +/** @brief Set lptimer Waveform Output Polarity High + * + * Set lptimer waveform output to reflect compare result between LPTIN_CNT + * and LPTIM_CMP. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_WAVPOL; +} + +/** @brief Set lptimer Waveform Output Polarity Low + * + * Set lptimer waveform output to reflect the inverse of the compare result + * between LPTIN_CNT and LPTIM_CMP. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_WAVPOL; +} + +/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 747ee549..ebcf5f78 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -54,6 +54,7 @@ OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += hash_common_f24.o OBJS += i2c_common_v1.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += ltdc_common_f47.o OBJS += pwr_common_v1.o pwr.o OBJS += rcc_common_all.o rcc.o diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 693bb58d..ff078655 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -54,6 +54,7 @@ OBJS += fmc_common_f47.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += ltdc_common_f47.o OBJS += pwr.o rcc.o OBJS += rcc_common_all.o diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 376ee203..cb75e4fe 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -40,6 +40,7 @@ OBJS += flash.o flash_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index a9743caf..857d3d5c 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -43,6 +43,7 @@ OBJS += flash_common_all.o flash_common_l01.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += pwr_common_v1.o pwr_common_v2.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index 514128f6..6a1594ff 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -46,6 +46,7 @@ OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o -- cgit v1.2.3