FEAT: [irq] Added the IInterruptable class for an IRQ managing

FEAT: [irq] Added a script for a gen an iqr enum and defines from openocd defines

3 files changed, 544 insertions, 0 deletions

diff --git a/irq/cm3cpp_irq.cpp b/irq/cm3cpp_irq.cpp
new file mode 100644
index 0000000..c7f0c84
--- /dev/null
+++ b/irq/cm3cpp_irq.cpp
@@ -0,0 +1,216 @@
+#include "cm3cpp_irq.h"
+
+#define DEFINE_CALLBACK(cfunc, int_enum)                                            \
+    void cfunc(void) {                                                              \
+        const uint32_t indx = static_cast<uint32_t>(Interrupt::int_enum);           \
+        isr_vector_table[indx]->call();                                             \
+    }
+
+namespace cm3cpp {
+
+struct EmptyInterrupt : public IInterruptable {
+    void call() {}
+    EmptyInterrupt() = default;
+    ~EmptyInterrupt() = default;
+} _empty_interrupt;
+
+constexpr uint32_t INTERRUPTS_COUNT = NVIC_IRQ_COUNT;
+static IInterruptable* isr_vector_table[INTERRUPTS_COUNT];
+
+struct InterruptInitializer {
+    InterruptInitializer() {
+        for (uint32_t i = 0; i < INTERRUPTS_COUNT; ++i) {
+            isr_vector_table[i] = &_empty_interrupt;  // init an irq table with
+        }                                             // empty functions for safe
+    }
+} _init;
+
+void IInterruptable::register_isr(Interrupt interrupt, IInterruptable* interrupt_owner)
+{
+    const uint32_t indx = static_cast<uint32_t>(interrupt);
+    isr_vector_table[indx] = interrupt_owner;
+}
+
+BEGIN_DECLS
+
+#ifdef STM32F2
+DEFINE_CALLBACK(nvic_wwdg_isr,             ISR_NVIC_WWDG)
+DEFINE_CALLBACK(pvd_isr,                   ISR_PVD)
+DEFINE_CALLBACK(tamp_stamp_isr,            ISR_TAMP_STAMP)
+DEFINE_CALLBACK(rtc_wkup_isr,              ISR_RTC_WKUP)
+DEFINE_CALLBACK(flash_isr,                 ISR_FLASH)
+DEFINE_CALLBACK(rcc_isr,                   ISR_RCC)
+DEFINE_CALLBACK(exti0_isr,                 ISR_EXTI0)
+DEFINE_CALLBACK(exti1_isr,                 ISR_EXTI1)
+DEFINE_CALLBACK(exti2_isr,                 ISR_EXTI2)
+DEFINE_CALLBACK(exti3_isr,                 ISR_EXTI3)
+DEFINE_CALLBACK(exti4_isr,                 ISR_EXTI4)
+DEFINE_CALLBACK(dma1_stream0_isr,          ISR_DMA1_STREAM0)
+DEFINE_CALLBACK(dma1_stream1_isr,          ISR_DMA1_STREAM1)
+DEFINE_CALLBACK(dma1_stream2_isr,          ISR_DMA1_STREAM2)
+DEFINE_CALLBACK(dma1_stream3_isr,          ISR_DMA1_STREAM3)
+DEFINE_CALLBACK(dma1_stream4_isr,          ISR_DMA1_STREAM4)
+DEFINE_CALLBACK(dma1_stream5_isr,          ISR_DMA1_STREAM5)
+DEFINE_CALLBACK(dma1_stream6_isr,          ISR_DMA1_STREAM6)
+DEFINE_CALLBACK(adc_isr,                   ISR_ADC)
+DEFINE_CALLBACK(can1_tx_isr,               ISR_CAN1_TX)
+DEFINE_CALLBACK(can1_rx0_isr,              ISR_CAN1_RX0)
+DEFINE_CALLBACK(can1_rx1_isr,              ISR_CAN1_RX1)
+DEFINE_CALLBACK(can1_sce_isr,              ISR_CAN1_SCE)
+DEFINE_CALLBACK(exti9_5_isr,               ISR_EXTI9_5)
+DEFINE_CALLBACK(tim1_brk_tim9_isr,         ISR_TIM1_BRK_TIM9)
+DEFINE_CALLBACK(tim1_up_tim10_isr,         ISR_TIM1_UP_TIM10)
+DEFINE_CALLBACK(tim1_trg_com_tim11_isr,    ISR_TIM1_TRG_COM_TIM11)
+DEFINE_CALLBACK(tim1_cc_isr,               ISR_TIM1_CC)
+DEFINE_CALLBACK(tim2_isr,                  ISR_TIM2)
+DEFINE_CALLBACK(tim3_isr,                  ISR_TIM3)
+DEFINE_CALLBACK(tim4_isr,                  ISR_TIM4)
+DEFINE_CALLBACK(i2c1_ev_isr,               ISR_I2C1_EV)
+DEFINE_CALLBACK(i2c1_er_isr,               ISR_I2C1_ER)
+DEFINE_CALLBACK(i2c2_ev_isr,               ISR_I2C2_EV)
+DEFINE_CALLBACK(i2c2_er_isr,               ISR_I2C2_ER)
+DEFINE_CALLBACK(spi1_isr,                  ISR_SPI1)
+DEFINE_CALLBACK(spi2_isr,                  ISR_SPI2)
+DEFINE_CALLBACK(usart1_isr,                ISR_USART1)
+DEFINE_CALLBACK(usart2_isr,                ISR_USART2)
+DEFINE_CALLBACK(usart3_isr,                ISR_USART3)
+DEFINE_CALLBACK(exti15_10_isr,             ISR_EXTI15_10)
+DEFINE_CALLBACK(rtc_alarm_isr,             ISR_RTC_ALARM)
+DEFINE_CALLBACK(usb_fs_wkup_isr,           ISR_USB_FS_WKUP)
+DEFINE_CALLBACK(tim8_brk_tim12_isr,        ISR_TIM8_BRK_TIM12)
+DEFINE_CALLBACK(tim8_up_tim13_isr,         ISR_TIM8_UP_TIM13)
+DEFINE_CALLBACK(tim8_trg_com_tim14_isr,    ISR_TIM8_TRG_COM_TIM14)
+DEFINE_CALLBACK(tim8_cc_isr,               ISR_TIM8_CC)
+DEFINE_CALLBACK(dma1_stream7_isr,          ISR_DMA1_STREAM7)
+DEFINE_CALLBACK(fsmc_isr,                  ISR_FSMC)
+DEFINE_CALLBACK(sdio_isr,                  ISR_SDIO)
+DEFINE_CALLBACK(tim5_isr,                  ISR_TIM5)
+DEFINE_CALLBACK(spi3_isr,                  ISR_SPI3)
+DEFINE_CALLBACK(uart4_isr,                 ISR_UART4)
+DEFINE_CALLBACK(uart5_isr,                 ISR_UART5)
+DEFINE_CALLBACK(tim6_dac_isr,              ISR_TIM6_DAC)
+DEFINE_CALLBACK(tim7_isr,                  ISR_TIM7)
+DEFINE_CALLBACK(dma2_stream0_isr,          ISR_DMA2_STREAM0)
+DEFINE_CALLBACK(dma2_stream1_isr,          ISR_DMA2_STREAM1)
+DEFINE_CALLBACK(dma2_stream2_isr,          ISR_DMA2_STREAM2)
+DEFINE_CALLBACK(dma2_stream3_isr,          ISR_DMA2_STREAM3)
+DEFINE_CALLBACK(dma2_stream4_isr,          ISR_DMA2_STREAM4)
+DEFINE_CALLBACK(eth_isr,                   ISR_ETH)
+DEFINE_CALLBACK(eth_wkup_isr,              ISR_ETH_WKUP)
+DEFINE_CALLBACK(can2_tx_isr,               ISR_CAN2_TX)
+DEFINE_CALLBACK(can2_rx0_isr,              ISR_CAN2_RX0)
+DEFINE_CALLBACK(can2_rx1_isr,              ISR_CAN2_RX1)
+DEFINE_CALLBACK(can2_sce_isr,              ISR_CAN2_SCE)
+DEFINE_CALLBACK(otg_fs_isr,                ISR_OTG_FS)
+DEFINE_CALLBACK(dma2_stream5_isr,          ISR_DMA2_STREAM5)
+DEFINE_CALLBACK(dma2_stream6_isr,          ISR_DMA2_STREAM6)
+DEFINE_CALLBACK(dma2_stream7_isr,          ISR_DMA2_STREAM7)
+DEFINE_CALLBACK(usart6_isr,                ISR_USART6)
+DEFINE_CALLBACK(i2c3_ev_isr,               ISR_I2C3_EV)
+DEFINE_CALLBACK(i2c3_er_isr,               ISR_I2C3_ER)
+DEFINE_CALLBACK(otg_hs_ep1_out_isr,        ISR_OTG_HS_EP1_OUT)
+DEFINE_CALLBACK(otg_hs_ep1_in_isr,         ISR_OTG_HS_EP1_IN)
+DEFINE_CALLBACK(otg_hs_wkup_isr,           ISR_OTG_HS_WKUP)
+DEFINE_CALLBACK(otg_hs_isr,                ISR_OTG_HS)
+DEFINE_CALLBACK(dcmi_isr,                  ISR_DCMI)
+DEFINE_CALLBACK(cryp_isr,                  ISR_CRYP)
+DEFINE_CALLBACK(hash_rng_isr,              ISR_HASH_RNG)
+#endif
+
+#ifdef STM32F4
+DEFINE_CALLBACK(nvic_wwdg_isr,             ISR_NVIC_WWDG)
+DEFINE_CALLBACK(pvd_isr,                   ISR_PVD)
+DEFINE_CALLBACK(tamp_stamp_isr,            ISR_TAMP_STAMP)
+DEFINE_CALLBACK(rtc_wkup_isr,              ISR_RTC_WKUP)
+DEFINE_CALLBACK(flash_isr,                 ISR_FLASH)
+DEFINE_CALLBACK(rcc_isr,                   ISR_RCC)
+DEFINE_CALLBACK(exti0_isr,                 ISR_EXTI0)
+DEFINE_CALLBACK(exti1_isr,                 ISR_EXTI1)
+DEFINE_CALLBACK(exti2_isr,                 ISR_EXTI2)
+DEFINE_CALLBACK(exti3_isr,                 ISR_EXTI3)
+DEFINE_CALLBACK(exti4_isr,                 ISR_EXTI4)
+DEFINE_CALLBACK(dma1_stream0_isr,          ISR_DMA1_STREAM0)
+DEFINE_CALLBACK(dma1_stream1_isr,          ISR_DMA1_STREAM1)
+DEFINE_CALLBACK(dma1_stream2_isr,          ISR_DMA1_STREAM2)
+DEFINE_CALLBACK(dma1_stream3_isr,          ISR_DMA1_STREAM3)
+DEFINE_CALLBACK(dma1_stream4_isr,          ISR_DMA1_STREAM4)
+DEFINE_CALLBACK(dma1_stream5_isr,          ISR_DMA1_STREAM5)
+DEFINE_CALLBACK(dma1_stream6_isr,          ISR_DMA1_STREAM6)
+DEFINE_CALLBACK(adc_isr,                   ISR_ADC)
+DEFINE_CALLBACK(can1_tx_isr,               ISR_CAN1_TX)
+DEFINE_CALLBACK(can1_rx0_isr,              ISR_CAN1_RX0)
+DEFINE_CALLBACK(can1_rx1_isr,              ISR_CAN1_RX1)
+DEFINE_CALLBACK(can1_sce_isr,              ISR_CAN1_SCE)
+DEFINE_CALLBACK(exti9_5_isr,               ISR_EXTI9_5)
+DEFINE_CALLBACK(tim1_brk_tim9_isr,         ISR_TIM1_BRK_TIM9)
+DEFINE_CALLBACK(tim1_up_tim10_isr,         ISR_TIM1_UP_TIM10)
+DEFINE_CALLBACK(tim1_trg_com_tim11_isr,    ISR_TIM1_TRG_COM_TIM11)
+DEFINE_CALLBACK(tim1_cc_isr,               ISR_TIM1_CC)
+DEFINE_CALLBACK(tim2_isr,                  ISR_TIM2)
+DEFINE_CALLBACK(tim3_isr,                  ISR_TIM3)
+DEFINE_CALLBACK(tim4_isr,                  ISR_TIM4)
+DEFINE_CALLBACK(i2c1_ev_isr,               ISR_I2C1_EV)
+DEFINE_CALLBACK(i2c1_er_isr,               ISR_I2C1_ER)
+DEFINE_CALLBACK(i2c2_ev_isr,               ISR_I2C2_EV)
+DEFINE_CALLBACK(i2c2_er_isr,               ISR_I2C2_ER)
+DEFINE_CALLBACK(spi1_isr,                  ISR_SPI1)
+DEFINE_CALLBACK(spi2_isr,                  ISR_SPI2)
+DEFINE_CALLBACK(usart1_isr,                ISR_USART1)
+DEFINE_CALLBACK(usart2_isr,                ISR_USART2)
+DEFINE_CALLBACK(usart3_isr,                ISR_USART3)
+DEFINE_CALLBACK(exti15_10_isr,             ISR_EXTI15_10)
+DEFINE_CALLBACK(rtc_alarm_isr,             ISR_RTC_ALARM)
+DEFINE_CALLBACK(usb_fs_wkup_isr,           ISR_USB_FS_WKUP)
+DEFINE_CALLBACK(tim8_brk_tim12_isr,        ISR_TIM8_BRK_TIM12)
+DEFINE_CALLBACK(tim8_up_tim13_isr,         ISR_TIM8_UP_TIM13)
+DEFINE_CALLBACK(tim8_trg_com_tim14_isr,    ISR_TIM8_TRG_COM_TIM14)
+DEFINE_CALLBACK(tim8_cc_isr,               ISR_TIM8_CC)
+DEFINE_CALLBACK(dma1_stream7_isr,          ISR_DMA1_STREAM7)
+DEFINE_CALLBACK(fsmc_isr,                  ISR_FSMC)
+DEFINE_CALLBACK(sdio_isr,                  ISR_SDIO)
+DEFINE_CALLBACK(tim5_isr,                  ISR_TIM5)
+DEFINE_CALLBACK(spi3_isr,                  ISR_SPI3)
+DEFINE_CALLBACK(uart4_isr,                 ISR_UART4)
+DEFINE_CALLBACK(uart5_isr,                 ISR_UART5)
+DEFINE_CALLBACK(tim6_dac_isr,              ISR_TIM6_DAC)
+DEFINE_CALLBACK(tim7_isr,                  ISR_TIM7)
+DEFINE_CALLBACK(dma2_stream0_isr,          ISR_DMA2_STREAM0)
+DEFINE_CALLBACK(dma2_stream1_isr,          ISR_DMA2_STREAM1)
+DEFINE_CALLBACK(dma2_stream2_isr,          ISR_DMA2_STREAM2)
+DEFINE_CALLBACK(dma2_stream3_isr,          ISR_DMA2_STREAM3)
+DEFINE_CALLBACK(dma2_stream4_isr,          ISR_DMA2_STREAM4)
+DEFINE_CALLBACK(eth_isr,                   ISR_ETH)
+DEFINE_CALLBACK(eth_wkup_isr,              ISR_ETH_WKUP)
+DEFINE_CALLBACK(can2_tx_isr,               ISR_CAN2_TX)
+DEFINE_CALLBACK(can2_rx0_isr,              ISR_CAN2_RX0)
+DEFINE_CALLBACK(can2_rx1_isr,              ISR_CAN2_RX1)
+DEFINE_CALLBACK(can2_sce_isr,              ISR_CAN2_SCE)
+DEFINE_CALLBACK(otg_fs_isr,                ISR_OTG_FS)
+DEFINE_CALLBACK(dma2_stream5_isr,          ISR_DMA2_STREAM5)
+DEFINE_CALLBACK(dma2_stream6_isr,          ISR_DMA2_STREAM6)
+DEFINE_CALLBACK(dma2_stream7_isr,          ISR_DMA2_STREAM7)
+DEFINE_CALLBACK(usart6_isr,                ISR_USART6)
+DEFINE_CALLBACK(i2c3_ev_isr,               ISR_I2C3_EV)
+DEFINE_CALLBACK(i2c3_er_isr,               ISR_I2C3_ER)
+DEFINE_CALLBACK(otg_hs_ep1_out_isr,        ISR_OTG_HS_EP1_OUT)
+DEFINE_CALLBACK(otg_hs_ep1_in_isr,         ISR_OTG_HS_EP1_IN)
+DEFINE_CALLBACK(otg_hs_wkup_isr,           ISR_OTG_HS_WKUP)
+DEFINE_CALLBACK(otg_hs_isr,                ISR_OTG_HS)
+DEFINE_CALLBACK(dcmi_isr,                  ISR_DCMI)
+DEFINE_CALLBACK(cryp_isr,                  ISR_CRYP)
+DEFINE_CALLBACK(hash_rng_isr,              ISR_HASH_RNG)
+DEFINE_CALLBACK(fpu_isr,                   ISR_FPU)
+DEFINE_CALLBACK(uart7_isr,                 ISR_UART7)
+DEFINE_CALLBACK(uart8_isr,                 ISR_UART8)
+DEFINE_CALLBACK(spi4_isr,                  ISR_SPI4)
+DEFINE_CALLBACK(spi5_isr,                  ISR_SPI5)
+DEFINE_CALLBACK(spi6_isr,                  ISR_SPI6)
+DEFINE_CALLBACK(sai1_isr,                  ISR_SAI1)
+DEFINE_CALLBACK(lcd_tft_isr,               ISR_LCD_TFT)
+DEFINE_CALLBACK(lcd_tft_err_isr,           ISR_LCD_TFT_ERR)
+DEFINE_CALLBACK(dma2d_isr,                 ISR_DMA2D)
+#endif
+
+END_DECLS
+
+} /* namespace hw */
diff --git a/irq/cm3cpp_irq.h b/irq/cm3cpp_irq.h
new file mode 100644
index 0000000..fdc00a2
--- /dev/null
+++ b/irq/cm3cpp_irq.h
@@ -0,0 +1,204 @@
+#pragma once
+
+#ifdef STM32F2
+#include <libopencm3/stm32/f2/nvic.h>
+#endif
+#ifdef STM32F4
+#include <libopencm3/stm32/f4/nvic.h>
+#endif
+
+namespace cm3cpp {
+
+#ifdef STM32F2
+enum class Interrupt : uint32_t {
+    ISR_NVIC_WWDG = 0,
+    ISR_PVD,
+    ISR_TAMP_STAMP,
+    ISR_RTC_WKUP,
+    ISR_FLASH,
+    ISR_RCC,
+    ISR_EXTI0,
+    ISR_EXTI1,
+    ISR_EXTI2,
+    ISR_EXTI3,
+    ISR_EXTI4,
+    ISR_DMA1_STREAM0,
+    ISR_DMA1_STREAM1,
+    ISR_DMA1_STREAM2,
+    ISR_DMA1_STREAM3,
+    ISR_DMA1_STREAM4,
+    ISR_DMA1_STREAM5,
+    ISR_DMA1_STREAM6,
+    ISR_ADC,
+    ISR_CAN1_TX,
+    ISR_CAN1_RX0,
+    ISR_CAN1_RX1,
+    ISR_CAN1_SCE,
+    ISR_EXTI9_5,
+    ISR_TIM1_BRK_TIM9,
+    ISR_TIM1_UP_TIM10,
+    ISR_TIM1_TRG_COM_TIM11,
+    ISR_TIM1_CC,
+    ISR_TIM2,
+    ISR_TIM3,
+    ISR_TIM4,
+    ISR_I2C1_EV,
+    ISR_I2C1_ER,
+    ISR_I2C2_EV,
+    ISR_I2C2_ER,
+    ISR_SPI1,
+    ISR_SPI2,
+    ISR_USART1,
+    ISR_USART2,
+    ISR_USART3,
+    ISR_EXTI15_10,
+    ISR_RTC_ALARM,
+    ISR_USB_FS_WKUP,
+    ISR_TIM8_BRK_TIM12,
+    ISR_TIM8_UP_TIM13,
+    ISR_TIM8_TRG_COM_TIM14,
+    ISR_TIM8_CC,
+    ISR_DMA1_STREAM7,
+    ISR_FSMC,
+    ISR_SDIO,
+    ISR_TIM5,
+    ISR_SPI3,
+    ISR_UART4,
+    ISR_UART5,
+    ISR_TIM6_DAC,
+    ISR_TIM7,
+    ISR_DMA2_STREAM0,
+    ISR_DMA2_STREAM1,
+    ISR_DMA2_STREAM2,
+    ISR_DMA2_STREAM3,
+    ISR_DMA2_STREAM4,
+    ISR_ETH,
+    ISR_ETH_WKUP,
+    ISR_CAN2_TX,
+    ISR_CAN2_RX0,
+    ISR_CAN2_RX1,
+    ISR_CAN2_SCE,
+    ISR_OTG_FS,
+    ISR_DMA2_STREAM5,
+    ISR_DMA2_STREAM6,
+    ISR_DMA2_STREAM7,
+    ISR_USART6,
+    ISR_I2C3_EV,
+    ISR_I2C3_ER,
+    ISR_OTG_HS_EP1_OUT,
+    ISR_OTG_HS_EP1_IN,
+    ISR_OTG_HS_WKUP,
+    ISR_OTG_HS,
+    ISR_DCMI,
+    ISR_CRYP,
+    ISR_HASH_RNG,
+};
+#endif
+
+#ifdef STM32F4
+enum Interrupt : uint32_t {
+    ISR_NVIC_WWDG = 0,
+    ISR_PVD,
+    ISR_TAMP_STAMP,
+    ISR_RTC_WKUP,
+    ISR_FLASH,
+    ISR_RCC,
+    ISR_EXTI0,
+    ISR_EXTI1,
+    ISR_EXTI2,
+    ISR_EXTI3,
+    ISR_EXTI4,
+    ISR_DMA1_STREAM0,
+    ISR_DMA1_STREAM1,
+    ISR_DMA1_STREAM2,
+    ISR_DMA1_STREAM3,
+    ISR_DMA1_STREAM4,
+    ISR_DMA1_STREAM5,
+    ISR_DMA1_STREAM6,
+    ISR_ADC,
+    ISR_CAN1_TX,
+    ISR_CAN1_RX0,
+    ISR_CAN1_RX1,
+    ISR_CAN1_SCE,
+    ISR_EXTI9_5,
+    ISR_TIM1_BRK_TIM9,
+    ISR_TIM1_UP_TIM10,
+    ISR_TIM1_TRG_COM_TIM11,
+    ISR_TIM1_CC,
+    ISR_TIM2,
+    ISR_TIM3,
+    ISR_TIM4,
+    ISR_I2C1_EV,
+    ISR_I2C1_ER,
+    ISR_I2C2_EV,
+    ISR_I2C2_ER,
+    ISR_SPI1,
+    ISR_SPI2,
+    ISR_USART1,
+    ISR_USART2,
+    ISR_USART3,
+    ISR_EXTI15_10,
+    ISR_RTC_ALARM,
+    ISR_USB_FS_WKUP,
+    ISR_TIM8_BRK_TIM12,
+    ISR_TIM8_UP_TIM13,
+    ISR_TIM8_TRG_COM_TIM14,
+    ISR_TIM8_CC,
+    ISR_DMA1_STREAM7,
+    ISR_FSMC,
+    ISR_SDIO,
+    ISR_TIM5,
+    ISR_SPI3,
+    ISR_UART4,
+    ISR_UART5,
+    ISR_TIM6_DAC,
+    ISR_TIM7,
+    ISR_DMA2_STREAM0,
+    ISR_DMA2_STREAM1,
+    ISR_DMA2_STREAM2,
+    ISR_DMA2_STREAM3,
+    ISR_DMA2_STREAM4,
+    ISR_ETH,
+    ISR_ETH_WKUP,
+    ISR_CAN2_TX,
+    ISR_CAN2_RX0,
+    ISR_CAN2_RX1,
+    ISR_CAN2_SCE,
+    ISR_OTG_FS,
+    ISR_DMA2_STREAM5,
+    ISR_DMA2_STREAM6,
+    ISR_DMA2_STREAM7,
+    ISR_USART6,
+    ISR_I2C3_EV,
+    ISR_I2C3_ER,
+    ISR_OTG_HS_EP1_OUT,
+    ISR_OTG_HS_EP1_IN,
+    ISR_OTG_HS_WKUP,
+    ISR_OTG_HS,
+    ISR_DCMI,
+    ISR_CRYP,
+    ISR_HASH_RNG,
+    ISR_FPU,
+    ISR_UART7,
+    ISR_UART8,
+    ISR_SPI4,
+    ISR_SPI5,
+    ISR_SPI6,
+    ISR_SAI1,
+    ISR_LCD_TFT,
+    ISR_LCD_TFT_ERR,
+    ISR_DMA2D,
+};
+#endif
+
+class IInterruptable
+{
+public:
+    IInterruptable() = default;
+    virtual ~IInterruptable() = default;
+
+    static void register_isr(Interrupt interrupt, IInterruptable* interrupt_owner);
+    virtual void call() = 0;
+};
+
+} /* namespace cm3cpp */
diff --git a/irq/gen_irq.py b/irq/gen_irq.py
new file mode 100644
index 0000000..50fdad5
--- /dev/null
+++ b/irq/gen_irq.py
@@ -0,0 +1,124 @@
+irq_defines = """
+#define NVIC_NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMP_STAMP_IRQ 2
+#define NVIC_RTC_WKUP_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_STREAM0_IRQ 11
+#define NVIC_DMA1_STREAM1_IRQ 12
+#define NVIC_DMA1_STREAM2_IRQ 13
+#define NVIC_DMA1_STREAM3_IRQ 14
+#define NVIC_DMA1_STREAM4_IRQ 15
+#define NVIC_DMA1_STREAM5_IRQ 16
+#define NVIC_DMA1_STREAM6_IRQ 17
+#define NVIC_ADC_IRQ 18
+#define NVIC_CAN1_TX_IRQ 19
+#define NVIC_CAN1_RX0_IRQ 20
+#define NVIC_CAN1_RX1_IRQ 21
+#define NVIC_CAN1_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_TIM9_IRQ 24
+#define NVIC_TIM1_UP_TIM10_IRQ 25
+#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_FS_WKUP_IRQ 42
+#define NVIC_TIM8_BRK_TIM12_IRQ 43
+#define NVIC_TIM8_UP_TIM13_IRQ 44
+#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_DMA1_STREAM7_IRQ 47
+#define NVIC_FSMC_IRQ 48
+#define NVIC_SDIO_IRQ 49
+#define NVIC_TIM5_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_UART4_IRQ 52
+#define NVIC_UART5_IRQ 53
+#define NVIC_TIM6_DAC_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_STREAM0_IRQ 56
+#define NVIC_DMA2_STREAM1_IRQ 57
+#define NVIC_DMA2_STREAM2_IRQ 58
+#define NVIC_DMA2_STREAM3_IRQ 59
+#define NVIC_DMA2_STREAM4_IRQ 60
+#define NVIC_ETH_IRQ 61
+#define NVIC_ETH_WKUP_IRQ 62
+#define NVIC_CAN2_TX_IRQ 63
+#define NVIC_CAN2_RX0_IRQ 64
+#define NVIC_CAN2_RX1_IRQ 65
+#define NVIC_CAN2_SCE_IRQ 66
+#define NVIC_OTG_FS_IRQ 67
+#define NVIC_DMA2_STREAM5_IRQ 68
+#define NVIC_DMA2_STREAM6_IRQ 69
+#define NVIC_DMA2_STREAM7_IRQ 70
+#define NVIC_USART6_IRQ 71
+#define NVIC_I2C3_EV_IRQ 72
+#define NVIC_I2C3_ER_IRQ 73
+#define NVIC_OTG_HS_EP1_OUT_IRQ 74
+#define NVIC_OTG_HS_EP1_IN_IRQ 75
+#define NVIC_OTG_HS_WKUP_IRQ 76
+#define NVIC_OTG_HS_IRQ 77
+#define NVIC_DCMI_IRQ 78
+#define NVIC_CRYP_IRQ 79
+#define NVIC_HASH_RNG_IRQ 80
+#define NVIC_FPU_IRQ 81
+#define NVIC_UART7_IRQ 82
+#define NVIC_UART8_IRQ 83
+#define NVIC_SPI4_IRQ 84
+#define NVIC_SPI5_IRQ 85
+#define NVIC_SPI6_IRQ 86
+#define NVIC_SAI1_IRQ 87
+#define NVIC_LCD_TFT_IRQ 88
+#define NVIC_LCD_TFT_ERR_IRQ 89
+#define NVIC_DMA2D_IRQ 90
+"""
+
+splitted_irqs = irq_defines.split("\n")[1:-1]
+splitted_irqs = [s[13:] for s in splitted_irqs]
+
+for i, irq in enumerate(splitted_irqs):
+    space_i = irq.find(' ')
+    splitted_irqs[i] = "ISR_" + irq[:space_i - 4]
+
+splitted_irqs_for_enum = []
+for i, irq in enumerate(splitted_irqs):
+    space_i = irq.find(' ')
+    if i == 0:
+        irq = "ISR_" + irq + " = 0,"
+    else:
+        irq = "ISR_" + irq + ","
+
+    splitted_irqs_for_enum.append(irq)
+
+f = open("irq_enum.txt", "w+")
+f.write("enum Interrupt : uint32_t {" + "\n")
+for irq in splitted_irqs_for_enum:
+    f.write("\t" + irq + "\n")
+f.write("};")
+f.close()
+
+defines = ["DEFINE_CALLBACK({}_isr, {:>25s})".format(s[4:].lower(), s) for s in splitted_irqs]
+
+f = open("irq_defines.txt", "w+")
+for define in defines:
+    f.write(define + "\n")
+f.close()
\ No newline at end of file