diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-04-24 21:34:43 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-04-24 21:34:43 +0300 |
commit | 4544db3f848f1d5d0f48d39c22c9636aecf73cf6 (patch) | |
tree | c0fec7492370d696c1558796304bd008e102990c /Documentation | |
parent | b9916af776013051a34ccf47bc5e13acffef16c3 (diff) | |
parent | 59bff30ad6cec6b5babc8132eb8dcb48f1c82be0 (diff) |
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- Ensure context synchronisation after a write to APIAKey.
- Fix bullet list formatting in Documentation/arm64/amu.rst to
eliminate doc warnings.
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
Documentation: arm64: fix amu.rst doc warnings
arm64: sync kernel APIAKey when installing
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/arm64/amu.rst | 47 |
1 files changed, 26 insertions, 21 deletions
diff --git a/Documentation/arm64/amu.rst b/Documentation/arm64/amu.rst index 5057b11100ed..036783ee327f 100644 --- a/Documentation/arm64/amu.rst +++ b/Documentation/arm64/amu.rst @@ -23,13 +23,14 @@ optional external memory-mapped interface. Version 1 of the Activity Monitors architecture implements a counter group of four fixed and architecturally defined 64-bit event counters. - - CPU cycle counter: increments at the frequency of the CPU. - - Constant counter: increments at the fixed frequency of the system - clock. - - Instructions retired: increments with every architecturally executed - instruction. - - Memory stall cycles: counts instruction dispatch stall cycles caused by - misses in the last level cache within the clock domain. + +- CPU cycle counter: increments at the frequency of the CPU. +- Constant counter: increments at the fixed frequency of the system + clock. +- Instructions retired: increments with every architecturally executed + instruction. +- Memory stall cycles: counts instruction dispatch stall cycles caused by + misses in the last level cache within the clock domain. When in WFI or WFE these counters do not increment. @@ -57,11 +58,12 @@ counters, only the presence of the extension. Firmware (code running at higher exception levels, e.g. arm-tf) support is needed to: - - Enable access for lower exception levels (EL2 and EL1) to the AMU - registers. - - Enable the counters. If not enabled these will read as 0. - - Save/restore the counters before/after the CPU is being put/brought up - from the 'off' power state. + +- Enable access for lower exception levels (EL2 and EL1) to the AMU + registers. +- Enable the counters. If not enabled these will read as 0. +- Save/restore the counters before/after the CPU is being put/brought up + from the 'off' power state. When using kernels that have this feature enabled but boot with broken firmware the user may experience panics or lockups when accessing the @@ -78,10 +80,11 @@ are not trapped in EL2/EL3. The fixed counters of AMUv1 are accessible though the following system register definitions: - - SYS_AMEVCNTR0_CORE_EL0 - - SYS_AMEVCNTR0_CONST_EL0 - - SYS_AMEVCNTR0_INST_RET_EL0 - - SYS_AMEVCNTR0_MEM_STALL_EL0 + +- SYS_AMEVCNTR0_CORE_EL0 +- SYS_AMEVCNTR0_CONST_EL0 +- SYS_AMEVCNTR0_INST_RET_EL0 +- SYS_AMEVCNTR0_MEM_STALL_EL0 Auxiliary platform specific counters can be accessed using SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15. @@ -93,9 +96,10 @@ Userspace access ---------------- Currently, access from userspace to the AMU registers is disabled due to: - - Security reasons: they might expose information about code executed in - secure mode. - - Purpose: AMU counters are intended for system management use. + +- Security reasons: they might expose information about code executed in + secure mode. +- Purpose: AMU counters are intended for system management use. Also, the presence of the feature is not visible to userspace. @@ -105,8 +109,9 @@ Virtualization Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM guest side is disabled due to: - - Security reasons: they might expose information about code executed - by other guests or the host. + +- Security reasons: they might expose information about code executed + by other guests or the host. Any attempt to access the AMU registers will result in an UNDEFINED exception being injected into the guest. |