From aeb871d67988059cbe1fdf499b57ae60a83f2291 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 7 Jul 2022 15:50:09 +0300 Subject: dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'iomux/pinctrl' child node of the SCU main node. Signed-off-by: Abel Vesa Signed-off-by: Viorel Suman Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 40 ---------------------- 1 file changed, 40 deletions(-) (limited to 'Documentation/devicetree/bindings/arm/freescale') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index ef7f5222ac48..5ec2a031194e 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -79,33 +79,7 @@ Required properties: See detailed Resource ID list from: include/dt-bindings/firmware/imx/rsrc.h -Pinctrl bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding uses the i.MX common pinctrl binding[3]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-iomuxc", - "fsl,imx8qxp-iomuxc", - "fsl,imx8dxl-iomuxc". - -Required properties for Pinctrl sub nodes: -- fsl,pins: Each entry consists of 3 integers which represents - the mux and config setting for one pin. The first 2 - integers are specified using a - PIN_FUNC_ID macro, which can be found in - , - , - . - The last integer CONFIG is the pad setting value like - pull-up on this pin. - - Please refer to i.MX8QXP Reference Manual for detailed - CONFIG settings. - [2] Documentation/devicetree/bindings/power/power-domain.yaml -[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt RTC bindings based on SCU Message Protocol ------------------------------------------------------------ @@ -184,18 +158,6 @@ firmware { &lsio_mu1 1 3 &lsio_mu1 3 3>; - iomuxc { - compatible = "fsl,imx8qxp-iomuxc"; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 - SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - ... - }; - ocotp: imx8qx-ocotp { compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; @@ -234,7 +196,5 @@ firmware { serial@5a060000 { ... - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; power-domains = <&pd IMX_SC_R_UART_0>; }; -- cgit v1.2.3