From 6c389328c985a3aa8575cf3a573a05c1d121fceb Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 11 Mar 2022 17:49:35 -0600 Subject: dt-bindings: pci: layerscape-pci: Add a optional property big-endian This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Link: https://lore.kernel.org/r/20220311234938.8706-2-leoyang.li@nxp.com Signed-off-by: Hou Zhiqiang Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a470..215d2ee65c83 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -40,6 +40,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { -- cgit v1.2.3 From 84f293b204ab1ef519278e7993e9930f03879627 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 11 Mar 2022 17:49:36 -0600 Subject: dt-bindings: pci: layerscape-pci: Update the description of SCFG property Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Link: https://lore.kernel.org/r/20220311234938.8706-3-leoyang.li@nxp.com Signed-off-by: Hou Zhiqiang Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 215d2ee65c83..f1115fcd8088 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -34,7 +34,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software -- cgit v1.2.3 From cddc1a9ab360d10891bf05e178ea225fb2791355 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Fri, 11 Mar 2022 17:49:37 -0600 Subject: dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a Add EP mode compatible string for ls1028a. Link: https://lore.kernel.org/r/20220311234938.8706-4-leoyang.li@nxp.com Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f1115fcd8088..8fd6039a826b 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -23,6 +23,7 @@ Required properties: "fsl,ls1012a-pcie" "fsl,ls1028a-pcie" EP mode: + "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" -- cgit v1.2.3 From a3b18f5f1d42e7e08eda5d131a34b352a50deb6e Mon Sep 17 00:00:00 2001 From: Li Yang Date: Fri, 11 Mar 2022 17:49:38 -0600 Subject: dt-bindings: pci: layerscape-pci: define AER/PME interrupts Different platforms using this controller are using different numbers of interrupt lines and the routing of events to these interrupt lines are different too. So instead of trying to define names for these interrupt lines, we define the more specific AER/PME events that are routed to these interrupt lines. For platforms which only has a single interrupt line for miscellaneous controller events, we can keep using the original "intr" name for backward compatibility. Also change the example from ls1021a to ls1088a for better representation. Link: https://lore.kernel.org/r/20220311234938.8706-5-leoyang.li@nxp.com Signed-off-by: Li Yang Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/layerscape-pci.txt | 58 ++++++++++++---------- 1 file changed, 32 insertions(+), 26 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 8fd6039a826b..ee8a4791a78b 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -31,8 +31,14 @@ Required properties: - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used + "pme": Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used + "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry is the physical PCIe controller index starting from '0'. @@ -47,27 +53,27 @@ Optional properties: Example: - pcie@3400000 { - compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - }; + pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <256>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; -- cgit v1.2.3 From f21949c1496807571ed3d09ed22e0ebeaec3e643 Mon Sep 17 00:00:00 2001 From: Alex Williamson Date: Wed, 20 Apr 2022 14:45:05 -0600 Subject: PCI/doc: Update obsolete pci_set_dma_mask() references The function is dma_set_mask(), fix a missed instance of the old pci_set_dma_mask() and a reference to a function that doesn't exist. Fixes: 05b0ebd06ae6 ("PCI/doc: cleanup references to the legacy PCI DMA API") Link: https://lore.kernel.org/r/165048747271.2959320.13475081883467312497.stgit@omen Signed-off-by: Alex Williamson Signed-off-by: Bjorn Helgaas Reviewed-by: Christoph Hellwig --- Documentation/PCI/pci.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/PCI/pci.rst b/Documentation/PCI/pci.rst index 67a850b55617..cced568d78e9 100644 --- a/Documentation/PCI/pci.rst +++ b/Documentation/PCI/pci.rst @@ -273,12 +273,12 @@ Set the DMA mask size While all drivers should explicitly indicate the DMA capability (e.g. 32 or 64 bit) of the PCI bus master, devices with more than 32-bit bus master capability for streaming data need the driver -to "register" this capability by calling pci_set_dma_mask() with +to "register" this capability by calling dma_set_mask() with appropriate parameters. In general this allows more efficient DMA on systems where System RAM exists above 4G _physical_ address. Drivers for all PCI-X and PCIe compliant devices must call -set_dma_mask() as they are 64-bit DMA devices. +dma_set_mask() as they are 64-bit DMA devices. Similarly, drivers must also "register" this capability if the device can directly address "coherent memory" in System RAM above 4G physical -- cgit v1.2.3 From 931262e646caae906d818c82390ebc1716263ff0 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 08:38:27 -0400 Subject: dt-bindings: PCI: Remove fallback from Rockchip DesignWare binding The snps,dw-pcie binds to a standalone driver. It is not fully compatible with the Rockchip implementation and causes a hang if it binds to the device. Remove this binding as a valid fallback. Link: https://lore.kernel.org/r/20220429123832.2376381-2-pgwipeout@gmail.com Signed-off-by: Peter Geis Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 142bbe577763..bc0a9d1db750 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -19,20 +19,10 @@ description: |+ allOf: - $ref: /schemas/pci/pci-bus.yaml# -# We need a select here so we don't match all nodes with 'snps,dw-pcie' -select: - properties: - compatible: - contains: - const: rockchip,rk3568-pcie - required: - - compatible - properties: compatible: items: - const: rockchip,rk3568-pcie - - const: snps,dw-pcie reg: items: @@ -110,7 +100,7 @@ examples: #size-cells = <2>; pcie3x2: pcie@fe280000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0800000 0x0 0x390000>, <0x0 0xfe280000 0x0 0x10000>, <0x3 0x80000000 0x0 0x100000>; -- cgit v1.2.3 From fa6dae5d82081e8d9f8e6a2baf7149442a6c1ba5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 19 May 2022 17:21:48 +0200 Subject: x86/PCI: Add kernel cmdline options to use/ignore E820 reserved regions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some firmware supplies PCI host bridge _CRS that includes address space unusable by PCI devices, e.g., space occupied by host bridge registers or used by hidden PCI devices. To avoid this unusable space, Linux currently excludes E820 reserved regions from _CRS windows; see 4dc2287c1805 ("x86: avoid E820 regions when allocating address space"). However, this use of E820 reserved regions to clip things out of _CRS is not supported by ACPI, UEFI, or PCI Firmware specs, and some systems have E820 reserved regions that cover the entire memory window from _CRS. 4dc2287c1805 clips the entire window, leaving no space for hot-added or uninitialized PCI devices. For example, from a Lenovo IdeaPad 3 15IIL 81WE: BIOS-e820: [mem 0x4bc50000-0xcfffffff] reserved pci_bus 0000:00: root bus resource [mem 0x65400000-0xbfffffff window] pci 0000:00:15.0: BAR 0: [mem 0x00000000-0x00000fff 64bit] pci 0000:00:15.0: BAR 0: no space for [mem size 0x00001000 64bit] Future patches will add quirks to enable/disable E820 clipping automatically. Add a "pci=no_e820" kernel command line option to disable clipping with E820 reserved regions. Also add a matching "pci=use_e820" option to enable clipping with E820 reserved regions if that has been disabled by default by further patches in this patch-set. Both options taint the kernel because they are intended for debugging and workaround purposes until a quirk can set them automatically. [bhelgaas: commit log, add printk] Link: https://bugzilla.redhat.com/show_bug.cgi?id=1868899 Lenovo IdeaPad 3 Link: https://lore.kernel.org/r/20220519152150.6135-2-hdegoede@redhat.com Signed-off-by: Hans de Goede Signed-off-by: Bjorn Helgaas Acked-by: Rafael J. Wysocki Cc: Benoit Grégoire Cc: Hui Wang --- Documentation/admin-guide/kernel-parameters.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 3f1cc5e317ed..2477b639d5c4 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4066,6 +4066,15 @@ please report a bug. nocrs [X86] Ignore PCI host bridge windows from ACPI. If you need to use this, please report a bug. + use_e820 [X86] Use E820 reservations to exclude parts of + PCI host bridge windows. This is a workaround + for BIOS defects in host bridge _CRS methods. + If you need to use this, please report a bug to + . + no_e820 [X86] Ignore E820 reservations for PCI host + bridge windows. This is the default on modern + hardware. If you need to use this, please report + a bug to . routeirq Do IRQ routing for all PCI devices. This is normally done in pci_enable_device(), so this option is a temporary workaround -- cgit v1.2.3 From a6e25b39adc3f68b9bc46f8e100345ee9bf62f8c Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 26 Mar 2022 11:38:09 +0530 Subject: dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to the one used on SM8250. Link: https://lore.kernel.org/r/20220326060810.1797516-2-bhupesh.sharma@linaro.org Signed-off-by: Bhupesh Sharma Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring Cc: Lorenzo Pieralisi Cc: Bjorn Andersson --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 0adb56d5645e..fd8b6d1912e7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -14,6 +14,7 @@ - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8150" for sm8150 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 @@ -159,7 +160,7 @@ - "pipe" PIPE clock - clock-names: - Usage: required for sc8180x and sm8250 + Usage: required for sc8180x, sm8150 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -266,7 +267,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845, sm8250 and sm8450 + Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450 Value type: Definition: Should contain the following entries - "pci" PCIe core reset -- cgit v1.2.3 From 075a9d55932edc8bddf85c6f8c0764928691cde4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 6 May 2022 18:21:00 +0300 Subject: dt-bindings: PCI: qcom: Convert to YAML Changes to the schema: - Fixed the ordering of clock-names/reset-names according to the dtsi files. - Mark vdda-supply as required only for apq/ipq8064 (as it was marked as generally required in the txt file). Changes to examples: - Inline clock and reset numbers rather than including dt-bindings files because of conflicts between the headers - Split ranges and reg properties to follow current practice - Change -gpio to -gpios - Update IRQ flags to LEVEL_HIGH rater than NONE - Removed extra "snps,dw-pcie" compatibility. Note: while it was not clearly described in text schema, the majority of Qualcomm platforms follow the snps,dw-pcie schema and use two compatibility strings in the DT files: platform-specific one and a fallback to the generic snps,dw-pcie one. However the platform itself is not compatible with the snps,dw-pcie interface, so we are going to remove it. Link: https://lore.kernel.org/r/20220506152107.1527552-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.txt | 398 -------------- .../devicetree/bindings/pci/qcom,pcie.yaml | 595 +++++++++++++++++++++ 2 files changed, 595 insertions(+), 398 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt deleted file mode 100644 index fd8b6d1912e7..000000000000 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ /dev/null @@ -1,398 +0,0 @@ -* Qualcomm PCI express root complex - -- compatible: - Usage: required - Value type: - Definition: Value should contain - - "qcom,pcie-ipq8064" for ipq8064 - - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - - "qcom,pcie-apq8064" for apq8064 - - "qcom,pcie-apq8084" for apq8084 - - "qcom,pcie-msm8996" for msm8996 or apq8096 - - "qcom,pcie-ipq4019" for ipq4019 - - "qcom,pcie-ipq8074" for ipq8074 - - "qcom,pcie-qcs404" for qcs404 - - "qcom,pcie-sc8180x" for sc8180x - - "qcom,pcie-sdm845" for sdm845 - - "qcom,pcie-sm8150" for sm8150 - - "qcom,pcie-sm8250" for sm8250 - - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 - - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - - "qcom,pcie-ipq6018" for ipq6018 - -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: - Definition: Must include the following entries - - "parf" Qualcomm specific registers - - "dbi" DesignWare PCIe registers - - "elbi" External local bus interface registers - - "config" PCIe configuration space - - "atu" ATU address space (optional) - -- device_type: - Usage: required - Value type: - Definition: Should be "pci". As specified in snps,dw-pcie.yaml - -- #address-cells: - Usage: required - Value type: - Definition: Should be 3. As specified in snps,dw-pcie.yaml - -- #size-cells: - Usage: required - Value type: - Definition: Should be 2. As specified in snps,dw-pcie.yaml - -- ranges: - Usage: required - Value type: - Definition: As specified in snps,dw-pcie.yaml - -- interrupts: - Usage: required - Value type: - Definition: MSI interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain "msi" - -- #interrupt-cells: - Usage: required - Value type: - Definition: Should be 1. As specified in snps,dw-pcie.yaml - -- interrupt-map-mask: - Usage: required - Value type: - Definition: As specified in snps,dw-pcie.yaml - -- interrupt-map: - Usage: required - Value type: - Definition: As specified in snps,dw-pcie.yaml - -- clocks: - Usage: required - Value type: - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: - Definition: Should contain the following entries - - "iface" Configuration AHB clock - -- clock-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "core" Clocks the pcie hw block - - "phy" Clocks the pcie PHY block - - "aux" Clocks the pcie AUX block - - "ref" Clocks the pcie ref block -- clock-names: - Usage: required for apq8084/ipq4019 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary (AUX) clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for msm8996/apq8096 - Value type: - Definition: Should contain the following entries - - "pipe" Pipe Clock driving internal logic - - "aux" Auxiliary (AUX) clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for ipq8074 - Value type: - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock - - "axi_s" AXI Slave clock - - "ahb" AHB clock - - "aux" Auxiliary clock - -- clock-names: - Usage: required for ipq6018 - Value type: - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock - - "axi_s" AXI Slave clock - - "axi_bridge" AXI bridge clock - - "rchng" - -- clock-names: - Usage: required for qcs404 - Value type: - Definition: Should contain the following entries - - "iface" AHB clock - - "aux" Auxiliary clock - - "master_bus" AXI Master clock - - "slave_bus" AXI Slave clock - -- clock-names: - Usage: required for sdm845 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - - "slave_q2a" Slave Q2A clock - - "tbu" PCIe TBU clock - - "pipe" PIPE clock - -- clock-names: - Usage: required for sc8180x, sm8150 and sm8250 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - - "slave_q2a" Slave Q2A clock - - "tbu" PCIe TBU clock - - "ddrss_sf_tbu" PCIe SF TBU clock - - "pipe" PIPE clock - -- clock-names: - Usage: required for sm8450-pcie0 and sm8450-pcie1 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - - "slave_q2a" Slave Q2A clock - - "tbu" PCIe TBU clock - - "ddrss_sf_tbu" PCIe SF TBU clock - - "pipe" PIPE clock - - "pipe_mux" PIPE MUX - - "phy_pipe" PIPE output clock - - "ref" REFERENCE clock - - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 - - "aggre1" Aggre NoC PCIe1 AXI clock - -- resets: - Usage: required - Value type: - Definition: List of phandle and reset specifier pairs as listed - in reset-names property - -- reset-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "axi" AXI reset - - "ahb" AHB reset - - "por" POR reset - - "pci" PCI reset - - "phy" PHY reset - -- reset-names: - Usage: required for apq8084 - Value type: - Definition: Should contain the following entries - - "core" Core reset - -- reset-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "axi_m" AXI master reset - - "axi_s" AXI slave reset - - "pipe" PIPE reset - - "axi_m_vmid" VMID reset - - "axi_s_xpu" XPU reset - - "parf" PARF reset - - "phy" PHY reset - - "axi_m_sticky" AXI sticky reset - - "pipe_sticky" PIPE sticky reset - - "pwr" PWR reset - - "ahb" AHB reset - - "phy_ahb" PHY AHB reset - - "ext" EXT reset - -- reset-names: - Usage: required for ipq8074 - Value type: - Definition: Should contain the following entries - - "pipe" PIPE reset - - "sleep" Sleep reset - - "sticky" Core Sticky reset - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "ahb" AHB Reset - - "axi_m_sticky" AXI Master Sticky reset - -- reset-names: - Usage: required for ipq6018 - Value type: - Definition: Should contain the following entries - - "pipe" PIPE reset - - "sleep" Sleep reset - - "sticky" Core Sticky reset - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "ahb" AHB Reset - - "axi_m_sticky" AXI Master Sticky reset - - "axi_s_sticky" AXI Slave Sticky reset - -- reset-names: - Usage: required for qcs404 - Value type: - Definition: Should contain the following entries - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "axi_m_sticky" AXI Master Sticky reset - - "pipe_sticky" PIPE sticky reset - - "pwr" PWR reset - - "ahb" AHB reset - -- reset-names: - Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450 - Value type: - Definition: Should contain the following entries - - "pci" PCIe core reset - -- power-domains: - Usage: required for apq8084 and msm8996/apq8096 - Value type: - Definition: A phandle and power domain specifier pair to the - power domain which is responsible for collapsing - and restoring power to the peripheral - -- vdda-supply: - Usage: required - Value type: - Definition: A phandle to the core analog power supply - -- vdda_phy-supply: - Usage: required for ipq/apq8064 - Value type: - Definition: A phandle to the analog power supply for PHY - -- vdda_refclk-supply: - Usage: required for ipq/apq8064 - Value type: - Definition: A phandle to the analog power supply for IC which generates - reference clock -- vddpe-3v3-supply: - Usage: optional - Value type: - Definition: A phandle to the PCIe endpoint power supply - -- phys: - Usage: required for apq8084 and qcs404 - Value type: - Definition: List of phandle(s) as listed in phy-names property - -- phy-names: - Usage: required for apq8084 and qcs404 - Value type: - Definition: Should contain "pciephy" - -- -gpios: - Usage: optional - Value type: - Definition: List of phandle and GPIO specifier pairs. Should contain - - "perst-gpios" PCIe endpoint reset signal line - - "wake-gpios" PCIe endpoint wake signal line - -* Example for ipq/apq8064 - pcie@1b500000 { - compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>, - <&gcc PCIE_AUX_CLK>, - <&gcc PCIE_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>, - <&gcc PCIE_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - pinctrl-0 = <&pcie_pins_default>; - pinctrl-names = "default"; - }; - -* Example for apq8084 - pcie0@fc520000 { - compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; - reg = <0xfc520000 0x2000>, - <0xff000000 0x1000>, - <0xff001000 0x1000>, - <0xff002000 0x2000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ - 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "iface", "master_bus", "slave_bus", "aux"; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE0_GDSC>; - vdda-supply = <&pma8084_l3>; - phys = <&pciephy0>; - phy-names = "pciephy"; - perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins_default>; - pinctrl-names = "default"; - }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml new file mode 100644 index 000000000000..16f765e96128 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -0,0 +1,595 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI express root complex + +maintainers: + - Bjorn Andersson + - Stanimir Varbanov + +description: | + Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare + PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064-v2 + - qcom,pcie-apq8064 + - qcom,pcie-apq8084 + - qcom,pcie-msm8996 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + - qcom,pcie-ipq6018 + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + maxItems: 5 + items: + enum: + - parf # Qualcomm specific registers + - dbi # DesignWare PCIe registers + - elbi # External local bus interface registers + - config # PCIe configuration space + - atu # ATU address space (optional) + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + # Common definitions for clocks, clock-names and reset. + # Platform constraints are described later. + clocks: + minItems: 3 + maxItems: 12 + + clock-names: + minItems: 3 + maxItems: 12 + + resets: + minItems: 1 + maxItems: 12 + + resets-names: + minItems: 1 + maxItems: 12 + + vdda-supply: + description: A phandle to the core analog power supply + + vdda_phy-supply: + description: A phandle to the core analog power supply for PHY + + vdda_refclk-supply: + description: A phandle to the core analog power supply for IC which generates reference clock + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + - resets + - reset-names + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + then: + properties: + clocks: + minItems: 3 + maxItems: 5 + clock-names: + minItems: 3 + items: + - const: core # Clocks the pcie hw block + - const: iface # Configuration AHB clock + - const: phy # Clocks the pcie PHY block + - const: aux # Clocks the pcie AUX block, not on apq8064 + - const: ref # Clocks the pcie ref block, not on apq8064 + resets: + minItems: 5 + maxItems: 6 + reset-names: + minItems: 5 + items: + - const: axi # AXI reset + - const: ahb # AHB reset + - const: por # POR reset + - const: pci # PCI reset + - const: phy # PHY reset + - const: ext # EXT reset, not on apq8064 + required: + - vdda-supply + - vdda_phy-supply + - vdda_refclk-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8084 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: iface # Configuration AHB clock + - const: master_bus # Master AXI clock + - const: slave_bus # Slave AXI clock + - const: aux # Auxiliary (AUX) clock + resets: + maxItems: 1 + reset-names: + items: + - const: core # Core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq4019 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: aux # Auxiliary (AUX) clock + - const: master_bus # Master AXI clock + - const: slave_bus # Slave AXI clock + resets: + minItems: 12 + maxItems: 12 + reset-names: + items: + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: pipe # PIPE reset + - const: axi_m_vmid # VMID reset + - const: axi_s_xpu # XPU reset + - const: parf # PARF reset + - const: phy # PHY reset + - const: axi_m_sticky # AXI sticky reset + - const: pipe_sticky # PIPE sticky reset + - const: pwr # PWR reset + - const: ahb # AHB reset + - const: phy_ahb # PHY AHB reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-msm8996 + then: + oneOf: + - properties: + clock-names: + items: + - const: pipe # Pipe Clock driving internal logic + - const: aux # Auxiliary (AUX) clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - properties: + clock-names: + items: + - const: pipe # Pipe Clock driving internal logic + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: cfg # Configuration clock + - const: aux # Auxiliary (AUX) clock + properties: + clocks: + minItems: 5 + maxItems: 5 + resets: false + reset-names: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq8074 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + resets: + minItems: 7 + maxItems: 7 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core Sticky reset + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: ahb # AHB Reset + - const: axi_m_sticky # AXI Master Sticky reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq6018 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core Sticky reset + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: ahb # AHB Reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: axi_s_sticky # AXI Slave Sticky reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-qcs404 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: iface # AHB clock + - const: aux # Auxiliary clock + - const: master_bus # AXI Master clock + - const: slave_bus # AXI Slave clock + resets: + minItems: 6 + maxItems: 6 + reset-names: + items: + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: pipe_sticky # PIPE sticky reset + - const: pwr # PWR reset + - const: ahb # AHB reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sdm845 + then: + oneOf: + # Unfortunately the "optional" ref clock is used in the middle of the list + - properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + properties: + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8180x + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + then: + oneOf: + # Unfortunately the "optional" ref clock is used in the middle of the list + - properties: + clocks: + minItems: 9 + maxItems: 9 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + properties: + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8450-pcie0 + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8450-pcie1 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + then: + required: + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + pcie@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000>, + <0x1b502000 0x80>, + <0x1b600000 0x100>, + <0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, + <0x82000000 0 0 0x08000000 0 0x07e00000>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc 41>, + <&gcc 43>, + <&gcc 44>, + <&gcc 42>, + <&gcc 248>; + clock-names = "core", "iface", "phy", "aux", "ref"; + resets = <&gcc 27>, + <&gcc 26>, + <&gcc 25>, + <&gcc 24>, + <&gcc 23>, + <&gcc 22>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + pinctrl-0 = <&pcie_pins_default>; + pinctrl-names = "default"; + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&ext_3p3v>; + }; + - | + #include + #include + pcie@fc520000 { + compatible = "qcom,pcie-apq8084"; + reg = <0xfc520000 0x2000>, + <0xff000000 0x1000>, + <0xff001000 0x1000>, + <0xff002000 0x2000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, + <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc 324>, + <&gcc 325>, + <&gcc 327>, + <&gcc 323>; + clock-names = "iface", "master_bus", "slave_bus", "aux"; + resets = <&gcc 81>; + reset-names = "core"; + power-domains = <&gcc 1>; + vdda-supply = <&pma8084_l3>; + phys = <&pciephy0>; + phy-names = "pciephy"; + perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins_default>; + pinctrl-names = "default"; + }; +... -- cgit v1.2.3 From 6700a9b00f0aad206903b6ff216db56faf964654 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 6 May 2022 18:21:01 +0300 Subject: dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms On MSM8996/APQ8096 platforms the PCIe controller doesn't have any resets. So move the requirement stanza under the corresponding if condition. Link: https://lore.kernel.org/r/20220506152107.1527552-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 16f765e96128..ce4f53cdaba0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -114,8 +114,6 @@ required: - interrupt-map - clocks - clock-names - - resets - - reset-names allOf: - $ref: /schemas/pci/pci-bus.yaml# @@ -504,6 +502,18 @@ allOf: required: - power-domains + - if: + not: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + then: + required: + - resets + - reset-names + unevaluatedProperties: false examples: -- cgit v1.2.3 From c6523c4a301d3adff7ddcf57515b9c847beb7566 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 6 May 2022 18:21:02 +0300 Subject: dt-bindings: PCI: qcom: Specify reg-names explicitly Instead of specifying the enum of possible reg-names, specify them explicitly. This allows us to specify which chipsets need the "atu" regions and which do not. Also it clearly describes which platforms enumerate PCIe cores using the dbi region and which use parf region for that. Link: https://lore.kernel.org/r/20220506152107.1527552-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.yaml | 91 ++++++++++++++++++++-- 1 file changed, 84 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index ce4f53cdaba0..e91ae436cafe 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -40,13 +40,6 @@ properties: reg-names: minItems: 4 maxItems: 5 - items: - enum: - - parf # Qualcomm specific registers - - dbi # DesignWare PCIe registers - - elbi # External local bus interface registers - - config # PCIe configuration space - - atu # ATU address space (optional) interrupts: maxItems: 1 @@ -117,6 +110,90 @@ required: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq6018 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8084 + - qcom,pcie-msm8996 + - qcom,pcie-sdm845 + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8180x + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - if: properties: compatible: -- cgit v1.2.3 From 3f467d122f27f3a0be7fa7f2f60c7dd9475c4a81 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 6 May 2022 18:21:03 +0300 Subject: dt-bindings: PCI: qcom: Add schema for sc7280 chipset Add support for sc7280-specific clock and reset definitions. Link: https://lore.kernel.org/r/20220506152107.1527552-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.yaml | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index e91ae436cafe..0b69b12b849e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -25,6 +25,7 @@ properties: - qcom,pcie-ipq4019 - qcom,pcie-ipq8074 - qcom,pcie-qcs404 + - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - qcom,pcie-sm8150 @@ -177,6 +178,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 @@ -412,6 +414,36 @@ allOf: - const: pwr # PWR reset - const: ahb # AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc7280 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: -- cgit v1.2.3