From d7445676e86900f8dc363825033ff62416c216e0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 1 Apr 2022 14:35:42 +0200 Subject: ARM: versatile: move integrator/realview/vexpress to versatile These are all fairly small platforms by now, and they are closely related. Just move them all into a single directory. Cc: Linus Walleij Cc: Liviu Dudau Cc: Lorenzo Pieralisi Tested-by: Sudeep Holla Acked-by: Sudeep Holla Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 6 - arch/arm/Makefile | 7 +- arch/arm/mach-integrator/Kconfig | 125 ------ arch/arm/mach-integrator/Makefile | 10 - arch/arm/mach-integrator/cm.h | 41 -- arch/arm/mach-integrator/common.h | 7 - arch/arm/mach-integrator/core.c | 96 ---- arch/arm/mach-integrator/hardware.h | 336 -------------- arch/arm/mach-integrator/integrator_ap.c | 202 --------- arch/arm/mach-integrator/integrator_cp.c | 147 ------ arch/arm/mach-realview/Kconfig | 103 ----- arch/arm/mach-realview/Makefile | 8 - arch/arm/mach-realview/platsmp-dt.c | 93 ---- arch/arm/mach-realview/realview-dt.c | 27 -- arch/arm/mach-versatile/Kconfig | 308 +++++++++++++ arch/arm/mach-versatile/Makefile | 32 +- arch/arm/mach-versatile/Makefile.boot | 4 + arch/arm/mach-versatile/dcscb.c | 172 +++++++ arch/arm/mach-versatile/dcscb_setup.S | 33 ++ arch/arm/mach-versatile/headsmp.S | 36 ++ arch/arm/mach-versatile/hotplug.c | 102 +++++ arch/arm/mach-versatile/integrator-cm.h | 41 ++ arch/arm/mach-versatile/integrator-hardware.h | 336 ++++++++++++++ arch/arm/mach-versatile/integrator.c | 94 ++++ arch/arm/mach-versatile/integrator.h | 7 + arch/arm/mach-versatile/integrator_ap.c | 200 +++++++++ arch/arm/mach-versatile/integrator_cp.c | 145 ++++++ arch/arm/mach-versatile/platsmp-realview.c | 93 ++++ arch/arm/mach-versatile/platsmp-vexpress.c | 93 ++++ arch/arm/mach-versatile/platsmp.c | 107 +++++ arch/arm/mach-versatile/platsmp.h | 11 + arch/arm/mach-versatile/realview.c | 27 ++ arch/arm/mach-versatile/spc.c | 598 +++++++++++++++++++++++++ arch/arm/mach-versatile/spc.h | 18 + arch/arm/mach-versatile/tc2_pm.c | 261 +++++++++++ arch/arm/mach-versatile/v2m-mps2.c | 17 + arch/arm/mach-versatile/v2m.c | 40 ++ arch/arm/mach-versatile/versatile.c | 185 ++++++++ arch/arm/mach-versatile/versatile_dt.c | 185 -------- arch/arm/mach-versatile/vexpress.h | 4 + arch/arm/mach-vexpress/Kconfig | 81 ---- arch/arm/mach-vexpress/Makefile | 19 - arch/arm/mach-vexpress/Makefile.boot | 4 - arch/arm/mach-vexpress/core.h | 4 - arch/arm/mach-vexpress/dcscb.c | 172 ------- arch/arm/mach-vexpress/dcscb_setup.S | 35 -- arch/arm/mach-vexpress/platsmp.c | 96 ---- arch/arm/mach-vexpress/spc.c | 598 ------------------------- arch/arm/mach-vexpress/spc.h | 18 - arch/arm/mach-vexpress/tc2_pm.c | 263 ----------- arch/arm/mach-vexpress/v2m-mps2.c | 17 - arch/arm/mach-vexpress/v2m.c | 40 -- arch/arm/plat-versatile/Makefile | 5 - arch/arm/plat-versatile/headsmp.S | 38 -- arch/arm/plat-versatile/hotplug.c | 102 ----- arch/arm/plat-versatile/include/plat/platsmp.h | 13 - arch/arm/plat-versatile/platsmp.c | 109 ----- 57 files changed, 2964 insertions(+), 3007 deletions(-) delete mode 100644 arch/arm/mach-integrator/Kconfig delete mode 100644 arch/arm/mach-integrator/Makefile delete mode 100644 arch/arm/mach-integrator/cm.h delete mode 100644 arch/arm/mach-integrator/common.h delete mode 100644 arch/arm/mach-integrator/core.c delete mode 100644 arch/arm/mach-integrator/hardware.h delete mode 100644 arch/arm/mach-integrator/integrator_ap.c delete mode 100644 arch/arm/mach-integrator/integrator_cp.c delete mode 100644 arch/arm/mach-realview/Kconfig delete mode 100644 arch/arm/mach-realview/Makefile delete mode 100644 arch/arm/mach-realview/platsmp-dt.c delete mode 100644 arch/arm/mach-realview/realview-dt.c create mode 100644 arch/arm/mach-versatile/Makefile.boot create mode 100644 arch/arm/mach-versatile/dcscb.c create mode 100644 arch/arm/mach-versatile/dcscb_setup.S create mode 100644 arch/arm/mach-versatile/headsmp.S create mode 100644 arch/arm/mach-versatile/hotplug.c create mode 100644 arch/arm/mach-versatile/integrator-cm.h create mode 100644 arch/arm/mach-versatile/integrator-hardware.h create mode 100644 arch/arm/mach-versatile/integrator.c create mode 100644 arch/arm/mach-versatile/integrator.h create mode 100644 arch/arm/mach-versatile/integrator_ap.c create mode 100644 arch/arm/mach-versatile/integrator_cp.c create mode 100644 arch/arm/mach-versatile/platsmp-realview.c create mode 100644 arch/arm/mach-versatile/platsmp-vexpress.c create mode 100644 arch/arm/mach-versatile/platsmp.c create mode 100644 arch/arm/mach-versatile/platsmp.h create mode 100644 arch/arm/mach-versatile/realview.c create mode 100644 arch/arm/mach-versatile/spc.c create mode 100644 arch/arm/mach-versatile/spc.h create mode 100644 arch/arm/mach-versatile/tc2_pm.c create mode 100644 arch/arm/mach-versatile/v2m-mps2.c create mode 100644 arch/arm/mach-versatile/v2m.c create mode 100644 arch/arm/mach-versatile/versatile.c delete mode 100644 arch/arm/mach-versatile/versatile_dt.c create mode 100644 arch/arm/mach-versatile/vexpress.h delete mode 100644 arch/arm/mach-vexpress/Kconfig delete mode 100644 arch/arm/mach-vexpress/Makefile delete mode 100644 arch/arm/mach-vexpress/Makefile.boot delete mode 100644 arch/arm/mach-vexpress/core.h delete mode 100644 arch/arm/mach-vexpress/dcscb.c delete mode 100644 arch/arm/mach-vexpress/dcscb_setup.S delete mode 100644 arch/arm/mach-vexpress/platsmp.c delete mode 100644 arch/arm/mach-vexpress/spc.c delete mode 100644 arch/arm/mach-vexpress/spc.h delete mode 100644 arch/arm/mach-vexpress/tc2_pm.c delete mode 100644 arch/arm/mach-vexpress/v2m-mps2.c delete mode 100644 arch/arm/mach-vexpress/v2m.c delete mode 100644 arch/arm/plat-versatile/Makefile delete mode 100644 arch/arm/plat-versatile/headsmp.S delete mode 100644 arch/arm/plat-versatile/hotplug.c delete mode 100644 arch/arm/plat-versatile/include/plat/platsmp.h delete mode 100644 arch/arm/plat-versatile/platsmp.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e8091e2d8a8..31f024e6e925 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -622,8 +622,6 @@ source "arch/arm/mach-hisi/Kconfig" source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-integrator/Kconfig" - source "arch/arm/mach-iop32x/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" @@ -675,8 +673,6 @@ source "arch/arm/mach-rda/Kconfig" source "arch/arm/mach-realtek/Kconfig" -source "arch/arm/mach-realview/Kconfig" - source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s3c/Kconfig" @@ -705,8 +701,6 @@ source "arch/arm/mach-ux500/Kconfig" source "arch/arm/mach-versatile/Kconfig" -source "arch/arm/mach-vexpress/Kconfig" - source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-zynq/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a2391b8de5a5..8740e3a63afb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi -machine-$(CONFIG_ARCH_INTEGRATOR) += integrator machine-$(CONFIG_ARCH_IOP32X) += iop32x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone @@ -187,7 +186,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp -machine-$(CONFIG_ARCH_MPS2) += vexpress machine-$(CONFIG_ARCH_MOXART) += moxart machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu @@ -207,7 +205,6 @@ machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom machine-$(CONFIG_ARCH_RDA) += rda machine-$(CONFIG_ARCH_REALTEK) += realtek -machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc machine-$(CONFIG_PLAT_SAMSUNG) += s3c @@ -220,10 +217,9 @@ machine-$(CONFIG_ARCH_STM32) += stm32 machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += ux500 -machine-$(CONFIG_ARCH_VERSATILE) += versatile -machine-$(CONFIG_ARCH_VEXPRESS) += vexpress machine-$(CONFIG_ARCH_VT8500) += vt8500 machine-$(CONFIG_ARCH_ZYNQ) += zynq +machine-$(CONFIG_PLAT_VERSATILE) += versatile machine-$(CONFIG_PLAT_SPEAR) += spear # Platform directory name. This list is sorted alphanumerically @@ -231,7 +227,6 @@ machine-$(CONFIG_PLAT_SPEAR) += spear plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa -plat-$(CONFIG_PLAT_VERSATILE) += versatile # The byte offset of the kernel image in RAM from the start of RAM. TEXT_OFFSET := $(textofs-y) diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig deleted file mode 100644 index d61ea616cf8e..000000000000 --- a/arch/arm/mach-integrator/Kconfig +++ /dev/null @@ -1,125 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menuconfig ARCH_INTEGRATOR - bool "ARM Ltd. Integrator family" - depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 - select ARM_AMBA - select CMA - select DMA_CMA - select HAVE_TCM - select CLK_ICST - select MFD_SYSCON - select PLAT_VERSATILE - select POWER_RESET - select POWER_RESET_VERSATILE - select POWER_SUPPLY - select SOC_INTEGRATOR_CM - select VERSATILE_FPGA_IRQ - help - Support for ARM's Integrator platform. - -if ARCH_INTEGRATOR - -config ARCH_INTEGRATOR_AP - bool "Support Integrator/AP and Integrator/PP2 platforms" - select INTEGRATOR_AP_TIMER - select SERIAL_AMBA_PL010 if TTY - select SERIAL_AMBA_PL010_CONSOLE if TTY - select SOC_BUS - help - Include support for the ARM(R) Integrator/AP and - Integrator/PP2 platforms. - -config INTEGRATOR_IMPD1 - bool "Include support for Integrator/IM-PD1" - depends on ARCH_INTEGRATOR_AP - select ARM_VIC - select GPIO_PL061 - select GPIOLIB - select REGULATOR - select REGULATOR_FIXED_VOLTAGE - help - The IM-PD1 is an add-on logic module for the Integrator which - allows ARM(R) Ltd PrimeCells to be developed and evaluated. - The IM-PD1 can be found on the Integrator/PP2 platform. - -config INTEGRATOR_CM720T - bool "Integrator/CM720T core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4T - select CPU_ARM720T - -config INTEGRATOR_CM920T - bool "Integrator/CM920T core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4T - select CPU_ARM920T - -config INTEGRATOR_CM922T_XA10 - bool "Integrator/CM922T-XA10 core module" - depends on ARCH_MULTI_V4T - depends on ARCH_INTEGRATOR_AP - select CPU_ARM922T - -config INTEGRATOR_CM926EJS - bool "Integrator/CM926EJ-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 - select CPU_ARM926T - -config INTEGRATOR_CM10200E_REV0 - bool "Integrator/CM10200E rev.0 core module" - depends on ARCH_INTEGRATOR_AP && n - depends on ARCH_MULTI_V5 - select CPU_ARM1020 - -config INTEGRATOR_CM10200E - bool "Integrator/CM10200E core module" - depends on ARCH_INTEGRATOR_AP && n - depends on ARCH_MULTI_V5 - select CPU_ARM1020E - -config INTEGRATOR_CM10220E - bool "Integrator/CM10220E core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 - select CPU_ARM1022 - -config INTEGRATOR_CM1026EJS - bool "Integrator/CM1026EJ-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 - select CPU_ARM1026 - -config INTEGRATOR_CM1136JFS - bool "Integrator/CM1136JF-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V6 - select CPU_V6 - -config ARCH_INTEGRATOR_CP - bool "Support Integrator/CP platform" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 - select ARM_TIMER_SP804 - select SERIAL_AMBA_PL011 if TTY - select SERIAL_AMBA_PL011_CONSOLE if TTY - select SOC_BUS - help - Include support for the ARM(R) Integrator CP platform. - -config INTEGRATOR_CT926 - bool "Integrator/CT926 (ARM926EJ-S) core tile" - depends on ARCH_INTEGRATOR_CP - depends on ARCH_MULTI_V5 - select CPU_ARM926T - -config INTEGRATOR_CTB36 - bool "Integrator/CTB36 (ARM1136JF-S) core tile" - depends on ARCH_INTEGRATOR_CP - depends on ARCH_MULTI_V6 - select CPU_V6 - -config ARCH_CINTEGRATOR - depends on ARCH_INTEGRATOR_CP - def_bool y - -endif diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile deleted file mode 100644 index 7857a55c90b0..000000000000 --- a/arch/arm/mach-integrator/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := core.o -obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o -obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o diff --git a/arch/arm/mach-integrator/cm.h b/arch/arm/mach-integrator/cm.h deleted file mode 100644 index f09ea18a50f8..000000000000 --- a/arch/arm/mach-integrator/cm.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * access the core module control register. - */ -u32 cm_get(void); -void cm_control(u32, u32); - -struct device_node; -void cm_init(void); -void cm_clear_irqs(void); - -#define CM_CTRL_LED (1 << 0) -#define CM_CTRL_nMBDET (1 << 1) -#define CM_CTRL_REMAP (1 << 2) - -/* - * Integrator/AP,PP2 specific - */ -#define CM_CTRL_HIGHVECTORS (1 << 4) -#define CM_CTRL_BIGENDIAN (1 << 5) -#define CM_CTRL_FASTBUS (1 << 6) -#define CM_CTRL_SYNC (1 << 7) - -/* - * ARM926/946/966 Integrator/CP specific - */ -#define CM_CTRL_LCDBIASEN (1 << 8) -#define CM_CTRL_LCDBIASUP (1 << 9) -#define CM_CTRL_LCDBIASDN (1 << 10) -#define CM_CTRL_LCDMUXSEL_MASK (7 << 11) -#define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) -#define CM_CTRL_LCDMUXSEL_VGA565_TFT555 (2 << 11) -#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) -#define CM_CTRL_LCDMUXSEL_VGA555_TFT555 (4 << 11) -#define CM_CTRL_LCDEN0 (1 << 14) -#define CM_CTRL_LCDEN1 (1 << 15) -#define CM_CTRL_STATIC1 (1 << 16) -#define CM_CTRL_STATIC2 (1 << 17) -#define CM_CTRL_STATIC (1 << 18) -#define CM_CTRL_n24BITEN (1 << 19) -#define CM_CTRL_EBIWP (1 << 20) diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h deleted file mode 100644 index f053aeebeb7a..000000000000 --- a/arch/arm/mach-integrator/common.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include -#include -extern struct amba_pl010_data ap_uart_data; -void integrator_init_early(void); -int integrator_init(bool is_cp); -void integrator_reserve(void); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c deleted file mode 100644 index 0fe5e1dc9d89..000000000000 --- a/arch/arm/mach-integrator/core.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-integrator/core.c - * - * Copyright (C) 2000-2003 Deep Blue Solutions Ltd - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "cm.h" -#include "common.h" - -static DEFINE_RAW_SPINLOCK(cm_lock); -static void __iomem *cm_base; - -/** - * cm_get - get the value from the CM_CTRL register - */ -u32 cm_get(void) -{ - return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); -} - -/** - * cm_control - update the CM_CTRL register. - * @mask: bits to change - * @set: bits to set - */ -void cm_control(u32 mask, u32 set) -{ - unsigned long flags; - u32 val; - - raw_spin_lock_irqsave(&cm_lock, flags); - val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; - writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); - raw_spin_unlock_irqrestore(&cm_lock, flags); -} - -void cm_clear_irqs(void) -{ - /* disable core module IRQs */ - writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + - IRQ_ENABLE_CLEAR); -} - -static const struct of_device_id cm_match[] = { - { .compatible = "arm,core-module-integrator"}, - { }, -}; - -void cm_init(void) -{ - struct device_node *cm = of_find_matching_node(NULL, cm_match); - - if (!cm) { - pr_crit("no core module node found in device tree\n"); - return; - } - cm_base = of_iomap(cm, 0); - if (!cm_base) { - pr_crit("could not remap core module\n"); - return; - } - cm_clear_irqs(); -} - -/* - * We need to stop things allocating the low memory; ideally we need a - * better implementation of GFP_DMA which does not assume that DMA-able - * memory starts at zero. - */ -void __init integrator_reserve(void) -{ - memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); -} diff --git a/arch/arm/mach-integrator/hardware.h b/arch/arm/mach-integrator/hardware.h deleted file mode 100644 index 81ce09e3ad45..000000000000 --- a/arch/arm/mach-integrator/hardware.h +++ /dev/null @@ -1,336 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * This file contains the hardware definitions of the Integrator. - * - * Copyright (C) 1998-1999 ARM Limited. - */ -#ifndef INTEGRATOR_HARDWARE_H -#define INTEGRATOR_HARDWARE_H - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xF0000000 // VA of IO -#define IO_SIZE 0x0B000000 // How much? -#define IO_START INTEGRATOR_HDR_BASE // PA of IO - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) -#define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) - -/* - * Integrator memory map - */ -#define INTEGRATOR_BOOT_ROM_LO 0x00000000 -#define INTEGRATOR_BOOT_ROM_HI 0x20000000 -#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ -#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K - -/* - * New Core Modules have different amounts of SSRAM, the amount of SSRAM - * fitted can be found in HDR_STAT. - * - * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to - * the minimum amount of SSRAM fitted on any core module. - * - * New Core Modules also alias the SSRAM. - * - */ -#define INTEGRATOR_SSRAM_BASE 0x00000000 -#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 -#define INTEGRATOR_SSRAM_SIZE SZ_256K - -#define INTEGRATOR_FLASH_BASE 0x24000000 -#define INTEGRATOR_FLASH_SIZE SZ_32M - -#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 -#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K - -/* - * SDRAM is a SIMM therefore the size is not known. - */ -#define INTEGRATOR_SDRAM_BASE 0x00040000 - -#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 -#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 -#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 -#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 - -/* - * Logic expansion modules - * - */ -#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 -#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 -#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 -#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 -#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 - -/* - * Integrator header card registers - */ -#define INTEGRATOR_HDR_ID_OFFSET 0x00 -#define INTEGRATOR_HDR_PROC_OFFSET 0x04 -#define INTEGRATOR_HDR_OSC_OFFSET 0x08 -#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C -#define INTEGRATOR_HDR_STAT_OFFSET 0x10 -#define INTEGRATOR_HDR_LOCK_OFFSET 0x14 -#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 -#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ -#define INTEGRATOR_HDR_IC_OFFSET 0x40 -#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 -#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 - -#define INTEGRATOR_HDR_BASE 0x10000000 -#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) -#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) -#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) -#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) -#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) -#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) -#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) -#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) -#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) -#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) -#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) - -#define INTEGRATOR_HDR_CTRL_LED 0x01 -#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 -#define INTEGRATOR_HDR_CTRL_REMAP 0x04 -#define INTEGRATOR_HDR_CTRL_RESET 0x08 -#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 -#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 -#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 -#define INTEGRATOR_HDR_CTRL_SYNC 0x80 - -#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 -#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 -#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C -#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 -#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 -#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B -#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 -#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 -#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A -#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F -#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 -#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 -#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E -#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 -#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 -#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D -#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 -#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 -#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C -#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 -#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 -#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B -#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 -#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 -#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A -#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F -#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 -#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 -#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E -#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 -#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 -#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF - -#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 -#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 -#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 -#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 -#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 -#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 -#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 -#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 -#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 -#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 -#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 - -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 -#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 -#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 - -#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) - -/* - * Integrator system registers - */ - -/* - * System Controller - */ -#define INTEGRATOR_SC_ID_OFFSET 0x00 -#define INTEGRATOR_SC_OSC_OFFSET 0x04 -#define INTEGRATOR_SC_CTRLS_OFFSET 0x08 -#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C -#define INTEGRATOR_SC_DEC_OFFSET 0x10 -#define INTEGRATOR_SC_ARB_OFFSET 0x14 -#define INTEGRATOR_SC_LOCK_OFFSET 0x1C - -#define INTEGRATOR_SC_BASE 0x11000000 -#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) -#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) -#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) -#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) -#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) -#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) -#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) -#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) - -#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 -#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 -#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 -#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C -#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C -#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF - -#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 -#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 -#define INTEGRATOR_SC_OSC_PCI_MASK 0x100 - -#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) -#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) -#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) -#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) -#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) -#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) -#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) - -/* - * External Bus Interface - */ -#define INTEGRATOR_EBI_BASE 0x12000000 - -#define INTEGRATOR_EBI_CSR0_OFFSET 0x00 -#define INTEGRATOR_EBI_CSR1_OFFSET 0x04 -#define INTEGRATOR_EBI_CSR2_OFFSET 0x08 -#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C -#define INTEGRATOR_EBI_LOCK_OFFSET 0x20 - -#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) -#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) -#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) -#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) -#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) - -#define INTEGRATOR_EBI_8_BIT 0x00 -#define INTEGRATOR_EBI_16_BIT 0x01 -#define INTEGRATOR_EBI_32_BIT 0x02 -#define INTEGRATOR_EBI_WRITE_ENABLE 0x04 -#define INTEGRATOR_EBI_SYNC 0x08 -#define INTEGRATOR_EBI_WS_2 0x00 -#define INTEGRATOR_EBI_WS_3 0x10 -#define INTEGRATOR_EBI_WS_4 0x20 -#define INTEGRATOR_EBI_WS_5 0x30 -#define INTEGRATOR_EBI_WS_6 0x40 -#define INTEGRATOR_EBI_WS_7 0x50 -#define INTEGRATOR_EBI_WS_8 0x60 -#define INTEGRATOR_EBI_WS_9 0x70 -#define INTEGRATOR_EBI_WS_10 0x80 -#define INTEGRATOR_EBI_WS_11 0x90 -#define INTEGRATOR_EBI_WS_12 0xA0 -#define INTEGRATOR_EBI_WS_13 0xB0 -#define INTEGRATOR_EBI_WS_14 0xC0 -#define INTEGRATOR_EBI_WS_15 0xD0 -#define INTEGRATOR_EBI_WS_16 0xE0 -#define INTEGRATOR_EBI_WS_17 0xF0 - - -#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ -#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ -#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ -#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ -#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ -#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ -#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ - -/* - * LED's & Switches - */ -#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 -#define INTEGRATOR_DBG_LEDS_OFFSET 0x04 -#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 - -#define INTEGRATOR_DBG_BASE 0x1A000000 -#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) -#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) -#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) - -#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ - -#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ -#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ -#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ -#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ -#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ -#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ - -/* PS2 Keyboard interface */ -#define KMI0_BASE INTEGRATOR_KBD_BASE - -/* PS2 Mouse interface */ -#define KMI1_BASE INTEGRATOR_MOUSE_BASE - -/* - * Integrator Interrupt Controllers - * - * - * Offsets from interrupt controller base - * - * System Controller interrupt controller base is - * - * INTEGRATOR_IC_BASE + (header_number << 6) - * - * Core Module interrupt controller base is - * - * INTEGRATOR_HDR_IC - */ -#define IRQ_STATUS 0 -#define IRQ_RAW_STATUS 0x04 -#define IRQ_ENABLE 0x08 -#define IRQ_ENABLE_SET 0x08 -#define IRQ_ENABLE_CLEAR 0x0C - -#define INT_SOFT_SET 0x10 -#define INT_SOFT_CLEAR 0x14 - -#define FIQ_STATUS 0x20 -#define FIQ_RAW_STATUS 0x24 -#define FIQ_ENABLE 0x28 -#define FIQ_ENABLE_SET 0x28 -#define FIQ_ENABLE_CLEAR 0x2C - - -/* - * LED's - */ -#define GREEN_LED 0x01 -#define YELLOW_LED 0x02 -#define RED_LED 0x04 -#define GREEN_LED_2 0x08 -#define ALL_LEDS 0x0F - -#define LED_BANK INTEGRATOR_DBG_LEDS - -/* - * Timer definitions - * - * Only use timer 1 & 2 - * (both run at 24MHz and will need the clock divider set to 16). - * - * Timer 0 runs at bus frequency - */ -#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE -#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) -#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) - -#define INTEGRATOR_CSR_BASE 0x10000000 -#define INTEGRATOR_CSR_SIZE 0x10000000 - -#endif /* INTEGRATOR_HARDWARE_H */ diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c deleted file mode 100644 index 58b02cbbea72..000000000000 --- a/arch/arm/mach-integrator/integrator_ap.c +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * linux/arch/arm/mach-integrator/integrator_ap.c - * - * Copyright (C) 2000-2003 Deep Blue Solutions Ltd - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "cm.h" -#include "common.h" - -/* Regmap to the AP system controller */ -static struct regmap *ap_syscon_map; - -/* - * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx - * is the (PA >> 12). - * - * Setup a VA for the Integrator interrupt controller (for header #0, - * just for now). - */ -#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) - -/* - * Logical Physical - * f1400000 14000000 Interrupt controller - * f1600000 16000000 UART 0 - */ - -static struct map_desc ap_io_desc[] __initdata __maybe_unused = { - { - .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE - } -}; - -static void __init ap_map_io(void) -{ - iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); -} - -#ifdef CONFIG_PM -static unsigned long ic_irq_enable; - -static int irq_suspend(void) -{ - ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); - return 0; -} - -static void irq_resume(void) -{ - /* disable all irq sources */ - cm_clear_irqs(); - writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); - writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); - - writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); -} -#else -#define irq_suspend NULL -#define irq_resume NULL -#endif - -static struct syscore_ops irq_syscore_ops = { - .suspend = irq_suspend, - .resume = irq_resume, -}; - -static int __init irq_syscore_init(void) -{ - register_syscore_ops(&irq_syscore_ops); - - return 0; -} - -device_initcall(irq_syscore_init); - -/* - * For the PL010 found in the Integrator/AP some of the UART control is - * implemented in the system controller and accessed using a callback - * from the driver. - */ -static void integrator_uart_set_mctrl(struct amba_device *dev, - void __iomem *base, unsigned int mctrl) -{ - unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; - u32 phybase = dev->res.start; - int ret; - - if (phybase == INTEGRATOR_UART0_BASE) { - /* UART0 */ - rts_mask = 1 << 4; - dtr_mask = 1 << 5; - } else { - /* UART1 */ - rts_mask = 1 << 6; - dtr_mask = 1 << 7; - } - - if (mctrl & TIOCM_RTS) - ctrlc |= rts_mask; - else - ctrls |= rts_mask; - - if (mctrl & TIOCM_DTR) - ctrlc |= dtr_mask; - else - ctrls |= dtr_mask; - - ret = regmap_write(ap_syscon_map, - INTEGRATOR_SC_CTRLS_OFFSET, - ctrls); - if (ret) - pr_err("MODEM: unable to write PL010 UART CTRLS\n"); - - ret = regmap_write(ap_syscon_map, - INTEGRATOR_SC_CTRLC_OFFSET, - ctrlc); - if (ret) - pr_err("MODEM: unable to write PL010 UART CRTLC\n"); -} - -struct amba_pl010_data ap_uart_data = { - .set_mctrl = integrator_uart_set_mctrl, -}; - -void __init ap_init_early(void) -{ -} - -static void __init ap_init_irq_of(void) -{ - cm_init(); - irqchip_init(); -} - -/* For the Device Tree, add in the UART callbacks as AUXDATA */ -static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, - "uart0", &ap_uart_data), - OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, - "uart1", &ap_uart_data), - { /* sentinel */ }, -}; - -static const struct of_device_id ap_syscon_match[] = { - { .compatible = "arm,integrator-ap-syscon"}, - { }, -}; - -static void __init ap_init_of(void) -{ - struct device_node *syscon; - - of_platform_default_populate(NULL, ap_auxdata_lookup, NULL); - - syscon = of_find_matching_node(NULL, ap_syscon_match); - if (!syscon) - return; - ap_syscon_map = syscon_node_to_regmap(syscon); - if (IS_ERR(ap_syscon_map)) { - pr_crit("could not find Integrator/AP system controller\n"); - return; - } -} - -static const char * ap_dt_board_compat[] = { - "arm,integrator-ap", - NULL, -}; - -DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") - .reserve = integrator_reserve, - .map_io = ap_map_io, - .init_early = ap_init_early, - .init_irq = ap_init_irq_of, - .init_machine = ap_init_of, - .dt_compat = ap_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c deleted file mode 100644 index b7eb4038798b..000000000000 --- a/arch/arm/mach-integrator/integrator_cp.c +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-integrator/integrator_cp.c - * - * Copyright (C) 2003 Deep Blue Solutions Ltd - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "cm.h" -#include "common.h" - -/* Base address to the core module header */ -static struct regmap *cm_map; -/* Base address to the CP controller */ -static void __iomem *intcp_con_base; - -#define CM_COUNTER_OFFSET 0x28 - -/* - * Logical Physical - * f1400000 14000000 Interrupt controller - * f1600000 16000000 UART 0 - * fca00000 ca000000 SIC - */ - -static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { - { - .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - } -}; - -static void __init intcp_map_io(void) -{ - iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); -} - -/* - * It seems that the card insertion interrupt remains active after - * we've acknowledged it. We therefore ignore the interrupt, and - * rely on reading it from the SIC. This also means that we must - * clear the latched interrupt. - */ -static unsigned int mmc_status(struct device *dev) -{ - unsigned int status = readl(__io_address(0xca000000 + 4)); - writel(8, intcp_con_base + 8); - - return status & 8; -} - -static struct mmci_platform_data mmc_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .status = mmc_status, -}; - -static u64 notrace intcp_read_sched_clock(void) -{ - unsigned int val; - - /* MMIO so discard return code */ - regmap_read(cm_map, CM_COUNTER_OFFSET, &val); - return val; -} - -static void __init intcp_init_early(void) -{ - cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator"); - if (IS_ERR(cm_map)) - return; - sched_clock_register(intcp_read_sched_clock, 32, 24000000); -} - -static void __init intcp_init_irq_of(void) -{ - cm_init(); - irqchip_init(); -} - -/* - * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA - * and enforce the bus names since these are used for clock lookups. - */ -static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE, - "mmci", &mmc_data), - { /* sentinel */ }, -}; - -static const struct of_device_id intcp_syscon_match[] = { - { .compatible = "arm,integrator-cp-syscon"}, - { }, -}; - -static void __init intcp_init_of(void) -{ - struct device_node *cpcon; - - cpcon = of_find_matching_node(NULL, intcp_syscon_match); - if (!cpcon) - return; - - intcp_con_base = of_iomap(cpcon, 0); - if (!intcp_con_base) - return; - - of_platform_default_populate(NULL, intcp_auxdata_lookup, NULL); -} - -static const char * intcp_dt_board_compat[] = { - "arm,integrator-cp", - NULL, -}; - -DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") - .reserve = integrator_reserve, - .map_io = intcp_map_io, - .init_early = intcp_init_early, - .init_irq = intcp_init_irq_of, - .init_machine = intcp_init_of, - .dt_compat = intcp_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig deleted file mode 100644 index a4c36024b5e8..000000000000 --- a/arch/arm/mach-realview/Kconfig +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menuconfig ARCH_REALVIEW - bool "ARM Ltd. RealView family" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 - select ARM_AMBA - select ARM_GIC - select ARM_TIMER_SP804 - select CLK_SP810 - select GPIO_PL061 if GPIOLIB - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select HAVE_PATA_PLATFORM - select HAVE_TCM - select CLK_ICST - select MACH_REALVIEW_EB if ARCH_MULTI_V5 - select MFD_SYSCON - select PLAT_VERSATILE - select POWER_RESET - select POWER_RESET_VERSATILE - select POWER_SUPPLY - select SOC_REALVIEW - help - This enables support for ARM Ltd RealView boards. - -if ARCH_REALVIEW - -config MACH_REALVIEW_EB - bool "Support RealView(R) Emulation Baseboard" - select ARM_GIC - select CPU_ARM926T if ARCH_MULTI_V5 - help - Include support for the ARM(R) RealView(R) Emulation Baseboard - platform. On an ARMv5 kernel, this will include support for - the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least - one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore - core tile options should be enabled. - -config REALVIEW_EB_ARM1136 - bool "Support ARM1136J(F)-S Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 - select CPU_V6 - help - Enable support for the ARM1136 tile fitted to the - Realview(R) Emulation Baseboard platform. - -config REALVIEW_EB_ARM1176 - bool "Support ARM1176JZ(F)-S Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 - help - Enable support for the ARM1176 tile fitted to the - Realview(R) Emulation Baseboard platform. - -config REALVIEW_EB_A9MP - bool "Support Multicore Cortex-A9 Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V7 - help - Enable support for the Cortex-A9MPCore tile fitted to the - Realview(R) Emulation Baseboard platform. - -config REALVIEW_EB_ARM11MP - bool "Support ARM11MPCore Tile" - depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 - select HAVE_SMP - help - Enable support for the ARM11MPCore tile fitted to the Realview(R) - Emulation Baseboard platform. - -config MACH_REALVIEW_PB11MP - bool "Support RealView(R) Platform Baseboard for ARM11MPCore" - depends on ARCH_MULTI_V6 - select HAVE_SMP - help - Include support for the ARM(R) RealView(R) Platform Baseboard for - the ARM11MPCore. This platform has an on-board ARM11MPCore and has - support for PCI-E and Compact Flash. - -# ARMv6 CPU without K extensions, but does have the new exclusive ops -config MACH_REALVIEW_PB1176 - bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" - depends on ARCH_MULTI_V6 - select CPU_V6 - select HAVE_TCM - help - Include support for the ARM(R) RealView(R) Platform Baseboard for - ARM1176JZF-S. - -config MACH_REALVIEW_PBA8 - bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" - depends on ARCH_MULTI_V7 - help - Include support for the ARM(R) RealView Platform Baseboard for - Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has - support for PCI-E and Compact Flash. - -config MACH_REALVIEW_PBX - bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9" - depends on ARCH_MULTI_V7 - select ZONE_DMA - help - Include support for the ARM(R) RealView(R) Platform Baseboard - Explore. - -endif diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile deleted file mode 100644 index e259091591b8..000000000000 --- a/arch/arm/mach-realview/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux kernel. -# -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-versatile/include - -obj-y += realview-dt.o -obj-$(CONFIG_SMP) += platsmp-dt.o diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c deleted file mode 100644 index 5ae783767a5d..000000000000 --- a/arch/arm/mach-realview/platsmp-dt.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 Linus Walleij - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 - -static const struct of_device_id realview_scu_match[] = { - { .compatible = "arm,arm11mp-scu", }, - { .compatible = "arm,cortex-a9-scu", }, - { .compatible = "arm,cortex-a5-scu", }, - { } -}; - -static const struct of_device_id realview_syscon_match[] = { - { .compatible = "arm,core-module-integrator", }, - { .compatible = "arm,realview-eb-syscon", }, - { .compatible = "arm,realview-pb11mp-syscon", }, - { .compatible = "arm,realview-pbx-syscon", }, - { }, -}; - -static void __init realview_smp_prepare_cpus(unsigned int max_cpus) -{ - struct device_node *np; - void __iomem *scu_base; - struct regmap *map; - unsigned int ncores; - int i; - - np = of_find_matching_node(NULL, realview_scu_match); - if (!np) { - pr_err("PLATSMP: No SCU base address\n"); - return; - } - scu_base = of_iomap(np, 0); - of_node_put(np); - if (!scu_base) { - pr_err("PLATSMP: No SCU remap\n"); - return; - } - - scu_enable(scu_base); - ncores = scu_get_core_count(scu_base); - pr_info("SCU: %d cores detected\n", ncores); - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - iounmap(scu_base); - - /* The syscon contains the magic SMP start address registers */ - np = of_find_matching_node(NULL, realview_syscon_match); - if (!np) { - pr_err("PLATSMP: No syscon match\n"); - return; - } - map = syscon_node_to_regmap(np); - if (IS_ERR(map)) { - pr_err("PLATSMP: No syscon regmap\n"); - return; - } - /* Put the boot address in this magic register */ - regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET, - __pa_symbol(versatile_secondary_startup)); -} - -#ifdef CONFIG_HOTPLUG_CPU -static void realview_cpu_die(unsigned int cpu) -{ - return versatile_immitation_cpu_die(cpu, 0x20); -} -#endif - -static const struct smp_operations realview_dt_smp_ops __initconst = { - .smp_prepare_cpus = realview_smp_prepare_cpus, - .smp_secondary_init = versatile_secondary_init, - .smp_boot_secondary = versatile_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = realview_cpu_die, -#endif -}; -CPU_METHOD_OF_DECLARE(realview_smp, "arm,realview-smp", &realview_dt_smp_ops); diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-realview/realview-dt.c deleted file mode 100644 index feab66080ba2..000000000000 --- a/arch/arm/mach-realview/realview-dt.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 Linaro Ltd. - * - * Author: Linus Walleij - */ -#include -#include -#include - -static const char *const realview_dt_platform_compat[] __initconst = { - "arm,realview-eb", - "arm,realview-pb1176", - "arm,realview-pb11mp", - "arm,realview-pba8", - "arm,realview-pbx", - NULL, -}; - -DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)") -#ifdef CONFIG_ZONE_DMA - .dma_zone_size = SZ_256M, -#endif - .dt_compat = realview_dt_platform_compat, - .l2c_aux_val = 0x0, - .l2c_aux_mask = ~0x0, -MACHINE_END diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index f78a1d358031..94b492c12e8d 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -16,3 +16,311 @@ config ARCH_VERSATILE help This enables support for ARM Ltd Versatile board. +menuconfig ARCH_INTEGRATOR + bool "ARM Ltd. Integrator family" + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 + select ARM_AMBA + select CMA + select DMA_CMA + select HAVE_TCM + select CLK_ICST + select MFD_SYSCON + select PLAT_VERSATILE + select POWER_RESET + select POWER_RESET_VERSATILE + select POWER_SUPPLY + select SOC_INTEGRATOR_CM + select VERSATILE_FPGA_IRQ + help + Support for ARM's Integrator platform. + +if ARCH_INTEGRATOR + +config ARCH_INTEGRATOR_AP + bool "Support Integrator/AP and Integrator/PP2 platforms" + select INTEGRATOR_AP_TIMER + select SERIAL_AMBA_PL010 if TTY + select SERIAL_AMBA_PL010_CONSOLE if TTY + select SOC_BUS + help + Include support for the ARM(R) Integrator/AP and + Integrator/PP2 platforms. + +config INTEGRATOR_IMPD1 + bool "Include support for Integrator/IM-PD1" + depends on ARCH_INTEGRATOR_AP + select ARM_VIC + select GPIO_PL061 + select GPIOLIB + select REGULATOR + select REGULATOR_FIXED_VOLTAGE + help + The IM-PD1 is an add-on logic module for the Integrator which + allows ARM(R) Ltd PrimeCells to be developed and evaluated. + The IM-PD1 can be found on the Integrator/PP2 platform. + +config INTEGRATOR_CM720T + bool "Integrator/CM720T core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V4T + select CPU_ARM720T + +config INTEGRATOR_CM920T + bool "Integrator/CM920T core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V4T + select CPU_ARM920T + +config INTEGRATOR_CM922T_XA10 + bool "Integrator/CM922T-XA10 core module" + depends on ARCH_MULTI_V4T + depends on ARCH_INTEGRATOR_AP + select CPU_ARM922T + +config INTEGRATOR_CM926EJS + bool "Integrator/CM926EJ-S core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V5 + select CPU_ARM926T + +config INTEGRATOR_CM10200E_REV0 + bool "Integrator/CM10200E rev.0 core module" + depends on ARCH_INTEGRATOR_AP && n + depends on ARCH_MULTI_V5 + select CPU_ARM1020 + +config INTEGRATOR_CM10200E + bool "Integrator/CM10200E core module" + depends on ARCH_INTEGRATOR_AP && n + depends on ARCH_MULTI_V5 + select CPU_ARM1020E + +config INTEGRATOR_CM10220E + bool "Integrator/CM10220E core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V5 + select CPU_ARM1022 + +config INTEGRATOR_CM1026EJS + bool "Integrator/CM1026EJ-S core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V5 + select CPU_ARM1026 + +config INTEGRATOR_CM1136JFS + bool "Integrator/CM1136JF-S core module" + depends on ARCH_INTEGRATOR_AP + depends on ARCH_MULTI_V6 + select CPU_V6 + +config ARCH_INTEGRATOR_CP + bool "Support Integrator/CP platform" + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + select ARM_TIMER_SP804 + select SERIAL_AMBA_PL011 if TTY + select SERIAL_AMBA_PL011_CONSOLE if TTY + select SOC_BUS + help + Include support for the ARM(R) Integrator CP platform. + +config INTEGRATOR_CT926 + bool "Integrator/CT926 (ARM926EJ-S) core tile" + depends on ARCH_INTEGRATOR_CP + depends on ARCH_MULTI_V5 + select CPU_ARM926T + +config INTEGRATOR_CTB36 + bool "Integrator/CTB36 (ARM1136JF-S) core tile" + depends on ARCH_INTEGRATOR_CP + depends on ARCH_MULTI_V6 + select CPU_V6 + +config ARCH_CINTEGRATOR + depends on ARCH_INTEGRATOR_CP + def_bool y + +endif + +menuconfig ARCH_REALVIEW + bool "ARM Ltd. RealView family" + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select ARM_TIMER_SP804 + select CLK_SP810 + select GPIO_PL061 if GPIOLIB + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select HAVE_PATA_PLATFORM + select HAVE_TCM + select CLK_ICST + select MACH_REALVIEW_EB if ARCH_MULTI_V5 + select MFD_SYSCON + select PLAT_VERSATILE + select POWER_RESET + select POWER_RESET_VERSATILE + select POWER_SUPPLY + select SOC_REALVIEW + help + This enables support for ARM Ltd RealView boards. + +if ARCH_REALVIEW + +config MACH_REALVIEW_EB + bool "Support RealView(R) Emulation Baseboard" + select ARM_GIC + select CPU_ARM926T if ARCH_MULTI_V5 + help + Include support for the ARM(R) RealView(R) Emulation Baseboard + platform. On an ARMv5 kernel, this will include support for + the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least + one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore + core tile options should be enabled. + +config REALVIEW_EB_ARM1136 + bool "Support ARM1136J(F)-S Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 + select CPU_V6 + help + Enable support for the ARM1136 tile fitted to the + Realview(R) Emulation Baseboard platform. + +config REALVIEW_EB_ARM1176 + bool "Support ARM1176JZ(F)-S Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 + help + Enable support for the ARM1176 tile fitted to the + Realview(R) Emulation Baseboard platform. + +config REALVIEW_EB_A9MP + bool "Support Multicore Cortex-A9 Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V7 + help + Enable support for the Cortex-A9MPCore tile fitted to the + Realview(R) Emulation Baseboard platform. + +config REALVIEW_EB_ARM11MP + bool "Support ARM11MPCore Tile" + depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 + select HAVE_SMP + help + Enable support for the ARM11MPCore tile fitted to the Realview(R) + Emulation Baseboard platform. + +config MACH_REALVIEW_PB11MP + bool "Support RealView(R) Platform Baseboard for ARM11MPCore" + depends on ARCH_MULTI_V6 + select HAVE_SMP + help + Include support for the ARM(R) RealView(R) Platform Baseboard for + the ARM11MPCore. This platform has an on-board ARM11MPCore and has + support for PCI-E and Compact Flash. + +# ARMv6 CPU without K extensions, but does have the new exclusive ops +config MACH_REALVIEW_PB1176 + bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S" + depends on ARCH_MULTI_V6 + select CPU_V6 + select HAVE_TCM + help + Include support for the ARM(R) RealView(R) Platform Baseboard for + ARM1176JZF-S. + +config MACH_REALVIEW_PBA8 + bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" + depends on ARCH_MULTI_V7 + help + Include support for the ARM(R) RealView Platform Baseboard for + Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has + support for PCI-E and Compact Flash. + +config MACH_REALVIEW_PBX + bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9" + depends on ARCH_MULTI_V7 + select ZONE_DMA + help + Include support for the ARM(R) RealView(R) Platform Baseboard + Explore. + +endif + +menuconfig ARCH_VEXPRESS + bool "ARM Ltd. Versatile Express family" + depends on ARCH_MULTI_V7 + select ARCH_SUPPORTS_BIG_ENDIAN + select ARM_AMBA + select ARM_GIC + select ARM_GLOBAL_TIMER + select ARM_TIMER_SP804 + select GPIOLIB + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select HAVE_PATA_PLATFORM + select CLK_ICST + select NO_IOPORT_MAP + select PLAT_VERSATILE + select POWER_RESET + select POWER_RESET_VEXPRESS + select POWER_SUPPLY + select REGULATOR if MMC_ARMMMCI + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select VEXPRESS_CONFIG + help + This option enables support for systems using Cortex processor based + ARM core and logic (FPGA) tiles on the Versatile Express motherboard, + for example: + + - CoreTile Express A5x2 (V2P-CA5s) + - CoreTile Express A9x4 (V2P-CA9) + - CoreTile Express A15x2 (V2P-CA15) + - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs + (Soft Macrocell Models) + - Versatile Express RTSMs (Models) + + You must boot using a Flattened Device Tree in order to use these + platforms. The traditional (ATAGs) boot method is not usable on + these boards with this option. + +if ARCH_VEXPRESS + +config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA + bool "Enable A5 and A9 only errata work-arounds" + default y + select ARM_ERRATA_643719 if SMP + select ARM_ERRATA_720789 + select PL310_ERRATA_753970 if CACHE_L2X0 + help + Provides common dependencies for Versatile Express platforms + based on Cortex-A5 and Cortex-A9 processors. In order to + build a working kernel, you must also enable relevant core + tile support or Flattened Device Tree based support options. + +config ARCH_VEXPRESS_DCSCB + bool "Dual Cluster System Control Block (DCSCB) support" + depends on MCPM + select ARM_CCI400_PORT_CTRL + help + Support for the Dual Cluster System Configuration Block (DCSCB). + This is needed to provide CPU and cluster power management + on RTSM implementing big.LITTLE. + +config ARCH_VEXPRESS_SPC + bool "Versatile Express Serial Power Controller (SPC)" + select PM_OPP + help + The TC2 (A15x2 A7x3) versatile express core tile integrates a logic + block called Serial Power Controller (SPC) that provides the interface + between the dual cluster test-chip and the M3 microcontroller that + carries out power management. + +config ARCH_VEXPRESS_TC2_PM + bool "Versatile Express TC2 power management" + depends on MCPM + select ARM_CCI400_PORT_CTRL + select ARCH_VEXPRESS_SPC + select ARM_CPU_SUSPEND + help + Support for CPU and cluster power management on Versatile Express + with a TC2 (A15x2 A7x3) big.LITTLE core tile. + +endif diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile index 2b907718d467..27d712bcf1af 100644 --- a/arch/arm/mach-versatile/Makefile +++ b/arch/arm/mach-versatile/Makefile @@ -3,4 +3,34 @@ # Makefile for the linux kernel. # -obj-y := versatile_dt.o +# versatile +obj-$(CONFIG_ARCH_VERSATILE) += versatile.o + +# integrator +obj-$(CONFIG_ARCH_INTEGRATOR) += integrator.o +obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o +obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o + +# realview +obj-$(CONFIG_ARCH_REALVIEW) += realview.o + +# vexpress +obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o +CFLAGS_dcscb.o += -march=armv7-a +CFLAGS_REMOVE_dcscb.o = -pg +obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o +CFLAGS_REMOVE_spc.o = -pg +obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o +CFLAGS_tc2_pm.o += -march=armv7-a +CFLAGS_REMOVE_tc2_pm.o = -pg + +# mps2 +obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o + +ifdef CONFIG_SMP +obj-y += headsmp.o platsmp.o +obj-$(CONFIG_ARCH_REALVIEW) += platsmp-realview.o +obj-$(CONFIG_ARCH_VEXPRESS) += platsmp-vexpress.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +endif diff --git a/arch/arm/mach-versatile/Makefile.boot b/arch/arm/mach-versatile/Makefile.boot new file mode 100644 index 000000000000..cec195d4fcba --- /dev/null +++ b/arch/arm/mach-versatile/Makefile.boot @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Empty file waiting for deletion once Makefile.boot isn't needed any more. +# Patch waits for application at +# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-versatile/dcscb.c b/arch/arm/mach-versatile/dcscb.c new file mode 100644 index 000000000000..866270e7f271 --- /dev/null +++ b/arch/arm/mach-versatile/dcscb.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dcscb.c - Dual Cluster System Configuration Block + * + * Created by: Nicolas Pitre, May 2012 + * Copyright: (C) 2012-2013 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "vexpress.h" + +#define RST_HOLD0 0x0 +#define RST_HOLD1 0x4 +#define SYS_SWRESET 0x8 +#define RST_STAT0 0xc +#define RST_STAT1 0x10 +#define EAG_CFG_R 0x20 +#define EAG_CFG_W 0x24 +#define KFC_CFG_R 0x28 +#define KFC_CFG_W 0x2c +#define DCS_CFG_R 0x30 + +static void __iomem *dcscb_base; +static int dcscb_allcpus_mask[2]; + +static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster) +{ + unsigned int rst_hold, cpumask = (1 << cpu); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster])) + return -EINVAL; + + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold &= ~(cpumask | (cpumask << 4)); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + return 0; +} + +static int dcscb_cluster_powerup(unsigned int cluster) +{ + unsigned int rst_hold; + + pr_debug("%s: cluster %u\n", __func__, cluster); + if (cluster >= 2) + return -EINVAL; + + /* remove cluster reset and add individual CPU's reset */ + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold &= ~(1 << 8); + rst_hold |= dcscb_allcpus_mask[cluster]; + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + return 0; +} + +static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) +{ + unsigned int rst_hold; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster])); + + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold |= (1 << cpu); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); +} + +static void dcscb_cluster_powerdown_prepare(unsigned int cluster) +{ + unsigned int rst_hold; + + pr_debug("%s: cluster %u\n", __func__, cluster); + BUG_ON(cluster >= 2); + + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold |= (1 << 8); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); +} + +static void dcscb_cpu_cache_disable(void) +{ + /* Disable and flush the local CPU cache. */ + v7_exit_coherency_flush(louis); +} + +static void dcscb_cluster_cache_disable(void) +{ + /* Flush all cache levels for this cluster. */ + v7_exit_coherency_flush(all); + + /* + * A full outer cache flush could be needed at this point + * on platforms with such a cache, depending on where the + * outer cache sits. In some cases the notion of a "last + * cluster standing" would need to be implemented if the + * outer cache is shared across clusters. In any case, when + * the outer cache needs flushing, there is no concurrent + * access to the cache controller to worry about and no + * special locking besides what is already provided by the + * MCPM state machinery is needed. + */ + + /* + * Disable cluster-level coherency by masking + * incoming snoops and DVM messages: + */ + cci_disable_port_by_cpu(read_cpuid_mpidr()); +} + +static const struct mcpm_platform_ops dcscb_power_ops = { + .cpu_powerup = dcscb_cpu_powerup, + .cluster_powerup = dcscb_cluster_powerup, + .cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare, + .cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare, + .cpu_cache_disable = dcscb_cpu_cache_disable, + .cluster_cache_disable = dcscb_cluster_cache_disable, +}; + +extern void dcscb_power_up_setup(unsigned int affinity_level); + +static int __init dcscb_init(void) +{ + struct device_node *node; + unsigned int cfg; + int ret; + + if (!cci_probed()) + return -ENODEV; + + node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); + if (!node) + return -ENODEV; + dcscb_base = of_iomap(node, 0); + if (!dcscb_base) + return -EADDRNOTAVAIL; + cfg = readl_relaxed(dcscb_base + DCS_CFG_R); + dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; + dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; + + ret = mcpm_platform_register(&dcscb_power_ops); + if (!ret) + ret = mcpm_sync_init(dcscb_power_up_setup); + if (ret) { + iounmap(dcscb_base); + return ret; + } + + pr_info("VExpress DCSCB support installed\n"); + + /* + * Future entries into the kernel can now go + * through the cluster entry vectors. + */ + vexpress_flags_set(__pa_symbol(mcpm_entry_point)); + + return 0; +} + +early_initcall(dcscb_init); diff --git a/arch/arm/mach-versatile/dcscb_setup.S b/arch/arm/mach-versatile/dcscb_setup.S new file mode 100644 index 000000000000..92d1fd9d7f6a --- /dev/null +++ b/arch/arm/mach-versatile/dcscb_setup.S @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Created by: Dave Martin, 2012-06-22 + * Copyright: (C) 2012-2013 Linaro Limited + */ + +#include + + +ENTRY(dcscb_power_up_setup) + + cmp r0, #0 @ check affinity level + beq 2f + +/* + * Enable cluster-level coherency, in preparation for turning on the MMU. + * The ACTLR SMP bit does not need to be set here, because cpu_resume() + * already restores that. + * + * A15/A7 may not require explicit L2 invalidation on reset, dependent + * on hardware integration decisions. + * For now, this code assumes that L2 is either already invalidated, + * or invalidation is not required. + */ + + b cci_enable_port_for_self + +2: @ Implementation-specific local CPU setup operations should go here, + @ if any. In this case, there is nothing to do. + + bx lr + +ENDPROC(dcscb_power_up_setup) diff --git a/arch/arm/mach-versatile/headsmp.S b/arch/arm/mach-versatile/headsmp.S new file mode 100644 index 000000000000..99c32db412ae --- /dev/null +++ b/arch/arm/mach-versatile/headsmp.S @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + */ +#include +#include +#include + +/* + * Realview/Versatile Express specific entry point for secondary CPUs. + * This provides a "holding pen" into which all secondary cores are held + * until we're ready for them to initialise. + */ +ENTRY(versatile_secondary_startup) + ARM_BE8(setend be) + mrc p15, 0, r0, c0, c0, 5 + bic r0, #0xff000000 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long versatile_cpu_release +ENDPROC(versatile_secondary_startup) diff --git a/arch/arm/mach-versatile/hotplug.c b/arch/arm/mach-versatile/hotplug.c new file mode 100644 index 000000000000..5a152175578b --- /dev/null +++ b/arch/arm/mach-versatile/hotplug.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This hotplug implementation is _specific_ to the situation found on + * ARM development platforms where there is _no_ possibility of actually + * taking a CPU offline, resetting it, or otherwise. Real platforms must + * NOT copy this code. + */ +#include +#include +#include + +#include +#include + +#include "platsmp.h" + +static inline void versatile_immitation_enter_lowpower(unsigned int actrl_mask) +{ + unsigned int v; + + asm volatile( + "mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %3\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C), "Ir" (actrl_mask) + : "cc"); +} + +static inline void versatile_immitation_leave_lowpower(unsigned int actrl_mask) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (actrl_mask) + : "cc"); +} + +static inline void versatile_immitation_do_lowpower(unsigned int cpu, int *spurious) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts. + * + * This code should not be used outside Versatile platforms. + */ + for (;;) { + wfi(); + + if (versatile_cpu_release == cpu_logical_map(cpu)) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +/* + * platform-specific code to shutdown a CPU. + * This code supports immitation-style CPU hotplug for Versatile/Realview/ + * Versatile Express platforms that are unable to do real CPU hotplug. + */ +void versatile_immitation_cpu_die(unsigned int cpu, unsigned int actrl_mask) +{ + int spurious = 0; + + versatile_immitation_enter_lowpower(actrl_mask); + versatile_immitation_do_lowpower(cpu, &spurious); + versatile_immitation_leave_lowpower(actrl_mask); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} diff --git a/arch/arm/mach-versatile/integrator-cm.h b/arch/arm/mach-versatile/integrator-cm.h new file mode 100644 index 000000000000..f09ea18a50f8 --- /dev/null +++ b/arch/arm/mach-versatile/integrator-cm.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * access the core module control register. + */ +u32 cm_get(void); +void cm_control(u32, u32); + +struct device_node; +void cm_init(void); +void cm_clear_irqs(void); + +#define CM_CTRL_LED (1 << 0) +#define CM_CTRL_nMBDET (1 << 1) +#define CM_CTRL_REMAP (1 << 2) + +/* + * Integrator/AP,PP2 specific + */ +#define CM_CTRL_HIGHVECTORS (1 << 4) +#define CM_CTRL_BIGENDIAN (1 << 5) +#define CM_CTRL_FASTBUS (1 << 6) +#define CM_CTRL_SYNC (1 << 7) + +/* + * ARM926/946/966 Integrator/CP specific + */ +#define CM_CTRL_LCDBIASEN (1 << 8) +#define CM_CTRL_LCDBIASUP (1 << 9) +#define CM_CTRL_LCDBIASDN (1 << 10) +#define CM_CTRL_LCDMUXSEL_MASK (7 << 11) +#define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) +#define CM_CTRL_LCDMUXSEL_VGA565_TFT555 (2 << 11) +#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) +#define CM_CTRL_LCDMUXSEL_VGA555_TFT555 (4 << 11) +#define CM_CTRL_LCDEN0 (1 << 14) +#define CM_CTRL_LCDEN1 (1 << 15) +#define CM_CTRL_STATIC1 (1 << 16) +#define CM_CTRL_STATIC2 (1 << 17) +#define CM_CTRL_STATIC (1 << 18) +#define CM_CTRL_n24BITEN (1 << 19) +#define CM_CTRL_EBIWP (1 << 20) diff --git a/arch/arm/mach-versatile/integrator-hardware.h b/arch/arm/mach-versatile/integrator-hardware.h new file mode 100644 index 000000000000..81ce09e3ad45 --- /dev/null +++ b/arch/arm/mach-versatile/integrator-hardware.h @@ -0,0 +1,336 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * This file contains the hardware definitions of the Integrator. + * + * Copyright (C) 1998-1999 ARM Limited. + */ +#ifndef INTEGRATOR_HARDWARE_H +#define INTEGRATOR_HARDWARE_H + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ +#define IO_BASE 0xF0000000 // VA of IO +#define IO_SIZE 0x0B000000 // How much? +#define IO_START INTEGRATOR_HDR_BASE // PA of IO + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) +#define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) + +/* + * Integrator memory map + */ +#define INTEGRATOR_BOOT_ROM_LO 0x00000000 +#define INTEGRATOR_BOOT_ROM_HI 0x20000000 +#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ +#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K + +/* + * New Core Modules have different amounts of SSRAM, the amount of SSRAM + * fitted can be found in HDR_STAT. + * + * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to + * the minimum amount of SSRAM fitted on any core module. + * + * New Core Modules also alias the SSRAM. + * + */ +#define INTEGRATOR_SSRAM_BASE 0x00000000 +#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 +#define INTEGRATOR_SSRAM_SIZE SZ_256K + +#define INTEGRATOR_FLASH_BASE 0x24000000 +#define INTEGRATOR_FLASH_SIZE SZ_32M + +#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 +#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K + +/* + * SDRAM is a SIMM therefore the size is not known. + */ +#define INTEGRATOR_SDRAM_BASE 0x00040000 + +#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 +#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 +#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 +#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 + +/* + * Logic expansion modules + * + */ +#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 +#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 +#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 +#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 +#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 + +/* + * Integrator header card registers + */ +#define INTEGRATOR_HDR_ID_OFFSET 0x00 +#define INTEGRATOR_HDR_PROC_OFFSET 0x04 +#define INTEGRATOR_HDR_OSC_OFFSET 0x08 +#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C +#define INTEGRATOR_HDR_STAT_OFFSET 0x10 +#define INTEGRATOR_HDR_LOCK_OFFSET 0x14 +#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 +#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ +#define INTEGRATOR_HDR_IC_OFFSET 0x40 +#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 +#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 + +#define INTEGRATOR_HDR_BASE 0x10000000 +#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) +#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) +#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) +#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) +#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) +#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) +#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) +#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) +#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) +#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) +#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) + +#define INTEGRATOR_HDR_CTRL_LED 0x01 +#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 +#define INTEGRATOR_HDR_CTRL_REMAP 0x04 +#define INTEGRATOR_HDR_CTRL_RESET 0x08 +#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 +#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 +#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 +#define INTEGRATOR_HDR_CTRL_SYNC 0x80 + +#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 +#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 +#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C +#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 +#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 +#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B +#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 +#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 +#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A +#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F +#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 +#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 +#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E +#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 +#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 +#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D +#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 +#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 +#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C +#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 +#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 +#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B +#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 +#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 +#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A +#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F +#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 +#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 +#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E +#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 +#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 +#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF + +#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 +#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 +#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 +#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 +#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 +#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 +#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 +#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 +#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 +#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 +#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 + +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 +#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 +#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 + +#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) + +/* + * Integrator system registers + */ + +/* + * System Controller + */ +#define INTEGRATOR_SC_ID_OFFSET 0x00 +#define INTEGRATOR_SC_OSC_OFFSET 0x04 +#define INTEGRATOR_SC_CTRLS_OFFSET 0x08 +#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C +#define INTEGRATOR_SC_DEC_OFFSET 0x10 +#define INTEGRATOR_SC_ARB_OFFSET 0x14 +#define INTEGRATOR_SC_LOCK_OFFSET 0x1C + +#define INTEGRATOR_SC_BASE 0x11000000 +#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) +#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) +#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) +#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) +#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) +#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) +#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) +#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) + +#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 +#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 +#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 +#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C +#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C +#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF + +#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 +#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 +#define INTEGRATOR_SC_OSC_PCI_MASK 0x100 + +#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) +#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) +#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) +#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) +#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) +#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) +#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) + +/* + * External Bus Interface + */ +#define INTEGRATOR_EBI_BASE 0x12000000 + +#define INTEGRATOR_EBI_CSR0_OFFSET 0x00 +#define INTEGRATOR_EBI_CSR1_OFFSET 0x04 +#define INTEGRATOR_EBI_CSR2_OFFSET 0x08 +#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C +#define INTEGRATOR_EBI_LOCK_OFFSET 0x20 + +#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) +#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) +#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) +#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) +#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) + +#define INTEGRATOR_EBI_8_BIT 0x00 +#define INTEGRATOR_EBI_16_BIT 0x01 +#define INTEGRATOR_EBI_32_BIT 0x02 +#define INTEGRATOR_EBI_WRITE_ENABLE 0x04 +#define INTEGRATOR_EBI_SYNC 0x08 +#define INTEGRATOR_EBI_WS_2 0x00 +#define INTEGRATOR_EBI_WS_3 0x10 +#define INTEGRATOR_EBI_WS_4 0x20 +#define INTEGRATOR_EBI_WS_5 0x30 +#define INTEGRATOR_EBI_WS_6 0x40 +#define INTEGRATOR_EBI_WS_7 0x50 +#define INTEGRATOR_EBI_WS_8 0x60 +#define INTEGRATOR_EBI_WS_9 0x70 +#define INTEGRATOR_EBI_WS_10 0x80 +#define INTEGRATOR_EBI_WS_11 0x90 +#define INTEGRATOR_EBI_WS_12 0xA0 +#define INTEGRATOR_EBI_WS_13 0xB0 +#define INTEGRATOR_EBI_WS_14 0xC0 +#define INTEGRATOR_EBI_WS_15 0xD0 +#define INTEGRATOR_EBI_WS_16 0xE0 +#define INTEGRATOR_EBI_WS_17 0xF0 + + +#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ +#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ +#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ +#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ +#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ +#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ +#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ + +/* + * LED's & Switches + */ +#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 +#define INTEGRATOR_DBG_LEDS_OFFSET 0x04 +#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 + +#define INTEGRATOR_DBG_BASE 0x1A000000 +#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) +#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) +#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) + +#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ + +#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ +#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ +#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ +#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ +#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ +#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ + +/* PS2 Keyboard interface */ +#define KMI0_BASE INTEGRATOR_KBD_BASE + +/* PS2 Mouse interface */ +#define KMI1_BASE INTEGRATOR_MOUSE_BASE + +/* + * Integrator Interrupt Controllers + * + * + * Offsets from interrupt controller base + * + * System Controller interrupt controller base is + * + * INTEGRATOR_IC_BASE + (header_number << 6) + * + * Core Module interrupt controller base is + * + * INTEGRATOR_HDR_IC + */ +#define IRQ_STATUS 0 +#define IRQ_RAW_STATUS 0x04 +#define IRQ_ENABLE 0x08 +#define IRQ_ENABLE_SET 0x08 +#define IRQ_ENABLE_CLEAR 0x0C + +#define INT_SOFT_SET 0x10 +#define INT_SOFT_CLEAR 0x14 + +#define FIQ_STATUS 0x20 +#define FIQ_RAW_STATUS 0x24 +#define FIQ_ENABLE 0x28 +#define FIQ_ENABLE_SET 0x28 +#define FIQ_ENABLE_CLEAR 0x2C + + +/* + * LED's + */ +#define GREEN_LED 0x01 +#define YELLOW_LED 0x02 +#define RED_LED 0x04 +#define GREEN_LED_2 0x08 +#define ALL_LEDS 0x0F + +#define LED_BANK INTEGRATOR_DBG_LEDS + +/* + * Timer definitions + * + * Only use timer 1 & 2 + * (both run at 24MHz and will need the clock divider set to 16). + * + * Timer 0 runs at bus frequency + */ +#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE +#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) +#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) + +#define INTEGRATOR_CSR_BASE 0x10000000 +#define INTEGRATOR_CSR_SIZE 0x10000000 + +#endif /* INTEGRATOR_HARDWARE_H */ diff --git a/arch/arm/mach-versatile/integrator.c b/arch/arm/mach-versatile/integrator.c new file mode 100644 index 000000000000..fdf9c4db08a7 --- /dev/null +++ b/arch/arm/mach-versatile/integrator.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2000-2003 Deep Blue Solutions Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "integrator-hardware.h" +#include "integrator-cm.h" +#include "integrator.h" + +static DEFINE_RAW_SPINLOCK(cm_lock); +static void __iomem *cm_base; + +/** + * cm_get - get the value from the CM_CTRL register + */ +u32 cm_get(void) +{ + return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); +} + +/** + * cm_control - update the CM_CTRL register. + * @mask: bits to change + * @set: bits to set + */ +void cm_control(u32 mask, u32 set) +{ + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&cm_lock, flags); + val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; + writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); + raw_spin_unlock_irqrestore(&cm_lock, flags); +} + +void cm_clear_irqs(void) +{ + /* disable core module IRQs */ + writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + + IRQ_ENABLE_CLEAR); +} + +static const struct of_device_id cm_match[] = { + { .compatible = "arm,core-module-integrator"}, + { }, +}; + +void cm_init(void) +{ + struct device_node *cm = of_find_matching_node(NULL, cm_match); + + if (!cm) { + pr_crit("no core module node found in device tree\n"); + return; + } + cm_base = of_iomap(cm, 0); + if (!cm_base) { + pr_crit("could not remap core module\n"); + return; + } + cm_clear_irqs(); +} + +/* + * We need to stop things allocating the low memory; ideally we need a + * better implementation of GFP_DMA which does not assume that DMA-able + * memory starts at zero. + */ +void __init integrator_reserve(void) +{ + memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); +} diff --git a/arch/arm/mach-versatile/integrator.h b/arch/arm/mach-versatile/integrator.h new file mode 100644 index 000000000000..f053aeebeb7a --- /dev/null +++ b/arch/arm/mach-versatile/integrator.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +extern struct amba_pl010_data ap_uart_data; +void integrator_init_early(void); +int integrator_init(bool is_cp); +void integrator_reserve(void); diff --git a/arch/arm/mach-versatile/integrator_ap.c b/arch/arm/mach-versatile/integrator_ap.c new file mode 100644 index 000000000000..44a69cc69376 --- /dev/null +++ b/arch/arm/mach-versatile/integrator_ap.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2000-2003 Deep Blue Solutions Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "integrator-hardware.h" +#include "integrator-cm.h" +#include "integrator.h" + +/* Regmap to the AP system controller */ +static struct regmap *ap_syscon_map; + +/* + * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx + * is the (PA >> 12). + * + * Setup a VA for the Integrator interrupt controller (for header #0, + * just for now). + */ +#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) + +/* + * Logical Physical + * f1400000 14000000 Interrupt controller + * f1600000 16000000 UART 0 + */ + +static struct map_desc ap_io_desc[] __initdata __maybe_unused = { + { + .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE + } +}; + +static void __init ap_map_io(void) +{ + iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); +} + +#ifdef CONFIG_PM +static unsigned long ic_irq_enable; + +static int irq_suspend(void) +{ + ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); + return 0; +} + +static void irq_resume(void) +{ + /* disable all irq sources */ + cm_clear_irqs(); + writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); + writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); + + writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); +} +#else +#define irq_suspend NULL +#define irq_resume NULL +#endif + +static struct syscore_ops irq_syscore_ops = { + .suspend = irq_suspend, + .resume = irq_resume, +}; + +static int __init irq_syscore_init(void) +{ + register_syscore_ops(&irq_syscore_ops); + + return 0; +} + +device_initcall(irq_syscore_init); + +/* + * For the PL010 found in the Integrator/AP some of the UART control is + * implemented in the system controller and accessed using a callback + * from the driver. + */ +static void integrator_uart_set_mctrl(struct amba_device *dev, + void __iomem *base, unsigned int mctrl) +{ + unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; + u32 phybase = dev->res.start; + int ret; + + if (phybase == INTEGRATOR_UART0_BASE) { + /* UART0 */ + rts_mask = 1 << 4; + dtr_mask = 1 << 5; + } else { + /* UART1 */ + rts_mask = 1 << 6; + dtr_mask = 1 << 7; + } + + if (mctrl & TIOCM_RTS) + ctrlc |= rts_mask; + else + ctrls |= rts_mask; + + if (mctrl & TIOCM_DTR) + ctrlc |= dtr_mask; + else + ctrls |= dtr_mask; + + ret = regmap_write(ap_syscon_map, + INTEGRATOR_SC_CTRLS_OFFSET, + ctrls); + if (ret) + pr_err("MODEM: unable to write PL010 UART CTRLS\n"); + + ret = regmap_write(ap_syscon_map, + INTEGRATOR_SC_CTRLC_OFFSET, + ctrlc); + if (ret) + pr_err("MODEM: unable to write PL010 UART CRTLC\n"); +} + +struct amba_pl010_data ap_uart_data = { + .set_mctrl = integrator_uart_set_mctrl, +}; + +void __init ap_init_early(void) +{ +} + +static void __init ap_init_irq_of(void) +{ + cm_init(); + irqchip_init(); +} + +/* For the Device Tree, add in the UART callbacks as AUXDATA */ +static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, + "uart0", &ap_uart_data), + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, + "uart1", &ap_uart_data), + { /* sentinel */ }, +}; + +static const struct of_device_id ap_syscon_match[] = { + { .compatible = "arm,integrator-ap-syscon"}, + { }, +}; + +static void __init ap_init_of(void) +{ + struct device_node *syscon; + + of_platform_default_populate(NULL, ap_auxdata_lookup, NULL); + + syscon = of_find_matching_node(NULL, ap_syscon_match); + if (!syscon) + return; + ap_syscon_map = syscon_node_to_regmap(syscon); + if (IS_ERR(ap_syscon_map)) { + pr_crit("could not find Integrator/AP system controller\n"); + return; + } +} + +static const char * ap_dt_board_compat[] = { + "arm,integrator-ap", + NULL, +}; + +DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") + .reserve = integrator_reserve, + .map_io = ap_map_io, + .init_early = ap_init_early, + .init_irq = ap_init_irq_of, + .init_machine = ap_init_of, + .dt_compat = ap_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-versatile/integrator_cp.c b/arch/arm/mach-versatile/integrator_cp.c new file mode 100644 index 000000000000..2ed4ded56b3f --- /dev/null +++ b/arch/arm/mach-versatile/integrator_cp.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2003 Deep Blue Solutions Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "integrator-hardware.h" +#include "integrator-cm.h" +#include "integrator.h" + +/* Base address to the core module header */ +static struct regmap *cm_map; +/* Base address to the CP controller */ +static void __iomem *intcp_con_base; + +#define CM_COUNTER_OFFSET 0x28 + +/* + * Logical Physical + * f1400000 14000000 Interrupt controller + * f1600000 16000000 UART 0 + * fca00000 ca000000 SIC + */ + +static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { + { + .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + } +}; + +static void __init intcp_map_io(void) +{ + iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); +} + +/* + * It seems that the card insertion interrupt remains active after + * we've acknowledged it. We therefore ignore the interrupt, and + * rely on reading it from the SIC. This also means that we must + * clear the latched interrupt. + */ +static unsigned int mmc_status(struct device *dev) +{ + unsigned int status = readl(__io_address(0xca000000 + 4)); + writel(8, intcp_con_base + 8); + + return status & 8; +} + +static struct mmci_platform_data mmc_data = { + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .status = mmc_status, +}; + +static u64 notrace intcp_read_sched_clock(void) +{ + unsigned int val; + + /* MMIO so discard return code */ + regmap_read(cm_map, CM_COUNTER_OFFSET, &val); + return val; +} + +static void __init intcp_init_early(void) +{ + cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator"); + if (IS_ERR(cm_map)) + return; + sched_clock_register(intcp_read_sched_clock, 32, 24000000); +} + +static void __init intcp_init_irq_of(void) +{ + cm_init(); + irqchip_init(); +} + +/* + * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA + * and enforce the bus names since these are used for clock lookups. + */ +static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE, + "mmci", &mmc_data), + { /* sentinel */ }, +}; + +static const struct of_device_id intcp_syscon_match[] = { + { .compatible = "arm,integrator-cp-syscon"}, + { }, +}; + +static void __init intcp_init_of(void) +{ + struct device_node *cpcon; + + cpcon = of_find_matching_node(NULL, intcp_syscon_match); + if (!cpcon) + return; + + intcp_con_base = of_iomap(cpcon, 0); + if (!intcp_con_base) + return; + + of_platform_default_populate(NULL, intcp_auxdata_lookup, NULL); +} + +static const char * intcp_dt_board_compat[] = { + "arm,integrator-cp", + NULL, +}; + +DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") + .reserve = integrator_reserve, + .map_io = intcp_map_io, + .init_early = intcp_init_early, + .init_irq = intcp_init_irq_of, + .init_machine = intcp_init_of, + .dt_compat = intcp_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-versatile/platsmp-realview.c b/arch/arm/mach-versatile/platsmp-realview.c new file mode 100644 index 000000000000..5d363385c801 --- /dev/null +++ b/arch/arm/mach-versatile/platsmp-realview.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Linus Walleij + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "platsmp.h" + +#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 + +static const struct of_device_id realview_scu_match[] = { + { .compatible = "arm,arm11mp-scu", }, + { .compatible = "arm,cortex-a9-scu", }, + { .compatible = "arm,cortex-a5-scu", }, + { } +}; + +static const struct of_device_id realview_syscon_match[] = { + { .compatible = "arm,core-module-integrator", }, + { .compatible = "arm,realview-eb-syscon", }, + { .compatible = "arm,realview-pb11mp-syscon", }, + { .compatible = "arm,realview-pbx-syscon", }, + { }, +}; + +static void __init realview_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np; + void __iomem *scu_base; + struct regmap *map; + unsigned int ncores; + int i; + + np = of_find_matching_node(NULL, realview_scu_match); + if (!np) { + pr_err("PLATSMP: No SCU base address\n"); + return; + } + scu_base = of_iomap(np, 0); + of_node_put(np); + if (!scu_base) { + pr_err("PLATSMP: No SCU remap\n"); + return; + } + + scu_enable(scu_base); + ncores = scu_get_core_count(scu_base); + pr_info("SCU: %d cores detected\n", ncores); + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + iounmap(scu_base); + + /* The syscon contains the magic SMP start address registers */ + np = of_find_matching_node(NULL, realview_syscon_match); + if (!np) { + pr_err("PLATSMP: No syscon match\n"); + return; + } + map = syscon_node_to_regmap(np); + if (IS_ERR(map)) { + pr_err("PLATSMP: No syscon regmap\n"); + return; + } + /* Put the boot address in this magic register */ + regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET, + __pa_symbol(versatile_secondary_startup)); +} + +#ifdef CONFIG_HOTPLUG_CPU +static void realview_cpu_die(unsigned int cpu) +{ + return versatile_immitation_cpu_die(cpu, 0x20); +} +#endif + +static const struct smp_operations realview_dt_smp_ops __initconst = { + .smp_prepare_cpus = realview_smp_prepare_cpus, + .smp_secondary_init = versatile_secondary_init, + .smp_boot_secondary = versatile_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = realview_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(realview_smp, "arm,realview-smp", &realview_dt_smp_ops); diff --git a/arch/arm/mach-versatile/platsmp-vexpress.c b/arch/arm/mach-versatile/platsmp-vexpress.c new file mode 100644 index 000000000000..1ee3c45e71c9 --- /dev/null +++ b/arch/arm/mach-versatile/platsmp-vexpress.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "platsmp.h" +#include "vexpress.h" + +bool __init vexpress_smp_init_ops(void) +{ +#ifdef CONFIG_MCPM + int cpu; + struct device_node *cpu_node, *cci_node; + + /* + * The best way to detect a multi-cluster configuration + * is to detect if the kernel can take over CCI ports + * control. Loop over possible CPUs and check if CCI + * port control is available. + * Override the default vexpress_smp_ops if so. + */ + for_each_possible_cpu(cpu) { + bool available; + + cpu_node = of_get_cpu_node(cpu, NULL); + if (WARN(!cpu_node, "Missing cpu device node!")) + return false; + + cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); + available = cci_node && of_device_is_available(cci_node); + of_node_put(cci_node); + of_node_put(cpu_node); + + if (!available) + return false; + } + + mcpm_smp_set_ops(); + return true; +#else + return false; +#endif +} + +static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = { + { .compatible = "arm,cortex-a5-scu", }, + { .compatible = "arm,cortex-a9-scu", }, + {} +}; + +static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *scu = of_find_matching_node(NULL, + vexpress_smp_dt_scu_match); + + if (scu) + scu_enable(of_iomap(scu, 0)); + + /* + * Write the address of secondary startup into the + * system-wide flags register. The boot monitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. + */ + vexpress_flags_set(__pa_symbol(versatile_secondary_startup)); +} + +#ifdef CONFIG_HOTPLUG_CPU +static void vexpress_cpu_die(unsigned int cpu) +{ + versatile_immitation_cpu_die(cpu, 0x40); +} +#endif + +const struct smp_operations vexpress_smp_dt_ops __initconst = { + .smp_prepare_cpus = vexpress_smp_dt_prepare_cpus, + .smp_secondary_init = versatile_secondary_init, + .smp_boot_secondary = versatile_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = vexpress_cpu_die, +#endif +}; diff --git a/arch/arm/mach-versatile/platsmp.c b/arch/arm/mach-versatile/platsmp.c new file mode 100644 index 000000000000..fa7378321e23 --- /dev/null +++ b/arch/arm/mach-versatile/platsmp.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This code is specific to the hardware found on ARM Realview and + * Versatile Express platforms where the CPUs are unable to be individually + * woken, and where there is no way to hot-unplug CPUs. Real platforms + * should not copy this code. + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "platsmp.h" + +/* + * versatile_cpu_release controls the release of CPUs from the holding + * pen in headsmp.S, which exists because we are not always able to + * control the release of individual CPUs from the board firmware. + * Production platforms do not need this. + */ +volatile int versatile_cpu_release = -1; + +/* + * Write versatile_cpu_release in a way that is guaranteed to be visible to + * all observers, irrespective of whether they're taking part in coherency + * or not. This is necessary for the hotplug code to work reliably. + */ +static void versatile_write_cpu_release(int val) +{ + versatile_cpu_release = val; + smp_wmb(); + sync_cache_w(&versatile_cpu_release); +} + +/* + * versatile_lock exists to avoid running the loops_per_jiffy delay loop + * calibrations on the secondary CPU while the requesting CPU is using + * the limited-bandwidth bus - which affects the calibration value. + * Production platforms do not need this. + */ +static DEFINE_RAW_SPINLOCK(versatile_lock); + +void versatile_secondary_init(unsigned int cpu) +{ + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + versatile_write_cpu_release(-1); + + /* + * Synchronise with the boot thread. + */ + raw_spin_lock(&versatile_lock); + raw_spin_unlock(&versatile_lock); +} + +int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + raw_spin_lock(&versatile_lock); + + /* + * This is really belt and braces; we hold unintended secondary + * CPUs in the holding pen until we're ready for them. However, + * since we haven't sent them a soft interrupt, they shouldn't + * be there. + */ + versatile_write_cpu_release(cpu_logical_map(cpu)); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (versatile_cpu_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + raw_spin_unlock(&versatile_lock); + + return versatile_cpu_release != -1 ? -ENOSYS : 0; +} diff --git a/arch/arm/mach-versatile/platsmp.h b/arch/arm/mach-versatile/platsmp.h new file mode 100644 index 000000000000..171a0ab72220 --- /dev/null +++ b/arch/arm/mach-versatile/platsmp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2011 ARM Ltd. + * All Rights Reserved + */ +extern volatile int versatile_cpu_release; + +extern void versatile_secondary_startup(void); +extern void versatile_secondary_init(unsigned int cpu); +extern int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle); +void versatile_immitation_cpu_die(unsigned int cpu, unsigned int actrl_mask); diff --git a/arch/arm/mach-versatile/realview.c b/arch/arm/mach-versatile/realview.c new file mode 100644 index 000000000000..feab66080ba2 --- /dev/null +++ b/arch/arm/mach-versatile/realview.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Linaro Ltd. + * + * Author: Linus Walleij + */ +#include +#include +#include + +static const char *const realview_dt_platform_compat[] __initconst = { + "arm,realview-eb", + "arm,realview-pb1176", + "arm,realview-pb11mp", + "arm,realview-pba8", + "arm,realview-pbx", + NULL, +}; + +DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)") +#ifdef CONFIG_ZONE_DMA + .dma_zone_size = SZ_256M, +#endif + .dt_compat = realview_dt_platform_compat, + .l2c_aux_val = 0x0, + .l2c_aux_mask = ~0x0, +MACHINE_END diff --git a/arch/arm/mach-versatile/spc.c b/arch/arm/mach-versatile/spc.c new file mode 100644 index 000000000000..1da11bdb1dfb --- /dev/null +++ b/arch/arm/mach-versatile/spc.c @@ -0,0 +1,598 @@ +/* + * Versatile Express Serial Power Controller (SPC) support + * + * Copyright (C) 2013 ARM Ltd. + * + * Authors: Sudeep KarkadaNagesha + * Achin Gupta + * Lorenzo Pieralisi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "spc.h" + +#define SPCLOG "vexpress-spc: " + +#define PERF_LVL_A15 0x00 +#define PERF_REQ_A15 0x04 +#define PERF_LVL_A7 0x08 +#define PERF_REQ_A7 0x0c +#define COMMS 0x10 +#define COMMS_REQ 0x14 +#define PWC_STATUS 0x18 +#define PWC_FLAG 0x1c + +/* SPC wake-up IRQs status and mask */ +#define WAKE_INT_MASK 0x24 +#define WAKE_INT_RAW 0x28 +#define WAKE_INT_STAT 0x2c +/* SPC power down registers */ +#define A15_PWRDN_EN 0x30 +#define A7_PWRDN_EN 0x34 +/* SPC per-CPU mailboxes */ +#define A15_BX_ADDR0 0x68 +#define A7_BX_ADDR0 0x78 + +/* SPC CPU/cluster reset statue */ +#define STANDBYWFI_STAT 0x3c +#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu)) +#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu))) + +/* SPC system config interface registers */ +#define SYSCFG_WDATA 0x70 +#define SYSCFG_RDATA 0x74 + +/* A15/A7 OPP virtual register base */ +#define A15_PERFVAL_BASE 0xC10 +#define A7_PERFVAL_BASE 0xC30 + +/* Config interface control bits */ +#define SYSCFG_START BIT(31) +#define SYSCFG_SCC (6 << 20) +#define SYSCFG_STAT (14 << 20) + +/* wake-up interrupt masks */ +#define GBL_WAKEUP_INT_MSK (0x3 << 10) + +/* TC2 static dual-cluster configuration */ +#define MAX_CLUSTERS 2 + +/* + * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS + * operation, the operation could start just before jiffie is about + * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz + */ +#define TIMEOUT_US 20000 + +#define MAX_OPPS 8 +#define CA15_DVFS 0 +#define CA7_DVFS 1 +#define SPC_SYS_CFG 2 +#define STAT_COMPLETE(type) ((1 << 0) << (type << 2)) +#define STAT_ERR(type) ((1 << 1) << (type << 2)) +#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type)) + +struct ve_spc_opp { + unsigned long freq; + unsigned long u_volt; +}; + +struct ve_spc_drvdata { + void __iomem *baseaddr; + /* + * A15s cluster identifier + * It corresponds to A15 processors MPIDR[15:8] bitfield + */ + u32 a15_clusid; + uint32_t cur_rsp_mask; + uint32_t cur_rsp_stat; + struct semaphore sem; + struct completion done; + struct ve_spc_opp *opps[MAX_CLUSTERS]; + int num_opps[MAX_CLUSTERS]; +}; + +static struct ve_spc_drvdata *info; + +static inline bool cluster_is_a15(u32 cluster) +{ + return cluster == info->a15_clusid; +} + +/** + * ve_spc_global_wakeup_irq() + * + * Function to set/clear global wakeup IRQs. Not protected by locking since + * it might be used in code paths where normal cacheable locks are not + * working. Locking must be provided by the caller to ensure atomicity. + * + * @set: if true, global wake-up IRQs are set, if false they are cleared + */ +void ve_spc_global_wakeup_irq(bool set) +{ + u32 reg; + + reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); + + if (set) + reg |= GBL_WAKEUP_INT_MSK; + else + reg &= ~GBL_WAKEUP_INT_MSK; + + writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); +} + +/** + * ve_spc_cpu_wakeup_irq() + * + * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since + * it might be used in code paths where normal cacheable locks are not + * working. Locking must be provided by the caller to ensure atomicity. + * + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * @cpu: mpidr[7:0] bitfield describing cpu affinity level + * @set: if true, wake-up IRQs are set, if false they are cleared + */ +void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set) +{ + u32 mask, reg; + + if (cluster >= MAX_CLUSTERS) + return; + + mask = BIT(cpu); + + if (!cluster_is_a15(cluster)) + mask <<= 4; + + reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); + + if (set) + reg |= mask; + else + reg &= ~mask; + + writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); +} + +/** + * ve_spc_set_resume_addr() - set the jump address used for warm boot + * + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * @cpu: mpidr[7:0] bitfield describing cpu affinity level + * @addr: physical resume address + */ +void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr) +{ + void __iomem *baseaddr; + + if (cluster >= MAX_CLUSTERS) + return; + + if (cluster_is_a15(cluster)) + baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2); + else + baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2); + + writel_relaxed(addr, baseaddr); +} + +/** + * ve_spc_powerdown() + * + * Function to enable/disable cluster powerdown. Not protected by locking + * since it might be used in code paths where normal cacheable locks are not + * working. Locking must be provided by the caller to ensure atomicity. + * + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * @enable: if true enables powerdown, if false disables it + */ +void ve_spc_powerdown(u32 cluster, bool enable) +{ + u32 pwdrn_reg; + + if (cluster >= MAX_CLUSTERS) + return; + + pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN; + writel_relaxed(enable, info->baseaddr + pwdrn_reg); +} + +static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster) +{ + return cluster_is_a15(cluster) ? + STANDBYWFI_STAT_A15_CPU_MASK(cpu) + : STANDBYWFI_STAT_A7_CPU_MASK(cpu); +} + +/** + * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) + * + * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * + * @return: non-zero if and only if the specified CPU is in WFI + * + * Take care when interpreting the result of this function: a CPU might + * be in WFI temporarily due to idle, and is not necessarily safely + * parked. + */ +int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) +{ + int ret; + u32 mask = standbywfi_cpu_mask(cpu, cluster); + + if (cluster >= MAX_CLUSTERS) + return 1; + + ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT); + + pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n", + __func__, STANDBYWFI_STAT, ret, mask); + + return ret & mask; +} + +static int ve_spc_get_performance(int cluster, u32 *freq) +{ + struct ve_spc_opp *opps = info->opps[cluster]; + u32 perf_cfg_reg = 0; + u32 perf; + + perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7; + + perf = readl_relaxed(info->baseaddr + perf_cfg_reg); + if (perf >= info->num_opps[cluster]) + return -EINVAL; + + opps += perf; + *freq = opps->freq; + + return 0; +} + +/* find closest match to given frequency in OPP table */ +static int ve_spc_round_performance(int cluster, u32 freq) +{ + int idx, max_opp = info->num_opps[cluster]; + struct ve_spc_opp *opps = info->opps[cluster]; + u32 fmin = 0, fmax = ~0, ftmp; + + freq /= 1000; /* OPP entries in kHz */ + for (idx = 0; idx < max_opp; idx++, opps++) { + ftmp = opps->freq; + if (ftmp >= freq) { + if (ftmp <= fmax) + fmax = ftmp; + } else { + if (ftmp >= fmin) + fmin = ftmp; + } + } + if (fmax != ~0) + return fmax * 1000; + else + return fmin * 1000; +} + +static int ve_spc_find_performance_index(int cluster, u32 freq) +{ + int idx, max_opp = info->num_opps[cluster]; + struct ve_spc_opp *opps = info->opps[cluster]; + + for (idx = 0; idx < max_opp; idx++, opps++) + if (opps->freq == freq) + break; + return (idx == max_opp) ? -EINVAL : idx; +} + +static int ve_spc_waitforcompletion(int req_type) +{ + int ret = wait_for_completion_interruptible_timeout( + &info->done, usecs_to_jiffies(TIMEOUT_US)); + if (ret == 0) + ret = -ETIMEDOUT; + else if (ret > 0) + ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO; + return ret; +} + +static int ve_spc_set_performance(int cluster, u32 freq) +{ + u32 perf_cfg_reg; + int ret, perf, req_type; + + if (cluster_is_a15(cluster)) { + req_type = CA15_DVFS; + perf_cfg_reg = PERF_LVL_A15; + } else { + req_type = CA7_DVFS; + perf_cfg_reg = PERF_LVL_A7; + } + + perf = ve_spc_find_performance_index(cluster, freq); + + if (perf < 0) + return perf; + + if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US))) + return -ETIME; + + init_completion(&info->done); + info->cur_rsp_mask = RESPONSE_MASK(req_type); + + writel(perf, info->baseaddr + perf_cfg_reg); + ret = ve_spc_waitforcompletion(req_type); + + info->cur_rsp_mask = 0; + up(&info->sem); + + return ret; +} + +static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data) +{ + int ret; + + if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US))) + return -ETIME; + + init_completion(&info->done); + info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG); + + /* Set the control value */ + writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS); + ret = ve_spc_waitforcompletion(SPC_SYS_CFG); + + if (ret == 0) + *data = readl(info->baseaddr + SYSCFG_RDATA); + + info->cur_rsp_mask = 0; + up(&info->sem); + + return ret; +} + +static irqreturn_t ve_spc_irq_handler(int irq, void *data) +{ + struct ve_spc_drvdata *drv_data = data; + uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS); + + if (info->cur_rsp_mask & status) { + info->cur_rsp_stat = status; + complete(&drv_data->done); + } + + return IRQ_HANDLED; +} + +/* + * +--------------------------+ + * | 31 20 | 19 0 | + * +--------------------------+ + * | m_volt | freq(kHz) | + * +--------------------------+ + */ +#define MULT_FACTOR 20 +#define VOLT_SHIFT 20 +#define FREQ_MASK (0xFFFFF) +static int ve_spc_populate_opps(uint32_t cluster) +{ + uint32_t data = 0, off, ret, idx; + struct ve_spc_opp *opps; + + opps = kcalloc(MAX_OPPS, sizeof(*opps), GFP_KERNEL); + if (!opps) + return -ENOMEM; + + info->opps[cluster] = opps; + + off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE; + for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) { + ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data); + if (!ret) { + opps->freq = (data & FREQ_MASK) * MULT_FACTOR; + opps->u_volt = (data >> VOLT_SHIFT) * 1000; + } else { + break; + } + } + info->num_opps[cluster] = idx; + + return ret; +} + +static int ve_init_opp_table(struct device *cpu_dev) +{ + int cluster; + int idx, ret = 0, max_opp; + struct ve_spc_opp *opps; + + cluster = topology_physical_package_id(cpu_dev->id); + cluster = cluster < 0 ? 0 : cluster; + + max_opp = info->num_opps[cluster]; + opps = info->opps[cluster]; + + for (idx = 0; idx < max_opp; idx++, opps++) { + ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); + if (ret) { + dev_warn(cpu_dev, "failed to add opp %lu %lu\n", + opps->freq, opps->u_volt); + return ret; + } + } + return ret; +} + +int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq) +{ + int ret; + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->baseaddr = baseaddr; + info->a15_clusid = a15_clusid; + + if (irq <= 0) { + pr_err(SPCLOG "Invalid IRQ %d\n", irq); + kfree(info); + return -EINVAL; + } + + init_completion(&info->done); + + readl_relaxed(info->baseaddr + PWC_STATUS); + + ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH + | IRQF_ONESHOT, "vexpress-spc", info); + if (ret) { + pr_err(SPCLOG "IRQ %d request failed\n", irq); + kfree(info); + return -ENODEV; + } + + sema_init(&info->sem, 1); + /* + * Multi-cluster systems may need this data when non-coherent, during + * cluster power-up/power-down. Make sure driver info reaches main + * memory. + */ + sync_cache_w(info); + sync_cache_w(&info); + + return 0; +} + +struct clk_spc { + struct clk_hw hw; + int cluster; +}; + +#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw) +static unsigned long spc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_spc *spc = to_clk_spc(hw); + u32 freq; + + if (ve_spc_get_performance(spc->cluster, &freq)) + return -EIO; + + return freq * 1000; +} + +static long spc_round_rate(struct clk_hw *hw, unsigned long drate, + unsigned long *parent_rate) +{ + struct clk_spc *spc = to_clk_spc(hw); + + return ve_spc_round_performance(spc->cluster, drate); +} + +static int spc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_spc *spc = to_clk_spc(hw); + + return ve_spc_set_performance(spc->cluster, rate / 1000); +} + +static struct clk_ops clk_spc_ops = { + .recalc_rate = spc_recalc_rate, + .round_rate = spc_round_rate, + .set_rate = spc_set_rate, +}; + +static struct clk *ve_spc_clk_register(struct device *cpu_dev) +{ + struct clk_init_data init; + struct clk_spc *spc; + + spc = kzalloc(sizeof(*spc), GFP_KERNEL); + if (!spc) + return ERR_PTR(-ENOMEM); + + spc->hw.init = &init; + spc->cluster = topology_physical_package_id(cpu_dev->id); + + spc->cluster = spc->cluster < 0 ? 0 : spc->cluster; + + init.name = dev_name(cpu_dev); + init.ops = &clk_spc_ops; + init.flags = CLK_GET_RATE_NOCACHE; + init.num_parents = 0; + + return devm_clk_register(cpu_dev, &spc->hw); +} + +static int __init ve_spc_clk_init(void) +{ + int cpu, cluster; + struct clk *clk; + bool init_opp_table[MAX_CLUSTERS] = { false }; + + if (!info) + return 0; /* Continue only if SPC is initialised */ + + if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) { + pr_err("failed to build OPP table\n"); + return -ENODEV; + } + + for_each_possible_cpu(cpu) { + struct device *cpu_dev = get_cpu_device(cpu); + if (!cpu_dev) { + pr_warn("failed to get cpu%d device\n", cpu); + continue; + } + clk = ve_spc_clk_register(cpu_dev); + if (IS_ERR(clk)) { + pr_warn("failed to register cpu%d clock\n", cpu); + continue; + } + if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) { + pr_warn("failed to register cpu%d clock lookup\n", cpu); + continue; + } + + cluster = topology_physical_package_id(cpu_dev->id); + if (init_opp_table[cluster]) + continue; + + if (ve_init_opp_table(cpu_dev)) + pr_warn("failed to initialise cpu%d opp table\n", cpu); + else if (dev_pm_opp_set_sharing_cpus(cpu_dev, + topology_core_cpumask(cpu_dev->id))) + pr_warn("failed to mark OPPs shared for cpu%d\n", cpu); + else + init_opp_table[cluster] = true; + } + + platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0); + return 0; +} +device_initcall(ve_spc_clk_init); diff --git a/arch/arm/mach-versatile/spc.h b/arch/arm/mach-versatile/spc.h new file mode 100644 index 000000000000..288569fdfcb9 --- /dev/null +++ b/arch/arm/mach-versatile/spc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * + * Copyright (C) 2012 ARM Limited + */ + + +#ifndef __SPC_H_ +#define __SPC_H_ + +int __init ve_spc_init(void __iomem *base, u32 a15_clusid, int irq); +void ve_spc_global_wakeup_irq(bool set); +void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); +void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); +void ve_spc_powerdown(u32 cluster, bool enable); +int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster); + +#endif diff --git a/arch/arm/mach-versatile/tc2_pm.c b/arch/arm/mach-versatile/tc2_pm.c new file mode 100644 index 000000000000..0fe78da0c109 --- /dev/null +++ b/arch/arm/mach-versatile/tc2_pm.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Created by: Nicolas Pitre, October 2012 + * Copyright: (C) 2012-2013 Linaro Limited + * + * Some portions of this file were originally written by Achin Gupta + * Copyright: (C) 2012 ARM Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "spc.h" + +/* SCC conf registers */ +#define RESET_CTRL 0x018 +#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu))) +#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu))) + +#define A15_CONF 0x400 +#define A7_CONF 0x500 +#define SYS_INFO 0x700 +#define SPC_BASE 0xb00 + +static void __iomem *scc; + +#define TC2_CLUSTERS 2 +#define TC2_MAX_CPUS_PER_CLUSTER 3 + +static unsigned int tc2_nr_cpus[TC2_CLUSTERS]; + +static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster) +{ + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) + return -EINVAL; + ve_spc_set_resume_addr(cluster, cpu, + __pa_symbol(mcpm_entry_point)); + ve_spc_cpu_wakeup_irq(cluster, cpu, true); + return 0; +} + +static int tc2_pm_cluster_powerup(unsigned int cluster) +{ + pr_debug("%s: cluster %u\n", __func__, cluster); + if (cluster >= TC2_CLUSTERS) + return -EINVAL; + ve_spc_powerdown(cluster, false); + return 0; +} + +static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) +{ + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); + ve_spc_cpu_wakeup_irq(cluster, cpu, true); + /* + * If the CPU is committed to power down, make sure + * the power controller will be in charge of waking it + * up upon IRQ, ie IRQ lines are cut from GIC CPU IF + * to the CPU by disabling the GIC CPU IF to prevent wfi + * from completing execution behind power controller back + */ + gic_cpu_if_down(0); +} + +static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster) +{ + pr_debug("%s: cluster %u\n", __func__, cluster); + BUG_ON(cluster >= TC2_CLUSTERS); + ve_spc_powerdown(cluster, true); + ve_spc_global_wakeup_irq(true); +} + +static void tc2_pm_cpu_cache_disable(void) +{ + v7_exit_coherency_flush(louis); +} + +static void tc2_pm_cluster_cache_disable(void) +{ + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { + /* + * On the Cortex-A15 we need to disable + * L2 prefetching before flushing the cache. + */ + asm volatile( + "mcr p15, 1, %0, c15, c0, 3 \n\t" + "isb \n\t" + "dsb " + : : "r" (0x400) ); + } + + v7_exit_coherency_flush(all); + cci_disable_port_by_cpu(read_cpuid_mpidr()); +} + +static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster) +{ + u32 mask = cluster ? + RESET_A7_NCORERESET(cpu) + : RESET_A15_NCORERESET(cpu); + + return !(readl_relaxed(scc + RESET_CTRL) & mask); +} + +#define POLL_MSEC 10 +#define TIMEOUT_MSEC 1000 + +static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster) +{ + unsigned tries; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); + + for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) { + pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n", + __func__, cpu, cluster, + readl_relaxed(scc + RESET_CTRL)); + + /* + * We need the CPU to reach WFI, but the power + * controller may put the cluster in reset and + * power it off as soon as that happens, before + * we have a chance to see STANDBYWFI. + * + * So we need to check for both conditions: + */ + if (tc2_core_in_reset(cpu, cluster) || + ve_spc_cpu_in_wfi(cpu, cluster)) + return 0; /* success: the CPU is halted */ + + /* Otherwise, wait and retry: */ + msleep(POLL_MSEC); + } + + return -ETIMEDOUT; /* timeout */ +} + +static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster) +{ + ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point)); +} + +static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster) +{ + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); + ve_spc_cpu_wakeup_irq(cluster, cpu, false); + ve_spc_set_resume_addr(cluster, cpu, 0); +} + +static void tc2_pm_cluster_is_up(unsigned int cluster) +{ + pr_debug("%s: cluster %u\n", __func__, cluster); + BUG_ON(cluster >= TC2_CLUSTERS); + ve_spc_powerdown(cluster, false); + ve_spc_global_wakeup_irq(false); +} + +static const struct mcpm_platform_ops tc2_pm_power_ops = { + .cpu_powerup = tc2_pm_cpu_powerup, + .cluster_powerup = tc2_pm_cluster_powerup, + .cpu_suspend_prepare = tc2_pm_cpu_suspend_prepare, + .cpu_powerdown_prepare = tc2_pm_cpu_powerdown_prepare, + .cluster_powerdown_prepare = tc2_pm_cluster_powerdown_prepare, + .cpu_cache_disable = tc2_pm_cpu_cache_disable, + .cluster_cache_disable = tc2_pm_cluster_cache_disable, + .wait_for_powerdown = tc2_pm_wait_for_powerdown, + .cpu_is_up = tc2_pm_cpu_is_up, + .cluster_is_up = tc2_pm_cluster_is_up, +}; + +/* + * Enable cluster-level coherency, in preparation for turning on the MMU. + */ +static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) +{ + asm volatile (" \n" +" cmp r0, #1 \n" +" bxne lr \n" +" b cci_enable_port_for_self "); +} + +static int __init tc2_pm_init(void) +{ + unsigned int mpidr, cpu, cluster; + int ret, irq; + u32 a15_cluster_id, a7_cluster_id, sys_info; + struct device_node *np; + + /* + * The power management-related features are hidden behind + * SCC registers. We need to extract runtime information like + * cluster ids and number of CPUs really available in clusters. + */ + np = of_find_compatible_node(NULL, NULL, + "arm,vexpress-scc,v2p-ca15_a7"); + scc = of_iomap(np, 0); + if (!scc) + return -ENODEV; + + a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; + a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; + if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS) + return -EINVAL; + + sys_info = readl_relaxed(scc + SYS_INFO); + tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf; + tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf; + + irq = irq_of_parse_and_map(np, 0); + + /* + * A subset of the SCC registers is also used to communicate + * with the SPC (power controller). We need to be able to + * drive it very early in the boot process to power up + * processors, so we initialize the SPC driver here. + */ + ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq); + if (ret) + return ret; + + if (!cci_probed()) + return -ENODEV; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) { + pr_err("%s: boot CPU is out of bound!\n", __func__); + return -EINVAL; + } + + ret = mcpm_platform_register(&tc2_pm_power_ops); + if (!ret) { + mcpm_sync_init(tc2_pm_power_up_setup); + /* test if we can (re)enable the CCI on our own */ + BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable) != 0); + pr_info("TC2 power management initialized\n"); + } + return ret; +} + +early_initcall(tc2_pm_init); diff --git a/arch/arm/mach-versatile/v2m-mps2.c b/arch/arm/mach-versatile/v2m-mps2.c new file mode 100644 index 000000000000..5b50d8e95cd7 --- /dev/null +++ b/arch/arm/mach-versatile/v2m-mps2.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + */ + +#include + +static const char *const mps2_compat[] __initconst = { + "arm,mps2", + NULL +}; + +DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)") + .dt_compat = mps2_compat, +MACHINE_END diff --git a/arch/arm/mach-versatile/v2m.c b/arch/arm/mach-versatile/v2m.c new file mode 100644 index 000000000000..79afdf2a90b6 --- /dev/null +++ b/arch/arm/mach-versatile/v2m.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + +#include "vexpress.h" + +#define SYS_FLAGSSET 0x030 +#define SYS_FLAGSCLR 0x034 + +void vexpress_flags_set(u32 data) +{ + static void __iomem *base; + + if (!base) { + struct device_node *node = of_find_compatible_node(NULL, NULL, + "arm,vexpress-sysreg"); + + base = of_iomap(node, 0); + } + + if (WARN_ON(!base)) + return; + + writel(~0, base + SYS_FLAGSCLR); + writel(data, base + SYS_FLAGSSET); +} + +static const char * const v2m_dt_match[] __initconst = { + "arm,vexpress", + NULL, +}; + +DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") + .dt_compat = v2m_dt_match, + .l2c_aux_val = 0x00400000, + .l2c_aux_mask = 0xfe0fffff, + .smp = smp_ops(vexpress_smp_dt_ops), + .smp_init = smp_init_ops(vexpress_smp_init_ops), +MACHINE_END diff --git a/arch/arm/mach-versatile/versatile.c b/arch/arm/mach-versatile/versatile.c new file mode 100644 index 000000000000..02ba68abe533 --- /dev/null +++ b/arch/arm/mach-versatile/versatile.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Versatile board support using the device tree + * + * Copyright (C) 2010 Secret Lab Technologies Ltd. + * Copyright (C) 2009 Jeremy Kerr + * Copyright (C) 2004 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* macro to get at MMIO space when running virtually */ +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) +#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n)) + +/* + * ------------------------------------------------------------------------ + * Versatile Registers + * ------------------------------------------------------------------------ + */ +#define VERSATILE_SYS_PCICTL_OFFSET 0x44 +#define VERSATILE_SYS_MCI_OFFSET 0x48 + +/* + * VERSATILE peripheral addresses + */ +#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ +#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ +#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ + +/* + * System controller bit assignment + */ +#define VERSATILE_REFCLK 0 +#define VERSATILE_TIMCLK 1 + +#define VERSATILE_TIMER1_EnSel 15 +#define VERSATILE_TIMER2_EnSel 17 +#define VERSATILE_TIMER3_EnSel 19 +#define VERSATILE_TIMER4_EnSel 21 + +static void __iomem *versatile_sys_base; + +unsigned int mmc_status(struct device *dev) +{ + struct amba_device *adev = container_of(dev, struct amba_device, dev); + u32 mask; + + if (adev->res.start == VERSATILE_MMCI0_BASE) + mask = 1; + else + mask = 2; + + return readl(versatile_sys_base + VERSATILE_SYS_MCI_OFFSET) & mask; +} + +static struct mmci_platform_data mmc0_plat_data = { + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .status = mmc_status, +}; + +static struct mmci_platform_data mmc1_plat_data = { + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .status = mmc_status, +}; + +/* + * Lookup table for attaching a specific name and platform_data pointer to + * devices as they get created by of_platform_populate(). Ideally this table + * would not exist, but the current clock implementation depends on some devices + * having a specific name. + */ +struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), + OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data), + {} +}; + +static struct map_desc versatile_io_desc[] __initdata __maybe_unused = { + { + .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), + .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE), + .length = SZ_4K * 9, + .type = MT_DEVICE + } +}; + +static void __init versatile_map_io(void) +{ + debug_ll_io_init(); + iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); +} + +static void __init versatile_init_early(void) +{ + u32 val; + + /* + * set clock frequency: + * VERSATILE_REFCLK is 32KHz + * VERSATILE_TIMCLK is 1MHz + */ + val = readl(__io_address(VERSATILE_SCTL_BASE)); + writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, + __io_address(VERSATILE_SCTL_BASE)); +} + +static void __init versatile_dt_pci_init(void) +{ + u32 val; + struct device_node *np; + struct property *newprop; + + np = of_find_compatible_node(NULL, NULL, "arm,versatile-pci"); + if (!np) + return; + + /* Check if PCI backplane is detected */ + val = readl(versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET); + if (val & 1) { + /* + * Enable PCI accesses. Note that the documentaton is + * inconsistent whether or not this is needed, but the old + * driver had it so we will keep it. + */ + writel(1, versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET); + goto out_put_node; + } + + newprop = kzalloc(sizeof(*newprop), GFP_KERNEL); + if (!newprop) + goto out_put_node; + + newprop->name = kstrdup("status", GFP_KERNEL); + newprop->value = kstrdup("disabled", GFP_KERNEL); + newprop->length = sizeof("disabled"); + of_update_property(np, newprop); + + pr_info("Not plugged into PCI backplane!\n"); + +out_put_node: + of_node_put(np); +} + +static void __init versatile_dt_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "arm,core-module-versatile"); + if (np) + versatile_sys_base = of_iomap(np, 0); + WARN_ON(!versatile_sys_base); + + versatile_dt_pci_init(); + + of_platform_default_populate(NULL, versatile_auxdata_lookup, NULL); +} + +static const char *const versatile_dt_match[] __initconst = { + "arm,versatile-ab", + "arm,versatile-pb", + NULL, +}; + +DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)") + .map_io = versatile_map_io, + .init_early = versatile_init_early, + .init_machine = versatile_dt_init, + .dt_compat = versatile_dt_match, +MACHINE_END diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c deleted file mode 100644 index 02ba68abe533..000000000000 --- a/arch/arm/mach-versatile/versatile_dt.c +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Versatile board support using the device tree - * - * Copyright (C) 2010 Secret Lab Technologies Ltd. - * Copyright (C) 2009 Jeremy Kerr - * Copyright (C) 2004 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* macro to get at MMIO space when running virtually */ -#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) -#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n)) - -/* - * ------------------------------------------------------------------------ - * Versatile Registers - * ------------------------------------------------------------------------ - */ -#define VERSATILE_SYS_PCICTL_OFFSET 0x44 -#define VERSATILE_SYS_MCI_OFFSET 0x48 - -/* - * VERSATILE peripheral addresses - */ -#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ -#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ -#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ - -/* - * System controller bit assignment - */ -#define VERSATILE_REFCLK 0 -#define VERSATILE_TIMCLK 1 - -#define VERSATILE_TIMER1_EnSel 15 -#define VERSATILE_TIMER2_EnSel 17 -#define VERSATILE_TIMER3_EnSel 19 -#define VERSATILE_TIMER4_EnSel 21 - -static void __iomem *versatile_sys_base; - -unsigned int mmc_status(struct device *dev) -{ - struct amba_device *adev = container_of(dev, struct amba_device, dev); - u32 mask; - - if (adev->res.start == VERSATILE_MMCI0_BASE) - mask = 1; - else - mask = 2; - - return readl(versatile_sys_base + VERSATILE_SYS_MCI_OFFSET) & mask; -} - -static struct mmci_platform_data mmc0_plat_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .status = mmc_status, -}; - -static struct mmci_platform_data mmc1_plat_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .status = mmc_status, -}; - -/* - * Lookup table for attaching a specific name and platform_data pointer to - * devices as they get created by of_platform_populate(). Ideally this table - * would not exist, but the current clock implementation depends on some devices - * having a specific name. - */ -struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), - OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data), - {} -}; - -static struct map_desc versatile_io_desc[] __initdata __maybe_unused = { - { - .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), - .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE), - .length = SZ_4K * 9, - .type = MT_DEVICE - } -}; - -static void __init versatile_map_io(void) -{ - debug_ll_io_init(); - iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); -} - -static void __init versatile_init_early(void) -{ - u32 val; - - /* - * set clock frequency: - * VERSATILE_REFCLK is 32KHz - * VERSATILE_TIMCLK is 1MHz - */ - val = readl(__io_address(VERSATILE_SCTL_BASE)); - writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, - __io_address(VERSATILE_SCTL_BASE)); -} - -static void __init versatile_dt_pci_init(void) -{ - u32 val; - struct device_node *np; - struct property *newprop; - - np = of_find_compatible_node(NULL, NULL, "arm,versatile-pci"); - if (!np) - return; - - /* Check if PCI backplane is detected */ - val = readl(versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET); - if (val & 1) { - /* - * Enable PCI accesses. Note that the documentaton is - * inconsistent whether or not this is needed, but the old - * driver had it so we will keep it. - */ - writel(1, versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET); - goto out_put_node; - } - - newprop = kzalloc(sizeof(*newprop), GFP_KERNEL); - if (!newprop) - goto out_put_node; - - newprop->name = kstrdup("status", GFP_KERNEL); - newprop->value = kstrdup("disabled", GFP_KERNEL); - newprop->length = sizeof("disabled"); - of_update_property(np, newprop); - - pr_info("Not plugged into PCI backplane!\n"); - -out_put_node: - of_node_put(np); -} - -static void __init versatile_dt_init(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "arm,core-module-versatile"); - if (np) - versatile_sys_base = of_iomap(np, 0); - WARN_ON(!versatile_sys_base); - - versatile_dt_pci_init(); - - of_platform_default_populate(NULL, versatile_auxdata_lookup, NULL); -} - -static const char *const versatile_dt_match[] __initconst = { - "arm,versatile-ab", - "arm,versatile-pb", - NULL, -}; - -DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)") - .map_io = versatile_map_io, - .init_early = versatile_init_early, - .init_machine = versatile_dt_init, - .dt_compat = versatile_dt_match, -MACHINE_END diff --git a/arch/arm/mach-versatile/vexpress.h b/arch/arm/mach-versatile/vexpress.h new file mode 100644 index 000000000000..bda78675c55d --- /dev/null +++ b/arch/arm/mach-versatile/vexpress.h @@ -0,0 +1,4 @@ +bool vexpress_smp_init_ops(void); +void vexpress_flags_set(u32 data); + +extern const struct smp_operations vexpress_smp_dt_ops; diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig deleted file mode 100644 index 2e6aff5a0f17..000000000000 --- a/arch/arm/mach-vexpress/Kconfig +++ /dev/null @@ -1,81 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_VEXPRESS - bool "ARM Ltd. Versatile Express family" - depends on ARCH_MULTI_V7 - select ARCH_SUPPORTS_BIG_ENDIAN - select ARM_AMBA - select ARM_GIC - select ARM_GLOBAL_TIMER - select ARM_TIMER_SP804 - select GPIOLIB - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select HAVE_PATA_PLATFORM - select CLK_ICST - select NO_IOPORT_MAP - select PLAT_VERSATILE - select POWER_RESET - select POWER_RESET_VEXPRESS - select POWER_SUPPLY - select REGULATOR if MMC_ARMMMCI - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select VEXPRESS_CONFIG - help - This option enables support for systems using Cortex processor based - ARM core and logic (FPGA) tiles on the Versatile Express motherboard, - for example: - - - CoreTile Express A5x2 (V2P-CA5s) - - CoreTile Express A9x4 (V2P-CA9) - - CoreTile Express A15x2 (V2P-CA15) - - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs - (Soft Macrocell Models) - - Versatile Express RTSMs (Models) - - You must boot using a Flattened Device Tree in order to use these - platforms. The traditional (ATAGs) boot method is not usable on - these boards with this option. - -if ARCH_VEXPRESS - -config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA - bool "Enable A5 and A9 only errata work-arounds" - default y - select ARM_ERRATA_643719 if SMP - select ARM_ERRATA_720789 - select PL310_ERRATA_753970 if CACHE_L2X0 - help - Provides common dependencies for Versatile Express platforms - based on Cortex-A5 and Cortex-A9 processors. In order to - build a working kernel, you must also enable relevant core - tile support or Flattened Device Tree based support options. - -config ARCH_VEXPRESS_DCSCB - bool "Dual Cluster System Control Block (DCSCB) support" - depends on MCPM - select ARM_CCI400_PORT_CTRL - help - Support for the Dual Cluster System Configuration Block (DCSCB). - This is needed to provide CPU and cluster power management - on RTSM implementing big.LITTLE. - -config ARCH_VEXPRESS_SPC - bool "Versatile Express Serial Power Controller (SPC)" - select PM_OPP - help - The TC2 (A15x2 A7x3) versatile express core tile integrates a logic - block called Serial Power Controller (SPC) that provides the interface - between the dual cluster test-chip and the M3 microcontroller that - carries out power management. - -config ARCH_VEXPRESS_TC2_PM - bool "Versatile Express TC2 power management" - depends on MCPM - select ARM_CCI400_PORT_CTRL - select ARCH_VEXPRESS_SPC - select ARM_CPU_SUSPEND - help - Support for CPU and cluster power management on Versatile Express - with a TC2 (A15x2 A7x3) big.LITTLE core tile. - -endif diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile deleted file mode 100644 index 3651a1ed0f2b..000000000000 --- a/arch/arm/mach-vexpress/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \ - -I$(srctree)/arch/arm/plat-versatile/include - -obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o -obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o -CFLAGS_dcscb.o += -march=armv7-a -CFLAGS_REMOVE_dcscb.o = -pg -obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o -CFLAGS_REMOVE_spc.o = -pg -obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o -CFLAGS_tc2_pm.o += -march=armv7-a -CFLAGS_REMOVE_tc2_pm.o = -pg -obj-$(CONFIG_SMP) += platsmp.o - -obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot deleted file mode 100644 index cec195d4fcba..000000000000 --- a/arch/arm/mach-vexpress/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# Empty file waiting for deletion once Makefile.boot isn't needed any more. -# Patch waits for application at -# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h deleted file mode 100644 index bda78675c55d..000000000000 --- a/arch/arm/mach-vexpress/core.h +++ /dev/null @@ -1,4 +0,0 @@ -bool vexpress_smp_init_ops(void); -void vexpress_flags_set(u32 data); - -extern const struct smp_operations vexpress_smp_dt_ops; diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c deleted file mode 100644 index a0554d7d04f7..000000000000 --- a/arch/arm/mach-vexpress/dcscb.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block - * - * Created by: Nicolas Pitre, May 2012 - * Copyright: (C) 2012-2013 Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "core.h" - -#define RST_HOLD0 0x0 -#define RST_HOLD1 0x4 -#define SYS_SWRESET 0x8 -#define RST_STAT0 0xc -#define RST_STAT1 0x10 -#define EAG_CFG_R 0x20 -#define EAG_CFG_W 0x24 -#define KFC_CFG_R 0x28 -#define KFC_CFG_W 0x2c -#define DCS_CFG_R 0x30 - -static void __iomem *dcscb_base; -static int dcscb_allcpus_mask[2]; - -static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster) -{ - unsigned int rst_hold, cpumask = (1 << cpu); - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster])) - return -EINVAL; - - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold &= ~(cpumask | (cpumask << 4)); - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); - return 0; -} - -static int dcscb_cluster_powerup(unsigned int cluster) -{ - unsigned int rst_hold; - - pr_debug("%s: cluster %u\n", __func__, cluster); - if (cluster >= 2) - return -EINVAL; - - /* remove cluster reset and add individual CPU's reset */ - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold &= ~(1 << 8); - rst_hold |= dcscb_allcpus_mask[cluster]; - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); - return 0; -} - -static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) -{ - unsigned int rst_hold; - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster])); - - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold |= (1 << cpu); - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); -} - -static void dcscb_cluster_powerdown_prepare(unsigned int cluster) -{ - unsigned int rst_hold; - - pr_debug("%s: cluster %u\n", __func__, cluster); - BUG_ON(cluster >= 2); - - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold |= (1 << 8); - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); -} - -static void dcscb_cpu_cache_disable(void) -{ - /* Disable and flush the local CPU cache. */ - v7_exit_coherency_flush(louis); -} - -static void dcscb_cluster_cache_disable(void) -{ - /* Flush all cache levels for this cluster. */ - v7_exit_coherency_flush(all); - - /* - * A full outer cache flush could be needed at this point - * on platforms with such a cache, depending on where the - * outer cache sits. In some cases the notion of a "last - * cluster standing" would need to be implemented if the - * outer cache is shared across clusters. In any case, when - * the outer cache needs flushing, there is no concurrent - * access to the cache controller to worry about and no - * special locking besides what is already provided by the - * MCPM state machinery is needed. - */ - - /* - * Disable cluster-level coherency by masking - * incoming snoops and DVM messages: - */ - cci_disable_port_by_cpu(read_cpuid_mpidr()); -} - -static const struct mcpm_platform_ops dcscb_power_ops = { - .cpu_powerup = dcscb_cpu_powerup, - .cluster_powerup = dcscb_cluster_powerup, - .cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare, - .cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare, - .cpu_cache_disable = dcscb_cpu_cache_disable, - .cluster_cache_disable = dcscb_cluster_cache_disable, -}; - -extern void dcscb_power_up_setup(unsigned int affinity_level); - -static int __init dcscb_init(void) -{ - struct device_node *node; - unsigned int cfg; - int ret; - - if (!cci_probed()) - return -ENODEV; - - node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); - if (!node) - return -ENODEV; - dcscb_base = of_iomap(node, 0); - if (!dcscb_base) - return -EADDRNOTAVAIL; - cfg = readl_relaxed(dcscb_base + DCS_CFG_R); - dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; - dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; - - ret = mcpm_platform_register(&dcscb_power_ops); - if (!ret) - ret = mcpm_sync_init(dcscb_power_up_setup); - if (ret) { - iounmap(dcscb_base); - return ret; - } - - pr_info("VExpress DCSCB support installed\n"); - - /* - * Future entries into the kernel can now go - * through the cluster entry vectors. - */ - vexpress_flags_set(__pa_symbol(mcpm_entry_point)); - - return 0; -} - -early_initcall(dcscb_init); diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S deleted file mode 100644 index 0614b2ebd354..000000000000 --- a/arch/arm/mach-vexpress/dcscb_setup.S +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/include/asm/dcscb_setup.S - * - * Created by: Dave Martin, 2012-06-22 - * Copyright: (C) 2012-2013 Linaro Limited - */ - -#include - - -ENTRY(dcscb_power_up_setup) - - cmp r0, #0 @ check affinity level - beq 2f - -/* - * Enable cluster-level coherency, in preparation for turning on the MMU. - * The ACTLR SMP bit does not need to be set here, because cpu_resume() - * already restores that. - * - * A15/A7 may not require explicit L2 invalidation on reset, dependent - * on hardware integration decisions. - * For now, this code assumes that L2 is either already invalidated, - * or invalidation is not required. - */ - - b cci_enable_port_for_self - -2: @ Implementation-specific local CPU setup operations should go here, - @ if any. In this case, there is nothing to do. - - bx lr - -ENDPROC(dcscb_power_up_setup) diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c deleted file mode 100644 index 99c93124aa68..000000000000 --- a/arch/arm/mach-vexpress/platsmp.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-vexpress/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "core.h" - -bool __init vexpress_smp_init_ops(void) -{ -#ifdef CONFIG_MCPM - int cpu; - struct device_node *cpu_node, *cci_node; - - /* - * The best way to detect a multi-cluster configuration - * is to detect if the kernel can take over CCI ports - * control. Loop over possible CPUs and check if CCI - * port control is available. - * Override the default vexpress_smp_ops if so. - */ - for_each_possible_cpu(cpu) { - bool available; - - cpu_node = of_get_cpu_node(cpu, NULL); - if (WARN(!cpu_node, "Missing cpu device node!")) - return false; - - cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); - available = cci_node && of_device_is_available(cci_node); - of_node_put(cci_node); - of_node_put(cpu_node); - - if (!available) - return false; - } - - mcpm_smp_set_ops(); - return true; -#else - return false; -#endif -} - -static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = { - { .compatible = "arm,cortex-a5-scu", }, - { .compatible = "arm,cortex-a9-scu", }, - {} -}; - -static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus) -{ - struct device_node *scu = of_find_matching_node(NULL, - vexpress_smp_dt_scu_match); - - if (scu) - scu_enable(of_iomap(scu, 0)); - - /* - * Write the address of secondary startup into the - * system-wide flags register. The boot monitor waits - * until it receives a soft interrupt, and then the - * secondary CPU branches to this address. - */ - vexpress_flags_set(__pa_symbol(versatile_secondary_startup)); -} - -#ifdef CONFIG_HOTPLUG_CPU -static void vexpress_cpu_die(unsigned int cpu) -{ - versatile_immitation_cpu_die(cpu, 0x40); -} -#endif - -const struct smp_operations vexpress_smp_dt_ops __initconst = { - .smp_prepare_cpus = vexpress_smp_dt_prepare_cpus, - .smp_secondary_init = versatile_secondary_init, - .smp_boot_secondary = versatile_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = vexpress_cpu_die, -#endif -}; diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c deleted file mode 100644 index 1da11bdb1dfb..000000000000 --- a/arch/arm/mach-vexpress/spc.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Versatile Express Serial Power Controller (SPC) support - * - * Copyright (C) 2013 ARM Ltd. - * - * Authors: Sudeep KarkadaNagesha - * Achin Gupta - * Lorenzo Pieralisi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "spc.h" - -#define SPCLOG "vexpress-spc: " - -#define PERF_LVL_A15 0x00 -#define PERF_REQ_A15 0x04 -#define PERF_LVL_A7 0x08 -#define PERF_REQ_A7 0x0c -#define COMMS 0x10 -#define COMMS_REQ 0x14 -#define PWC_STATUS 0x18 -#define PWC_FLAG 0x1c - -/* SPC wake-up IRQs status and mask */ -#define WAKE_INT_MASK 0x24 -#define WAKE_INT_RAW 0x28 -#define WAKE_INT_STAT 0x2c -/* SPC power down registers */ -#define A15_PWRDN_EN 0x30 -#define A7_PWRDN_EN 0x34 -/* SPC per-CPU mailboxes */ -#define A15_BX_ADDR0 0x68 -#define A7_BX_ADDR0 0x78 - -/* SPC CPU/cluster reset statue */ -#define STANDBYWFI_STAT 0x3c -#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu)) -#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu))) - -/* SPC system config interface registers */ -#define SYSCFG_WDATA 0x70 -#define SYSCFG_RDATA 0x74 - -/* A15/A7 OPP virtual register base */ -#define A15_PERFVAL_BASE 0xC10 -#define A7_PERFVAL_BASE 0xC30 - -/* Config interface control bits */ -#define SYSCFG_START BIT(31) -#define SYSCFG_SCC (6 << 20) -#define SYSCFG_STAT (14 << 20) - -/* wake-up interrupt masks */ -#define GBL_WAKEUP_INT_MSK (0x3 << 10) - -/* TC2 static dual-cluster configuration */ -#define MAX_CLUSTERS 2 - -/* - * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS - * operation, the operation could start just before jiffie is about - * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz - */ -#define TIMEOUT_US 20000 - -#define MAX_OPPS 8 -#define CA15_DVFS 0 -#define CA7_DVFS 1 -#define SPC_SYS_CFG 2 -#define STAT_COMPLETE(type) ((1 << 0) << (type << 2)) -#define STAT_ERR(type) ((1 << 1) << (type << 2)) -#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type)) - -struct ve_spc_opp { - unsigned long freq; - unsigned long u_volt; -}; - -struct ve_spc_drvdata { - void __iomem *baseaddr; - /* - * A15s cluster identifier - * It corresponds to A15 processors MPIDR[15:8] bitfield - */ - u32 a15_clusid; - uint32_t cur_rsp_mask; - uint32_t cur_rsp_stat; - struct semaphore sem; - struct completion done; - struct ve_spc_opp *opps[MAX_CLUSTERS]; - int num_opps[MAX_CLUSTERS]; -}; - -static struct ve_spc_drvdata *info; - -static inline bool cluster_is_a15(u32 cluster) -{ - return cluster == info->a15_clusid; -} - -/** - * ve_spc_global_wakeup_irq() - * - * Function to set/clear global wakeup IRQs. Not protected by locking since - * it might be used in code paths where normal cacheable locks are not - * working. Locking must be provided by the caller to ensure atomicity. - * - * @set: if true, global wake-up IRQs are set, if false they are cleared - */ -void ve_spc_global_wakeup_irq(bool set) -{ - u32 reg; - - reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); - - if (set) - reg |= GBL_WAKEUP_INT_MSK; - else - reg &= ~GBL_WAKEUP_INT_MSK; - - writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); -} - -/** - * ve_spc_cpu_wakeup_irq() - * - * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since - * it might be used in code paths where normal cacheable locks are not - * working. Locking must be provided by the caller to ensure atomicity. - * - * @cluster: mpidr[15:8] bitfield describing cluster affinity level - * @cpu: mpidr[7:0] bitfield describing cpu affinity level - * @set: if true, wake-up IRQs are set, if false they are cleared - */ -void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set) -{ - u32 mask, reg; - - if (cluster >= MAX_CLUSTERS) - return; - - mask = BIT(cpu); - - if (!cluster_is_a15(cluster)) - mask <<= 4; - - reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); - - if (set) - reg |= mask; - else - reg &= ~mask; - - writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); -} - -/** - * ve_spc_set_resume_addr() - set the jump address used for warm boot - * - * @cluster: mpidr[15:8] bitfield describing cluster affinity level - * @cpu: mpidr[7:0] bitfield describing cpu affinity level - * @addr: physical resume address - */ -void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr) -{ - void __iomem *baseaddr; - - if (cluster >= MAX_CLUSTERS) - return; - - if (cluster_is_a15(cluster)) - baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2); - else - baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2); - - writel_relaxed(addr, baseaddr); -} - -/** - * ve_spc_powerdown() - * - * Function to enable/disable cluster powerdown. Not protected by locking - * since it might be used in code paths where normal cacheable locks are not - * working. Locking must be provided by the caller to ensure atomicity. - * - * @cluster: mpidr[15:8] bitfield describing cluster affinity level - * @enable: if true enables powerdown, if false disables it - */ -void ve_spc_powerdown(u32 cluster, bool enable) -{ - u32 pwdrn_reg; - - if (cluster >= MAX_CLUSTERS) - return; - - pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN; - writel_relaxed(enable, info->baseaddr + pwdrn_reg); -} - -static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster) -{ - return cluster_is_a15(cluster) ? - STANDBYWFI_STAT_A15_CPU_MASK(cpu) - : STANDBYWFI_STAT_A7_CPU_MASK(cpu); -} - -/** - * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) - * - * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster - * @cluster: mpidr[15:8] bitfield describing cluster affinity level - * - * @return: non-zero if and only if the specified CPU is in WFI - * - * Take care when interpreting the result of this function: a CPU might - * be in WFI temporarily due to idle, and is not necessarily safely - * parked. - */ -int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) -{ - int ret; - u32 mask = standbywfi_cpu_mask(cpu, cluster); - - if (cluster >= MAX_CLUSTERS) - return 1; - - ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT); - - pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n", - __func__, STANDBYWFI_STAT, ret, mask); - - return ret & mask; -} - -static int ve_spc_get_performance(int cluster, u32 *freq) -{ - struct ve_spc_opp *opps = info->opps[cluster]; - u32 perf_cfg_reg = 0; - u32 perf; - - perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7; - - perf = readl_relaxed(info->baseaddr + perf_cfg_reg); - if (perf >= info->num_opps[cluster]) - return -EINVAL; - - opps += perf; - *freq = opps->freq; - - return 0; -} - -/* find closest match to given frequency in OPP table */ -static int ve_spc_round_performance(int cluster, u32 freq) -{ - int idx, max_opp = info->num_opps[cluster]; - struct ve_spc_opp *opps = info->opps[cluster]; - u32 fmin = 0, fmax = ~0, ftmp; - - freq /= 1000; /* OPP entries in kHz */ - for (idx = 0; idx < max_opp; idx++, opps++) { - ftmp = opps->freq; - if (ftmp >= freq) { - if (ftmp <= fmax) - fmax = ftmp; - } else { - if (ftmp >= fmin) - fmin = ftmp; - } - } - if (fmax != ~0) - return fmax * 1000; - else - return fmin * 1000; -} - -static int ve_spc_find_performance_index(int cluster, u32 freq) -{ - int idx, max_opp = info->num_opps[cluster]; - struct ve_spc_opp *opps = info->opps[cluster]; - - for (idx = 0; idx < max_opp; idx++, opps++) - if (opps->freq == freq) - break; - return (idx == max_opp) ? -EINVAL : idx; -} - -static int ve_spc_waitforcompletion(int req_type) -{ - int ret = wait_for_completion_interruptible_timeout( - &info->done, usecs_to_jiffies(TIMEOUT_US)); - if (ret == 0) - ret = -ETIMEDOUT; - else if (ret > 0) - ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO; - return ret; -} - -static int ve_spc_set_performance(int cluster, u32 freq) -{ - u32 perf_cfg_reg; - int ret, perf, req_type; - - if (cluster_is_a15(cluster)) { - req_type = CA15_DVFS; - perf_cfg_reg = PERF_LVL_A15; - } else { - req_type = CA7_DVFS; - perf_cfg_reg = PERF_LVL_A7; - } - - perf = ve_spc_find_performance_index(cluster, freq); - - if (perf < 0) - return perf; - - if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US))) - return -ETIME; - - init_completion(&info->done); - info->cur_rsp_mask = RESPONSE_MASK(req_type); - - writel(perf, info->baseaddr + perf_cfg_reg); - ret = ve_spc_waitforcompletion(req_type); - - info->cur_rsp_mask = 0; - up(&info->sem); - - return ret; -} - -static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data) -{ - int ret; - - if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US))) - return -ETIME; - - init_completion(&info->done); - info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG); - - /* Set the control value */ - writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS); - ret = ve_spc_waitforcompletion(SPC_SYS_CFG); - - if (ret == 0) - *data = readl(info->baseaddr + SYSCFG_RDATA); - - info->cur_rsp_mask = 0; - up(&info->sem); - - return ret; -} - -static irqreturn_t ve_spc_irq_handler(int irq, void *data) -{ - struct ve_spc_drvdata *drv_data = data; - uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS); - - if (info->cur_rsp_mask & status) { - info->cur_rsp_stat = status; - complete(&drv_data->done); - } - - return IRQ_HANDLED; -} - -/* - * +--------------------------+ - * | 31 20 | 19 0 | - * +--------------------------+ - * | m_volt | freq(kHz) | - * +--------------------------+ - */ -#define MULT_FACTOR 20 -#define VOLT_SHIFT 20 -#define FREQ_MASK (0xFFFFF) -static int ve_spc_populate_opps(uint32_t cluster) -{ - uint32_t data = 0, off, ret, idx; - struct ve_spc_opp *opps; - - opps = kcalloc(MAX_OPPS, sizeof(*opps), GFP_KERNEL); - if (!opps) - return -ENOMEM; - - info->opps[cluster] = opps; - - off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE; - for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) { - ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data); - if (!ret) { - opps->freq = (data & FREQ_MASK) * MULT_FACTOR; - opps->u_volt = (data >> VOLT_SHIFT) * 1000; - } else { - break; - } - } - info->num_opps[cluster] = idx; - - return ret; -} - -static int ve_init_opp_table(struct device *cpu_dev) -{ - int cluster; - int idx, ret = 0, max_opp; - struct ve_spc_opp *opps; - - cluster = topology_physical_package_id(cpu_dev->id); - cluster = cluster < 0 ? 0 : cluster; - - max_opp = info->num_opps[cluster]; - opps = info->opps[cluster]; - - for (idx = 0; idx < max_opp; idx++, opps++) { - ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); - if (ret) { - dev_warn(cpu_dev, "failed to add opp %lu %lu\n", - opps->freq, opps->u_volt); - return ret; - } - } - return ret; -} - -int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq) -{ - int ret; - info = kzalloc(sizeof(*info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - info->baseaddr = baseaddr; - info->a15_clusid = a15_clusid; - - if (irq <= 0) { - pr_err(SPCLOG "Invalid IRQ %d\n", irq); - kfree(info); - return -EINVAL; - } - - init_completion(&info->done); - - readl_relaxed(info->baseaddr + PWC_STATUS); - - ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH - | IRQF_ONESHOT, "vexpress-spc", info); - if (ret) { - pr_err(SPCLOG "IRQ %d request failed\n", irq); - kfree(info); - return -ENODEV; - } - - sema_init(&info->sem, 1); - /* - * Multi-cluster systems may need this data when non-coherent, during - * cluster power-up/power-down. Make sure driver info reaches main - * memory. - */ - sync_cache_w(info); - sync_cache_w(&info); - - return 0; -} - -struct clk_spc { - struct clk_hw hw; - int cluster; -}; - -#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw) -static unsigned long spc_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_spc *spc = to_clk_spc(hw); - u32 freq; - - if (ve_spc_get_performance(spc->cluster, &freq)) - return -EIO; - - return freq * 1000; -} - -static long spc_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *parent_rate) -{ - struct clk_spc *spc = to_clk_spc(hw); - - return ve_spc_round_performance(spc->cluster, drate); -} - -static int spc_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_spc *spc = to_clk_spc(hw); - - return ve_spc_set_performance(spc->cluster, rate / 1000); -} - -static struct clk_ops clk_spc_ops = { - .recalc_rate = spc_recalc_rate, - .round_rate = spc_round_rate, - .set_rate = spc_set_rate, -}; - -static struct clk *ve_spc_clk_register(struct device *cpu_dev) -{ - struct clk_init_data init; - struct clk_spc *spc; - - spc = kzalloc(sizeof(*spc), GFP_KERNEL); - if (!spc) - return ERR_PTR(-ENOMEM); - - spc->hw.init = &init; - spc->cluster = topology_physical_package_id(cpu_dev->id); - - spc->cluster = spc->cluster < 0 ? 0 : spc->cluster; - - init.name = dev_name(cpu_dev); - init.ops = &clk_spc_ops; - init.flags = CLK_GET_RATE_NOCACHE; - init.num_parents = 0; - - return devm_clk_register(cpu_dev, &spc->hw); -} - -static int __init ve_spc_clk_init(void) -{ - int cpu, cluster; - struct clk *clk; - bool init_opp_table[MAX_CLUSTERS] = { false }; - - if (!info) - return 0; /* Continue only if SPC is initialised */ - - if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) { - pr_err("failed to build OPP table\n"); - return -ENODEV; - } - - for_each_possible_cpu(cpu) { - struct device *cpu_dev = get_cpu_device(cpu); - if (!cpu_dev) { - pr_warn("failed to get cpu%d device\n", cpu); - continue; - } - clk = ve_spc_clk_register(cpu_dev); - if (IS_ERR(clk)) { - pr_warn("failed to register cpu%d clock\n", cpu); - continue; - } - if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) { - pr_warn("failed to register cpu%d clock lookup\n", cpu); - continue; - } - - cluster = topology_physical_package_id(cpu_dev->id); - if (init_opp_table[cluster]) - continue; - - if (ve_init_opp_table(cpu_dev)) - pr_warn("failed to initialise cpu%d opp table\n", cpu); - else if (dev_pm_opp_set_sharing_cpus(cpu_dev, - topology_core_cpumask(cpu_dev->id))) - pr_warn("failed to mark OPPs shared for cpu%d\n", cpu); - else - init_opp_table[cluster] = true; - } - - platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0); - return 0; -} -device_initcall(ve_spc_clk_init); diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h deleted file mode 100644 index 288569fdfcb9..000000000000 --- a/arch/arm/mach-vexpress/spc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * - * Copyright (C) 2012 ARM Limited - */ - - -#ifndef __SPC_H_ -#define __SPC_H_ - -int __init ve_spc_init(void __iomem *base, u32 a15_clusid, int irq); -void ve_spc_global_wakeup_irq(bool set); -void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); -void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); -void ve_spc_powerdown(u32 cluster, bool enable); -int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster); - -#endif diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c deleted file mode 100644 index e96c42ae3602..000000000000 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support - * - * Created by: Nicolas Pitre, October 2012 - * Copyright: (C) 2012-2013 Linaro Limited - * - * Some portions of this file were originally written by Achin Gupta - * Copyright: (C) 2012 ARM Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "spc.h" - -/* SCC conf registers */ -#define RESET_CTRL 0x018 -#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu))) -#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu))) - -#define A15_CONF 0x400 -#define A7_CONF 0x500 -#define SYS_INFO 0x700 -#define SPC_BASE 0xb00 - -static void __iomem *scc; - -#define TC2_CLUSTERS 2 -#define TC2_MAX_CPUS_PER_CLUSTER 3 - -static unsigned int tc2_nr_cpus[TC2_CLUSTERS]; - -static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster) -{ - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) - return -EINVAL; - ve_spc_set_resume_addr(cluster, cpu, - __pa_symbol(mcpm_entry_point)); - ve_spc_cpu_wakeup_irq(cluster, cpu, true); - return 0; -} - -static int tc2_pm_cluster_powerup(unsigned int cluster) -{ - pr_debug("%s: cluster %u\n", __func__, cluster); - if (cluster >= TC2_CLUSTERS) - return -EINVAL; - ve_spc_powerdown(cluster, false); - return 0; -} - -static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) -{ - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); - ve_spc_cpu_wakeup_irq(cluster, cpu, true); - /* - * If the CPU is committed to power down, make sure - * the power controller will be in charge of waking it - * up upon IRQ, ie IRQ lines are cut from GIC CPU IF - * to the CPU by disabling the GIC CPU IF to prevent wfi - * from completing execution behind power controller back - */ - gic_cpu_if_down(0); -} - -static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster) -{ - pr_debug("%s: cluster %u\n", __func__, cluster); - BUG_ON(cluster >= TC2_CLUSTERS); - ve_spc_powerdown(cluster, true); - ve_spc_global_wakeup_irq(true); -} - -static void tc2_pm_cpu_cache_disable(void) -{ - v7_exit_coherency_flush(louis); -} - -static void tc2_pm_cluster_cache_disable(void) -{ - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { - /* - * On the Cortex-A15 we need to disable - * L2 prefetching before flushing the cache. - */ - asm volatile( - "mcr p15, 1, %0, c15, c0, 3 \n\t" - "isb \n\t" - "dsb " - : : "r" (0x400) ); - } - - v7_exit_coherency_flush(all); - cci_disable_port_by_cpu(read_cpuid_mpidr()); -} - -static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster) -{ - u32 mask = cluster ? - RESET_A7_NCORERESET(cpu) - : RESET_A15_NCORERESET(cpu); - - return !(readl_relaxed(scc + RESET_CTRL) & mask); -} - -#define POLL_MSEC 10 -#define TIMEOUT_MSEC 1000 - -static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster) -{ - unsigned tries; - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); - - for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) { - pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n", - __func__, cpu, cluster, - readl_relaxed(scc + RESET_CTRL)); - - /* - * We need the CPU to reach WFI, but the power - * controller may put the cluster in reset and - * power it off as soon as that happens, before - * we have a chance to see STANDBYWFI. - * - * So we need to check for both conditions: - */ - if (tc2_core_in_reset(cpu, cluster) || - ve_spc_cpu_in_wfi(cpu, cluster)) - return 0; /* success: the CPU is halted */ - - /* Otherwise, wait and retry: */ - msleep(POLL_MSEC); - } - - return -ETIMEDOUT; /* timeout */ -} - -static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster) -{ - ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point)); -} - -static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster) -{ - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); - ve_spc_cpu_wakeup_irq(cluster, cpu, false); - ve_spc_set_resume_addr(cluster, cpu, 0); -} - -static void tc2_pm_cluster_is_up(unsigned int cluster) -{ - pr_debug("%s: cluster %u\n", __func__, cluster); - BUG_ON(cluster >= TC2_CLUSTERS); - ve_spc_powerdown(cluster, false); - ve_spc_global_wakeup_irq(false); -} - -static const struct mcpm_platform_ops tc2_pm_power_ops = { - .cpu_powerup = tc2_pm_cpu_powerup, - .cluster_powerup = tc2_pm_cluster_powerup, - .cpu_suspend_prepare = tc2_pm_cpu_suspend_prepare, - .cpu_powerdown_prepare = tc2_pm_cpu_powerdown_prepare, - .cluster_powerdown_prepare = tc2_pm_cluster_powerdown_prepare, - .cpu_cache_disable = tc2_pm_cpu_cache_disable, - .cluster_cache_disable = tc2_pm_cluster_cache_disable, - .wait_for_powerdown = tc2_pm_wait_for_powerdown, - .cpu_is_up = tc2_pm_cpu_is_up, - .cluster_is_up = tc2_pm_cluster_is_up, -}; - -/* - * Enable cluster-level coherency, in preparation for turning on the MMU. - */ -static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) -{ - asm volatile (" \n" -" cmp r0, #1 \n" -" bxne lr \n" -" b cci_enable_port_for_self "); -} - -static int __init tc2_pm_init(void) -{ - unsigned int mpidr, cpu, cluster; - int ret, irq; - u32 a15_cluster_id, a7_cluster_id, sys_info; - struct device_node *np; - - /* - * The power management-related features are hidden behind - * SCC registers. We need to extract runtime information like - * cluster ids and number of CPUs really available in clusters. - */ - np = of_find_compatible_node(NULL, NULL, - "arm,vexpress-scc,v2p-ca15_a7"); - scc = of_iomap(np, 0); - if (!scc) - return -ENODEV; - - a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; - a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; - if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS) - return -EINVAL; - - sys_info = readl_relaxed(scc + SYS_INFO); - tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf; - tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf; - - irq = irq_of_parse_and_map(np, 0); - - /* - * A subset of the SCC registers is also used to communicate - * with the SPC (power controller). We need to be able to - * drive it very early in the boot process to power up - * processors, so we initialize the SPC driver here. - */ - ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq); - if (ret) - return ret; - - if (!cci_probed()) - return -ENODEV; - - mpidr = read_cpuid_mpidr(); - cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); - cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) { - pr_err("%s: boot CPU is out of bound!\n", __func__); - return -EINVAL; - } - - ret = mcpm_platform_register(&tc2_pm_power_ops); - if (!ret) { - mcpm_sync_init(tc2_pm_power_up_setup); - /* test if we can (re)enable the CCI on our own */ - BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable) != 0); - pr_info("TC2 power management initialized\n"); - } - return ret; -} - -early_initcall(tc2_pm_init); diff --git a/arch/arm/mach-vexpress/v2m-mps2.c b/arch/arm/mach-vexpress/v2m-mps2.c deleted file mode 100644 index 5b50d8e95cd7..000000000000 --- a/arch/arm/mach-vexpress/v2m-mps2.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 ARM Limited - * - * Author: Vladimir Murzin - */ - -#include - -static const char *const mps2_compat[] __initconst = { - "arm,mps2", - NULL -}; - -DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)") - .dt_compat = mps2_compat, -MACHINE_END diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c deleted file mode 100644 index ffe7c7a85ae9..000000000000 --- a/arch/arm/mach-vexpress/v2m.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -#include "core.h" - -#define SYS_FLAGSSET 0x030 -#define SYS_FLAGSCLR 0x034 - -void vexpress_flags_set(u32 data) -{ - static void __iomem *base; - - if (!base) { - struct device_node *node = of_find_compatible_node(NULL, NULL, - "arm,vexpress-sysreg"); - - base = of_iomap(node, 0); - } - - if (WARN_ON(!base)) - return; - - writel(~0, base + SYS_FLAGSCLR); - writel(data, base + SYS_FLAGSSET); -} - -static const char * const v2m_dt_match[] __initconst = { - "arm,vexpress", - NULL, -}; - -DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") - .dt_compat = v2m_dt_match, - .l2c_aux_val = 0x00400000, - .l2c_aux_mask = 0xfe0fffff, - .smp = smp_ops(vexpress_smp_dt_ops), - .smp_init = smp_init_ops(vexpress_smp_init_ops), -MACHINE_END diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile deleted file mode 100644 index 5de44a57c4de..000000000000 --- a/arch/arm/plat-versatile/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include - -obj-$(CONFIG_SMP) += headsmp.o platsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S deleted file mode 100644 index 09d9fc30c8ca..000000000000 --- a/arch/arm/plat-versatile/headsmp.S +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/plat-versatile/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - */ -#include -#include -#include - -/* - * Realview/Versatile Express specific entry point for secondary CPUs. - * This provides a "holding pen" into which all secondary cores are held - * until we're ready for them to initialise. - */ -ENTRY(versatile_secondary_startup) - ARM_BE8(setend be) - mrc p15, 0, r0, c0, c0, 5 - bic r0, #0xff000000 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup - - .align -1: .long . - .long versatile_cpu_release -ENDPROC(versatile_secondary_startup) diff --git a/arch/arm/plat-versatile/hotplug.c b/arch/arm/plat-versatile/hotplug.c deleted file mode 100644 index 2e9dca38bec0..000000000000 --- a/arch/arm/plat-versatile/hotplug.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This hotplug implementation is _specific_ to the situation found on - * ARM development platforms where there is _no_ possibility of actually - * taking a CPU offline, resetting it, or otherwise. Real platforms must - * NOT copy this code. - */ -#include -#include -#include - -#include -#include - -#include - -static inline void versatile_immitation_enter_lowpower(unsigned int actrl_mask) -{ - unsigned int v; - - asm volatile( - "mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %3\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C), "Ir" (actrl_mask) - : "cc"); -} - -static inline void versatile_immitation_leave_lowpower(unsigned int actrl_mask) -{ - unsigned int v; - - asm volatile( - "mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C), "Ir" (actrl_mask) - : "cc"); -} - -static inline void versatile_immitation_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts. - * - * This code should not be used outside Versatile platforms. - */ - for (;;) { - wfi(); - - if (versatile_cpu_release == cpu_logical_map(cpu)) { - /* - * OK, proper wakeup, we're done - */ - break; - } - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - -/* - * platform-specific code to shutdown a CPU. - * This code supports immitation-style CPU hotplug for Versatile/Realview/ - * Versatile Express platforms that are unable to do real CPU hotplug. - */ -void versatile_immitation_cpu_die(unsigned int cpu, unsigned int actrl_mask) -{ - int spurious = 0; - - versatile_immitation_enter_lowpower(actrl_mask); - versatile_immitation_do_lowpower(cpu, &spurious); - versatile_immitation_leave_lowpower(actrl_mask); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); -} diff --git a/arch/arm/plat-versatile/include/plat/platsmp.h b/arch/arm/plat-versatile/include/plat/platsmp.h deleted file mode 100644 index 500605f48b80..000000000000 --- a/arch/arm/plat-versatile/include/plat/platsmp.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * linux/arch/arm/plat-versatile/include/plat/platsmp.h - * - * Copyright (C) 2011 ARM Ltd. - * All Rights Reserved - */ -extern volatile int versatile_cpu_release; - -extern void versatile_secondary_startup(void); -extern void versatile_secondary_init(unsigned int cpu); -extern int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle); -void versatile_immitation_cpu_die(unsigned int cpu, unsigned int actrl_mask); diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c deleted file mode 100644 index 3567296cec2a..000000000000 --- a/arch/arm/plat-versatile/platsmp.c +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/plat-versatile/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This code is specific to the hardware found on ARM Realview and - * Versatile Express platforms where the CPUs are unable to be individually - * woken, and where there is no way to hot-unplug CPUs. Real platforms - * should not copy this code. - */ -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -/* - * versatile_cpu_release controls the release of CPUs from the holding - * pen in headsmp.S, which exists because we are not always able to - * control the release of individual CPUs from the board firmware. - * Production platforms do not need this. - */ -volatile int versatile_cpu_release = -1; - -/* - * Write versatile_cpu_release in a way that is guaranteed to be visible to - * all observers, irrespective of whether they're taking part in coherency - * or not. This is necessary for the hotplug code to work reliably. - */ -static void versatile_write_cpu_release(int val) -{ - versatile_cpu_release = val; - smp_wmb(); - sync_cache_w(&versatile_cpu_release); -} - -/* - * versatile_lock exists to avoid running the loops_per_jiffy delay loop - * calibrations on the secondary CPU while the requesting CPU is using - * the limited-bandwidth bus - which affects the calibration value. - * Production platforms do not need this. - */ -static DEFINE_RAW_SPINLOCK(versatile_lock); - -void versatile_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - versatile_write_cpu_release(-1); - - /* - * Synchronise with the boot thread. - */ - raw_spin_lock(&versatile_lock); - raw_spin_unlock(&versatile_lock); -} - -int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - raw_spin_lock(&versatile_lock); - - /* - * This is really belt and braces; we hold unintended secondary - * CPUs in the holding pen until we're ready for them. However, - * since we haven't sent them a soft interrupt, they shouldn't - * be there. - */ - versatile_write_cpu_release(cpu_logical_map(cpu)); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (versatile_cpu_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - raw_spin_unlock(&versatile_lock); - - return versatile_cpu_release != -1 ? -ENOSYS : 0; -} -- cgit v1.2.3 From 482c27273f52ad336e8d076f96f91b358dcb7d0c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 22 Oct 2019 10:42:51 +0200 Subject: ARM: ep93xx: renumber interrupts With the move to irq domains, no irqchip must start at number 0, so shift all the hardwired IRQ numbers by one. Tested-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/mach-ep93xx/core.c | 4 +- arch/arm/mach-ep93xx/include/mach/irqs.h | 122 ++++++++++++++++--------------- 2 files changed, 65 insertions(+), 61 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index a3b4e843456a..e4569a5acc3f 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -75,8 +75,8 @@ void __init ep93xx_map_io(void) *************************************************************************/ void __init ep93xx_init_irq(void) { - vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); - vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); + vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0); + vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0); } diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/include/mach/irqs.h index 244daf83ce6d..60c69c4ed7e1 100644 --- a/arch/arm/mach-ep93xx/include/mach/irqs.h +++ b/arch/arm/mach-ep93xx/include/mach/irqs.h @@ -6,69 +6,73 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#define IRQ_EP93XX_COMMRX 2 -#define IRQ_EP93XX_COMMTX 3 -#define IRQ_EP93XX_TIMER1 4 -#define IRQ_EP93XX_TIMER2 5 -#define IRQ_EP93XX_AACINTR 6 -#define IRQ_EP93XX_DMAM2P0 7 -#define IRQ_EP93XX_DMAM2P1 8 -#define IRQ_EP93XX_DMAM2P2 9 -#define IRQ_EP93XX_DMAM2P3 10 -#define IRQ_EP93XX_DMAM2P4 11 -#define IRQ_EP93XX_DMAM2P5 12 -#define IRQ_EP93XX_DMAM2P6 13 -#define IRQ_EP93XX_DMAM2P7 14 -#define IRQ_EP93XX_DMAM2P8 15 -#define IRQ_EP93XX_DMAM2P9 16 -#define IRQ_EP93XX_DMAM2M0 17 -#define IRQ_EP93XX_DMAM2M1 18 -#define IRQ_EP93XX_GPIO0MUX 19 -#define IRQ_EP93XX_GPIO1MUX 20 -#define IRQ_EP93XX_GPIO2MUX 21 -#define IRQ_EP93XX_GPIO3MUX 22 -#define IRQ_EP93XX_UART1RX 23 -#define IRQ_EP93XX_UART1TX 24 -#define IRQ_EP93XX_UART2RX 25 -#define IRQ_EP93XX_UART2TX 26 -#define IRQ_EP93XX_UART3RX 27 -#define IRQ_EP93XX_UART3TX 28 -#define IRQ_EP93XX_KEY 29 -#define IRQ_EP93XX_TOUCH 30 +#define IRQ_EP93XX_VIC0 1 + +#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) +#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) +#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) +#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) +#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) +#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) +#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) +#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) +#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) +#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) +#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) +#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) +#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) +#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) +#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) +#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) +#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) +#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) +#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) +#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) +#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) +#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) +#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) +#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) +#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) +#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) +#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) +#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) +#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) #define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc -#define IRQ_EP93XX_EXT0 32 -#define IRQ_EP93XX_EXT1 33 -#define IRQ_EP93XX_EXT2 34 -#define IRQ_EP93XX_64HZ 35 -#define IRQ_EP93XX_WATCHDOG 36 -#define IRQ_EP93XX_RTC 37 -#define IRQ_EP93XX_IRDA 38 -#define IRQ_EP93XX_ETHERNET 39 -#define IRQ_EP93XX_EXT3 40 -#define IRQ_EP93XX_PROG 41 -#define IRQ_EP93XX_1HZ 42 -#define IRQ_EP93XX_VSYNC 43 -#define IRQ_EP93XX_VIDEO_FIFO 44 -#define IRQ_EP93XX_SSP1RX 45 -#define IRQ_EP93XX_SSP1TX 46 -#define IRQ_EP93XX_GPIO4MUX 47 -#define IRQ_EP93XX_GPIO5MUX 48 -#define IRQ_EP93XX_GPIO6MUX 49 -#define IRQ_EP93XX_GPIO7MUX 50 -#define IRQ_EP93XX_TIMER3 51 -#define IRQ_EP93XX_UART1 52 -#define IRQ_EP93XX_SSP 53 -#define IRQ_EP93XX_UART2 54 -#define IRQ_EP93XX_UART3 55 -#define IRQ_EP93XX_USB 56 -#define IRQ_EP93XX_ETHERNET_PME 57 -#define IRQ_EP93XX_DSP 58 -#define IRQ_EP93XX_GPIO_AB 59 -#define IRQ_EP93XX_SAI 60 +#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) + +#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) +#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) +#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) +#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) +#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) +#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) +#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) +#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) +#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) +#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) +#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) +#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) +#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) +#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) +#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) +#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) +#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) +#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) +#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) +#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) +#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) +#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) +#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) +#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) +#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) +#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) +#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) +#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) +#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff -#define NR_EP93XX_IRQS (64 + 24) +#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) #define EP93XX_BOARD_IRQS 32 -- cgit v1.2.3 From 36f1a4ae6b60a9fbd9a35a3b257dc6e53b5feff1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 20 Sep 2019 10:10:03 +0200 Subject: ARM: ep93xx: enable SPARSE_IRQ Without CONFIG_SPARSE_IRQ, we rely on mach/irqs.h to define NR_IRQS globally. Do the minimal conversion by setting .nr_irqs in each machine descriptor. Only the vision_ep9307 machine has extra IRQs for GPIOs, so make .nr_irqs the original value there, while using the plain NR_EP93XX_IRQS everywhere else. Cc: Hartley Sweeten Cc: Hubert Feurstein Cc: Lukasz Majewski Tested-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 2 + arch/arm/mach-ep93xx/adssphere.c | 1 + arch/arm/mach-ep93xx/core.c | 1 + arch/arm/mach-ep93xx/edb93xx.c | 8 +++ arch/arm/mach-ep93xx/gesbc9312.c | 1 + arch/arm/mach-ep93xx/include/mach/irqs.h | 83 -------------------------------- arch/arm/mach-ep93xx/irqs.h | 76 +++++++++++++++++++++++++++++ arch/arm/mach-ep93xx/micro9.c | 4 ++ arch/arm/mach-ep93xx/simone.c | 1 + arch/arm/mach-ep93xx/snappercl15.c | 1 + arch/arm/mach-ep93xx/soc.h | 1 + arch/arm/mach-ep93xx/ts72xx.c | 3 +- arch/arm/mach-ep93xx/vision_ep9307.c | 1 + 13 files changed, 99 insertions(+), 84 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/include/mach/irqs.h create mode 100644 arch/arm/mach-ep93xx/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31f024e6e925..5177e54cc14c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -358,6 +358,8 @@ config ARCH_EP93XX select CPU_ARM920T select GPIOLIB select COMMON_CLK + select IRQ_DOMAIN + select SPARSE_IRQ help This enables support for the Cirrus EP93xx series of CPUs. diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 8d5e349a7a6d..0c48d3c5b8e7 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -32,6 +32,7 @@ static void __init adssphere_init_machine(void) MACHINE_START(ADSSPHERE, "ADS Sphere board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index e4569a5acc3f..2d58e273c96d 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -47,6 +47,7 @@ #include #include "soc.h" +#include "irqs.h" /************************************************************************* * Static I/O mappings that are needed for all EP93xx platforms diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index af0e22471ebd..4b90899a66e9 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -243,6 +243,7 @@ static void __init edb93xx_init_machine(void) MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") /* Maintainer: H Hartley Sweeten */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -255,6 +256,7 @@ MACHINE_END MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") /* Maintainer: George Kashperko */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -267,6 +269,7 @@ MACHINE_END MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -279,6 +282,7 @@ MACHINE_END MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") /* Maintainer: Herbert Valerio Riedel */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -291,6 +295,7 @@ MACHINE_END MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") /* Maintainer: H Hartley Sweeten */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -303,6 +308,7 @@ MACHINE_END MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") /* Maintainer: Toufeeq Hussain */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -315,6 +321,7 @@ MACHINE_END MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -327,6 +334,7 @@ MACHINE_END MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index d7f9890321eb..0b7043e3e178 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -32,6 +32,7 @@ static void __init gesbc9312_init_machine(void) MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/include/mach/irqs.h b/arch/arm/mach-ep93xx/include/mach/irqs.h deleted file mode 100644 index 60c69c4ed7e1..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/irqs.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/irqs.h - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_EP93XX_VIC0 1 - -#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) -#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) -#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) -#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) -#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) -#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) -#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) -#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) -#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) -#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) -#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) -#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) -#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) -#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) -#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) -#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) -#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) -#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) -#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) -#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) -#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) -#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) -#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) -#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) -#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) -#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) -#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) -#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) -#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) -#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc - -#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) - -#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) -#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) -#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) -#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) -#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) -#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) -#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) -#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) -#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) -#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) -#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) -#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) -#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) -#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) -#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) -#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) -#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) -#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) -#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) -#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) -#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) -#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) -#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) -#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) -#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) -#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) -#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) -#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) -#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) -#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff - -#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) - -#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) -#define EP93XX_BOARD_IRQS 32 - -#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS) - - -#endif diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h new file mode 100644 index 000000000000..353201b90c66 --- /dev/null +++ b/arch/arm/mach-ep93xx/irqs.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define IRQ_EP93XX_VIC0 1 + +#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) +#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) +#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) +#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) +#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) +#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) +#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) +#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) +#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) +#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) +#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) +#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) +#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) +#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) +#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) +#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) +#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) +#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) +#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) +#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) +#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) +#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) +#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) +#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) +#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) +#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) +#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) +#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) +#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) +#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc + +#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) + +#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) +#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) +#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) +#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) +#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) +#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) +#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) +#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) +#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) +#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) +#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) +#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) +#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) +#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) +#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) +#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) +#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) +#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) +#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) +#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) +#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) +#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) +#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) +#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) +#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) +#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) +#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) +#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) +#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) +#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff + +#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) + +#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) +#define EP93XX_BOARD_IRQS 32 + +#endif diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index e6ead8ded6ee..c121c459aa17 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -76,6 +76,7 @@ static void __init micro9_init_machine(void) MACHINE_START(MICRO9, "Contec Micro9-High") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -88,6 +89,7 @@ MACHINE_END MACHINE_START(MICRO9M, "Contec Micro9-Mid") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -100,6 +102,7 @@ MACHINE_END MACHINE_START(MICRO9L, "Contec Micro9-Lite") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -112,6 +115,7 @@ MACHINE_END MACHINE_START(MICRO9S, "Contec Micro9-Slim") /* Maintainer: Hubert Feurstein */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 5291053023b2..569e72413561 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -119,6 +119,7 @@ static void __init simone_init_machine(void) MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") /* Maintainer: Ryan Mallon */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index e200d69471e9..1dfb725671b1 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -153,6 +153,7 @@ static void __init snappercl15_init_machine(void) MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") /* Maintainer: Ryan Mallon */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index 94ef7f275f94..f0986e288d19 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h @@ -10,6 +10,7 @@ #define _EP93XX_SOC_H #include +#include "irqs.h" /* * EP93xx Physical Memory Map: diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 12eff8c8074d..e70bac011407 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -22,7 +22,6 @@ #include "gpio-ep93xx.h" #include "hardware.h" -#include #include #include @@ -350,6 +349,7 @@ static void __init ts72xx_init_machine(void) MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, @@ -413,6 +413,7 @@ static void __init bk3_init_machine(void) MACHINE_START(BK3, "Liebherr controller BK3.1") /* Maintainer: Lukasz Majewski */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index e46281e60bf7..30d9cf3791eb 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -302,6 +302,7 @@ static void __init vision_init_machine(void) MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") /* Maintainer: H Hartley Sweeten */ .atag_offset = 0x100, + .nr_irqs = NR_EP93XX_IRQS + EP93XX_BOARD_IRQS, .map_io = vision_map_io, .init_irq = ep93xx_init_irq, .init_time = ep93xx_timer_init, -- cgit v1.2.3 From 4e5f36f84614ce59b140ae6706603d76e6e0cdbe Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 20 Sep 2019 10:18:31 +0200 Subject: ARM: ep93xx: make mach/ep93xx-regs.h local Nothing relies on it outside of arch/arm/mach-ep93xx/, so just move it there. Cc: Hartley Sweeten Tested-by: Alexander Sverdlin Signed-off-by: Arnd Bergmann --- arch/arm/mach-ep93xx/ep93xx-regs.h | 38 ++++++++++++++++++++++ arch/arm/mach-ep93xx/gpio-ep93xx.h | 2 +- arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | 42 ------------------------- arch/arm/mach-ep93xx/include/mach/uncompress.h | 1 - arch/arm/mach-ep93xx/soc.h | 2 +- 5 files changed, 40 insertions(+), 45 deletions(-) create mode 100644 arch/arm/mach-ep93xx/ep93xx-regs.h delete mode 100644 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ep93xx/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93xx-regs.h new file mode 100644 index 000000000000..8fa3646de0a4 --- /dev/null +++ b/arch/arm/mach-ep93xx/ep93xx-regs.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ARCH_EP93XX_REGS_H +#define __ASM_ARCH_EP93XX_REGS_H + +/* + * EP93xx linux memory map: + * + * virt phys size + * fe800000 5M per-platform mappings + * fed00000 80800000 2M APB + * fef00000 80000000 1M AHB + */ + +#define EP93XX_AHB_PHYS_BASE 0x80000000 +#define EP93XX_AHB_VIRT_BASE 0xfef00000 +#define EP93XX_AHB_SIZE 0x00100000 + +#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x)) +#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) + +#define EP93XX_APB_PHYS_BASE 0x80800000 +#define EP93XX_APB_VIRT_BASE 0xfed00000 +#define EP93XX_APB_SIZE 0x00200000 + +#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) +#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) + +/* APB UARTs */ +#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) +#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) + +#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000) +#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) + +#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) +#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) + +#endif diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio-ep93xx.h index 242af4a401ea..7b46eb7e5507 100644 --- a/arch/arm/mach-ep93xx/gpio-ep93xx.h +++ b/arch/arm/mach-ep93xx/gpio-ep93xx.h @@ -4,7 +4,7 @@ #ifndef __GPIO_EP93XX_H #define __GPIO_EP93XX_H -#include +#include "ep93xx-regs.h" #define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h deleted file mode 100644 index 6839ea032e58..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h - */ - -#ifndef __ASM_ARCH_EP93XX_REGS_H -#define __ASM_ARCH_EP93XX_REGS_H - -/* - * EP93xx linux memory map: - * - * virt phys size - * fe800000 5M per-platform mappings - * fed00000 80800000 2M APB - * fef00000 80000000 1M AHB - */ - -#define EP93XX_AHB_PHYS_BASE 0x80000000 -#define EP93XX_AHB_VIRT_BASE 0xfef00000 -#define EP93XX_AHB_SIZE 0x00100000 - -#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x)) -#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) - -#define EP93XX_APB_PHYS_BASE 0x80800000 -#define EP93XX_APB_VIRT_BASE 0xfed00000 -#define EP93XX_APB_SIZE 0x00200000 - -#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) -#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) - -/* APB UARTs */ -#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) -#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) - -#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000) -#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) - -#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) -#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) - -#endif diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h index b3ec1db988db..e20bcab702b2 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -5,7 +5,6 @@ * Copyright (C) 2006 Lennert Buytenhek */ -#include #include static unsigned char __raw_readb(unsigned int ptr) diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index f0986e288d19..3245ebbd5069 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h @@ -9,7 +9,7 @@ #ifndef _EP93XX_SOC_H #define _EP93XX_SOC_H -#include +#include "ep93xx-regs.h" #include "irqs.h" /* -- cgit v1.2.3 From 0361c7e504b1fa3c2901643088e2f29c0354ab31 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 1 Apr 2022 15:58:09 +0200 Subject: ARM: ep93xx: multiplatform support With the clock support and the interrupts out of the way, ep93xx can be compiled into the same kernel image as the other ARMv4/v5 platforms. The last obstacle are the two workarounds for broken boot loaders that require us to re-initialize the ethernet controller and/or the watchdog on certain machines. Move this code into the decompressor sources directly, checking for each possibly affected machine individually. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 16 ----- arch/arm/boot/compressed/misc-ep93xx.h | 86 +++++++++++++++++++++++++ arch/arm/boot/compressed/misc.c | 4 ++ arch/arm/configs/ep93xx_defconfig | 2 + arch/arm/mach-ep93xx/Kconfig | 12 ++++ arch/arm/mach-ep93xx/include/mach/uncompress.h | 89 -------------------------- 6 files changed, 104 insertions(+), 105 deletions(-) create mode 100644 arch/arm/boot/compressed/misc-ep93xx.h delete mode 100644 arch/arm/mach-ep93xx/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5177e54cc14c..2bd611beefe1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -347,22 +347,6 @@ config ARCH_MULTIPLATFORM select SPARSE_IRQ select USE_OF -config ARCH_EP93XX - bool "EP93xx-based" - select ARCH_SPARSEMEM_ENABLE - select ARM_AMBA - imply ARM_PATCH_PHYS_VIRT - select ARM_VIC - select AUTO_ZRELADDR - select CLKSRC_MMIO - select CPU_ARM920T - select GPIOLIB - select COMMON_CLK - select IRQ_DOMAIN - select SPARSE_IRQ - help - This enables support for the Cirrus EP93xx series of CPUs. - config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 diff --git a/arch/arm/boot/compressed/misc-ep93xx.h b/arch/arm/boot/compressed/misc-ep93xx.h new file mode 100644 index 000000000000..3dc942589cba --- /dev/null +++ b/arch/arm/boot/compressed/misc-ep93xx.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2006 Lennert Buytenhek + */ + +#include + +static inline unsigned int __raw_readl(unsigned int ptr) +{ + return *((volatile unsigned int *)ptr); +} + +static inline void __raw_writeb(unsigned char value, unsigned int ptr) +{ + *((volatile unsigned char *)ptr) = value; +} + +static inline void __raw_writel(unsigned int value, unsigned int ptr) +{ + *((volatile unsigned int *)ptr) = value; +} + +/* + * Some bootloaders don't turn off DMA from the ethernet MAC before + * jumping to linux, which means that we might end up with bits of RX + * status and packet data scribbled over the uncompressed kernel image. + * Work around this by resetting the ethernet MAC before we uncompress. + */ +#define PHYS_ETH_SELF_CTL 0x80010020 +#define ETH_SELF_CTL_RESET 0x00000001 + +static inline void ep93xx_ethernet_reset(void) +{ + unsigned int v; + + /* Reset the ethernet MAC. */ + v = __raw_readl(PHYS_ETH_SELF_CTL); + __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); + + /* Wait for reset to finish. */ + while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) + ; +} + +#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000 +#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 +#define TS72XX_WDT_FEED_VAL 0x05 + +static inline void __maybe_unused ts72xx_watchdog_disable(void) +{ + __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE); + __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE); +} + +static inline void ep93xx_decomp_setup(void) +{ + if (machine_is_ts72xx()) + ts72xx_watchdog_disable(); + + if (machine_is_adssphere() || + machine_is_edb9301() || + machine_is_edb9302() || + machine_is_edb9302a() || + machine_is_edb9302a() || + machine_is_edb9307() || + machine_is_edb9307a() || + machine_is_edb9307a() || + machine_is_edb9312() || + machine_is_edb9315() || + machine_is_edb9315a() || + machine_is_edb9315a() || + machine_is_gesbc9312() || + machine_is_micro9() || + machine_is_micro9l() || + machine_is_micro9m() || + machine_is_micro9s() || + machine_is_micro9m() || + machine_is_micro9l() || + machine_is_micro9s() || + machine_is_sim_one() || + machine_is_snapper_cl15() || + machine_is_ts72xx() || + machine_is_bk3() || + machine_is_vision_ep9307()) + ep93xx_ethernet_reset(); +} diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index c3c66ff2d696..cb2e069dc73f 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -23,6 +23,7 @@ unsigned int __machine_arch_type; #include #include #include "misc.h" +#include "misc-ep93xx.h" static void putstr(const char *ptr); @@ -143,6 +144,9 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, free_mem_end_ptr = free_mem_ptr_end_p; __machine_arch_type = arch_id; +#ifdef CONFIG_ARCH_EP93XX + ep93xx_decomp_setup(); +#endif arch_decomp_setup(); putstr("Uncompressing Linux..."); diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 88d5ecc2121e..fef802b7af8c 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -11,6 +11,8 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_MULTI_V4T=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_EP93XX=y CONFIG_MACH_ADSSPHERE=y CONFIG_MACH_EDB9301=y diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 15c68a646d51..aa502ab57404 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -1,4 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_EP93XX + bool "EP93xx-based" + depends on ARCH_MULTI_V4T + select ARCH_SPARSEMEM_ENABLE + select ARM_AMBA + select ARM_VIC + select CLKSRC_MMIO + select CPU_ARM920T + select GPIOLIB + help + This enables support for the Cirrus EP93xx series of CPUs. + if ARCH_EP93XX menu "Cirrus EP93xx Implementation Options" diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h deleted file mode 100644 index e20bcab702b2..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-ep93xx/include/mach/uncompress.h - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include - -static unsigned char __raw_readb(unsigned int ptr) -{ - return *((volatile unsigned char *)ptr); -} - -static unsigned int __raw_readl(unsigned int ptr) -{ - return *((volatile unsigned int *)ptr); -} - -static void __raw_writeb(unsigned char value, unsigned int ptr) -{ - *((volatile unsigned char *)ptr) = value; -} - -static void __raw_writel(unsigned int value, unsigned int ptr) -{ - *((volatile unsigned int *)ptr) = value; -} - -#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00) -#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18) -#define UART_FLAG_TXFF 0x20 - -static inline void putc(int c) -{ - int i; - - for (i = 0; i < 10000; i++) { - /* Transmit fifo not full? */ - if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) - break; - } - - __raw_writeb(c, PHYS_UART_DATA); -} - -static inline void flush(void) -{ -} - - -/* - * Some bootloaders don't turn off DMA from the ethernet MAC before - * jumping to linux, which means that we might end up with bits of RX - * status and packet data scribbled over the uncompressed kernel image. - * Work around this by resetting the ethernet MAC before we uncompress. - */ -#define PHYS_ETH_SELF_CTL 0x80010020 -#define ETH_SELF_CTL_RESET 0x00000001 - -static void ethernet_reset(void) -{ - unsigned int v; - - /* Reset the ethernet MAC. */ - v = __raw_readl(PHYS_ETH_SELF_CTL); - __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); - - /* Wait for reset to finish. */ - while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) - ; -} - -#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000 -#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 -#define TS72XX_WDT_FEED_VAL 0x05 - -static void __maybe_unused ts72xx_watchdog_disable(void) -{ - __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE); - __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE); -} - -static void arch_decomp_setup(void) -{ - if (machine_is_ts72xx()) - ts72xx_watchdog_disable(); - ethernet_reset(); -} -- cgit v1.2.3 From 09f6b27d5ddd9ad0ec096d1b0f8decdacc70f0f8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 23 Feb 2014 11:30:13 +0100 Subject: ARM: dove: multiplatform support The dove platform is now ready to be enabled for multiplatform support, this patch does the switch over by modifying the Kconfig file, the defconfig and removing the last mach/*.h header that becomes obsolete with this. This work was originally done in 2015 as all the ARMv7 machiens gove moved over to multiplatform builds, but at the time it conflicted with some patches that Russell was trying to upstream, so we left it at that. I hope that there is no longer a need to keep dove separate from the rest, so we can either add it to the other ARMv7 platforms, or just replace it with the DT based platform code for the same hardware in mach-mvebu and remove mach-dove entirely. Acked-by: Andrew Lunn Cc: Russell King Cc: Jason Cooper Cc: Sebastian Hesselbarth Cc: Gregory Clement Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 14 ------------ arch/arm/configs/dove_defconfig | 2 ++ arch/arm/mach-dove/Kconfig | 16 +++++++++---- arch/arm/mach-dove/Makefile | 2 ++ arch/arm/mach-dove/include/mach/uncompress.h | 34 ---------------------------- 5 files changed, 16 insertions(+), 52 deletions(-) delete mode 100644 arch/arm/mach-dove/include/mach/uncompress.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2bd611beefe1..faf696173af7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -383,20 +383,6 @@ config ARCH_IXP4XX help Support for Intel's IXP4XX (XScale) family of processors. -config ARCH_DOVE - bool "Marvell Dove" - select CPU_PJ4 - select GPIOLIB - select HAVE_PCI - select MVEBU_MBUS - select PINCTRL - select PINCTRL_DOVE - select PLAT_ORION_LEGACY - select SPARSE_IRQ - select PM_GENERIC_DOMAINS if PM - help - Support for the Marvell Dove SoC 88AP510 - config ARCH_PXA bool "PXA2xx/PXA3xx-based" select ARCH_MTD_XIP diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 33074fdab2ea..f8fb4758f80d 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -8,6 +8,8 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y CONFIG_ARCH_DOVE=y CONFIG_MACH_DOVE_DB=y CONFIG_MACH_CM_A510=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 7747fe64420a..c30c69c664ea 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -1,7 +1,17 @@ # SPDX-License-Identifier: GPL-2.0 -if ARCH_DOVE +menuconfig ARCH_DOVE + bool "Marvell Dove" if ARCH_MULTI_V7 + select CPU_PJ4 + select GPIOLIB + select MVEBU_MBUS + select PINCTRL + select PINCTRL_DOVE + select PLAT_ORION_LEGACY + select PM_GENERIC_DOMAINS if PM + help + Support for the Marvell Dove SoC 88AP510 -menu "Marvell Dove Implementations" +if ARCH_DOVE config DOVE_LEGACY bool @@ -21,6 +31,4 @@ config MACH_CM_A510 Say 'Y' here if you want your kernel to support the CompuLab CM-A510 Board. -endmenu - endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index cdf163cab738..e83f6492834d 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include + obj-y += common.o obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h deleted file mode 100644 index ddf873f35e2b..000000000000 --- a/arch/arm/mach-dove/include/mach/uncompress.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define UART0_PHYS_BASE (0xf1000000 + 0x12000) - -#define UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) -#define UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) - -#define LSR_THRE 0x20 - -static inline void putc(const char c) -{ - int i; - - for (i = 0; i < 0x1000; i++) { - /* Transmit fifo not full? */ - if (*UART_LSR & LSR_THRE) - break; - } - - *UART_THR = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -- cgit v1.2.3 From 91276c0fa4b405c90d7a7fafdca84ae18a516bbf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 2 Apr 2022 12:29:36 +0200 Subject: ARM: s3c24xx: remove support for ISA drivers on BAST PC/104 BAST is the one machine that theoretically supports unmodified ISA drivers for hardware on its PC/104 connector, using a custom version of the inb()/outb() and inw()/outw() macros. This is incompatible with the generic version used in asm/io.h, and can't easily be used in a multiplatform kernel. Removing the special case for 16-bit I/O port access on BAST gets us closer to multiplatform, at the expense of any PC/104 users with 16-bit cards having to either use an older kernel or modify their ISA drivers to manually ioremap() the area and use readw()/write() in place of inw()/outw(). Either way is probably ok, given that there is a recurring discussion about dropping s3c24xx altogether, and many traditional ISA drivers are already gone. Machines other than BAST already have no support for ISA drivers, though a couple of them do map one of the external chip-selects into the ISA port range, using the same address for 8-bit and 16-bit I/O. It is unlikely that anything actually uses this mapping, but it's also easy to keep this working by mapping it to the normal platform-independent PCI I/O base that is otherwise unused on s3c24xx. The mach/map-base.h file is no longer referenced in global headers and can be moved into the platform directory. Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - arch/arm/mach-s3c/Kconfig.s3c24xx | 1 - arch/arm/mach-s3c/cpu.c | 2 +- arch/arm/mach-s3c/include/mach/io-s3c24xx.h | 50 ----------------------------- arch/arm/mach-s3c/include/mach/io.h | 8 ----- arch/arm/mach-s3c/include/mach/map-base.h | 42 ------------------------ arch/arm/mach-s3c/irq-pm-s3c24xx.c | 2 +- arch/arm/mach-s3c/mach-anubis.c | 5 --- arch/arm/mach-s3c/mach-bast.c | 5 --- arch/arm/mach-s3c/mach-osiris.c | 5 --- arch/arm/mach-s3c/mach-rx3715.c | 6 ---- arch/arm/mach-s3c/mach-smdk2416.c | 10 ------ arch/arm/mach-s3c/mach-smdk2440.c | 10 ------ arch/arm/mach-s3c/mach-smdk2443.c | 10 ------ arch/arm/mach-s3c/mach-vr1000.c | 5 --- arch/arm/mach-s3c/map-base.h | 48 +++++++++++++++++++++++++++ arch/arm/mach-s3c/map-s3c24xx.h | 2 +- arch/arm/mach-s3c/map-s3c64xx.h | 2 +- 18 files changed, 52 insertions(+), 162 deletions(-) delete mode 100644 arch/arm/mach-s3c/include/mach/io-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/io.h delete mode 100644 arch/arm/mach-s3c/include/mach/map-base.h create mode 100644 arch/arm/mach-s3c/map-base.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index faf696173af7..2242d2ae8854 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,7 +444,6 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GPIO_SAMSUNG select GPIOLIB - select NEED_MACH_IO_H select S3C2410_WATCHDOG select SAMSUNG_ATAGS select USE_OF diff --git a/arch/arm/mach-s3c/Kconfig.s3c24xx b/arch/arm/mach-s3c/Kconfig.s3c24xx index 000e3e234f71..d47df6427e89 100644 --- a/arch/arm/mach-s3c/Kconfig.s3c24xx +++ b/arch/arm/mach-s3c/Kconfig.s3c24xx @@ -181,7 +181,6 @@ config MACH_AML_M5900 config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" - select ISA select MACH_BAST_IDE select S3C2410_COMMON_DCLK select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ diff --git a/arch/arm/mach-s3c/cpu.c b/arch/arm/mach-s3c/cpu.c index 6e9772555f0d..05a6b4be1768 100644 --- a/arch/arm/mach-s3c/cpu.c +++ b/arch/arm/mach-s3c/cpu.c @@ -10,7 +10,7 @@ #include #include -#include +#include "map-base.h" #include "cpu.h" unsigned long samsung_cpu_id; diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h deleted file mode 100644 index 738b775d3336..000000000000 --- a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H -#define __ASM_ARM_ARCH_IO_S3C24XX_H - -#include - -/* - * ISA style IO, for each machine to sort out mappings for, - * if it implements it. We reserve two 16M regions for ISA, - * so the PC/104 can use separate addresses for 8-bit and - * 16-bit port I/O. - */ -#define PCIO_BASE S3C_ADDR(0x02000000) -#define IO_SPACE_LIMIT 0x00ffffff -#define S3C24XX_VA_ISA_WORD (PCIO_BASE) -#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000) - -#ifdef CONFIG_ISA - -#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p)) -#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p)) -#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p)) - -#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p)) -#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p)) -#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p)) - -#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l) -#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l) -#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l) - -#else - -#define __io(x) (PCIO_BASE + (x)) - -#endif - -#endif diff --git a/arch/arm/mach-s3c/include/mach/io.h b/arch/arm/mach-s3c/include/mach/io.h deleted file mode 100644 index 30a0135708dc..000000000000 --- a/arch/arm/mach-s3c/include/mach/io.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Krzysztof Kozlowski - */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "io-s3c24xx.h" -#endif diff --git a/arch/arm/mach-s3c/include/mach/map-base.h b/arch/arm/mach-s3c/include/mach/map-base.h deleted file mode 100644 index 34b39ded0e2e..000000000000 --- a/arch/arm/mach-s3c/include/mach/map-base.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C - Memory map definitions (virtual addresses) - */ - -#ifndef __ASM_PLAT_MAP_H -#define __ASM_PLAT_MAP_H __FILE__ - -/* Fit all our registers in at 0xF6000000 upwards, trying to use as - * little of the VA space as possible so vmalloc and friends have a - * better chance of getting memory. - * - * we try to ensure stuff like the IRQ registers are available for - * an single MOVS instruction (ie, only 8 bits of set data) - */ - -#define S3C_ADDR_BASE 0xF6000000 - -#ifndef __ASSEMBLY__ -#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) -#else -#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) -#endif - -#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ -#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ -#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ -#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ -#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ - -/* This is used for the CPU specific mappings that may be needed, so that - * they do not need to directly used S3C_ADDR() and thus make it easier to - * modify the space for mapping. - */ -#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) - -#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/mach-s3c/irq-pm-s3c24xx.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c index 4d5e28312d91..55f41135ad70 100644 --- a/arch/arm/mach-s3c/irq-pm-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-pm-s3c24xx.c @@ -15,7 +15,7 @@ #include "cpu.h" #include "pm.h" -#include +#include "map-base.h" #include "map-s3c.h" #include "regs-irq.h" diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 04147cc0adcc..60df40052209 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -57,11 +57,6 @@ static struct map_desc anubis_iodesc[] __initdata = { .pfn = __phys_to_pfn(0x0), .length = SZ_4M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(0x0), - .length = SZ_4M, - .type = MT_DEVICE, }, /* we could possibly compress the next set down into a set of smaller tables diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 27e8d5950228..5ac24e406157 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -75,11 +75,6 @@ static struct map_desc bast_iodesc[] __initdata = { .pfn = PA_CS2(BAST_PA_ISAIO), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, }, /* bast CPLD control registers, and external interrupt controls */ { diff --git a/arch/arm/mach-s3c/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c index 3aefb9d22340..8387773f4fd4 100644 --- a/arch/arm/mach-s3c/mach-osiris.c +++ b/arch/arm/mach-s3c/mach-osiris.c @@ -58,11 +58,6 @@ static struct map_desc osiris_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C2410_CS5), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS5), - .length = SZ_16M, - .type = MT_DEVICE, }, /* CPLD control registers */ diff --git a/arch/arm/mach-s3c/mach-rx3715.c b/arch/arm/mach-s3c/mach-rx3715.c index 9fd2d9dc3689..586cb0fdfce0 100644 --- a/arch/arm/mach-s3c/mach-rx3715.c +++ b/arch/arm/mach-s3c/mach-rx3715.c @@ -48,13 +48,7 @@ static struct map_desc rx3715_iodesc[] __initdata = { /* dump ISA space somewhere unused */ - { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS3), .length = SZ_1M, diff --git a/arch/arm/mach-s3c/mach-smdk2416.c b/arch/arm/mach-s3c/mach-smdk2416.c index 4d883a792cc6..38b4a7cd4178 100644 --- a/arch/arm/mach-s3c/mach-smdk2416.c +++ b/arch/arm/mach-s3c/mach-smdk2416.c @@ -53,16 +53,6 @@ static struct map_desc smdk2416_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-smdk2440.c b/arch/arm/mach-s3c/mach-smdk2440.c index 7f6fe0db04f3..392554b1eba2 100644 --- a/arch/arm/mach-s3c/mach-smdk2440.c +++ b/arch/arm/mach-s3c/mach-smdk2440.c @@ -43,16 +43,6 @@ static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-smdk2443.c b/arch/arm/mach-s3c/mach-smdk2443.c index fc54c91ade56..4c541a03e49e 100644 --- a/arch/arm/mach-s3c/mach-smdk2443.c +++ b/arch/arm/mach-s3c/mach-smdk2443.c @@ -40,16 +40,6 @@ static struct map_desc smdk2443_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = __phys_to_pfn(S3C2410_CS2), - .length = 0x10000, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, - .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), - .length = SZ_4M, - .type = MT_DEVICE, - }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, diff --git a/arch/arm/mach-s3c/mach-vr1000.c b/arch/arm/mach-s3c/mach-vr1000.c index 5c3d07cf2e79..3aa8c707f8a2 100644 --- a/arch/arm/mach-s3c/mach-vr1000.c +++ b/arch/arm/mach-s3c/mach-vr1000.c @@ -67,11 +67,6 @@ static struct map_desc vr1000_iodesc[] __initdata = { .pfn = PA_CS2(BAST_PA_ISAIO), .length = SZ_16M, .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, }, /* CPLD control registers, and external interrupt controls */ diff --git a/arch/arm/mach-s3c/map-base.h b/arch/arm/mach-s3c/map-base.h new file mode 100644 index 000000000000..463a995b399b --- /dev/null +++ b/arch/arm/mach-s3c/map-base.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C - Memory map definitions (virtual addresses) + */ + +#ifndef __ASM_PLAT_MAP_H +#define __ASM_PLAT_MAP_H __FILE__ + +/* Fit all our registers in at 0xF6000000 upwards, trying to use as + * little of the VA space as possible so vmalloc and friends have a + * better chance of getting memory. + * + * we try to ensure stuff like the IRQ registers are available for + * an single MOVS instruction (ie, only 8 bits of set data) + */ + +#define S3C_ADDR_BASE 0xF6000000 + +#ifndef __ASSEMBLY__ +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#else +#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) +#endif + +#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ +#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ +#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ +#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ + +/* ISA device mapping for BAST to use with inb()/outb() on 8-bit I/O. + * 16-bit I/O on BAST now requires driver modifications to manually + * ioremap CS3. + */ +#define S3C24XX_VA_ISA_BYTE PCI_IOBASE + +/* This is used for the CPU specific mappings that may be needed, so that + * they do not need to directly used S3C_ADDR() and thus make it easier to + * modify the space for mapping. + */ +#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) + +#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/mach-s3c/map-s3c24xx.h b/arch/arm/mach-s3c/map-s3c24xx.h index b5dba78a9dd7..f8d075b11d6f 100644 --- a/arch/arm/mach-s3c/map-s3c24xx.h +++ b/arch/arm/mach-s3c/map-s3c24xx.h @@ -9,7 +9,7 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H -#include +#include "map-base.h" #include "map-s3c.h" /* diff --git a/arch/arm/mach-s3c/map-s3c64xx.h b/arch/arm/mach-s3c/map-s3c64xx.h index d7740d2a77c4..9de1c58bcb06 100644 --- a/arch/arm/mach-s3c/map-s3c64xx.h +++ b/arch/arm/mach-s3c/map-s3c64xx.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H __FILE__ -#include +#include "map-base.h" #include "map-s3c.h" /* -- cgit v1.2.3 From c78a41fc04f0209cba1e62ccbe6a4844633515e7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 2 Apr 2022 15:28:18 +0200 Subject: ARM: s3c24xx: convert to sparse-irq As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 2 + arch/arm/mach-s3c/bast-ide.c | 2 +- arch/arm/mach-s3c/bast-irq.c | 2 +- arch/arm/mach-s3c/dev-audio-s3c64xx.c | 2 +- arch/arm/mach-s3c/dev-uart-s3c64xx.c | 2 +- arch/arm/mach-s3c/devs.c | 2 +- arch/arm/mach-s3c/gpio-samsung.c | 2 +- arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h | 213 ------------------------- arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h | 172 -------------------- arch/arm/mach-s3c/include/mach/irqs.h | 9 -- arch/arm/mach-s3c/irq-s3c24xx.c | 2 +- arch/arm/mach-s3c/irqs-s3c24xx.h | 219 ++++++++++++++++++++++++++ arch/arm/mach-s3c/irqs-s3c64xx.h | 172 ++++++++++++++++++++ arch/arm/mach-s3c/irqs.h | 9 ++ arch/arm/mach-s3c/mach-amlm5900.c | 2 + arch/arm/mach-s3c/mach-anubis.c | 1 + arch/arm/mach-s3c/mach-anw6410.c | 2 +- arch/arm/mach-s3c/mach-at2440evb.c | 1 + arch/arm/mach-s3c/mach-bast.c | 1 + arch/arm/mach-s3c/mach-crag6410-module.c | 2 +- arch/arm/mach-s3c/mach-crag6410.c | 2 +- arch/arm/mach-s3c/mach-gta02.c | 1 + arch/arm/mach-s3c/mach-h1940.c | 1 + arch/arm/mach-s3c/mach-hmt.c | 2 +- arch/arm/mach-s3c/mach-jive.c | 2 +- arch/arm/mach-s3c/mach-mini2440.c | 3 +- arch/arm/mach-s3c/mach-mini6410.c | 2 +- arch/arm/mach-s3c/mach-n30.c | 2 + arch/arm/mach-s3c/mach-ncp.c | 2 +- arch/arm/mach-s3c/mach-nexcoder.c | 1 + arch/arm/mach-s3c/mach-osiris.c | 1 + arch/arm/mach-s3c/mach-otom.c | 1 + arch/arm/mach-s3c/mach-qt2410.c | 1 + arch/arm/mach-s3c/mach-real6410.c | 2 +- arch/arm/mach-s3c/mach-rx1950.c | 1 + arch/arm/mach-s3c/mach-rx3715.c | 1 + arch/arm/mach-s3c/mach-smartq5.c | 2 +- arch/arm/mach-s3c/mach-smartq7.c | 2 +- arch/arm/mach-s3c/mach-smdk2410.c | 1 + arch/arm/mach-s3c/mach-smdk2413.c | 3 + arch/arm/mach-s3c/mach-smdk2416.c | 1 + arch/arm/mach-s3c/mach-smdk2440.c | 1 + arch/arm/mach-s3c/mach-smdk2443.c | 2 +- arch/arm/mach-s3c/mach-smdk6400.c | 2 +- arch/arm/mach-s3c/mach-smdk6410.c | 2 +- arch/arm/mach-s3c/mach-tct_hammer.c | 1 + arch/arm/mach-s3c/mach-vr1000.c | 1 + arch/arm/mach-s3c/mach-vstms.c | 1 + arch/arm/mach-s3c/pl080.c | 2 +- arch/arm/mach-s3c/pm-core-s3c24xx.h | 2 +- arch/arm/mach-s3c/pm-s3c2412.c | 2 +- arch/arm/mach-s3c/pm-s3c64xx.c | 2 +- arch/arm/mach-s3c/pm.c | 2 +- arch/arm/mach-s3c/s3c2443.c | 2 +- arch/arm/mach-s3c/s3c24xx.h | 2 +- arch/arm/mach-s3c/s3c64xx.c | 2 +- arch/arm/mach-s3c/simtec-usb.c | 2 +- 57 files changed, 457 insertions(+), 424 deletions(-) delete mode 100644 arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h delete mode 100644 arch/arm/mach-s3c/include/mach/irqs.h create mode 100644 arch/arm/mach-s3c/irqs-s3c24xx.h create mode 100644 arch/arm/mach-s3c/irqs-s3c64xx.h create mode 100644 arch/arm/mach-s3c/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2242d2ae8854..c06e008c90ab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,8 +444,10 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GPIO_SAMSUNG select GPIOLIB + select IRQ_DOMAIN select S3C2410_WATCHDOG select SAMSUNG_ATAGS + select SPARSE_IRQ select USE_OF select WATCHDOG help diff --git a/arch/arm/mach-s3c/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c index da64db1811d8..67f0adc1fec0 100644 --- a/arch/arm/mach-s3c/bast-ide.c +++ b/arch/arm/mach-s3c/bast-ide.c @@ -20,7 +20,7 @@ #include #include "map.h" -#include +#include "irqs.h" #include "bast.h" diff --git a/arch/arm/mach-s3c/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c index d299f124e6dc..cfc2ddc65513 100644 --- a/arch/arm/mach-s3c/bast-irq.c +++ b/arch/arm/mach-s3c/bast-irq.c @@ -16,7 +16,7 @@ #include #include "regs-irq.h" -#include +#include "irqs.h" #include "bast.h" diff --git a/arch/arm/mach-s3c/dev-audio-s3c64xx.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c index fc2f077afd24..909e82c148ba 100644 --- a/arch/arm/mach-s3c/dev-audio-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c @@ -10,7 +10,7 @@ #include #include -#include +#include "irqs.h" #include "map.h" #include "devs.h" diff --git a/arch/arm/mach-s3c/dev-uart-s3c64xx.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c index 8288e8d6c092..f9c947b8971b 100644 --- a/arch/arm/mach-s3c/dev-uart-s3c64xx.c +++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c @@ -16,7 +16,7 @@ #include #include #include "map.h" -#include +#include "irqs.h" #include "devs.h" diff --git a/arch/arm/mach-s3c/devs.c b/arch/arm/mach-s3c/devs.c index 1e266fc24f9b..9ac07c023adf 100644 --- a/arch/arm/mach-s3c/devs.c +++ b/arch/arm/mach-s3c/devs.c @@ -38,7 +38,7 @@ #include #include -#include +#include "irqs.h" #include "map.h" #include "gpio-samsung.h" #include "gpio-cfg.h" diff --git a/arch/arm/mach-s3c/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index fda2c01f5a08..b7fc7c41309c 100644 --- a/arch/arm/mach-s3c/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -26,7 +26,7 @@ #include -#include +#include "irqs.h" #include "map.h" #include "regs-gpio.h" #include "gpio-samsung.h" diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h b/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h deleted file mode 100644 index aaf3bae08b52..000000000000 --- a/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks - */ - - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - */ - -#define S3C2410_CPUIRQ_OFFSET (16) - -#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) - -/* main cpu interrupts */ -#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ -#define IRQ_EINT1 S3C2410_IRQ(1) -#define IRQ_EINT2 S3C2410_IRQ(2) -#define IRQ_EINT3 S3C2410_IRQ(3) -#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ -#define IRQ_EINT8t23 S3C2410_IRQ(5) -#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ -#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ -#define IRQ_BATT_FLT S3C2410_IRQ(7) -#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ -#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ -#define IRQ_TIMER0 S3C2410_IRQ(10) -#define IRQ_TIMER1 S3C2410_IRQ(11) -#define IRQ_TIMER2 S3C2410_IRQ(12) -#define IRQ_TIMER3 S3C2410_IRQ(13) -#define IRQ_TIMER4 S3C2410_IRQ(14) -#define IRQ_UART2 S3C2410_IRQ(15) -#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ -#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ -#define IRQ_DMA1 S3C2410_IRQ(18) -#define IRQ_DMA2 S3C2410_IRQ(19) -#define IRQ_DMA3 S3C2410_IRQ(20) -#define IRQ_SDI S3C2410_IRQ(21) -#define IRQ_SPI0 S3C2410_IRQ(22) -#define IRQ_UART1 S3C2410_IRQ(23) -#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ -#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ -#define IRQ_USBD S3C2410_IRQ(25) -#define IRQ_USBH S3C2410_IRQ(26) -#define IRQ_IIC S3C2410_IRQ(27) -#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ -#define IRQ_SPI1 S3C2410_IRQ(29) -#define IRQ_RTC S3C2410_IRQ(30) -#define IRQ_ADCPARENT S3C2410_IRQ(31) - -/* interrupts generated from the external interrupts sources */ -#define IRQ_EINT0_2412 S3C2410_IRQ(32) -#define IRQ_EINT1_2412 S3C2410_IRQ(33) -#define IRQ_EINT2_2412 S3C2410_IRQ(34) -#define IRQ_EINT3_2412 S3C2410_IRQ(35) -#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ -#define IRQ_EINT5 S3C2410_IRQ(37) -#define IRQ_EINT6 S3C2410_IRQ(38) -#define IRQ_EINT7 S3C2410_IRQ(39) -#define IRQ_EINT8 S3C2410_IRQ(40) -#define IRQ_EINT9 S3C2410_IRQ(41) -#define IRQ_EINT10 S3C2410_IRQ(42) -#define IRQ_EINT11 S3C2410_IRQ(43) -#define IRQ_EINT12 S3C2410_IRQ(44) -#define IRQ_EINT13 S3C2410_IRQ(45) -#define IRQ_EINT14 S3C2410_IRQ(46) -#define IRQ_EINT15 S3C2410_IRQ(47) -#define IRQ_EINT16 S3C2410_IRQ(48) -#define IRQ_EINT17 S3C2410_IRQ(49) -#define IRQ_EINT18 S3C2410_IRQ(50) -#define IRQ_EINT19 S3C2410_IRQ(51) -#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ -#define IRQ_EINT21 S3C2410_IRQ(53) -#define IRQ_EINT22 S3C2410_IRQ(54) -#define IRQ_EINT23 S3C2410_IRQ(55) - -#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) -#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) - -#define IRQ_LCD_FIFO S3C2410_IRQ(56) -#define IRQ_LCD_FRAME S3C2410_IRQ(57) - -/* IRQs for the interal UARTs, and ADC - * these need to be ordered in number of appearance in the - * SUBSRC mask register -*/ - -#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) - -#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ -#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) -#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) - -#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ -#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) -#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) - -#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ -#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) -#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) - -#define IRQ_TC S3C2410_IRQSUB(9) -#define IRQ_ADC S3C2410_IRQSUB(10) - -/* extra irqs for s3c2412 */ - -#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) - -#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) -#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) - - -#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) -#define IRQ_S3C2416_DMA S3C2410_IRQ(17) -#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) -#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) -#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) - -#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) -#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) -#define IRQ_S32416_WDT S3C2410_IRQSUB(27) -#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) - -/* second interrupt-register of s3c2416/s3c2450 */ - -#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) -#define IRQ_S3C2416_2D S3C2416_IRQ(0) -#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) -#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) -#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3) -#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4) -#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5) -#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) -#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) - -/* extra irqs for s3c2440 */ - -#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ -#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ -#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) -#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) - -/* irqs for s3c2443 */ - -#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ -#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ -#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ -#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ -#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ - -#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ - -#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 -#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC - -#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) -#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) - -#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) - -/* UART3 */ -#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) -#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) -#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) - -#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) -#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) - -#if defined(CONFIG_CPU_S3C2416) -#define NR_IRQS (IRQ_S3C2416_I2S1 + 1) -#else -#define NR_IRQS (IRQ_S3C2443_AC97 + 1) -#endif - -/* compatibility define. */ -#define IRQ_UART3 IRQ_S3C2443_UART3 -#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 -#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 -#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 - -#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 -#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 - -#ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 -#else -#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 -#endif - -/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ -#define FIQ_START IRQ_EINT0 - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h b/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h deleted file mode 100644 index c244e480e6b3..000000000000 --- a/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - IRQ support - */ - -#ifndef __ASM_MACH_S3C64XX_IRQS_H -#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - * - * note, since we're using the VICs, our start must be a - * mulitple of 32 to allow the common code to work - */ - -#define S3C_IRQ_OFFSET (32) - -#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) - -#define IRQ_VIC0_BASE S3C_IRQ(0) -#define IRQ_VIC1_BASE S3C_IRQ(32) - -/* VIC based IRQs */ - -#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) -#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) - -/* VIC0 */ - -#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) -#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) -#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) -#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) -#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) -#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) -#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) -#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) -#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) -#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) -#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) -#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) -#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) -#define IRQ_2D S3C64XX_IRQ_VIC0(11) -#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) -#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) -#define IRQ_BATF S3C64XX_IRQ_VIC0(14) -#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) -#define IRQ_MFC S3C64XX_IRQ_VIC0(16) -#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) -#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) -#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) -#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) -#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) -#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) -#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) -#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) -#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) -#define IRQ_WDT S3C64XX_IRQ_VIC0(26) -#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) -#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) -#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) -#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) -#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) - -/* VIC1 */ - -#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) -#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) -#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) -#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) -#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) -#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) -#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) -#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) -#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) -#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) -#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) -#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) -#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) -#define IRQ_NFC S3C64XX_IRQ_VIC1(13) -#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) -#define IRQ_USBH S3C64XX_IRQ_VIC1(15) -#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) -#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) -#define IRQ_IIC S3C64XX_IRQ_VIC1(18) -#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) -#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) -#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) -#define IRQ_MSM S3C64XX_IRQ_VIC1(22) -#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) -#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) -#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) -#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ -#define IRQ_OTG S3C64XX_IRQ_VIC1(26) -#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) -#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) -#define IRQ_SEC S3C64XX_IRQ_VIC1(29) -#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) -#define IRQ_TC IRQ_PENDN -#define IRQ_ADC S3C64XX_IRQ_VIC1(31) - -/* compatibility for device defines */ - -#define IRQ_IIC1 IRQ_S3C6410_IIC1 - -/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series - * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE - * which we place after the pair of VICs. */ - -#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) - -#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) -#define IRQ_EINT(x) S3C_EINT(x) -#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) - -/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) - * that they are sourced from the GPIO pins but with a different scheme for - * priority and source indication. - * - * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO - * interrupts, but for historical reasons they are kept apart from these - * next interrupts. - * - * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the - * machine specific support files. - */ - -#define IRQ_EINT_GROUP1_NR (15) -#define IRQ_EINT_GROUP2_NR (8) -#define IRQ_EINT_GROUP3_NR (5) -#define IRQ_EINT_GROUP4_NR (14) -#define IRQ_EINT_GROUP5_NR (7) -#define IRQ_EINT_GROUP6_NR (10) -#define IRQ_EINT_GROUP7_NR (16) -#define IRQ_EINT_GROUP8_NR (15) -#define IRQ_EINT_GROUP9_NR (9) - -#define IRQ_EINT_GROUP_BASE S3C_EINT(28) -#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) -#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) -#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) -#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) -#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) -#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) -#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) -#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) -#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) - -#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) - -/* Some boards have their own IRQs behind this */ -#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) - -/* Set the default nr_irqs, boards can override if necessary */ -#define S3C64XX_NR_IRQS IRQ_BOARD_START - -/* Compatibility */ - -#define IRQ_ONENAND IRQ_ONENAND0 -#define IRQ_I2S0 IRQ_S3C6410_IIS - -#endif /* __ASM_MACH_S3C64XX_IRQS_H */ - diff --git a/arch/arm/mach-s3c/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs.h deleted file mode 100644 index 0bff1c1c8eb0..000000000000 --- a/arch/arm/mach-s3c/include/mach/irqs.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifdef CONFIG_ARCH_S3C24XX -#include "irqs-s3c24xx.h" -#endif - -#ifdef CONFIG_ARCH_S3C64XX -#include "irqs-s3c64xx.h" -#endif diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 3776d5206f9b..088cc04b7431 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -26,7 +26,7 @@ #include #include -#include +#include "irqs.h" #include "regs-irq.h" #include "regs-gpio.h" diff --git a/arch/arm/mach-s3c/irqs-s3c24xx.h b/arch/arm/mach-s3c/irqs-s3c24xx.h new file mode 100644 index 000000000000..fecbf7e440c6 --- /dev/null +++ b/arch/arm/mach-s3c/irqs-s3c24xx.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks + */ + + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + */ + +#define S3C2410_CPUIRQ_OFFSET (16) + +#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) + +/* main cpu interrupts */ +#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ +#define IRQ_EINT1 S3C2410_IRQ(1) +#define IRQ_EINT2 S3C2410_IRQ(2) +#define IRQ_EINT3 S3C2410_IRQ(3) +#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ +#define IRQ_EINT8t23 S3C2410_IRQ(5) +#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ +#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ +#define IRQ_BATT_FLT S3C2410_IRQ(7) +#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ +#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ +#define IRQ_TIMER0 S3C2410_IRQ(10) +#define IRQ_TIMER1 S3C2410_IRQ(11) +#define IRQ_TIMER2 S3C2410_IRQ(12) +#define IRQ_TIMER3 S3C2410_IRQ(13) +#define IRQ_TIMER4 S3C2410_IRQ(14) +#define IRQ_UART2 S3C2410_IRQ(15) +#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ +#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ +#define IRQ_DMA1 S3C2410_IRQ(18) +#define IRQ_DMA2 S3C2410_IRQ(19) +#define IRQ_DMA3 S3C2410_IRQ(20) +#define IRQ_SDI S3C2410_IRQ(21) +#define IRQ_SPI0 S3C2410_IRQ(22) +#define IRQ_UART1 S3C2410_IRQ(23) +#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ +#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ +#define IRQ_USBD S3C2410_IRQ(25) +#define IRQ_USBH S3C2410_IRQ(26) +#define IRQ_IIC S3C2410_IRQ(27) +#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ +#define IRQ_SPI1 S3C2410_IRQ(29) +#define IRQ_RTC S3C2410_IRQ(30) +#define IRQ_ADCPARENT S3C2410_IRQ(31) + +/* interrupts generated from the external interrupts sources */ +#define IRQ_EINT0_2412 S3C2410_IRQ(32) +#define IRQ_EINT1_2412 S3C2410_IRQ(33) +#define IRQ_EINT2_2412 S3C2410_IRQ(34) +#define IRQ_EINT3_2412 S3C2410_IRQ(35) +#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ +#define IRQ_EINT5 S3C2410_IRQ(37) +#define IRQ_EINT6 S3C2410_IRQ(38) +#define IRQ_EINT7 S3C2410_IRQ(39) +#define IRQ_EINT8 S3C2410_IRQ(40) +#define IRQ_EINT9 S3C2410_IRQ(41) +#define IRQ_EINT10 S3C2410_IRQ(42) +#define IRQ_EINT11 S3C2410_IRQ(43) +#define IRQ_EINT12 S3C2410_IRQ(44) +#define IRQ_EINT13 S3C2410_IRQ(45) +#define IRQ_EINT14 S3C2410_IRQ(46) +#define IRQ_EINT15 S3C2410_IRQ(47) +#define IRQ_EINT16 S3C2410_IRQ(48) +#define IRQ_EINT17 S3C2410_IRQ(49) +#define IRQ_EINT18 S3C2410_IRQ(50) +#define IRQ_EINT19 S3C2410_IRQ(51) +#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ +#define IRQ_EINT21 S3C2410_IRQ(53) +#define IRQ_EINT22 S3C2410_IRQ(54) +#define IRQ_EINT23 S3C2410_IRQ(55) + +#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) +#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) + +#define IRQ_LCD_FIFO S3C2410_IRQ(56) +#define IRQ_LCD_FRAME S3C2410_IRQ(57) + +/* IRQs for the interal UARTs, and ADC + * these need to be ordered in number of appearance in the + * SUBSRC mask register +*/ + +#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) + +#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ +#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) +#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) + +#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ +#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) +#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) + +#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ +#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) +#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) + +#define IRQ_TC S3C2410_IRQSUB(9) +#define IRQ_ADC S3C2410_IRQSUB(10) + +#define NR_IRQS_S3C2410 (S3C2410_IRQSUB(10) + 1) + +/* extra irqs for s3c2412 */ + +#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) + +#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) +#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) + +#define NR_IRQS_S3C2412 (S3C2410_IRQSUB(14) + 1) + +#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) +#define IRQ_S3C2416_DMA S3C2410_IRQ(17) +#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) +#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) +#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) + +#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) +#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) +#define IRQ_S32416_WDT S3C2410_IRQSUB(27) +#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) + +/* second interrupt-register of s3c2416/s3c2450 */ + +#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) +#define IRQ_S3C2416_2D S3C2416_IRQ(0) +#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) +#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) +#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3) +#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4) +#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5) +#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6) +#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7) + +#define NR_IRQS_S3C2416 (S3C2416_IRQ(7) + 1) + +/* extra irqs for s3c2440/s3c2442 */ + +#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ +#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ + +#define NR_IRQS_S3C2442 (S3C2410_IRQSUB(12) + 1) + +#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) +#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) + +#define NR_IRQS_S3C2440 (S3C2410_IRQSUB(14) + 1) + +/* irqs for s3c2443 */ + +#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ +#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ +#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ +#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ +#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ + +#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ + +#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 +#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC + +#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) +#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) + +#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) + +/* UART3 */ +#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) +#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) +#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) + +#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) +#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) + +#define NR_IRQS_S3C2443 (S3C2410_IRQSUB(28) + 1) + +/* compatibility define. */ +#define IRQ_UART3 IRQ_S3C2443_UART3 +#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 +#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 +#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 + +#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 +#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 + +#ifdef CONFIG_CPU_S3C2440 +#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 +#else +#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 +#endif + +/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ +#define FIQ_START IRQ_EINT0 + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c/irqs-s3c64xx.h b/arch/arm/mach-s3c/irqs-s3c64xx.h new file mode 100644 index 000000000000..c244e480e6b3 --- /dev/null +++ b/arch/arm/mach-s3c/irqs-s3c64xx.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - IRQ support + */ + +#ifndef __ASM_MACH_S3C64XX_IRQS_H +#define __ASM_MACH_S3C64XX_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S3C_IRQ_OFFSET (32) + +#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) + +#define IRQ_VIC0_BASE S3C_IRQ(0) +#define IRQ_VIC1_BASE S3C_IRQ(32) + +/* VIC based IRQs */ + +#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) + +/* VIC0 */ + +#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) +#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) +#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) +#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) +#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) +#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) +#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) +#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) +#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) +#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) +#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) +#define IRQ_2D S3C64XX_IRQ_VIC0(11) +#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) +#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) +#define IRQ_BATF S3C64XX_IRQ_VIC0(14) +#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) +#define IRQ_MFC S3C64XX_IRQ_VIC0(16) +#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) +#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) +#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) +#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) +#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) +#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) +#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) +#define IRQ_WDT S3C64XX_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) +#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) +#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) +#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) +#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) +#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) +#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) +#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) +#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) +#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) +#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) +#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) +#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) +#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) +#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) +#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) +#define IRQ_NFC S3C64XX_IRQ_VIC1(13) +#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) +#define IRQ_USBH S3C64XX_IRQ_VIC1(15) +#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) +#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) +#define IRQ_IIC S3C64XX_IRQ_VIC1(18) +#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) +#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) +#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) +#define IRQ_MSM S3C64XX_IRQ_VIC1(22) +#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) +#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) +#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S3C64XX_IRQ_VIC1(26) +#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) +#define IRQ_SEC S3C64XX_IRQ_VIC1(29) +#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S3C64XX_IRQ_VIC1(31) + +/* compatibility for device defines */ + +#define IRQ_IIC1 IRQ_S3C6410_IIC1 + +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE + * which we place after the pair of VICs. */ + +#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) + +#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) +#define IRQ_EINT(x) S3C_EINT(x) +#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) + +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP3_NR (5) +#define IRQ_EINT_GROUP4_NR (14) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +#define IRQ_EINT_GROUP7_NR (16) +#define IRQ_EINT_GROUP8_NR (15) +#define IRQ_EINT_GROUP9_NR (9) + +#define IRQ_EINT_GROUP_BASE S3C_EINT(28) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) + +/* Some boards have their own IRQs behind this */ +#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) + +/* Set the default nr_irqs, boards can override if necessary */ +#define S3C64XX_NR_IRQS IRQ_BOARD_START + +/* Compatibility */ + +#define IRQ_ONENAND IRQ_ONENAND0 +#define IRQ_I2S0 IRQ_S3C6410_IIS + +#endif /* __ASM_MACH_S3C64XX_IRQS_H */ + diff --git a/arch/arm/mach-s3c/irqs.h b/arch/arm/mach-s3c/irqs.h new file mode 100644 index 000000000000..0bff1c1c8eb0 --- /dev/null +++ b/arch/arm/mach-s3c/irqs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "irqs-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "irqs-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c index 94c4512ace17..f85e5885e9b4 100644 --- a/arch/arm/mach-s3c/mach-amlm5900.c +++ b/arch/arm/mach-s3c/mach-amlm5900.c @@ -239,7 +239,9 @@ static void __init amlm5900_init(void) MACHINE_START(AML_M5900, "AML_M5900") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = amlm5900_map_io, + .nr_irqs = NR_IRQS_S3C2410, .init_irq = s3c2410_init_irq, .init_machine = amlm5900_init, .init_time = amlm5900_init_time, diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 60df40052209..4536f3e66e27 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -414,6 +414,7 @@ static void __init anubis_init(void) MACHINE_START(ANUBIS, "Simtec-Anubis") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2440, .map_io = anubis_map_io, .init_machine = anubis_init, .init_irq = s3c2440_init_irq, diff --git a/arch/arm/mach-s3c/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c index 825714e9ac66..b67eae43e04f 100644 --- a/arch/arm/mach-s3c/mach-anw6410.c +++ b/arch/arm/mach-s3c/mach-anw6410.c @@ -40,7 +40,7 @@ #include "devs.h" #include "cpu.h" -#include +#include "irqs.h" #include "regs-gpio.h" #include "gpio-samsung.h" diff --git a/arch/arm/mach-s3c/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c index c6a5a51d84aa..743403d873e0 100644 --- a/arch/arm/mach-s3c/mach-at2440evb.c +++ b/arch/arm/mach-s3c/mach-at2440evb.c @@ -225,6 +225,7 @@ static void __init at2440evb_init(void) MACHINE_START(AT2440EVB, "AT2440EVB") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2440, .map_io = at2440evb_map_io, .init_machine = at2440evb_init, .init_irq = s3c2440_init_irq, diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 5ac24e406157..a33ceab81e09 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -575,6 +575,7 @@ static void __init bast_init(void) MACHINE_START(BAST, "Simtec-BAST") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = bast_map_io, .init_irq = s3c2410_init_irq, .init_machine = bast_init, diff --git a/arch/arm/mach-s3c/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c index 5d1d4b67a4b7..4edde13b89b5 100644 --- a/arch/arm/mach-s3c/mach-crag6410-module.c +++ b/arch/arm/mach-s3c/mach-crag6410-module.c @@ -28,7 +28,7 @@ #include #include "cpu.h" -#include +#include "irqs.h" #include "crag6410.h" diff --git a/arch/arm/mach-s3c/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c index e3e0fe897bcc..9a45474d1bf7 100644 --- a/arch/arm/mach-s3c/mach-crag6410.c +++ b/arch/arm/mach-s3c/mach-crag6410.c @@ -47,7 +47,7 @@ #include "map.h" #include "regs-gpio.h" #include "gpio-samsung.h" -#include +#include "irqs.h" #include "fb.h" #include "sdhci.h" diff --git a/arch/arm/mach-s3c/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c index 418939ce0fc3..abfdce765525 100644 --- a/arch/arm/mach-s3c/mach-gta02.c +++ b/arch/arm/mach-s3c/mach-gta02.c @@ -572,6 +572,7 @@ static void __init gta02_init_time(void) MACHINE_START(NEO1973_GTA02, "GTA02") /* Maintainer: Nelson Castillo */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2442, .map_io = gta02_map_io, .init_irq = s3c2442_init_irq, .init_machine = gta02_machine_init, diff --git a/arch/arm/mach-s3c/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c index 8a43ed1c4c4d..032b18837855 100644 --- a/arch/arm/mach-s3c/mach-h1940.c +++ b/arch/arm/mach-s3c/mach-h1940.c @@ -793,6 +793,7 @@ static void __init h1940_init(void) MACHINE_START(H1940, "IPAQ-H1940") /* Maintainer: Ben Dooks */ .atag_offset = 0x100, + .nr_irqs = NR_IRQS_S3C2410, .map_io = h1940_map_io, .reserve = h1940_reserve, .init_irq = s3c2410_init_irq, diff --git a/arch/arm/mach-s3c/mach-hmt.c b/arch/arm/mach-s3c/mach-hmt.c index b287e9987311..49ba16c447aa 100644 --- a/arch/arm/mach-s3c/mach-hmt.c +++ b/arch/arm/mach-s3c/mach-hmt.c @@ -26,7 +26,7 @@ #include