From 38fef73c21d117cf992fb5ec6e30630e54e13f4f Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Thu, 16 Jul 2015 10:37:31 +0300 Subject: xtensa: implement fake NMI In case perf IRQ is the highest of the medium-level IRQs, and is alone on its level, it may be treated as NMI: - LOCKLEVEL is defined to be one level less than EXCM level, - IRQ masking never lowers current IRQ level, - new fake exception cause code, EXCCAUSE_MAPPED_NMI is assigned to that IRQ; new second level exception handler, do_nmi, assigned to it handles it as NMI, - atomic operations in configurations without s32c1i still need to mask all interrupts. Cc: Peter Zijlstra Acked-by: Peter Zijlstra (Intel) Signed-off-by: Max Filippov --- arch/xtensa/kernel/irq.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/xtensa/kernel/irq.c') diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index 32b60568ee45..91ba60563021 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c @@ -29,6 +29,7 @@ #include atomic_t irq_err_count; +DECLARE_PER_CPU(unsigned long, nmi_count); asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs) { @@ -57,11 +58,18 @@ asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs) int arch_show_interrupts(struct seq_file *p, int prec) { + unsigned cpu __maybe_unused; #ifdef CONFIG_SMP show_ipi_list(p, prec); #endif seq_printf(p, "%*s: ", prec, "ERR"); seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); +#if XTENSA_FAKE_NMI + seq_printf(p, "%*s:", prec, "NMI"); + for_each_online_cpu(cpu) + seq_printf(p, " %10lu", per_cpu(nmi_count, cpu)); + seq_puts(p, " Non-maskable interrupts\n"); +#endif return 0; } -- cgit v1.2.3