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authorcvs2svn <>2011-04-28 20:46:35 +0400
committercvs2svn <>2011-04-28 20:46:35 +0400
commit987809e55fded80e657210e23938dc4a04cf49d9 (patch)
treef8d5d2f84cfd2b2f7c8233b624d19d6411827444 /include/opcode/sparc.h
parent5a90197d170232b79d26ee980ecc9771ea41c633 (diff)
This commit was manufactured by cvs2svn to create tag 'cgen-cgen-snapshot-20110501
snapshot-20110501'. Sprout from gdb_7_3-branch 2011-03-31 14:40:12 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'gdb_7_3-branch'.' Cherrypick from master 2011-04-28 16:46:34 UTC Joseph Myers <joseph@codesourcery.com> ' * configure.ac (*-*-dragonfly*, *-*-freebsd*, *-*-netbsd*,': ChangeLog Makefile.def Makefile.in Makefile.tpl config.sub config/ChangeLog config/bootstrap-lto.mk configure configure.ac Delete: djunpack.bat include/COPYING include/COPYING3 include/ChangeLog include/ChangeLog-9103 include/MAINTAINERS include/alloca-conf.h include/ansidecl.h include/aout/ChangeLog include/aout/adobe.h include/aout/aout64.h include/aout/ar.h include/aout/dynix3.h include/aout/encap.h include/aout/host.h include/aout/hp.h include/aout/hp300hpux.h include/aout/hppa.h include/aout/ranlib.h include/aout/reloc.h include/aout/stab.def include/aout/stab_gnu.h include/aout/sun4.h include/bfdlink.h include/binary-io.h include/bout.h include/cgen/ChangeLog include/cgen/basic-modes.h include/cgen/basic-ops.h include/cgen/bitset.h include/coff/ChangeLog include/coff/ChangeLog-9103 include/coff/alpha.h include/coff/apollo.h include/coff/arm.h include/coff/aux-coff.h include/coff/ecoff.h include/coff/external.h include/coff/go32exe.h include/coff/h8300.h include/coff/h8500.h include/coff/i386.h include/coff/i860.h include/coff/i960.h include/coff/ia64.h include/coff/internal.h include/coff/m68k.h include/coff/m88k.h include/coff/mcore.h include/coff/mips.h include/coff/mipspe.h include/coff/or32.h include/coff/pe.h include/coff/powerpc.h include/coff/rs6000.h include/coff/rs6k64.h include/coff/sh.h include/coff/sparc.h include/coff/sym.h include/coff/symconst.h include/coff/ti.h include/coff/tic30.h include/coff/tic4x.h include/coff/tic54x.h include/coff/tic80.h include/coff/w65.h include/coff/we32k.h include/coff/x86_64.h include/coff/xcoff.h include/coff/z80.h include/coff/z8k.h include/demangle.h include/dis-asm.h include/dwarf2.h include/dyn-string.h include/elf/ChangeLog include/elf/ChangeLog-9103 include/elf/alpha.h include/elf/arc.h include/elf/arm.h include/elf/avr.h include/elf/bfin.h include/elf/common.h include/elf/cr16.h include/elf/cr16c.h include/elf/cris.h include/elf/crx.h include/elf/d10v.h include/elf/d30v.h include/elf/dlx.h include/elf/dwarf.h include/elf/external.h include/elf/fr30.h include/elf/frv.h include/elf/h8.h include/elf/hppa.h include/elf/i370.h include/elf/i386.h include/elf/i860.h include/elf/i960.h include/elf/ia64.h include/elf/internal.h include/elf/ip2k.h include/elf/iq2000.h include/elf/lm32.h include/elf/m32c.h include/elf/m32r.h include/elf/m68hc11.h include/elf/m68k.h include/elf/mcore.h include/elf/mep.h include/elf/microblaze.h include/elf/mips.h include/elf/mmix.h include/elf/mn10200.h include/elf/mn10300.h include/elf/moxie.h include/elf/msp430.h include/elf/mt.h include/elf/openrisc.h include/elf/or32.h include/elf/pj.h include/elf/ppc.h include/elf/ppc64.h include/elf/reloc-macros.h include/elf/rx.h include/elf/s390.h include/elf/score.h include/elf/sh.h include/elf/sparc.h include/elf/spu.h include/elf/tic6x-attrs.h include/elf/tic6x.h include/elf/v850.h include/elf/vax.h include/elf/vxworks.h include/elf/x86-64.h include/elf/xc16x.h include/elf/xstormy16.h include/elf/xtensa.h include/fibheap.h include/filenames.h include/floatformat.h include/fnmatch.h include/fopen-bin.h include/fopen-same.h include/fopen-vms.h include/gdb/ChangeLog include/gdb/callback.h include/gdb/fileio.h include/gdb/remote-sim.h include/gdb/signals.def include/gdb/signals.h include/gdb/sim-arm.h include/gdb/sim-bfin.h include/gdb/sim-cr16.h include/gdb/sim-d10v.h include/gdb/sim-frv.h include/gdb/sim-h8300.h include/gdb/sim-lm32.h include/gdb/sim-m32c.h include/gdb/sim-ppc.h include/gdb/sim-rx.h include/gdb/sim-sh.h include/gdbm.h include/getopt.h include/hashtab.h include/hp-symtab.h include/ieee.h include/libiberty.h include/lto-symtab.h include/md5.h include/nlm/ChangeLog include/nlm/alpha-ext.h include/nlm/common.h include/nlm/external.h include/nlm/i386-ext.h include/nlm/internal.h include/nlm/ppc-ext.h include/nlm/sparc32-ext.h include/oasys.h include/objalloc.h include/obstack.h include/opcode/ChangeLog include/opcode/ChangeLog-9103 include/opcode/alpha.h include/opcode/arc.h include/opcode/arm.h include/opcode/avr.h include/opcode/bfin.h include/opcode/cgen.h include/opcode/convex.h include/opcode/cr16.h include/opcode/cris.h include/opcode/crx.h include/opcode/d10v.h include/opcode/d30v.h include/opcode/dlx.h include/opcode/h8300.h include/opcode/hppa.h include/opcode/i370.h include/opcode/i386.h include/opcode/i860.h include/opcode/i960.h include/opcode/ia64.h include/opcode/m68hc11.h include/opcode/m68k.h include/opcode/m88k.h include/opcode/mips.h include/opcode/mmix.h include/opcode/mn10200.h include/opcode/mn10300.h include/opcode/moxie.h include/opcode/msp430.h include/opcode/np1.h include/opcode/ns32k.h include/opcode/or32.h include/opcode/pdp11.h include/opcode/pj.h include/opcode/pn.h include/opcode/ppc.h include/opcode/pyr.h include/opcode/rx.h include/opcode/s390.h include/opcode/score-datadep.h include/opcode/score-inst.h include/opcode/sparc.h include/opcode/spu-insns.h include/opcode/spu.h include/opcode/tahoe.h include/opcode/tic30.h include/opcode/tic4x.h include/opcode/tic54x.h include/opcode/tic6x-control-registers.h include/opcode/tic6x-insn-formats.h include/opcode/tic6x-opcode-table.h include/opcode/tic6x.h include/opcode/tic80.h include/opcode/v850.h include/opcode/vax.h include/os9k.h include/partition.h include/plugin-api.h include/progress.h include/safe-ctype.h include/sha1.h include/simple-object.h include/som/ChangeLog include/som/aout.h include/som/clock.h include/som/internal.h include/som/lst.h include/som/reloc.h include/sort.h include/splay-tree.h include/symcat.h include/vms/ChangeLog include/vms/dcx.h include/vms/dmt.h include/vms/dsc.h include/vms/dst.h include/vms/eeom.h include/vms/egps.h include/vms/egsd.h include/vms/egst.h include/vms/egsy.h include/vms/eiaf.h include/vms/eicp.h include/vms/eidc.h include/vms/eiha.h include/vms/eihd.h include/vms/eihi.h include/vms/eihs.h include/vms/eihvn.h include/vms/eisd.h include/vms/emh.h include/vms/eobjrec.h include/vms/esdf.h include/vms/esdfm.h include/vms/esdfv.h include/vms/esgps.h include/vms/esrf.h include/vms/etir.h include/vms/internal.h include/vms/lbr.h include/vms/prt.h include/vms/shl.h include/xregex.h include/xregex2.h include/xtensa-config.h include/xtensa-isa-internal.h include/xtensa-isa.h texinfo/texinfo.tex
Diffstat (limited to 'include/opcode/sparc.h')
-rw-r--r--include/opcode/sparc.h237
1 files changed, 0 insertions, 237 deletions
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
deleted file mode 100644
index 0d6511c2a..000000000
--- a/include/opcode/sparc.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Definitions for opcode table for the sparc.
- Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
- 2003, 2005, 2010 Free Software Foundation, Inc.
-
- This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
- the GNU Binutils.
-
- GAS/GDB is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- GAS/GDB is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GAS or GDB; see the file COPYING3. If not, write to
- the Free Software Foundation, 51 Franklin Street - Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
-#include "ansidecl.h"
-
-/* The SPARC opcode table (and other related data) is defined in
- the opcodes library in sparc-opc.c. If you change anything here, make
- sure you fix up that file, and vice versa. */
-
- /* FIXME-someday: perhaps the ,a's and such should be embedded in the
- instruction's name rather than the args. This would make gas faster, pinsn
- slower, but would mess up some macros a bit. xoxorich. */
-
-/* List of instruction sets variations.
- These values are such that each element is either a superset of a
- preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
- returns non-zero.
- The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
- Don't change this without updating sparc-opc.c. */
-
-enum sparc_opcode_arch_val
-{
- SPARC_OPCODE_ARCH_V6 = 0,
- SPARC_OPCODE_ARCH_V7,
- SPARC_OPCODE_ARCH_V8,
- SPARC_OPCODE_ARCH_SPARCLET,
- SPARC_OPCODE_ARCH_SPARCLITE,
- /* V9 variants must appear last. */
- SPARC_OPCODE_ARCH_V9,
- SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
- SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
- SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
-};
-
-/* The highest architecture in the table. */
-#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
-
-/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
- insn encoding/decoding. */
-#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
-
-/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
-#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
-
-/* Table of cpu variants. */
-
-typedef struct sparc_opcode_arch
-{
- const char *name;
- /* Mask of sparc_opcode_arch_val's supported.
- EG: For v7 this would be
- (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
- These are short's because sparc_opcode.architecture is. */
- short supported;
-} sparc_opcode_arch;
-
-extern const struct sparc_opcode_arch sparc_opcode_archs[];
-
-/* Given architecture name, look up it's sparc_opcode_arch_val value. */
-extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
-
-/* Return the bitmask of supported architectures for ARCH. */
-#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
-
-/* Non-zero if ARCH1 conflicts with ARCH2.
- IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
-#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
- (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
- != SPARC_OPCODE_SUPPORTED (ARCH1)) \
- && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
- != SPARC_OPCODE_SUPPORTED (ARCH2)))
-
-/* Structure of an opcode table entry. */
-
-typedef struct sparc_opcode
-{
- const char *name;
- unsigned long match; /* Bits that must be set. */
- unsigned long lose; /* Bits that must not be set. */
- const char *args;
- /* This was called "delayed" in versions before the flags. */
- char flags;
- short architecture; /* Bitmask of sparc_opcode_arch_val's. */
-} sparc_opcode;
-
-#define F_DELAYED 1 /* Delayed branch. */
-#define F_ALIAS 2 /* Alias for a "real" instruction. */
-#define F_UNBR 4 /* Unconditional branch. */
-#define F_CONDBR 8 /* Conditional branch. */
-#define F_JSR 16 /* Subroutine call. */
-#define F_FLOAT 32 /* Floating point instruction (not a branch). */
-#define F_FBR 64 /* Floating point branch. */
-/* FIXME: Add F_ANACHRONISTIC flag for v9. */
-
-/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
- macro), which is 64 bits. It is handled as a special case.
-
- The match component is a mask saying which bits must match a particular
- opcode in order for an instruction to be an instance of that opcode.
-
- The args component is a string containing one character for each operand of the
- instruction.
-
- Kinds of operands:
- # Number used by optimizer. It is ignored.
- 1 rs1 register.
- 2 rs2 register.
- d rd register.
- e frs1 floating point register.
- v frs1 floating point register (double/even).
- V frs1 floating point register (quad/multiple of 4).
- f frs2 floating point register.
- B frs2 floating point register (double/even).
- R frs2 floating point register (quad/multiple of 4).
- g frsd floating point register.
- H frsd floating point register (double/even).
- J frsd floating point register (quad/multiple of 4).
- b crs1 coprocessor register
- c crs2 coprocessor register
- D crsd coprocessor register
- m alternate space register (asr) in rd
- M alternate space register (asr) in rs1
- h 22 high bits.
- X 5 bit unsigned immediate
- Y 6 bit unsigned immediate
- 3 SIAM mode (3 bits). (v9b)
- K MEMBAR mask (7 bits). (v9)
- j 10 bit Immediate. (v9)
- I 11 bit Immediate. (v9)
- i 13 bit Immediate.
- n 22 bit immediate.
- k 2+14 bit PC relative immediate. (v9)
- G 19 bit PC relative immediate. (v9)
- l 22 bit PC relative immediate.
- L 30 bit PC relative immediate.
- a Annul. The annul bit is set.
- A Alternate address space. Stored as 8 bits.
- C Coprocessor state register.
- F floating point state register.
- p Processor state register.
- N Branch predict clear ",pn" (v9)
- T Branch predict set ",pt" (v9)
- z %icc. (v9)
- Z %xcc. (v9)
- q Floating point queue.
- r Single register that is both rs1 and rd.
- O Single register that is both rs2 and rd.
- Q Coprocessor queue.
- S Special case.
- t Trap base register.
- w Window invalid mask register.
- y Y register.
- u sparclet coprocessor registers in rd position
- U sparclet coprocessor registers in rs1 position
- E %ccr. (v9)
- s %fprs. (v9)
- P %pc. (v9)
- W %tick. (v9)
- o %asi. (v9)
- 6 %fcc0. (v9)
- 7 %fcc1. (v9)
- 8 %fcc2. (v9)
- 9 %fcc3. (v9)
- ! Privileged Register in rd (v9)
- ? Privileged Register in rs1 (v9)
- * Prefetch function constant. (v9)
- x OPF field (v9 impdep).
- 0 32/64 bit immediate for set or setx (v9) insns
- _ Ancillary state register in rd (v9a)
- / Ancillary state register in rs1 (v9a)
-
- The following chars are unused: (note: ,[] are used as punctuation)
- [45]. */
-
-#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
-#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
-#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
-#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
-#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
-#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
-#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
-#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
-#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
-#define F1(x) (OP (x))
-#define DISP30(x) ((x) & 0x3fffffff)
-#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
-#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
-#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
-#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
-#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
-#define ASI_RS2(x) (SIMM13 (x))
-#define MEMBAR(x) ((x) & 0x7f)
-#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
-
-#define ANNUL (1 << 29)
-#define BPRED (1 << 19) /* V9. */
-#define IMMED F3I (1)
-#define RD_G0 RD (~0)
-#define RS1_G0 RS1 (~0)
-#define RS2_G0 RS2 (~0)
-
-extern const struct sparc_opcode sparc_opcodes[];
-extern const int sparc_num_opcodes;
-
-extern int sparc_encode_asi (const char *);
-extern const char *sparc_decode_asi (int);
-extern int sparc_encode_membar (const char *);
-extern const char *sparc_decode_membar (int);
-extern int sparc_encode_prefetch (const char *);
-extern const char *sparc_decode_prefetch (int);
-extern int sparc_encode_sparclet_cpreg (const char *);
-extern const char *sparc_decode_sparclet_cpreg (int);
-
-/* Local Variables:
- fill-column: 131
- comment-column: 0
- End: */
-