This commit was manufactured by cvs2svn to create branch 'jimb-jimb-macro-020506-branchpointjimb-macro-020506-branch

macro-020506-branch'.

Sprout from gdb_5_2-branch 2002-03-11 00:01:12 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'gdb_5_2-branch'.'
Cherrypick from master 2002-05-05 18:58:17 UTC Alexandre Oliva <aoliva@redhat.com> '* configure.in (noconfigdirs): Don't disable libgcj on':
    ChangeLog
    MAINTAINERS
    Makefile.in
    config.guess
    config.sub
    config/ChangeLog
    config/acinclude.m4
    config/mh-a68bsd
    config/mh-apollo68
    config/mh-cxux
    config/mh-decstation
    config/mh-dgux
    config/mh-dgux386
    config/mh-djgpp
    config/mh-hp300
    config/mh-hpux
    config/mh-hpux8
    config/mh-interix
    config/mh-irix5
    config/mh-irix6
    config/mh-lynxrs6k
    config/mh-mingw32
    config/mh-ncr3000
    config/mh-ncrsvr43
    config/mh-necv4
    config/mh-openedition
    config/mh-riscos
    config/mh-sco
    config/mh-solaris
    config/mh-sysv
    config/mh-sysv4
    config/mh-sysv5
    config/mt-aix43
    config/mt-alphaieee
    config/mt-linux
    configure
    configure.in
    include/ChangeLog
    include/coff/ChangeLog
    include/coff/rs6k64.h
    include/dyn-string.h
    include/elf/ChangeLog
    include/elf/dwarf2.h
    include/floatformat.h
    include/opcode/ChangeLog
    include/opcode/i386.h
    include/opcode/mips.h
    include/opcode/pdp11.h
    include/xregex2.h
    ltmain.sh
Delete:
    config/mh-irix4
    config/mh-lynxos
    config/mh-sun3
    config/mh-vaxult2
    config/mt-armpic
    config/mt-elfalphapic
    config/mt-i370pic
    config/mt-ia64pic
    config/mt-m68kpic
    config/mt-papic
    config/mt-ppcpic
    config/mt-s390pic
    config/mt-sparcpic
    config/mt-x86pic

4 files changed, 40 insertions, 6 deletions

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 8d637716b..2882ce568 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,19 @@
+2002-04-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386.h: Add intel mode cmpsd and movsd.
+	Put them before SSE2 insns, so that rep prefix works.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
+	instructions.
+	(OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
+	may be passed along with the ISA bitmask.
+
+2002-03-05  Paul Koning  <pkoning@equallogic.com>
+
+	* pdp11.h: Add format codes for float instruction formats.
+
 2002-02-25  Alan Modra  <amodra@bigpond.net.au>
 
 	* ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 43d7208ad..0171f62ed 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1231,6 +1231,9 @@ static const template i386_optab[] = {
 {"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
 {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
 {"cmppd",     3, 0x660fc2,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+/* Intel mode string compare.  */
+{"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
 {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
 {"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
 {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
@@ -1249,6 +1252,9 @@ static const template i386_optab[] = {
 {"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
 {"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
+/* Intel mode string move.  */
+{"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
 {"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
 {"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LongMem, 0 } },
 {"movupd",    2, 0x660f10,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 1469e1072..96c7a576e 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -316,6 +316,11 @@ struct mips_opcode
 #define INSN_ISA32                0x00000200
 #define INSN_ISA64                0x00000400
 
+/* Masks used for MIPS-defined ASEs.  */
+
+/* MIPS-3D ASE */
+#define INSN_MIPS3D               0x00004000
+
 /* Chip specific instructions.  These are bitmasks.  */
 
 /* MIPS R4650 instruction.  */
@@ -367,10 +372,10 @@ struct mips_opcode
 #define CPU_MIPS64      64
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 
-/* Test for membership in an ISA including chip specific ISAs.
-   INSN is pointer to an element of the opcode table; ISA is the
-   specified ISA to test against; and CPU is the CPU specific ISA
-   to test, or zero if no CPU specific ISA test is desired.  */
+/* Test for membership in an ISA including chip specific ISAs.  INSN
+   is pointer to an element of the opcode table; ISA is the specified
+   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
+   test, or zero if no CPU specific ISA test is desired.  */
 
 #define OPCODE_IS_MEMBER(insn, isa, cpu)				\
     (((insn)->membership & isa) != 0					\
diff --git a/include/opcode/pdp11.h b/include/opcode/pdp11.h
index 3cd7123b4..228c221fc 100644
--- a/include/opcode/pdp11.h
+++ b/include/opcode/pdp11.h
@@ -1,5 +1,5 @@
 /* PDP-11 opcde list.
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2002 Free Software Foundation, Inc.
 
 This file is part of GDB and GAS.
 
@@ -27,7 +27,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307
 #define PDP11_OPCODE_REG_OP	 3	/* register and generic operand */
 #define PDP11_OPCODE_REG_OP_REV	 4	/* register and generic operand,
 					   reversed syntax */
-#define PDP11_OPCODE_AC_OP	 5	/* fpu accumulator and generic
+#define PDP11_OPCODE_AC_FOP	 5	/* fpu accumulator and generic float
 					   operand */
 #define PDP11_OPCODE_OP_OP	 6	/* two generic operands */
 #define PDP11_OPCODE_DISPL	 7	/* pc-relative displacement */
@@ -37,6 +37,13 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307
 #define PDP11_OPCODE_IMM6	10	/* 6-bit immediate */
 #define PDP11_OPCODE_IMM3	11	/* 3-bit immediate */
 #define PDP11_OPCODE_ILLEGAL	12	/* illegal instruction */
+#define PDP11_OPCODE_FOP_AC	13	/* generic float argument, then fpu
+					   accumulator */
+#define PDP11_OPCODE_FOP	14	/* generic float operand */
+#define PDP11_OPCODE_AC_OP	15	/* fpu accumulator and generic int
+					   operand */
+#define PDP11_OPCODE_OP_AC	16	/* generic int argument, then fpu
+					   accumulator */
 
 /*
  * PDP-11 instruction set extensions.