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| author | Tamar Christina <tamar.christina@arm.com> | 2018-10-26 12:18:17 +0300 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-31 14:14:57 +0300 |
| commit | 9a7f131e0e4dcb4833c4b5eb8c04643a05c3c7e3 (patch) | |
| tree | 2616a62a4ad7afd3179a931992ac239a83c086c7 /libgloss/aarch64 | |
| parent | 2bbe8697d8f14eca88d8d45c11a5a58e879a3c0f (diff) | |
Initialize SVE system registers.
This patch initializes the SVE system registers if available
and initializes the vector length to the maximum supported.
This is done according to the SVE specification [1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
Diffstat (limited to 'libgloss/aarch64')
| -rw-r--r-- | libgloss/aarch64/cpu-init/rdimon-aem-el3.S | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/libgloss/aarch64/cpu-init/rdimon-aem-el3.S b/libgloss/aarch64/cpu-init/rdimon-aem-el3.S index 9edbccde5..e00f0b2c8 100644 --- a/libgloss/aarch64/cpu-init/rdimon-aem-el3.S +++ b/libgloss/aarch64/cpu-init/rdimon-aem-el3.S @@ -145,6 +145,33 @@ _flat_map: dsb sy msr sctlr_el3, x0 isb + + /* Determine if SVE is available. */ + mrs x0, id_aa64pfr0_el1 + tbz x0, 32, .Lnosve + + /* set up CPTR_EL3.TZ to 1. */ + mrs x0, cptr_el3 + + /* TZ is bit 8 of CPTR_EL3. */ + orr x0, x0, #0x100 + msr cptr_el3, x0 + isb + + /* set up vector lenght in ZCR_EL3 (4 LSB). */ + mov x2, #0xF + + /* Try to set the maximum value supported by the architecture (2048). + SVE Arch. + + "If this field is set to a value that is not supported by the + implementation then reading the register must return the highest + supported vector length that is less than the value written." */ + mrs x1, s3_6_c1_c2_0 /* mrs x1, zcr_el3. */ + bfi x1, x2, 0, 4 + msr s3_6_c1_c2_0, x1 /* msr zcr_el3, x1. */ + isb +.Lnosve: ret .data |