2006-01-16 Nathan Sidwell <nathan@codesourcery.com>

        * mt/Makefile.in (SCRIPTS, CRT0): Add ms2 files.
        (crt0-ms2.o): New target.
        * mt/crt0-ms2.S, mt/exit-ms2.c, mt/ms2.ld, mt/startup-ms2.S: New.

5 files changed, 1249 insertions, 4 deletions

diff --git a/libgloss/mt/Makefile.in b/libgloss/mt/Makefile.in
index d8d9fa182..031c864ba 100644
--- a/libgloss/mt/Makefile.in
+++ b/libgloss/mt/Makefile.in
@@ -56,10 +56,10 @@ OBJCOPY = `if [ -f ${objroot}/../binutils/objcopy ] ; \
 	then echo ${objroot}/../binutils/objcopy ; \
 	else t='$(program_transform_name)'; echo objcopy | sed -e $$t ; fi`
 
-SCRIPTS = 16-002.ld  16-003.ld  64-001.ld
-CRT0 = crt0.o crt0-64-001.o crt0-16-002.o crt0-16-003.o \
-	startup-64-001.o startup-16-002.o startup-16-003.o \
-	exit.o exit-64-001.o exit-16-002.o exit-16-003.o
+SCRIPTS = 16-002.ld  16-003.ld  64-001.ld ms2.ld
+CRT0 = crt0.o crt0-64-001.o crt0-16-002.o crt0-16-003.o crt0-ms2.o \
+	startup-64-001.o startup-16-002.o startup-16-003.o startup-ms2.o \
+	exit.o exit-64-001.o exit-16-002.o exit-16-003.o exit-ms2.o
 
 SIM_BSP = libsim.a
 SIM_OBJS = access.o chmod.o close.o \
@@ -97,6 +97,7 @@ crt0.o: $(srcdir)/crt0.S
 crt0-16-002.o: $(srcdir)/crt0-16-002.S
 crt0-16-003.o: $(srcdir)/crt0-16-003.S
 crt0-64-001.o: $(srcdir)/crt0-64-001.S
+crt0-ms2.o: $(srcdir)/crt0-ms2.S
 
 trap.o:	$(srcdir)/trap.S
 
diff --git a/libgloss/mt/crt0-ms2.S b/libgloss/mt/crt0-ms2.S
new file mode 100644
index 000000000..2efaebdea
--- /dev/null
+++ b/libgloss/mt/crt0-ms2.S
@@ -0,0 +1,121 @@
+; crt0.s - Startup code for the ms2. This code initializes the C
+;              run-time model.
+;
+;
+; Copyright 2001, 2002, 2003, 2004 Morpho Technologies
+;
+
+	; Create a label for the start of the eh_frame section.
+	.section .eh_frame
+__eh_frame_begin:
+
+	.text
+	.global	_start
+_start:
+	;; Initialize the stack pointer
+	ldui	sp, #%hi16(__stack)
+	addui	sp, sp, #%lo16(__stack)
+	or	fp, sp, sp
+	;; Zero the bss space
+	ldui	r9, #%hi16(__bss_start)
+	addui	r9, r9, #%lo16(__bss_start)
+	ldui	r10, #%hi16(__bss_end)
+	addui	r10, r10, #%lo16(__bss_end)
+	or	r0, r0, r0
+	brle	r10, r9, .Lnext1
+	or	r0, r0, r0
+.Lcpy0:	
+	stw	r0, r9, #0
+	addi	r9, r9, #4
+	or	r0, r0, r0	; nop
+	brle	r9, r10, .Lcpy0
+	or	r0, r0, r0	; nop
+
+.Lnext1:
+	;; Copy data from ROM to Frame Buffer (on-chip memory)
+	ldui	r9, #%hi16(_fbdata_start)
+	ori	r9, r9, #%lo16(_fbdata_start)
+	ldui	r10, #%hi16(_fbdata_end)
+	ori	r10, r10, #%lo16(_fbdata_end)
+	ldui	r11, #%hi16(_fbdata_vma)
+	brle	r10, r9, .Lnext2
+	ori	r11, r11, #%lo16(_fbdata_vma)
+.Lcpy1:
+	ldw	r5, r9, #$0
+	addi	r9, r9, #$4
+	stw	r5, r11, #$0
+	brlt	r9, r10, .Lcpy1
+	addi	r11, r11, #$4
+
+.Lnext2:
+	;; Zero the frame buffer bss section
+        ldui    r9, #%hi16(_fbbss_start)
+        ori     r9, r9, #%lo16(_fbbss_start)
+        ldui    r10, #%hi16(_fbbss_end)
+        ori     r10, r10, #%lo16(_fbbss_end)
+	or	r0, r0, r0
+	brle	r10, r9, .Lnext3
+	or	r0, r0, r0
+.Lcpy2:
+        stw     r0, r9, #$0
+        addi    r9, r9, #$4
+        or      r0, r0, r0
+        brle    r9, r10, .Lcpy2
+        or      r0, r0, r0
+
+.Lnext3:
+	;; Copy data from ROM to SRAM (another on-chip memory)
+	ldui	r9, #%hi16(_sram_data_start)
+	ori	r9, r9, #%lo16(_sram_data_start)
+	ldui	r10, #%hi16(_sram_data_end)
+	ori	r10, r10, #%lo16(_sram_data_end)
+	ldui	r11, #%hi16(_sram_data_vma)
+	brle	r10, r9, .Lnext4
+	ori	r11, r11, #%lo16(_sram_data_vma)
+.Lcpy3:
+	ldw	r5, r9, #$0
+	addi	r9, r9, #$4
+	stw	r5, r11, #$0
+	brlt	r9, r10, .Lcpy3
+	addi	r11, r11, #$4
+
+.Lnext4:
+	;; Call global and static constructors
+	ldui	r10, #%hi16(_init)
+	ori	r10, r10, #%lo16(_init)
+	or	r0, r0, r0	; nop
+	or	r0, r0, r0	; nop, added 06Sep05
+	jal	r14, r10
+	or	r0, r0, r0	; nop
+
+	;; Call main
+	ldui	r10, #%hi16(main)
+	ori	r10, r10, #%lo16(main)
+	or	r0, r0, r0	; nop
+	or	r0, r0, r0	; nop, added 06Sep05
+	jal	r14, r10
+	or	r0, r0, r0	; nop
+
+	;; DJK - Added 12Nov01. Pass main's return value to exit.
+	or	r1, r11, r0
+
+	;; Jump to exit
+	ldui	r10, #%hi16(exit)
+	ori	r10, r10, #%lo16(exit)
+	or	r0, r0, r0	; nop
+	or	r0, r0, r0	; nop, added 06Sep05
+	jal	r14, r10
+	or	r0, r0, r0	; nop
+
+	;; Exit does not return, however, this code is to catch an
+	;;   error if it does. Set the processor into sleep mode.
+	ori	r1, r0, #$1
+	stw	r1, r0, #%lo16(_DEBUG_HALT_REG)
+	or	r0, r0, r0
+	or	r0, r0, r0
+	or	r0, r0, r0
+	or	r0, r0, r0
+	or	r0, r0, r0
+.Lend:
+	jmp .Lend
+	or	r0, r0, r0
diff --git a/libgloss/mt/exit-ms2.c b/libgloss/mt/exit-ms2.c
new file mode 100644
index 000000000..93a3f852b
--- /dev/null
+++ b/libgloss/mt/exit-ms2.c
@@ -0,0 +1,12 @@
+#include <_ansi.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+
+void _exit (n)
+{
+  // Set bit #0 in the _DEBUG_HALT_REG to trigger program exit to
+  // the simulator. (The simulator will return a SIGQUIT signal.)
+  asm("ori r1, r0, #$1\n");
+  asm("stw r1, r0, #$fffff300\n");
+}  // exit
diff --git a/libgloss/mt/ms2.ld b/libgloss/mt/ms2.ld
new file mode 100644
index 000000000..0c6bdf20f
--- /dev/null
+++ b/libgloss/mt/ms2.ld
@@ -0,0 +1,271 @@
+OUTPUT_FORMAT("elf32-mt", "elf32-mt", "elf32-mt")
+OUTPUT_ARCH(mt)
+ENTRY(__boot_start)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x0, LENGTH = 16M
+  sram (wx) : ORIGIN = 0xfef00000, LENGTH = 64K
+  frame-buffer (w) : ORIGIN = 0xff000000, LENGTH = 80K
+  dma-ram (w) : ORIGIN = 0x1000000, LENGTH = 32M
+  ports (w) : ORIGIN = 0xfffff000, LENGTH = 4K
+}
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x0;
+  PROVIDE(__executable_start = 0x0);
+  .interp         : { *(.interp) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
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+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
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+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+
+  .startup        : { *startup-16-003.o(.startup) } >ram =0
+  . = 0x40;
+
+  .init           : { KEEP (*(.init)) } >ram =0
+  .plt            : { *(.plt) } >ram
+  .text           :
+  {
+    *startup-16-004.o(.text);
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >ram =0
+  .fini           : { KEEP (*(.fini)) } >ram =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram
+  .rodata1        : { *(.rodata1) } >ram
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) } >ram
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram
+  .eh_frame_hdr   : { *(.eh_frame_hdr) } >ram
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >ram
+  .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >ram
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(256) + (. & (256 - 1));
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >ram
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >ram
+  /* Thread Local Storage sections  */
+  .tdata          : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >ram
+  .tbss           : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array  : { *(.preinit_array) } >ram
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { *(.init_array) } >ram
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { *(.fini_array) } >ram
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >ram
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >ram
+  .jcr            : { KEEP (*(.jcr)) } >ram
+  .data.rel.ro    : { *(.data.rel.ro.local) *(.data.rel.ro*) } >ram
+  .dynamic        : { *(.dynamic) } >ram
+
+  /* DJK - Re-align the data section from the read-only section. */
+  . = ALIGN(16) + (. & (16 - 1));
+  PROVIDE (_data = .);
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >ram
+  .data1          : { *(.data1) } >ram
+  .got            : { *(.got.plt) *(.got) } >ram
+
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          : { *(.sdata .sdata.* .gnu.linkonce.s.*) } >ram
+  _edata = .;
+  PROVIDE ( edata = . );
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  } >ram
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+    . = ALIGN(32 / 8);
+  } >ram
+  . = ALIGN(32 / 8);
+  __bss_start = ADDR ( .sbss ) ;
+  __bss_end = __bss_start + SIZEOF ( .sbss ) + SIZEOF ( .bss ) - 4 ;
+  _end = .;
+  PROVIDE (end = .);
+
+  /* DJK - Initialized frame buffer data is copied from RAM to FB. */
+  .auxbss         : AT (ADDR(.bss) + SIZEOF(.bss)) { *(.auxbss) } >frame-buffer
+  .auxdata        : AT (LOADADDR(.auxbss) + SIZEOF(.auxbss))
+  {
+    *(.auxdata.bank0)
+    . = ALIGN(0x4000);
+    *(.auxdata.bank1)
+    . = ALIGN(0x4000);
+    *(.auxdata.bank2)
+    . = ALIGN(0x4000);
+    *(.auxdata.bank3)
+    . = ALIGN(0x4000);
+    *(.auxdata.bank4)
+    *(.auxdata)
+  } >frame-buffer
+
+  _fbbss_start = ADDR ( .auxbss );
+  _fbbss_end = _fbbss_start + SIZEOF ( .auxbss ) - 4;
+  _fbdata_start = LOADADDR ( .auxdata );
+  _fbdata_end = _fbdata_start + SIZEOF ( .auxdata ) ;
+  _fbdata_vma = ADDR ( .auxdata );
+
+  PROVIDE (__FRAME_BUFFER_START = ADDR(.auxbss) );
+  PROVIDE (__FRAME_BUFFER_SIZE = 0x14000);
+  PROVIDE (__FRAME_BUFFER_END = __FRAME_BUFFER_START + __FRAME_BUFFER_SIZE);
+
+  /* For now, locate data ahead of code in onchip sram/memory. */
+  .sram           : AT (LOADADDR(.auxdata) + SIZEOF(.auxdata))
+  {
+    *(.data.sram)
+    . = ALIGN(4) ; /* Make sure that instructions are aligned... */
+    *(.text.sram)
+  } >sram
+  
+  _sram_data_start = LOADADDR ( .sram );
+  _sram_data_end = _sram_data_start + SIZEOF ( .sram ) ;
+  _sram_data_vma = ADDR ( .sram );
+
+  .dma            : { _dma_start = .; *(.dma) _dma_end = .; } >dma-ram
+  .internal_io (NOLOAD) : { *(.internal_io) } >ports
+
+  /* Stabs debugging sections.  */
+  .stab            0 : { *(.stab) }
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+  .stab.indexstr   0 : { *(.stab.indexstr) }
+  .comment         0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug           0 : { *(.debug) }
+  .line            0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo   0 : { *(.debug_srcinfo) }
+  .debug_sfnames   0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges   0 : { *(.debug_aranges) }
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+  /* DWARF 2 */
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+  .debug_str       0 : { *(.debug_str) }
+  .debug_loc       0 : { *(.debug_loc) }
+  .debug_macinfo   0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  /* In a multi-core environment, each core is given its own stack space
+     equal to __stack_size, growing downwards. */
+  PROVIDE (__stack = 0x97ff0);
+  PROVIDE (__stack_size = 0x800);
+
+  .stack (DEFINED(__stack) ? __stack : 0x007ffff0) :
+  {
+     __stack = .;
+    *(.stack)
+    LONG(0xdeaddead)
+  }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/libgloss/mt/startup-ms2.S b/libgloss/mt/startup-ms2.S
new file mode 100644
index 000000000..f11e3fa6a
--- /dev/null
+++ b/libgloss/mt/startup-ms2.S
@@ -0,0 +1,840 @@
+/*
+ *
+ * interrupt_vectors.s -- the interrupt handler jump table. 
+ *
+ *
+ * There are a total of 32 interrupt vector possible, however, only
+ *   11 of those are currently used (the others are reserved). The
+ *   order of vectors is as follows:
+ *
+ *     1. Boot Vector. Vector for power-on/reset.
+ *     2. Software Vector. Vector for handling the SI instruction (an
+ *          explicit interrupt caused by software).
+ *     3. Break Vector. Vector for handling the Break instruction.
+ *     4. Device 0 Vector. Service vector for device zero. 
+ *     5. Device 1 Vector. Service vector for device one. 
+ *     6. Device 2 Vector. Service vector for device two. 
+ *     7. Device 3 Vector. Service vector for device three. 
+ *     8. Device 4 Vector. Service vector for device four. 
+ *     9. Device 5 Vector. Service vector for device five. 
+ *    10. Device 6 Vector. Service vector for device six. 
+ *    11. Device 7 Vector. Service vector for device seven. 
+ *
+ *   The rest of the interrupt vectors are reserved for future use.
+ *
+ *
+ * Each jump table entry consists of the following two instructions:
+ *
+ *   jmp Label		; Label as appropriate
+ *   nop 		; implemented as or r0,r0,r0
+ *
+ *   The following labels are reserved for the vectors named above,
+ *   respectively:
+ *
+ *     _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
+ *     _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
+ *
+ *   28Apr05 (DJK) Added support for the overflow vector.
+ *
+ *   XXXXXXX (DJK) Modified for the MS2 target
+ *
+ *   09Jan04 (DJK) Modified internal I/O port definitions for the
+ *                   MS1-16-003.
+ *
+ *   10Oct01 (DJK) The memory map is finalized and the first 4K of address
+ *                   space is now reserved for memory-mapped I/O devices.
+ *                   (There is over 2K unused, reserved space in this area.)
+ *
+ *   26Sep01 (DJK) The memory map is changed and the device interrupts are
+ *                   now memory-mapped.
+ *
+ *
+ *
+ * Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
+ *
+ */
+
+	.section .startup, "a", @progbits
+	.global __boot_start
+__boot_start:
+_INTERRUPT_VECTOR_TABLE:
+	jmp	_BOOTIVEC		; Boot vector
+	or	r0, r0, r0
+	jmp	_SOFTIVEC		; Vector for SI instruction
+	or	r0, r0, r0
+	jmp	_BRKIVEC		; Vector for Break instruction
+	or	r0, r0, r0
+	; The illegal instruction trap is not implemented.
+_RESERVED1_IVEC:
+	jmp	_RESERVED1_IVEC
+	or	r0, r0, r0
+	jmp	_OVFIVEC
+	or	r0, r0, r0
+_RESERVED2_IVEC:
+	jmp	_RESERVED2_IVEC
+	or	r0, r0, r0
+_RESERVED3_IVEC:
+	jmp	_RESERVED3_IVEC
+	or	r0, r0, r0
+_RESERVED4_IVEC:
+	jmp	_RESERVED4_IVEC
+	or	r0, r0, r0
+
+
+	.text
+
+	.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
+	.equ SI_IOPORT_BIT, 0x1
+	.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
+	.equ BRK_IOPORT_BIT, 0x1
+
+	.global _BOOTIVEC
+_BOOTIVEC:
+	; Initialize the interrupt controller's interrupt vector registers
+	ldui	r1, #%hi16(_IVEC_DEFAULT)
+	ori	r1, r1, #%lo16(_IVEC_DEFAULT)
+	stw	r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
+	stw	r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
+
+	; Statically initialized data must be copied from ROM to RAM.
+	; This is done in the C run-time start-up code (crt0.o).
+
+	; Jump to the beginning of the application and enable interrupts.
+	jmp	_start
+	ei
+
+
+	; Handler for the SI instruction. To perform a system call, the
+	; C model uses a trapping mechanism which executes an SI instruction.
+	; The Morpho Technologies simulator simply performs a branch to
+	; this vector to simulate the SI instruction (this is as the hardware
+	; behaves). In order to trigger the simulator that a system call
+	; is needed a write into the I/O register at address $40005 to
+	; set bit #2 (0x4) is necessary.
+	;
+	; The above address has been changed to 0x00031C and the bit number
+	; is zero. (The manifest constants have been changed to reflect this.)
+	.global _SOFTIVEC
+_SOFTIVEC:
+	; Build a frame to save registers.
+	subi	sp, sp, #$8
+	stw	r9, sp, #$4
+	ldui	r9, #%hi16(SI_IOPORT_ADR)
+	stw	r10, sp, #$0
+	ori	r9, r9, #%lo16(SI_IOPORT_ADR)
+	ori	r10, r0, #SI_IOPORT_BIT
+	stw	r10, r9, #$0
+	; SYS_call is handled by simulator here...
+	or	r0, r0, r0
+	ldw	r10, sp, #$0
+	or	r0, r0, r0
+	ldw	r9, sp, #$4
+	reti	r14
+	addi	sp, sp, #$8
+
+
+
+	.global _BRKIVEC
+_BRKIVEC:
+	; Build a frame to save registers.
+	subi	sp, sp, #$8
+	stw	r9, sp, #$4
+	ldui	r9, #%hi16(BRK_IOPORT_ADR)
+	stw	r10, sp, #$0
+	ori	r9, r9, #%lo16(BRK_IOPORT_ADR)
+	ori	r10, r0, #BRK_IOPORT_BIT
+	stw	r10, r9, #$0
+	or	r0, r0, r0
+	or	r0, r0, r0
+	or	r0, r0, r0
+	or	r0, r0, r0
+	or	r0, r0, r0
+	ldw	r10, sp, #$0
+	ldw	r9, sp, #$4
+	reti	r15
+	addi	sp, sp, #$8
+
+
+	.global _OVFIVEC
+_OVFIVEC:
+	addi	r15, r15, #$4
+	or	r0, r0, r0
+	or	r0, r0, r0	; added 06Sep05
+	reti	r15
+	or	r0, r0, r0
+
+
+	.global _IVEC_DEFAULT
+_IVEC_DEFAULT:
+	reti	r15
+	or	r0, r0, r0
+
+
+	.section .internal_io, "a", @progbits
+	.fill 256		; Fill the first page.
+
+	; This is the memory-mapped I/O region.
+
+	; Hardware Interrupt Registers
+	;.org 0xfffff100
+	.global _DEV0_INTERRUPT_REG
+_DEV0_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV1_INTERRUPT_REG
+_DEV1_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV2_INTERRUPT_REG
+_DEV2_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV3_INTERRUPT_REG
+_DEV3_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV4_INTERRUPT_REG
+_DEV4_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV5_INTERRUPT_REG
+_DEV5_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV6_INTERRUPT_REG
+_DEV6_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV7_INTERRUPT_REG
+_DEV7_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV8_INTERRUPT_REG
+_DEV8_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV9_INTERRUPT_REG
+_DEV9_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV10_INTERRUPT_REG
+_DEV10_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV11_INTERRUPT_REG
+_DEV11_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV12_INTERRUPT_REG
+_DEV12_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV13_INTERRUPT_REG
+_DEV13_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV14_INTERRUPT_REG
+_DEV14_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV15_INTERRUPT_REG
+_DEV15_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV16_INTERRUPT_REG
+_DEV16_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV17_INTERRUPT_REG
+_DEV17_INTERRUPT_REG:
+	.word	0x00000000
+
+	.global _DEV18_INTERRUPT_REG
+_DEV18_INTERRUPT_REG:
+	.word	0x00000000
+
+	; 128 bytes minus nineteen registers (four bytes per register)
+	.fill (128 - 19 * 4)
+
+	.global	_INTERRUPT_MASK_REG
+_INTERRUPT_MASK_REG:
+	.word	0x00000000
+
+	.global	_INTERRUPT_PENDING_REG
+_INTERRUPT_PENDING_REG:
+	.word	0x00000000
+
+	; 16 bytes minus two registers (four bytes per register)
+	.fill (16 - 2 * 4)
+
+	.global _DEV0_INTERRUPT_LEVEL_REG
+_DEV0_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV1_INTERRUPT_LEVEL_REG
+_DEV1_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV2_INTERRUPT_LEVEL_REG
+_DEV2_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV3_INTERRUPT_LEVEL_REG
+_DEV3_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV4_INTERRUPT_LEVEL_REG
+_DEV4_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV5_INTERRUPT_LEVEL_REG
+_DEV5_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV6_INTERRUPT_LEVEL_REG
+_DEV6_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV7_INTERRUPT_LEVEL_REG
+_DEV7_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV8_INTERRUPT_LEVEL_REG
+_DEV8_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV9_INTERRUPT_LEVEL_REG
+_DEV9_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV10_INTERRUPT_LEVEL_REG
+_DEV10_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV11_INTERRUPT_LEVEL_REG
+_DEV11_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV12_INTERRUPT_LEVEL_REG
+_DEV12_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV13_INTERRUPT_LEVEL_REG
+_DEV13_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV14_INTERRUPT_LEVEL_REG
+_DEV14_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV15_INTERRUPT_LEVEL_REG
+_DEV15_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV16_INTERRUPT_LEVEL_REG
+_DEV16_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV17_INTERRUPT_LEVEL_REG
+_DEV17_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	.global _DEV18_INTERRUPT_LEVEL_REG
+_DEV18_INTERRUPT_LEVEL_REG:
+	.word	0x00000000
+
+	; 128 bytes minus twenty-three registers (four bytes per register)
+	.fill (128 - 23 * 4)
+
+
+	;.org 0xfffff200
+	; MorphoSys Decoder Registers
+	.global _MS_DEC_CIRC_BUFF_SEL_REG
+_MS_DEC_CIRC_BUFF_SEL_REG:
+	.word	0x00000000
+
+	.global _MS_DEC_SKIP_FACTOR_REG
+_MS_DEC_SKIP_FACTOR_REG:
+	.word	0x00000000
+
+	.global _MS_DEC_CUSTOM_PERM_REG
+_MS_DEC_CUSTOM_PERM_REG:
+	.word	0x00000000
+
+	.global _MS_DEC_CTXT_BASE_REG
+_MS_DEC_CTXT_BASE_REG:
+	.word	0x00000000
+
+	.global _MS_DEC_LOOKUP_TBL_REG
+_MS_DEC_LOOKUP_TBL_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF0_I_REG
+_MS_CIRC_BUFF0_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF0_P_REG
+_MS_CIRC_BUFF0_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF0_B_REG
+_MS_DATA_BUFF0_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF0_S_REG
+_MS_DATA_BUFF0_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF1_I_REG
+_MS_CIRC_BUFF1_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF1_P_REG
+_MS_CIRC_BUFF1_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF1_B_REG
+_MS_DATA_BUFF1_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF1_S_REG
+_MS_DATA_BUFF1_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF2_I_REG
+_MS_CIRC_BUFF2_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF2_P_REG
+_MS_CIRC_BUFF2_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF2_B_REG
+_MS_DATA_BUFF2_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF2_S_REG
+_MS_DATA_BUFF2_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF3_I_REG
+_MS_CIRC_BUFF3_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF3_P_REG
+_MS_CIRC_BUFF3_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF3_B_REG
+_MS_DATA_BUFF3_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF3_S_REG
+_MS_DATA_BUFF3_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF4_I_REG
+_MS_CIRC_BUFF4_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF4_P_REG
+_MS_CIRC_BUFF4_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF4_B_REG
+_MS_DATA_BUFF4_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF4_S_REG
+_MS_DATA_BUFF4_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF5_I_REG
+_MS_CIRC_BUFF5_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF5_P_REG
+_MS_CIRC_BUFF5_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF5_B_REG
+_MS_DATA_BUFF5_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF5_S_REG
+_MS_DATA_BUFF5_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF6_I_REG
+_MS_CIRC_BUFF6_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF6_P_REG
+_MS_CIRC_BUFF6_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF6_B_REG
+_MS_DATA_BUFF6_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF6_S_REG
+_MS_DATA_BUFF6_S_REG:
+	.word	0x00000000
+
+	.global _MS_CIRC_BUFF7_I_REG
+_MS_CIRC_BUFF7_I_REG:
+	.word (__FRAME_BUFFER_END)
+
+	.global _MS_CIRC_BUFF7_P_REG
+_MS_CIRC_BUFF7_P_REG:
+	.word __FRAME_BUFFER_SIZE
+
+	.global _MS_DATA_BUFF7_B_REG
+_MS_DATA_BUFF7_B_REG:
+	.word	0x00000000
+
+	.global _MS_DATA_BUFF7_S_REG
+_MS_DATA_BUFF7_S_REG:
+	.word	0x00000000
+
+	.global _MS_OMEGA_PERM1_REG
+_MS_OMEGA_PERM1_REG:
+	.word	0x00000000
+
+	.global _MS_WRITE_FB_ADDR_REG
+_MS_WRITE_FB_ADDR_REG:
+	.word	0x00000000
+
+	.global _MS_OMEGA_PERM2_REG
+_MS_OMEGA_PERM2_REG:
+	.word	0x00000000
+
+
+	; 256 bytes minus forty registers (four bytes per register)
+	.fill (256 - 40 * 4)
+
+
+
+	;.org 0xfffff300
+	; Debug Registers
+	.global _DEBUG_HALT_REG
+_DEBUG_HALT_REG:
+	.word	0x00000000
+
+	.global _DEBUG_BREAK_REG
+_DEBUG_BREAK_REG:
+	.word	0x00000000
+
+	.global _DEBUG_CRITICAL_REG
+_DEBUG_OWNERSHIP_REG:
+	.word	0x00000000
+
+	.global _DEBUG_KERNEL_ID_REG
+_DEBUG_KERNEL_ID_REG:
+	.word	0x00000000
+
+	.global _DEBUG_IRQ_STATUS_REG
+_DEBUG_IRQ_STATUS_REG:
+	.word	0x00000000
+
+	; There are two reserved registers.
+	.fill (2 * 4)
+
+	.global _DEBUG_SW_SYSREQ_REG
+_DEBUG_SW_SYSREQ_REG:
+	.word	0x00000000
+
+	; 128 bytes minus eight registers (four bytes per register)
+	.fill (128 - 8 * 4)
+
+	.global _EXTENDED_GP0_REG
+_EXTENDED_GP0_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP1_REG
+_EXTENDED_GP1_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP2_REG
+_EXTENDED_GP2_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP3_REG
+_EXTENDED_GP3_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP4_REG
+_EXTENDED_GP4_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP5_REG
+_EXTENDED_GP5_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP6_REG
+_EXTENDED_GP6_REG:
+	.word	0x00000000
+
+	.global _EXTENDED_GP7_REG
+_EXTENDED_GP7_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_EN_NC_MEM_REG
+_MEM_CTRL_EN_NC_MEM_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_BASE0_ADDR_REG
+_MEM_CTRL_BASE0_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_MASK0_ADDR_REG
+_MEM_CTRL_MASK0_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_BASE1_ADDR_REG
+_MEM_CTRL_BASE1_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_MASK1_ADDR_REG
+_MEM_CTRL_MASK1_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_BASE2_ADDR_REG
+_MEM_CTRL_BASE2_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_MASK2_ADDR_REG
+_MEM_CTRL_MASK2_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_BASE3_ADDR_REG
+_MEM_CTRL_BASE3_ADDR_REG:
+	.word	0x00000000
+
+	.global _MEM_CTRL_MASK3_ADDR_REG
+_MEM_CTRL_MASK3_ADDR_REG:
+	.word	0x00000000
+
+	; 128 bytes minus seventeen registers (four bytes per register)
+	.fill (128 - 17 * 4)
+
+
+
+	; Reserved memory-map space
+	.fill (256 + 256)
+
+
+
+	;.org 0xfffff600
+	; Timer Registers
+	.global _TIMER0_VAL_REG
+_TIMER0_VAL_REG:
+	.word	0x00000000
+
+	.global _TIMER1_VAL_REG
+_TIMER1_VAL_REG:
+	.word	0x00000000
+
+	.global _TIMER2_VAL_REG
+_TIMER2_VAL_REG:
+	.word	0x00000000
+
+	.global _TIMER3_VAL_REG
+_TIMER3_VAL_REG:
+	.word	0x00000000
+
+	; 256 bytes minus four registers (four bytes per register)
+	.fill (256 - 4 * 4)
+
+
+
+	;.org 0xfffff700
+	; Output Line Control Registers
+	.global _OUTPUT0_CTRL
+_OUTPUT0_CTRL:
+	.word	0x00000000
+
+	.global _OUTPUT1_CTRL
+_OUTPUT1_CTRL:
+	.word	0x00000000
+
+	.global _OUTPUT2_CTRL
+_OUTPUT2_CTRL:
+	.word	0x00000000
+
+	.global _OUTPUT3_CTRL
+_OUTPUT3_CTRL:
+	.word	0x00000000
+
+	.global _OUTPUT4_CTRL
+_OUTPUT4_CTRL:
+	.word	0x00000000
+
+	.global _OUTPUT5_CTRL
+_OUTPUT5_CTRL:
+	.word	0x00000000
+
+	.global _OUTPUT6_CTRL
+_OUTPUT6_CTRL:
+	.word	0x00000000
+
+	; 128 bytes minus seven registers (four bytes per register)
+	.fill (128 - 7 * 4)
+
+	.global _INPUT0_CTRL
+_INPUT0_CTRL:
+	.word	0x00000000
+
+	; 128 bytes minus one register (four bytes per register)
+	.fill (128 - 1 * 4)
+
+
+
+	;.org 0xfffff800
+	; IQ Buffer Registers
+	.global _IQ_BUFF_CTRL_REG
+_IQ_BUFF_CTRL_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_STATUS_REG
+_IQ_BUFF_STATUS_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_PARAMETER1_REG
+_IQ_BUFF_PARAMETER1_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_TRANSFER_SIZE1_REG
+_IQ_BUFF_TRANSFER_SIZE1_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_FB_BASE1_REG
+_IQ_BUFF_FB_BASE1_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_FB_SIZE1_REG
+_IQ_BUFF_FB_SIZE1_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_PARAMETER2_REG
+_IQ_BUFF_PARAMETER2_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_TRANSFER_SIZE2_REG
+_IQ_BUFF_TRANSFER_SIZE2_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_FB_BASE2_REG
+_IQ_BUFF_FB_BASE2_REG:
+	.word	0x00000000
+
+	.global _IQ_BUFF_FB_SIZE2_REG
+_IQ_BUFF_FB_SIZE2_REG:
+	.word	0x00000000
+
+	; 256 bytes minus ten registers (four bytes per register)
+	.fill (256 - 10 * 4)
+
+
+
+	;.org 0xfffff900
+	; DMA Controller
+	.global _DMA_CTRL_REG
+_DMA_CTRL_REG:
+	.word	0x00000000
+
+	.global _DMA_STATUS_REG
+_DMA_STATUS_REG:
+	.word	0x00000000
+
+	.global _DMA_CH0_EADDR_REG
+_DMA_CH0_EADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH0_IADDR_REG
+_DMA_CH0_IADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH0_SIZE_REG
+_DMA_CH0_SIZE_REG:
+	.word	0x00000000
+
+	.global _DMA_CH1_EADDR_REG
+_DMA_CH1_EADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH1_IADDR_REG
+_DMA_CH1_IADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH1_SIZE_REG
+_DMA_CH1_SIZE_REG:
+	.word	0x00000000
+
+	.global _DMA_CH2_EADDR_REG
+_DMA_CH2_EADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH2_IADDR_REG
+_DMA_CH2_IADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH2_SIZE_REG
+_DMA_CH2_SIZE_REG:
+	.word	0x00000000
+
+	.global _DMA_CH3_EADDR_REG
+_DMA_CH3_EADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH3_IADDR_REG
+_DMA_CH3_IADDR_REG:
+	.word	0x00000000
+
+	.global _DMA_CH3_SIZE_REG
+_DMA_CH3_SIZE_REG:
+	.word	0x00000000
+
+	; 256 bytes minus fourteen registers (four bytes per register)
+	.fill (256 - 14 * 4)
+
+
+
+	;.org 0xfffffa00
+	; Sequence Generator
+	.global _SEQ_GEN_CTRL_STATUS_REG
+_SEQ_GEN_CTRL_STATUS_REG:
+	.word	0x00000000
+
+	.global _SEQ_GEN_MASK_REGS
+_SEQ_GEN_MASK_REGS:
+	.fill (302 * 4)
+
+	.global _SEQ_GEN_SHIFT_REG
+_SEQ_GEN_SHIFT_REG:
+	.word	0x00000000
+
+	; 256 bytes minus seven registers (four bytes per register)
+	.fill (256 - 48 * 4)
+
+
+
+	; Reserved memory-map space
+	.fill (0x1000 - 0xf00)