diff options
author | DJ Delorie <dj@redhat.com> | 2015-01-17 01:21:34 +0300 |
---|---|---|
committer | DJ Delorie <dj@redhat.com> | 2015-01-17 01:21:34 +0300 |
commit | 70e52cba1b27fe65dc743b44bb73dc1a5c718bbe (patch) | |
tree | 0fcaa64a3af83dd1d81ae49b4b3128d2916bc5bb /libgloss/rl78/rl78.ld | |
parent | a62dbcd6e03ff182e7d36ea60d953f447db72d62 (diff) |
* rl78/crt0.S: Initialize .saddr. Avoid using SEL.
* rl78/rl78-sim.ld: Add .saddr/.frodata section.
* rl78/rl78.ld: Likewise.
* rl78/rl78-sim.ld: Make room for virtual register banks.
* rl78/rl78.ld: Likewise.
* rl78/vregs.h: New.
* rl78-sys.h: Use it.
* rl78/swrite.S: New.
* rl78/Makefile.in: Build it.
* rl78/write.c: Use it.
Diffstat (limited to 'libgloss/rl78/rl78.ld')
-rw-r--r-- | libgloss/rl78/rl78.ld | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/libgloss/rl78/rl78.ld b/libgloss/rl78/rl78.ld index f062e2c90..ab137f50f 100644 --- a/libgloss/rl78/rl78.ld +++ b/libgloss/rl78/rl78.ld @@ -43,8 +43,10 @@ MEMORY { IVEC (r) : ORIGIN = 0x00004, LENGTH = 0x0007c OPT (r) : ORIGIN = 0x000c0, LENGTH = 0x00004 ROM (r) : ORIGIN = 0x000d8, LENGTH = 0x0ff28 - RAM (w) : ORIGIN = 0xfef00, LENGTH = 0x00fe0 - STACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002 +/* The G10 variant needs to use RAM for virtual registers. */ + RAM (w) : ORIGIN = 0xfef00, LENGTH = 0x00f20 + STACK (w) : ORIGIN = 0xffe20, LENGTH = 0x00002 + SADDR (w) : ORIGIN = 0xffe20, LENGTH = 0x000a0 } SECTIONS @@ -126,6 +128,15 @@ SECTIONS *(.stack) } + .saddr : { + . = ALIGN(2); + PROVIDE (__saddrstart = .); + *(.saddr) + . = ALIGN(2); + } >SADDR AT>ROM + PROVIDE(__romsaddrstart = LOADADDR(.saddr)); + PROVIDE (__romsaddrcopysize = SIZEOF(.saddr)); + .rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : { . = ALIGN(2); *(.plt) @@ -169,6 +180,10 @@ SECTIONS KEEP (*(.dtors)) } > ROM + .frodata : { + *(.frodata) + } > ROM + .text : { PROVIDE (_start = .); @@ -210,7 +225,7 @@ SECTIONS /* DWARF 2 */ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } |