ARC: Use new definitions for optional ARC CPU features

GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:

    * __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
      -mbarrel-shifter
    * __ARC_LL64__ instead of __LL64__ for -mll64
    * __ARCEM__ instead of __EM__ for -mcpu=arcem
    * __ARCHS__ instead of __HS__ for -mcpu=archs
    * etc (not used in newlib)

This patch updates assembly routines for ARC to use new definitions instead
of a deprecated ones. To ensure compatibility with older compiler new
definitions are also defined in asm.h if needed, based on deprecated
preprocessor definitions.

*** newlib/ChangeLog ***
2015-12-15  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* libc/machine/arc/asm.h: Define new GCC definition for old compiler.
	* libc/machine/arc/memcmp-bs-norm.S: Use new GCC defines to detect
	  processor features.
	* libc/machine/arc/memcmp.S: Likewise.
	* libc/machine/arc/memcpy-archs.S: Likewise.
	* libc/machine/arc/memcpy-bs.S: Likewise.
	* libc/machine/arc/memcpy.S: Likewise.
	* libc/machine/arc/memset-archs.S: Likewise.
	* libc/machine/arc/memset-bs.S: Likewise.
	* libc/machine/arc/memset.S: Likewise.
	* libc/machine/arc/setjmp.S: Likewise.
	* libc/machine/arc/strchr-bs-norm.S: Likewise.
	* libc/machine/arc/strchr-bs.S: Likewise.
	* libc/machine/arc/strchr.S: Likewise.
	* libc/machine/arc/strcmp-archs.S: Likewise.
	* libc/machine/arc/strcmp.S: Likewise.
	* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
	* libc/machine/arc/strcpy-bs.S: Likewise.
	* libc/machine/arc/strcpy.S: Likewise.
	* libc/machine/arc/strlen-bs-norm.S: Likewise.
	* libc/machine/arc/strlen-bs.S: Likewise.
	* libc/machine/arc/strlen.S: Likewise.
	* libc/machine/arc/strncpy-bs.S: Likewise.
	* libc/machine/arc/strncpy.S: Likewise.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>

1 files changed, 15 insertions, 13 deletions

diff --git a/newlib/libc/machine/arc/memcmp-bs-norm.S b/newlib/libc/machine/arc/memcmp-bs-norm.S
index 990ceef75..be2464ac0 100644
--- a/newlib/libc/machine/arc/memcmp-bs-norm.S
+++ b/newlib/libc/machine/arc/memcmp-bs-norm.S
@@ -35,7 +35,9 @@
 
 #include "asm.h"
 
-#if !defined (__ARC601__) && defined (__ARC_NORM__) && defined (__Xbarrel_shifter)
+#if !defined (__ARC601__) && defined (__ARC_NORM__) \
+    && defined (__ARC_BARREL_SHIFTER__)
+
 #ifdef __LITTLE_ENDIAN__
 #define WORD2 r2
 #define SHIFT r3
@@ -47,7 +49,7 @@
 ENTRY (memcmp)
 	or	r12,r0,r1
 	asl_s	r12,r12,30
-#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
+#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
 	sub_l	r3,r2,1
 	brls	r2,r12,.Lbytewise
 #else
@@ -57,7 +59,7 @@ ENTRY (memcmp)
 	ld	r4,[r0,0]
 	ld	r5,[r1,0]
 	lsr.f	lp_count,r3,3
-#ifdef __EM__
+#ifdef __ARCEM__
 	/* A branch can't be the last instruction in a zero overhead loop.
 	   So we move the branch to the start of the loop, duplicate it
 	   after the end, and set up r12 so that the branch isn't taken
@@ -74,12 +76,12 @@ ENTRY (memcmp)
 	brne	r4,r5,.Leven
 	ld.a	r4,[r0,8]
 	ld.a	r5,[r1,8]
-#ifdef __EM__
+#ifdef __ARCEM__
 .Loop_end:
 	brne	WORD2,r12,.Lodd
 #else
 	brne	WORD2,r12,.Lodd
-#ifdef __HS__
+#ifdef __ARCHS__
 	nop
 #endif
 .Loop_end:
@@ -90,7 +92,7 @@ ENTRY (memcmp)
 	ld	r4,[r0,4]
 	ld	r5,[r1,4]
 #ifdef __LITTLE_ENDIAN__
-#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
+#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
 	nop_s
 	; one more load latency cycle
 .Last_cmp:
@@ -167,14 +169,14 @@ ENTRY (memcmp)
 	bset.cs	r0,r0,31
 .Lodd:
 	cmp_s	WORD2,r12
-#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
+#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
 	mov_s	r0,1
 	j_s.d	[blink]
 	bset.cs	r0,r0,31
-#else /* !__ARC700__ */
+#else
 	j_s.d	[blink]
 	rrc	r0,2
-#endif /* !__ARC700__ */
+#endif /* __ARC700__ || __ARCEM__ || __ARCHS__ */
 #endif /* ENDIAN */
 	.balign	4
 .Lbytewise:
@@ -182,7 +184,7 @@ ENTRY (memcmp)
 	ldb	r4,[r0,0]
 	ldb	r5,[r1,0]
 	lsr.f	lp_count,r3
-#ifdef __EM__
+#ifdef __ARCEM__
 	mov	r12,r3
 	lpne	.Lbyte_end
 	brne	r3,r12,.Lbyte_odd
@@ -194,12 +196,12 @@ ENTRY (memcmp)
 	brne	r4,r5,.Lbyte_even
 	ldb.a	r4,[r0,2]
 	ldb.a	r5,[r1,2]
-#ifdef __EM__
+#ifdef __ARCEM__
 .Lbyte_end:
 	brne	r3,r12,.Lbyte_odd
 #else
 	brne	r3,r12,.Lbyte_odd
-#ifdef __HS__
+#ifdef __ARCHS__
 	nop
 #endif
 .Lbyte_end:
@@ -218,6 +220,6 @@ ENTRY (memcmp)
 	j_s.d	[blink]
 	mov_l	r0,0
 ENDFUNC (memcmp)
-#endif /* !__ARC601__ && __ARC_NORM__ && __Xbarrel_shifter */
+#endif /* !__ARC601__ && __ARC_NORM__ && __ARC_BARREL_SHIFTER__ */
 
 #endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */