diff options
author | Anton Kolesov <Anton.Kolesov@synopsys.com> | 2015-10-23 21:24:50 +0300 |
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committer | Corinna Vinschen <corinna@vinschen.de> | 2015-11-12 16:14:17 +0300 |
commit | c0a99f02933e1e58197e61d0b2c6e0b3824a2119 (patch) | |
tree | 62baf46db6e25fb589f83cb1b2aabd945f9b32ca /newlib/libc/machine/arc/strlen-bs-norm.S | |
parent | acdfcb0a0af54715bc37ed1c767bfe901b679357 (diff) |
Add support for ARC to newlib
newlib/ChangeLog:
2015-11-12 Anton Kolesov <Anton.Kolesov@synopsys.com>
* configure.host: Add ARC support.
* libc/include/machine/setjmp.h: Likewise.
* libc/machine/configure: Likewise.
* libc/machine/configure.in: Likewise.
* libc/machine/arc/Makefile.am: Likewise.
* libc/machine/arc/Makefile.in: Likewise.
* libc/machine/arc/aclocal.m4: Likewise.
* libc/machine/arc/asm.h: Likewise.
* libc/machine/arc/configure: Likewise.
* libc/machine/arc/configure.in: Likewise.
* libc/machine/arc/memcmp-bs-norm.S: Likewise.
* libc/machine/arc/memcmp-stub.c: Likewise.
* libc/machine/arc/memcmp.S: Likewise.
* libc/machine/arc/memcpy-archs.S: Likewise.
* libc/machine/arc/memcpy-bs.S: Likewise.
* libc/machine/arc/memcpy-stub.c: Likewise.
* libc/machine/arc/memcpy.S: Likewise.
* libc/machine/arc/memset-archs.S: Likewise.
* libc/machine/arc/memset-bs.S: Likewise.
* libc/machine/arc/memset-stub.c: Likewise.
* libc/machine/arc/memset.S: Likewise.
* libc/machine/arc/setjmp.S: Likewise.
* libc/machine/arc/strchr-bs-norm.S: Likewise.
* libc/machine/arc/strchr-bs.S: Likewise.
* libc/machine/arc/strchr-stub.c: Likewise.
* libc/machine/arc/strchr.S: Likewise.
* libc/machine/arc/strcmp-archs.S: Likewise.
* libc/machine/arc/strcmp-stub.c: Likewise.
* libc/machine/arc/strcmp.S: Likewise.
* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
* libc/machine/arc/strcpy-bs.S: Likewise.
* libc/machine/arc/strcpy-stub.c: Likewise.
* libc/machine/arc/strcpy.S: Likewise.
* libc/machine/arc/strlen-bs-norm.S: Likewise.
* libc/machine/arc/strlen-bs.S: Likewise.
* libc/machine/arc/strlen-stub.c: Likewise.
* libc/machine/arc/strlen.S: Likewise.
* libc/machine/arc/strncpy-bs.S: Likewise.
* libc/machine/arc/strncpy-stub.c: Likewise.
* libc/machine/arc/strncpy.S: Likewise.
Diffstat (limited to 'newlib/libc/machine/arc/strlen-bs-norm.S')
-rw-r--r-- | newlib/libc/machine/arc/strlen-bs-norm.S | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/newlib/libc/machine/arc/strlen-bs-norm.S b/newlib/libc/machine/arc/strlen-bs-norm.S new file mode 100644 index 000000000..32312404d --- /dev/null +++ b/newlib/libc/machine/arc/strlen-bs-norm.S @@ -0,0 +1,115 @@ +/* + Copyright (c) 2015, Synopsys, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + 1) Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2) Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3) Neither the name of the Synopsys, Inc., nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* This implementation is optimized for performance. For code size a generic + implementation of this function from newlib/libc/string/strlen.c will be + used. */ +#if !defined (__OPTIMIZE_SIZE__) && !defined (PREFER_SIZE_OVER_SPEED) + +#include "asm.h" +#if (defined (__ARC700__) || defined (__EM__) || defined (__HS__)) \ + && defined (__ARC_NORM__) && defined (__Xbarrel_shifter) + +ENTRY (strlen) + or r3,r0,7 + ld r2,[r3,-7] + ld.a r6,[r3,-3] + mov r4,0x01010101 + ; uses long immediate +#ifdef __LITTLE_ENDIAN__ + asl_s r1,r0,3 + btst_s r0,2 + asl r7,r4,r1 + ror r5,r4 + sub r1,r2,r7 + bic_s r1,r1,r2 + mov.eq r7,r4 + sub r12,r6,r7 + bic r12,r12,r6 + or.eq r12,r12,r1 + and r12,r12,r5 + brne r12,0,.Learly_end +#else /* BIG ENDIAN */ + ror r5,r4 + btst_s r0,2 + mov_s r1,31 + sub3 r7,r1,r0 + sub r1,r2,r4 + bic_s r1,r1,r2 + bmsk r1,r1,r7 + sub r12,r6,r4 + bic r12,r12,r6 + bmsk.ne r12,r12,r7 + or.eq r12,r12,r1 + and r12,r12,r5 + brne r12,0,.Learly_end +#endif /* ENDIAN */ + +.Loop: + ld_s r2,[r3,4] + ld.a r6,[r3,8] + ; stall for load result + sub r1,r2,r4 + bic_s r1,r1,r2 + sub r12,r6,r4 + bic r12,r12,r6 + or_l r12,r12,r1 + and r12,r12,r5 + breq_l r12,0,.Loop +.Lend: + and.f r1,r1,r5 + sub.ne r3,r3,4 + mov.eq r1,r12 +#ifdef __LITTLE_ENDIAN__ + sub_s r2,r1,1 + bic_s r2,r2,r1 + norm r1,r2 + sub_s r0,r0,3 + lsr_s r1,r1,3 + sub r0,r3,r0 + j_s.d [blink] + sub_l r0,r0,r1 +#else /* BIG ENDIAN */ + lsr_s r1,r1,7 + mov.eq r2,r6 + bic_s r1,r1,r2 + norm r1,r1 + sub r0,r3,r0 + lsr_s r1,r1,3 + j_s.d [blink] + add_l r0,r0,r1 +#endif /* ENDIAN */ +.Learly_end: + b.d .Lend + sub_s.ne r1,r1,r1 +ENDFUNC (strlen) +#endif /* (__ARC700__ || __EM__ || __HS__) && __ARC_NORM__ && _Xbarrel_shifter */ + +#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */ |