diff options
| author | Jeff Johnston <jjohnstn@redhat.com> | 2016-05-02 19:04:40 +0300 |
|---|---|---|
| committer | Jeff Johnston <jjohnstn@redhat.com> | 2016-05-02 19:04:40 +0300 |
| commit | 11afe8f6b65d391ab47e3948c469a0c28c1b41eb (patch) | |
| tree | 21a53870a5c3bf33d8ffd87470ea8283462c0db0 /newlib/testsuite | |
| parent | cd494f7038ac739bee69775f91e02693f2734e79 (diff) | |
Fix support ARC processors without barrel-shifter
crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.
Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/crt0.S: Fix support for processors without barrel-shifter.
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
Diffstat (limited to 'newlib/testsuite')
0 files changed, 0 insertions, 0 deletions