diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 21 | ||||
| -rw-r--r-- | include/opcode/m68hc11.h | 21 | ||||
| -rw-r--r-- | include/opcode/mips.h | 1 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 24 |
4 files changed, 60 insertions, 7 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 385b19152..b950eefc3 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,24 @@ +2002-08-19 Elena Zannoni <ezannoni@redhat.com> + + From matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 + instructions. + (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, + PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the + e500x2 Integer select, branch locking, performance monitor, + cache locking and machine check APUs, respectively. + (PPC_OPCODE_EFS): New opcode type for efs* instructions. + (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11.h (M6812_OP_PAGE): Define to identify call operand. + (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, + M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 + memory banks. + (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value. + 2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> * mips.h (INSN_MIPS16): New define. diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h index 52a246130..a538026f8 100644 --- a/include/opcode/m68hc11.h +++ b/include/opcode/m68hc11.h @@ -1,6 +1,6 @@ /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright 1999, 2000 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. @@ -191,7 +191,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * /* Flags of the SPSR register. */ #define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ #define M6811_WCOL 0x40 /* Write Collision */ -#define M6811_MODF 0x20 /* Mode Fault */ +#define M6811_MODF 0x10 /* Mode Fault */ /* Flags of the ADCTL register. */ #define M6811_CCF 0x80 /* Conversions Complete Flag */ @@ -212,8 +212,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * /* Flags of the OC1M register. */ #define M6811_OC1M7 0x80 /* Output Compare 7 */ #define M6811_OC1M6 0x40 /* 6 */ -#define M6811_OC1M5 0x40 /* 5 */ -#define M6811_OC1M4 0x40 /* 4 */ +#define M6811_OC1M5 0x20 /* 5 */ +#define M6811_OC1M4 0x10 /* 4 */ #define M6811_OC1M3 0x08 /* 3 */ /* Flags of the OC1D register. */ @@ -341,7 +341,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ #define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ #define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ -#define M6811_OP_MASK 0x0FFFF +#define M6812_OP_PAGE 0x4000 /* Page number */ +#define M6811_OP_MASK 0x07FFF +#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ #define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */ #define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */ #define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */ @@ -376,6 +378,13 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ #define M6811_OP_LOW_ADDR 0x02000000 +#define M68HC12_BANK_VIRT 0x01000000 +#define M68HC12_BANK_MASK 0x00003fff +#define M68HC12_BANK_BASE 0x00008000 +#define M68HC12_BANK_SHIFT 14 +#define M68HC12_BANK_PAGE_MASK 0x0ff + + /* CPU identification. */ #define cpu6811 0x01 #define cpu6812 0x02 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 312a2ac17..1a39640ca 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -377,7 +377,6 @@ struct mips_opcode /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ #define CPU_UNKNOWN 0 /* Gas internal use. */ -#define CPU_R2000 2000 #define CPU_R3000 3000 #define CPU_R3900 3900 #define CPU_R4000 4000 diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index f7db66f63..ffd313acd 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -107,6 +107,30 @@ extern const int powerpc_num_opcodes; /* Opcode isn't supported by Power4 architecture. */ #define PPC_OPCODE_NOPOWER4 (040000) +/* Opcode is only supported by POWERPC Classic architecture. */ +#define PPC_OPCODE_CLASSIC (0100000) + +/* Opcode is only supported by e500x2 Core. */ +#define PPC_OPCODE_SPE (0200000) + +/* Opcode is supported by e500x2 Integer select APU. */ +#define PPC_OPCODE_ISEL (0400000) + +/* Opcode is an e500 SPE floating point instruction. */ +#define PPC_OPCODE_EFS (01000000) + +/* Opcode is supported by branch locking APU. */ +#define PPC_OPCODE_BRLOCK (02000000) + +/* Opcode is supported by performance monitor APU. */ +#define PPC_OPCODE_PMR (04000000) + +/* Opcode is supported by cache locking APU. */ +#define PPC_OPCODE_CACHELCK (010000000) + +/* Opcode is supported by machine check APU. */ +#define PPC_OPCODE_RFMCI (020000000) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) |