diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 72 | ||||
| -rw-r--r-- | include/opcode/alpha.h | 7 | ||||
| -rw-r--r-- | include/opcode/arc.h | 52 | ||||
| -rw-r--r-- | include/opcode/cgen.h | 177 | ||||
| -rw-r--r-- | include/opcode/d10v.h | 5 | ||||
| -rw-r--r-- | include/opcode/d30v.h | 4 | ||||
| -rw-r--r-- | include/opcode/h8300.h | 38 | ||||
| -rw-r--r-- | include/opcode/i370.h | 8 | ||||
| -rw-r--r-- | include/opcode/i386.h | 24 | ||||
| -rw-r--r-- | include/opcode/i860.h | 6 | ||||
| -rw-r--r-- | include/opcode/mips.h | 2 | ||||
| -rw-r--r-- | include/opcode/mn10300.h | 8 | ||||
| -rw-r--r-- | include/opcode/or32.h | 130 | ||||
| -rw-r--r-- | include/opcode/pj.h | 4 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 57 | ||||
| -rw-r--r-- | include/opcode/s390.h | 3 | ||||
| -rw-r--r-- | include/opcode/sparc.h | 23 | ||||
| -rw-r--r-- | include/opcode/tic80.h | 25 | ||||
| -rw-r--r-- | include/opcode/v850.h | 8 |
19 files changed, 381 insertions, 272 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 9785f4ec4..8aa84533e 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,75 @@ +2003-08-19 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other + PPC_OPCODE_* defines. + +2003-08-16 Jason Eckhardt <jle@rice.edu> + + * i860.h (fmov.ds): Expand as famov.ds. + (fmov.sd): Expand as famov.sd. + (pfmov.ds): Expand as pfamov.ds. + +2003-08-07 Michael Meissner <gnu@the-meissners.org> + + * cgen.h: Remove PARAM macro usage in all prototypes. + (CGEN_EXTRACT_INFO): Use void * instead of PTR. + (cgen_print_fn): Ditto. + (CGEN_HW_ENTRY): Ditto. + (CGEN_MAYBE_MULTI_IFLD): Ditto. + (struct cgen_insn): Ditto. + (CGEN_CPU_TABLE): Ditto. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * alpha.h: Remove PARAMS macro. + * arc.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * i370.h: Likewise. + * or32.h: Likewise. + * pj.h: Likewise. + * ppc.h: Likewise. + * sparc.h: Likewise. + * tic80.h: Likewise. + * v850.h: Likewise. + +2003-07-18 Michael Snyder <msnyder@redhat.com> + + * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting. + +2003-07-15 Richard Sandiford <rsandifo@redhat.com> + + * mips.h (CPU_RM7000): New macro. + (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. + +2003-07-09 Alexandre Oliva <aoliva@redhat.com> + + 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> + * mn10300.h (AM33_2): Renamed from AM33. + 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> + * mn10300.h (AM332, FMT_D3): Defined. + (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. + (MN10300_OPERAND_FPCR): Likewise. + +2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. + +2003-06-25 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. + (IMM8U, IMM8U_NS): Define. + (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. + +2003-06-25 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and + mov.l ERs,@(dd:32,ERd) entries. + +2003-06-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Support Intel Precott New Instructions. + 2003-06-10 Gary Hade <garyhade@us.ibm.com> * ppc.h (PPC_OPERAND_DQ): Define. diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h index 487b69605..efe16260e 100644 --- a/include/opcode/alpha.h +++ b/include/opcode/alpha.h @@ -1,5 +1,5 @@ /* alpha.h -- Header file for Alpha opcode table - Copyright 1996, 1999 Free Software Foundation, Inc. + Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode table written by Ian Lance Taylor. @@ -108,8 +108,7 @@ struct alpha_operand string (the operand will be inserted in any case). If the operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - unsigned (*insert) PARAMS ((unsigned instruction, int op, - const char **errmsg)); + unsigned (*insert) (unsigned instruction, int op, const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -128,7 +127,7 @@ struct alpha_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - int (*extract) PARAMS ((unsigned instruction, int *invalid)); + int (*extract) (unsigned instruction, int *invalid); }; /* Elements in the table are retrieved by indexing with values from diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 3da68ec80..629979d54 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -1,5 +1,6 @@ /* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 2001 Free Software Foundation, Inc. + Copyright 1994, 1995, 1997, 2001, 2002, 2003 + Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and @@ -17,7 +18,8 @@ You should have received a copy of the GNU General Public License along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + the Free Software Foundation, 59 Temple Place - Suite 330, Boston, + MA 02111-1307, USA. */ /* List of the various cpu types. @@ -226,10 +228,9 @@ struct arc_operand { REG is non-NULL when inserting a register value. */ - arc_insn (*insert) PARAMS ((arc_insn insn, - const struct arc_operand *operand, int mods, - const struct arc_operand_value *reg, long value, - const char **errmsg)); + arc_insn (*insert) + (arc_insn insn, const struct arc_operand *operand, int mods, + const struct arc_operand_value *reg, long value, const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -255,10 +256,9 @@ struct arc_operand { Operands that have a printable form like registers and suffixes have their struct arc_operand_value pointer stored in OPVAL. */ - long (*extract) PARAMS ((arc_insn *insn, - const struct arc_operand *operand, - int mods, const struct arc_operand_value **opval, - int *invalid)); + long (*extract) + (arc_insn *insn, const struct arc_operand *operand, int mods, + const struct arc_operand_value **opval, int *invalid); }; /* Bits that say what version of cpu we have. These should be passed to @@ -302,22 +302,22 @@ extern const int arc_reg_names_count; extern unsigned char arc_operand_map[]; /* Utility fns in arc-opc.c. */ -int arc_get_opcode_mach PARAMS ((int, int)); +int arc_get_opcode_mach (int, int); /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ -void arc_opcode_init_tables PARAMS ((int)); -void arc_opcode_init_insert PARAMS ((void)); -void arc_opcode_init_extract PARAMS ((void)); -const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *)); -const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int)); -int arc_opcode_limm_p PARAMS ((long *)); +void arc_opcode_init_tables (int); +void arc_opcode_init_insert (void); +void arc_opcode_init_extract (void); +const struct arc_opcode *arc_opcode_lookup_asm (const char *); +const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); +int arc_opcode_limm_p (long *); const struct arc_operand_value *arc_opcode_lookup_suffix - PARAMS ((const struct arc_operand *type, int value)); -int arc_opcode_supported PARAMS ((const struct arc_opcode *)); -int arc_opval_supported PARAMS ((const struct arc_operand_value *)); -int arc_limm_fixup_adjust PARAMS ((arc_insn)); -int arc_insn_is_j PARAMS ((arc_insn)); -int arc_insn_not_jl PARAMS ((arc_insn)); -int arc_operand_type PARAMS ((int)); -struct arc_operand_value *get_ext_suffix PARAMS ((char *)); -int arc_get_noshortcut_flag PARAMS ((void)); + (const struct arc_operand *type, int value); +int arc_opcode_supported (const struct arc_opcode *); +int arc_opval_supported (const struct arc_operand_value *); +int arc_limm_fixup_adjust (arc_insn); +int arc_insn_is_j (arc_insn); +int arc_insn_not_jl (arc_insn); +int arc_operand_type (int); +struct arc_operand_value *get_ext_suffix (char *); +int arc_get_noshortcut_flag (void); diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 76a0af47b..16366fd0d 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -242,9 +242,9 @@ typedef struct cgen_fields CGEN_FIELDS; typedef struct { /* A pointer to the disassemble_info struct. - We don't require dis-asm.h so we use PTR for the type here. + We don't require dis-asm.h so we use void * for the type here. If NULL, BYTES is full of valid data (VALID == -1). */ - PTR dis_info; + void *dis_info; /* Points to a working buffer of sufficient size. */ unsigned char *insn_bytes; /* Mask of bytes that are valid in INSN_BYTES. */ @@ -265,8 +265,8 @@ typedef struct { If not it is left alone. The result is NULL if success or an error message. */ typedef const char * (cgen_parse_fn) - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, - const char **strp_, CGEN_FIELDS *fields_)); + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + const char **strp_, CGEN_FIELDS *fields_); /* Insert handler. CD is a cpu table descriptor. @@ -279,9 +279,9 @@ typedef const char * (cgen_parse_fn) #ifdef __BFD_H_SEEN__ typedef const char * (cgen_insert_fn) - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, - bfd_vma pc_)); + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, + bfd_vma pc_); #else typedef const char * (cgen_insert_fn) (); #endif @@ -300,9 +300,9 @@ typedef const char * (cgen_insert_fn) (); #ifdef __BFD_H_SEEN__ typedef int (cgen_extract_fn) - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, - CGEN_FIELDS *fields_, bfd_vma pc_)); + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, + CGEN_FIELDS *fields_, bfd_vma pc_); #else typedef int (cgen_extract_fn) (); #endif @@ -319,8 +319,8 @@ typedef int (cgen_extract_fn) (); #ifdef __BFD_H_SEEN__ typedef void (cgen_print_fn) - PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, bfd_vma pc_, int len_)); + (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, bfd_vma pc_, int len_); #else typedef void (cgen_print_fn) (); #endif @@ -384,9 +384,9 @@ enum cgen_parse_operand_result #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ typedef const char * (cgen_parse_operand_fn) - PARAMS ((CGEN_CPU_DESC, - enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *)); + (CGEN_CPU_DESC, + enum cgen_parse_operand_type, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *); #else typedef const char * (cgen_parse_operand_fn) (); #endif @@ -394,11 +394,11 @@ typedef const char * (cgen_parse_operand_fn) (); /* Set the cgen_parse_operand_fn callback. */ extern void cgen_set_parse_operand_fn - PARAMS ((CGEN_CPU_DESC, cgen_parse_operand_fn)); + (CGEN_CPU_DESC, cgen_parse_operand_fn); /* Called before trying to match a table entry with the insn. */ -extern void cgen_init_parse_operand PARAMS ((CGEN_CPU_DESC)); +extern void cgen_init_parse_operand (CGEN_CPU_DESC); /* Operand values (keywords, integers, symbols, etc.) */ @@ -422,7 +422,7 @@ typedef struct /* There is currently no example where both index specs and value specs are required, so for now both are clumped under "asm_data". */ enum cgen_asm_type asm_type; - PTR asm_data; + void *asm_data; #ifndef CGEN_HW_NBOOL_ATTRS #define CGEN_HW_NBOOL_ATTRS 1 #endif @@ -453,9 +453,9 @@ typedef struct { } CGEN_HW_TABLE; extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name - PARAMS ((CGEN_CPU_DESC, const char *)); + (CGEN_CPU_DESC, const char *); extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num - PARAMS ((CGEN_CPU_DESC, unsigned int)); + (CGEN_CPU_DESC, unsigned int); /* This struct is used to describe things like register names, etc. */ @@ -543,41 +543,41 @@ typedef struct /* Lookup a keyword from its name. */ const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name - PARAMS ((CGEN_KEYWORD *, const char *)); + (CGEN_KEYWORD *, const char *); /* Lookup a keyword from its value. */ const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value - PARAMS ((CGEN_KEYWORD *, int)); + (CGEN_KEYWORD *, int); /* Add a keyword. */ -void cgen_keyword_add PARAMS ((CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *)); +void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); /* Keyword searching. This can be used to retrieve every keyword, or a subset. */ CGEN_KEYWORD_SEARCH cgen_keyword_search_init - PARAMS ((CGEN_KEYWORD *, const char *)); + (CGEN_KEYWORD *, const char *); const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next - PARAMS ((CGEN_KEYWORD_SEARCH *)); + (CGEN_KEYWORD_SEARCH *); /* Operand value support routines. */ extern const char *cgen_parse_keyword - PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); + (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ extern const char *cgen_parse_signed_integer - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + (CGEN_CPU_DESC, const char **, int, long *); extern const char *cgen_parse_unsigned_integer - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); + (CGEN_CPU_DESC, const char **, int, unsigned long *); extern const char *cgen_parse_address - PARAMS ((CGEN_CPU_DESC, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *)); + (CGEN_CPU_DESC, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *); extern const char *cgen_validate_signed_integer - PARAMS ((long, long, long)); + (long, long, long); extern const char *cgen_validate_unsigned_integer - PARAMS ((unsigned long, unsigned long, unsigned long)); + (unsigned long, unsigned long, unsigned long); #endif /* Operand modes. */ @@ -621,7 +621,7 @@ typedef struct cgen_maybe_multi_ifield n: indexed by array of more cgen_maybe_multi_ifields. */ union { - const PTR p; + const void *p; const struct cgen_maybe_multi_ifield * multi; const struct cgen_ifld * leaf; } val; @@ -705,9 +705,9 @@ typedef struct { } CGEN_OPERAND_TABLE; extern const CGEN_OPERAND * cgen_operand_lookup_by_name - PARAMS ((CGEN_CPU_DESC, const char *)); + (CGEN_CPU_DESC, const char *); extern const CGEN_OPERAND * cgen_operand_lookup_by_num - PARAMS ((CGEN_CPU_DESC, int)); + (CGEN_CPU_DESC, int); /* Instruction operand instances. @@ -1061,8 +1061,8 @@ typedef struct /* Return number of instructions. This includes any added at run-time. */ -extern int cgen_insn_count PARAMS ((CGEN_CPU_DESC)); -extern int cgen_macro_insn_count PARAMS ((CGEN_CPU_DESC)); +extern int cgen_insn_count (CGEN_CPU_DESC); +extern int cgen_macro_insn_count (CGEN_CPU_DESC); /* Macros to access the other insn elements not recorded in CGEN_IBASE. */ @@ -1126,9 +1126,10 @@ typedef struct cgen_minsn_expansion { If the expansion fails (e.g. "no match") NULL is returned. Space for the expansion is obtained with malloc. It is up to the caller to free it. */ - const char * (* fn) PARAMS ((const struct cgen_minsn_expansion *, - const char *, const char **, int *, - CGEN_OPERAND **)); + const char * (* fn) + (const struct cgen_minsn_expansion *, + const char *, const char **, int *, + CGEN_OPERAND **); #define CGEN_MIEXPN_FN(ex) ((ex)->fn) /* Instruction(s) the macro expands to. @@ -1146,15 +1147,15 @@ typedef struct cgen_minsn_expansion { may contain further macro invocations. */ extern const char * cgen_expand_macro_insn - PARAMS ((CGEN_CPU_DESC, const struct cgen_minsn_expansion *, - const char *, const char **, int *, CGEN_OPERAND **)); + (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, + const char *, const char **, int *, CGEN_OPERAND **); /* The assembler insn table is hashed based on some function of the mnemonic (the actually hashing done is up to the target, but we provide a few examples like the first letter or a function of the entire mnemonic). */ extern CGEN_INSN_LIST * cgen_asm_lookup_insn - PARAMS ((CGEN_CPU_DESC, const char *)); + (CGEN_CPU_DESC, const char *); #define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) @@ -1162,7 +1163,7 @@ extern CGEN_INSN_LIST * cgen_asm_lookup_insn instruction (the actually hashing done is up to the target). */ extern CGEN_INSN_LIST * cgen_dis_lookup_insn - PARAMS ((CGEN_CPU_DESC, const char *, CGEN_INSN_INT)); + (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); /* FIXME: delete these two */ #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) @@ -1246,25 +1247,24 @@ typedef struct cgen_cpu_desc int int_insn_p; /* Called to rebuild the tables after something has changed. */ - void (*rebuild_tables) PARAMS ((CGEN_CPU_DESC)); + void (*rebuild_tables) (CGEN_CPU_DESC); /* Operand parser callback. */ cgen_parse_operand_fn * parse_operand_fn; /* Parse/insert/extract/print cover fns for operands. */ const char * (*parse_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, const char **, - CGEN_FIELDS *fields_)); + (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); #ifdef __BFD_H_SEEN__ const char * (*insert_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, - CGEN_INSN_BYTES_PTR, bfd_vma pc_)); + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, + CGEN_INSN_BYTES_PTR, bfd_vma pc_); int (*extract_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *fields_, bfd_vma pc_)); + (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *fields_, bfd_vma pc_); void (*print_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, PTR info_, CGEN_FIELDS * fields_, - void const *attrs_, bfd_vma pc_, int length_)); + (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, + void const *attrs_, bfd_vma pc_, int length_); #else const char * (*insert_operand) (); int (*extract_operand) (); @@ -1280,19 +1280,19 @@ typedef struct cgen_cpu_desc #define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) /* Set the bitsize field. */ - void (*set_fields_bitsize) PARAMS ((CGEN_FIELDS *fields_, int size_)); + void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); #define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) /* CGEN_FIELDS accessors. */ int (*get_int_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); + (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); void (*set_int_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_)); + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); #ifdef __BFD_H_SEEN__ bfd_vma (*get_vma_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); + (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); void (*set_vma_operand) - PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_)); + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); #else long (*get_vma_operand) (); void (*set_vma_operand) (); @@ -1314,19 +1314,19 @@ typedef struct cgen_cpu_desc #define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) /* Return non-zero if insn should be added to hash table. */ - int (* asm_hash_p) PARAMS ((const CGEN_INSN *)); + int (* asm_hash_p) (const CGEN_INSN *); /* Assembler hash function. */ - unsigned int (* asm_hash) PARAMS ((const char *)); + unsigned int (* asm_hash) (const char *); /* Number of entries in assembler hash table. */ unsigned int asm_hash_size; /* Return non-zero if insn should be added to hash table. */ - int (* dis_hash_p) PARAMS ((const CGEN_INSN *)); + int (* dis_hash_p) (const CGEN_INSN *); /* Disassembler hash function. */ - unsigned int (* dis_hash) PARAMS ((const char *, CGEN_INSN_INT)); + unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); /* Number of entries in disassembler hash table. */ unsigned int dis_hash_size; @@ -1381,81 +1381,80 @@ extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); /* Cover fn to handle simple case. */ -extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) PARAMS ((const char *mach_name_, - enum cgen_endian endian_)); +extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) + (const char *mach_name_, enum cgen_endian endian_); /* Close it. */ -extern void CGEN_SYM (cpu_close) PARAMS ((CGEN_CPU_DESC)); +extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); /* Initialize the opcode table for use. Called by init_asm/init_dis. */ -extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_)); +extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); /* build the insn selection regex. called by init_opcode_table */ -extern char * CGEN_SYM(build_insn_regex) PARAMS ((CGEN_INSN *insn_)); +extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); /* Initialize the ibld table for use. Called by init_asm/init_dis. */ -extern void CGEN_SYM (init_ibld_table) PARAMS ((CGEN_CPU_DESC cd_)); +extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); /* Initialize an cpu table for assembler or disassembler use. These must be called immediately after cpu_open. */ -extern void CGEN_SYM (init_asm) PARAMS ((CGEN_CPU_DESC)); -extern void CGEN_SYM (init_dis) PARAMS ((CGEN_CPU_DESC)); +extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); +extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); /* Initialize the operand instance table for use. */ -extern void CGEN_SYM (init_opinst_table) PARAMS ((CGEN_CPU_DESC cd_)); +extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); /* Assemble an instruction. */ extern const CGEN_INSN * CGEN_SYM (assemble_insn) - PARAMS ((CGEN_CPU_DESC, const char *, CGEN_FIELDS *, - CGEN_INSN_BYTES_PTR, char **)); + (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, + CGEN_INSN_BYTES_PTR, char **); extern const CGEN_KEYWORD CGEN_SYM (operand_mach); -extern int CGEN_SYM (get_mach) PARAMS ((const char *)); +extern int CGEN_SYM (get_mach) (const char *); /* Operand index computation. */ extern const CGEN_INSN * cgen_lookup_insn - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, CGEN_FIELDS *fields_, int alias_p_)); + (CGEN_CPU_DESC, const CGEN_INSN * insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, CGEN_FIELDS *fields_, int alias_p_); extern void cgen_get_insn_operands - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, - const CGEN_FIELDS *fields_, int *indices_)); + (CGEN_CPU_DESC, const CGEN_INSN * insn_, + const CGEN_FIELDS *fields_, int *indices_); extern const CGEN_INSN * cgen_lookup_get_insn_operands - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, int *indices_, CGEN_FIELDS *fields_)); + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, int *indices_, CGEN_FIELDS *fields_); /* Cover fns to bfd_get/set. */ extern CGEN_INSN_INT cgen_get_insn_value - PARAMS ((CGEN_CPU_DESC, unsigned char *, int)); + (CGEN_CPU_DESC, unsigned char *, int); extern void cgen_put_insn_value - PARAMS ((CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); /* Read in a cpu description file. ??? For future concerns, including adding instructions to the assembler/ disassembler at run-time. */ -extern const char * cgen_read_cpu_file - PARAMS ((CGEN_CPU_DESC, const char * filename_)); +extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); /* Allow signed overflow of instruction fields. */ -extern void cgen_set_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); +extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); /* Generate an error message if a signed field in an instruction overflows. */ -extern void cgen_clear_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); +extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); /* Will an error message be generated if a signed field in an instruction overflows ? */ -extern unsigned int cgen_signed_overflow_ok_p PARAMS ((CGEN_CPU_DESC)); +extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); #endif /* CGEN_H */ diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h index cc27850b0..74d9006f1 100644 --- a/include/opcode/d10v.h +++ b/include/opcode/d10v.h @@ -1,5 +1,6 @@ /* d10v.h -- Header file for D10V opcode table - Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -198,7 +199,7 @@ struct pd_reg }; extern const struct pd_reg d10v_predefined_registers[]; -int d10v_reg_name_cnt PARAMS ((void)); +int d10v_reg_name_cnt (void); /* an expressionS only has one register type, so we fake it */ /* by setting high bits to indicate type */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index c18874b66..809bdeb7d 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -1,5 +1,5 @@ /* d30v.h -- Header file for D30V opcode table - Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions This file is part of GDB, GAS, and the GNU binutils. @@ -32,7 +32,7 @@ struct pd_reg }; extern const struct pd_reg pre_defined_registers[]; -int reg_name_cnt PARAMS ((void)); +int reg_name_cnt (void); /* the number of control registers */ #define MAX_CONTROL_REG 64 diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h index 4318dccbc..20793a0a9 100644 --- a/include/opcode/h8300.h +++ b/include/opcode/h8300.h @@ -117,6 +117,7 @@ enum h8_flags { B31 = 0x40000000, /* Bit 3 must be high. */ E = 0x80000000, /* End of nibble sequence. */ + /* Immediates smaller than 8 bits are always unsigned. */ IMM3 = IMM | L_3, IMM4 = IMM | L_4, IMM5 = IMM | L_5, @@ -124,15 +125,14 @@ enum h8_flags { IMM2 = IMM | L_2, IMM8 = IMM | SRC | L_8, + IMM8U = IMM | SRC | L_8U, IMM16 = IMM | SRC | L_16, IMM16U = IMM | SRC | L_16U, IMM32 = IMM | SRC | L_32, IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, - IMM2_NS = IMM2 | NO_SYMBOLS, IMM4_NS = IMM4 | NO_SYMBOLS, - IMM8_NS = IMM8 | NO_SYMBOLS, - IMM16_NS = IMM16 | NO_SYMBOLS, + IMM8U_NS = IMM8U | NO_SYMBOLS, IMM16U_NS = IMM16U | NO_SYMBOLS, RD8 = DST | L_8 | REG, @@ -1475,7 +1475,7 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, - MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8_NS), + MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, @@ -1501,7 +1501,7 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, - MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8_NS), + MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, @@ -1518,7 +1518,8 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, @@ -1535,7 +1536,8 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, @@ -1625,17 +1627,17 @@ struct h8_opcode h8_opcodes[] = DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), - DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), - DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (INDEXB16 | DST, 0xD, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (INDEXW16 | DST, 0xE, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (INDEXL16 | DST, 0xF, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (INDEXB32 | DST, 0xD, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (INDEXW32 | DST, 0xE, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (INDEXL32 | DST, 0xF, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (ABS16DST | DST, 0x4, 0x0, DSTABS16LIST), - DO_MOVA2 (ABS32DST | DST, 0x4, 0x8, DSTABS32LIST), + DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), + DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST), + DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST), {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, diff --git a/include/opcode/i370.h b/include/opcode/i370.h index 155a3cf86..e317f2364 100644 --- a/include/opcode/i370.h +++ b/include/opcode/i370.h @@ -1,5 +1,5 @@ /* i370.h -- Header file for S/390 opcode table - Copyright 1994, 1995, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1994, 1995, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. PowerPC version written by Ian Lance Taylor, Cygnus Support Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> @@ -159,8 +159,8 @@ struct i370_operand string (the operand will be inserted in any case). If the operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op, - const char **errmsg)); + i370_insn_t (*insert) + (i370_insn_t instruction, long op, const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -179,7 +179,7 @@ struct i370_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((i370_insn_t instruction, int *invalid)); + long (*extract) (i370_insn_t instruction, int *invalid); /* One bit syntax flags. */ unsigned long flags; diff --git a/include/opcode/i386.h b/include/opcode/i386.h index 71c204c81..cb3a99a4e 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -1302,6 +1302,30 @@ static const template i386_optab[] = { {"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +/* Prescott New Instructions. */ + +{"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +/* Intel Syntax */ +{"fisttpd", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ +{"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} }, +{"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +/* Need to ensure only "mwait %eax,%ecx" is accepted. */ +{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} }, + /* AMD 3DNow! instructions. */ {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, diff --git a/include/opcode/i860.h b/include/opcode/i860.h index 6e2a683a4..b46a5e5a4 100644 --- a/include/opcode/i860.h +++ b/include/opcode/i860.h @@ -494,9 +494,9 @@ static const struct i860_opcode i860_opcodes[] = /* Floating point pseudo-instructions. */ { "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ { "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ -{ "fmov.sd", 0x480000b0, 0xb7e0054f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */ -{ "fmov.ds", 0x48000130, 0xb7e004cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */ -{ "pfmov.ds", 0x48000530, 0xb73000cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */ +{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ +{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ +{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ { "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ { 0, 0, 0, 0, 0 }, diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 476c8e311..65434a778 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -451,6 +451,7 @@ struct mips_opcode #define CPU_VR5400 5400 #define CPU_VR5500 5500 #define CPU_R6000 6000 +#define CPU_RM7000 7000 #define CPU_R8000 8000 #define CPU_R10000 10000 #define CPU_R12000 12000 @@ -469,6 +470,7 @@ struct mips_opcode #define OPCODE_IS_MEMBER(insn, isa, cpu) \ (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h index 0de7f451a..bd7faa110 100644 --- a/include/opcode/mn10300.h +++ b/include/opcode/mn10300.h @@ -135,6 +135,12 @@ extern const struct mn10300_operand mn10300_operands[]; #define MN10300_OPERAND_24BIT 0x800000 +#define MN10300_OPERAND_FSREG 0x1000000 + +#define MN10300_OPERAND_FDREG 0x2000000 + +#define MN10300_OPERAND_FPCR 0x4000000 + /* Opcode Formats. */ #define FMT_S0 1 #define FMT_S1 2 @@ -151,11 +157,13 @@ extern const struct mn10300_operand mn10300_operands[]; #define FMT_D8 13 #define FMT_D9 14 #define FMT_D10 15 +#define FMT_D3 16 /* Variants of the mn10300 which have additional opcodes. */ #define MN103 300 #define AM30 300 #define AM33 330 +#define AM33_2 332 #endif /* MN10300_H */ diff --git a/include/opcode/or32.h b/include/opcode/or32.h index 4609a48db..d72b9bda3 100644 --- a/include/opcode/or32.h +++ b/include/opcode/or32.h @@ -1,5 +1,5 @@ /* Table of opcodes for the OpenRISC 1000 ISA. - Copyright 2002 Free Software Foundation, Inc. + Copyright 2002, 2003 Free Software Foundation, Inc. Contributed by Damjan Lampret (lampret@opencores.org). This file is part of or1k_gen_isa, or1ksim, GDB and GAS. @@ -27,10 +27,6 @@ #define NUM_UNSIGNED (0) #define NUM_SIGNED (1) -#ifndef PARAMS -#define PARAMS(x) x -#endif - #define MAX_GPRS 32 #define PAGE_SIZE 4096 #undef __HALF_WORD_INSN__ @@ -71,7 +67,7 @@ struct or32_opcode /* Opcode and operand encoding. */ char *encoding; - void (*exec) PARAMS ((void)); + void (*exec) (void); unsigned int flags; }; @@ -93,59 +89,59 @@ extern struct insn_op_struct } **op_start; #ifdef HAS_EXECUTION -extern void l_invalid PARAMS ((void)); -extern void l_sfne PARAMS ((void)); -extern void l_bf PARAMS ((void)); -extern void l_add PARAMS ((void)); -extern void l_sw PARAMS ((void)); -extern void l_sb PARAMS ((void)); -extern void l_sh PARAMS ((void)); -extern void l_lwz PARAMS ((void)); -extern void l_lbs PARAMS ((void)); -extern void l_lbz PARAMS ((void)); -extern void l_lhs PARAMS ((void)); -extern void l_lhz PARAMS ((void)); -extern void l_movhi PARAMS ((void)); -extern void l_and PARAMS ((void)); -extern void l_or PARAMS ((void)); -extern void l_xor PARAMS ((void)); -extern void l_sub PARAMS ((void)); -extern void l_mul PARAMS ((void)); -extern void l_div PARAMS ((void)); -extern void l_divu PARAMS ((void)); -extern void l_sll PARAMS ((void)); -extern void l_sra PARAMS ((void)); -extern void l_srl PARAMS ((void)); -extern void l_j PARAMS ((void)); -extern void l_jal PARAMS ((void)); -extern void l_jalr PARAMS ((void)); -extern void l_jr PARAMS ((void)); -extern void l_rfe PARAMS ((void)); -extern void l_nop PARAMS ((void)); -extern void l_bnf PARAMS ((void)); -extern void l_sfeq PARAMS ((void)); -extern void l_sfgts PARAMS ((void)); -extern void l_sfges PARAMS ((void)); -extern void l_sflts PARAMS ((void)); -extern void l_sfles PARAMS ((void)); -extern void l_sfgtu PARAMS ((void)); -extern void l_sfgeu PARAMS ((void)); -extern void l_sfltu PARAMS ((void)); -extern void l_sfleu PARAMS ((void)); -extern void l_mtspr PARAMS ((void)); -extern void l_mfspr PARAMS ((void)); -extern void l_sys PARAMS ((void)); -extern void l_trap PARAMS ((void)); /* CZ 21/06/01. */ -extern void l_macrc PARAMS ((void)); -extern void l_mac PARAMS ((void)); -extern void l_msb PARAMS ((void)); -extern void l_invalid PARAMS ((void)); -extern void l_cust1 PARAMS ((void)); -extern void l_cust2 PARAMS ((void)); -extern void l_cust3 PARAMS ((void)); -extern void l_cust4 PARAMS ((void)); +extern void l_invalid (void); +extern void l_sfne (void); +extern void l_bf (void); +extern void l_add (void); +extern void l_sw (void); +extern void l_sb (void); +extern void l_sh (void); +extern void l_lwz (void); +extern void l_lbs (void); +extern void l_lbz (void); +extern void l_lhs (void); +extern void l_lhz (void); +extern void l_movhi (void); +extern void l_and (void); +extern void l_or (void); +extern void l_xor (void); +extern void l_sub (void); +extern void l_mul (void); +extern void l_div (void); +extern void l_divu (void); +extern void l_sll (void); +extern void l_sra (void); +extern void l_srl (void); +extern void l_j (void); +extern void l_jal (void); +extern void l_jalr (void); +extern void l_jr (void); +extern void l_rfe (void); +extern void l_nop (void); +extern void l_bnf (void); +extern void l_sfeq (void); +extern void l_sfgts (void); +extern void l_sfges (void); +extern void l_sflts (void); +extern void l_sfles (void); +extern void l_sfgtu (void); +extern void l_sfgeu (void); +extern void l_sfltu (void); +extern void l_sfleu (void); +extern void l_mtspr (void); +extern void l_mfspr (void); +extern void l_sys (void); +extern void l_trap (void); /* CZ 21/06/01. */ +extern void l_macrc (void); +extern void l_mac (void); +extern void l_msb (void); +extern void l_invalid (void); +extern void l_cust1 (void); +extern void l_cust2 (void); +extern void l_cust3 (void); +extern void l_cust4 (void); #endif -extern void l_none PARAMS ((void)); +extern void l_none (void); extern const struct or32_letter or32_letters[]; @@ -154,31 +150,31 @@ extern const struct or32_opcode or32_opcodes[]; extern const unsigned int or32_num_opcodes; /* Calculates instruction length in bytes. Always 4 for OR32. */ -extern int insn_len PARAMS ((int)); +extern int insn_len (int); /* Is individual insn's operand signed or unsigned? */ -extern int letter_signed PARAMS ((char)); +extern int letter_signed (char); /* Number of letters in the individual lettered operand. */ -extern int letter_range PARAMS ((char)); +extern int letter_range (char); /* MM: Returns index of given instruction name. */ -extern int insn_index PARAMS ((char *)); +extern int insn_index (char *); /* MM: Returns instruction name from index. */ -extern const char *insn_name PARAMS ((int)); +extern const char *insn_name (int); /* MM: Constructs new FSM, based on or32_opcodes. */ -extern void build_automata PARAMS ((void)); +extern void build_automata (void); /* MM: Destructs FSM. */ -extern void destruct_automata PARAMS ((void)); +extern void destruct_automata (void); /* MM: Decodes instruction using FSM. Call build_automata first. */ -extern int insn_decode PARAMS ((unsigned int)); +extern int insn_decode (unsigned int); /* Disassemble one instruction from insn to disassemble. Return the size of the instruction. */ -int disassemble_insn PARAMS ((unsigned long)); +int disassemble_insn (unsigned long); #endif diff --git a/include/opcode/pj.h b/include/opcode/pj.h index 5779507be..f9e44dbef 100644 --- a/include/opcode/pj.h +++ b/include/opcode/pj.h @@ -1,5 +1,5 @@ /* Definitions for decoding the picoJava opcode table. - Copyright 1999 Free Software Foundation, Inc. + Copyright 1999, 2002, 2003 Free Software Foundation, Inc. Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). This program is free software; you can redistribute it and/or modify @@ -44,6 +44,6 @@ typedef struct pj_opc_info_t unsigned char arg[2]; union { const char *name; - void (*func) PARAMS ((struct pj_opc_info_t *, char *)); + void (*func) (struct pj_opc_info_t *, char *); } u; } pj_opc_info_t; diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index c4adf712b..342237e8d 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -59,77 +59,80 @@ extern const int powerpc_num_opcodes; /* Values defined for the flags field of a struct powerpc_opcode. */ /* Opcode is defined for the PowerPC architecture. */ -#define PPC_OPCODE_PPC (01) +#define PPC_OPCODE_PPC 1 /* Opcode is defined for the POWER (RS/6000) architecture. */ -#define PPC_OPCODE_POWER (02) +#define PPC_OPCODE_POWER 2 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ -#define PPC_OPCODE_POWER2 (04) +#define PPC_OPCODE_POWER2 4 /* Opcode is only defined on 32 bit architectures. */ -#define PPC_OPCODE_32 (010) +#define PPC_OPCODE_32 8 /* Opcode is only defined on 64 bit architectures. */ -#define PPC_OPCODE_64 (020) +#define PPC_OPCODE_64 0x10 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, but it also supports many additional POWER instructions. */ -#define PPC_OPCODE_601 (040) +#define PPC_OPCODE_601 0x20 /* Opcode is supported in both the Power and PowerPC architectures (ie, compiler's -mcpu=common or assembler's -mcom). */ -#define PPC_OPCODE_COMMON (0100) +#define PPC_OPCODE_COMMON 0x40 /* Opcode is supported for any Power or PowerPC platform (this is for the assembler's -many option, and it eliminates duplicates). */ -#define PPC_OPCODE_ANY (0200) +#define PPC_OPCODE_ANY 0x80 /* Opcode is supported as part of the 64-bit bridge. */ -#define PPC_OPCODE_64_BRIDGE (0400) +#define PPC_OPCODE_64_BRIDGE 0x100 /* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC (01000) +#define PPC_OPCODE_ALTIVEC 0x200 /* Opcode is supported by PowerPC 403 processor. */ -#define PPC_OPCODE_403 (02000) +#define PPC_OPCODE_403 0x400 /* Opcode is supported by PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE (04000) +#define PPC_OPCODE_BOOKE 0x800 /* Opcode is only supported by 64-bit PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE64 (010000) +#define PPC_OPCODE_BOOKE64 0x1000 + +/* Opcode is supported by PowerPC 440 processor. */ +#define PPC_OPCODE_440 0x2000 /* Opcode is only supported by Power4 architecture. */ -#define PPC_OPCODE_POWER4 (020000) +#define PPC_OPCODE_POWER4 0x4000 /* Opcode isn't supported by Power4 architecture. */ -#define PPC_OPCODE_NOPOWER4 (040000) +#define PPC_OPCODE_NOPOWER4 0x8000 /* Opcode is only supported by POWERPC Classic architecture. */ -#define PPC_OPCODE_CLASSIC (0100000) +#define PPC_OPCODE_CLASSIC 0x10000 /* Opcode is only supported by e500x2 Core. */ -#define PPC_OPCODE_SPE (0200000) +#define PPC_OPCODE_SPE 0x20000 /* Opcode is supported by e500x2 Integer select APU. */ -#define PPC_OPCODE_ISEL (0400000) +#define PPC_OPCODE_ISEL 0x40000 /* Opcode is an e500 SPE floating point instruction. */ -#define PPC_OPCODE_EFS (01000000) +#define PPC_OPCODE_EFS 0x80000 /* Opcode is supported by branch locking APU. */ -#define PPC_OPCODE_BRLOCK (02000000) +#define PPC_OPCODE_BRLOCK 0x100000 /* Opcode is supported by performance monitor APU. */ -#define PPC_OPCODE_PMR (04000000) +#define PPC_OPCODE_PMR 0x200000 /* Opcode is supported by cache locking APU. */ -#define PPC_OPCODE_CACHELCK (010000000) +#define PPC_OPCODE_CACHELCK 0x400000 /* Opcode is supported by machine check APU. */ -#define PPC_OPCODE_RFMCI (020000000) +#define PPC_OPCODE_RFMCI 0x800000 /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -160,9 +163,8 @@ struct powerpc_operand string (the operand will be inserted in any case). If the operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - unsigned long (*insert) PARAMS ((unsigned long instruction, long op, - int dialect, - const char **errmsg)); + unsigned long (*insert) + (unsigned long instruction, long op, int dialect, const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -181,8 +183,7 @@ struct powerpc_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((unsigned long instruction, int dialect, - int *invalid)); + long (*extract) (unsigned long instruction, int dialect, int *invalid); /* One bit syntax flags. */ unsigned long flags; diff --git a/include/opcode/s390.h b/include/opcode/s390.h index 6e32723b2..f582a4e51 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -34,7 +34,8 @@ enum s390_opcode_cpu_val { S390_OPCODE_G5 = 0, S390_OPCODE_G6, - S390_OPCODE_Z900 + S390_OPCODE_Z900, + S390_OPCODE_Z990 }; /* The opcode table is an array of struct s390_opcode. */ diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index c41292364..c3364933a 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -1,6 +1,6 @@ /* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002 - Free Software Foundation, Inc. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, + 2003 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. @@ -74,8 +74,7 @@ struct sparc_opcode_arch { extern const struct sparc_opcode_arch sparc_opcode_archs[]; /* Given architecture name, look up it's sparc_opcode_arch_val value. */ -extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch - PARAMS ((const char *)); +extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); /* Return the bitmask of supported architectures for ARCH. */ #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) @@ -223,14 +222,14 @@ The following chars are unused: (note: ,[] are used as punctuation) extern const struct sparc_opcode sparc_opcodes[]; extern const int sparc_num_opcodes; -extern int sparc_encode_asi PARAMS ((const char *)); -extern const char *sparc_decode_asi PARAMS ((int)); -extern int sparc_encode_membar PARAMS ((const char *)); -extern const char *sparc_decode_membar PARAMS ((int)); -extern int sparc_encode_prefetch PARAMS ((const char *)); -extern const char *sparc_decode_prefetch PARAMS ((int)); -extern int sparc_encode_sparclet_cpreg PARAMS ((const char *)); -extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); +extern int sparc_encode_asi (const char *); +extern const char *sparc_decode_asi (int); +extern int sparc_encode_membar (const char *); +extern const char *sparc_decode_membar (int); +extern int sparc_encode_prefetch (const char *); +extern const char *sparc_decode_prefetch (int); +extern int sparc_encode_sparclet_cpreg (const char *); +extern const char *sparc_decode_sparclet_cpreg (int); /* * Local Variables: diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h index 01159e46b..c6a79df28 100644 --- a/include/opcode/tic80.h +++ b/include/opcode/tic80.h @@ -1,5 +1,5 @@ /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table - Copyright 1996, 1997 Free Software Foundation, Inc. + Copyright 1996, 1997, 2003 Free Software Foundation, Inc. Written by Fred Fish (fnf@cygnus.com), Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -90,8 +90,8 @@ struct tic80_operand operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - unsigned long (*insert) PARAMS ((unsigned long instruction, long op, - const char **errmsg)); + unsigned long (*insert) + (unsigned long instruction, long op, const char **errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -111,7 +111,7 @@ struct tic80_operand this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((unsigned long instruction, int *invalid)); + long (*extract) (unsigned long instruction, int *invalid); /* One bit syntax flags. */ @@ -265,13 +265,18 @@ struct predefined_symbol #define PDS_NAME(pdsp) ((pdsp) -> name) #define PDS_VALUE(pdsp) ((pdsp) -> value) -extern const struct predefined_symbol tic80_predefined_symbols[]; /* Translation array */ -extern const int tic80_num_predefined_symbols; /* How many members in the array */ +/* Translation array. */ +extern const struct predefined_symbol tic80_predefined_symbols[]; +/* How many members in the array. */ +extern const int tic80_num_predefined_symbols; -const char *tic80_value_to_symbol PARAMS ((int val, int class)); /* Translate value to symbolic name */ -int tic80_symbol_to_value PARAMS ((char *name, int class)); /* Translate symbolic name to value */ +/* Translate value to symbolic name. */ +const char *tic80_value_to_symbol (int val, int class); -const struct predefined_symbol * -tic80_next_predefined_symbol PARAMS ((const struct predefined_symbol *)); +/* Translate symbolic name to value. */ +int tic80_symbol_to_value (char *name, int class); + +const struct predefined_symbol *tic80_next_predefined_symbol + (const struct predefined_symbol *); #endif /* TIC80_H */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h index 2183bc858..f6a1eb466 100644 --- a/include/opcode/v850.h +++ b/include/opcode/v850.h @@ -1,5 +1,5 @@ /* v850.h -- Header file for NEC V850 opcode table - Copyright 1996, 1997, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc. Written by J.T. Conklin, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -95,8 +95,8 @@ struct v850_operand string (the operand will be inserted in any case). If the operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ - unsigned long (* insert) PARAMS ((unsigned long instruction, long op, - const char ** errmsg)); + unsigned long (* insert) + (unsigned long instruction, long op, const char ** errmsg); /* Extraction function. This is used by the disassembler. To extract this operand type from an instruction, check this field. @@ -114,7 +114,7 @@ struct v850_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid)); + unsigned long (* extract) (unsigned long instruction, int * invalid); /* One bit syntax flags. */ int flags; |