diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 30 | ||||
| -rw-r--r-- | include/opcode/cgen.h | 14 | ||||
| -rw-r--r-- | include/opcode/i386.h | 12 | ||||
| -rw-r--r-- | include/opcode/mips.h | 25 | ||||
| -rw-r--r-- | include/opcode/pdp11.h | 78 | ||||
| -rw-r--r-- | include/opcode/s390.h | 130 |
6 files changed, 259 insertions, 30 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 138423458..b4e688844 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,27 @@ +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * pdp11.h: New file. + +2001-02-12 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): SSE integer converison instructions have + 64bit versions on x86-64. + +2001-02-10 Nick Clifton <nickc@redhat.com> + + * mips.h: Remove extraneous whitespace. Formating change to allow + for future contribution. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h: New file. + +2001-02-02 Patrick Macdonald <patrickm@redhat.com> + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. + (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. + (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. + 2001-01-24 Karsten Keil <kkeil@suse.de> * i386.h (i386_optab): Fix swapgs @@ -9,7 +33,7 @@ (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. Remove duplicate "ldw j(s,b),x". Sort some entries. -Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> +2001-01-13 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Fix pusha and ret templates. @@ -656,7 +680,7 @@ Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, CGEN_MODE_UINT. -Sat Jan 16 01:29:25 1999 Jeffrey A Law (law@cygnus.com) +1999-01-16 Jeffrey A Law (law@cygnus.com) * hppa.h (bv): Fix mask. @@ -1007,7 +1031,7 @@ Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> * tic30.h: New file. -Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> +Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> * cgen.h: Add prototypes for cgen_save_fixups(), cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index f7962cd77..e208a5455 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -736,25 +736,21 @@ typedef struct the data is recorded in the parse/insert/extract/print switch statements. */ /* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_BYTES 40 +#define CGEN_MAX_SYNTAX_ELEMENTS 40 /* A target may know its own precise maximum. Assert that it falls below the above limit. */ -#ifdef CGEN_ACTUAL_MAX_SYNTAX_BYTES -#if CGEN_ACTUAL_MAX_SYNTAX_BYTES > CGEN_MAX_SYNTAX_BYTES -#error "CGEN_ACTUAL_MAX_SYNTAX_BYTES too high - enlarge CGEN_MAX_SYNTAX_BYTES" +#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS +#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS +#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" #endif #endif -#if !defined(MAX_OPERANDS) || MAX_OPERANDS <= 127 -typedef unsigned char CGEN_SYNTAX_CHAR_TYPE; -#else typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; -#endif typedef struct { - CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_BYTES]; + CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; } CGEN_SYNTAX; #define CGEN_SYNTAX_STRING(syn) (syn->syntax) diff --git a/include/opcode/i386.h b/include/opcode/i386.h index 07124c40c..2ab783e63 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -1112,10 +1112,10 @@ static const template i386_optab[] = { {"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, {"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, {"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, -{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, {"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, {"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, {"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, @@ -1212,7 +1212,7 @@ static const template i386_optab[] = { {"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, {"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, {"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, FP|Modrm, { Reg32|LongMem, RegXMM, 0 } }, +{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, {"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, {"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, @@ -1250,11 +1250,11 @@ static const template i386_optab[] = { {"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, Reg32, 0 } }, +{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, {"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, {"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM, 0 } }, diff --git a/include/opcode/mips.h b/include/opcode/mips.h index c493d08dc..ab30d1c91 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -30,9 +30,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) Make sure you use fields that are appropriate for the instruction, - of course. + of course. - The 'i' format uses OP, RS, RT and IMMEDIATE. + The 'i' format uses OP, RS, RT and IMMEDIATE. The 'j' format uses OP and TARGET. @@ -123,7 +123,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_SH_HINT 16 #define OP_MASK_HINT 0x1f #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ -#define OP_MASK_MMI 0x3f +#define OP_MASK_MMI 0x3f #define OP_SH_MMISUB 6 #define OP_MASK_MMISUB 0x1f #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ @@ -366,14 +366,15 @@ struct mips_opcode /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. + to test, or zero if no CPU specific ISA test is desired. The gp32 arg is set when you need to force 32-bit register usage on a machine with 64-bit registers; see the documentation under -mgp32 in the MIPS gas docs. */ #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \ ((((insn)->membership & isa) != 0 \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ + && ((insn)->membership & INSN_GP32 ? gp32 : 1) \ + ) \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ @@ -381,7 +382,7 @@ struct mips_opcode || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)) /* This is a list of macro expanded instructions. - + _I appended means immediate _A appended means address _AB appended means address with base register @@ -446,11 +447,11 @@ enum M_DLA_AB, M_DLI, M_DMUL, - M_DMUL_I, + M_DMUL_I, M_DMULO, - M_DMULO_I, + M_DMULO_I, M_DMULOU, - M_DMULOU_I, + M_DMULOU_I, M_DREM_3, M_DREM_3I, M_DREMU_3, @@ -505,11 +506,11 @@ enum M_LWR_AB, M_LWU_AB, M_MUL, - M_MUL_I, + M_MUL_I, M_MULO, - M_MULO_I, + M_MULO_I, M_MULOU, - M_MULOU_I, + M_MULOU_I, M_NOR_I, M_OR_I, M_REM_3, diff --git a/include/opcode/pdp11.h b/include/opcode/pdp11.h new file mode 100644 index 000000000..891b74f9a --- /dev/null +++ b/include/opcode/pdp11.h @@ -0,0 +1,78 @@ +/* PDP-11 opcde list. + Copyright (C) 2001 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * PDP-11 opcode types. + */ + +#define PDP11_OPCODE_NO_OPS 0 +#define PDP11_OPCODE_REG 1 /* register */ +#define PDP11_OPCODE_OP 2 /* generic operand */ +#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ +#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, + reversed syntax */ +#define PDP11_OPCODE_AC_OP 5 /* fpu accumulator and generic + operand */ +#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ +#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ +#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative + displacement */ +#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ +#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ +#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ +#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ + +/* + * PDP-11 instruction set extensions. + * + * Please keep the numbers low, as they are used as indices into + * an array. + */ + +#define PDP11_NONE 0 /* not in instruction set */ +#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ +#define PDP11_CSM 2 /* commercial instruction set */ +#define PDP11_CIS 3 /* commercial instruction set */ +#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ +#define PDP11_FIS 5 /* KEV11 floating-point instructions */ +#define PDP11_FPP 6 /* FP-11 floating-point instructions */ +#define PDP11_LEIS 7 /* limited extended instruction set + (11/40 etc) */ +#define PDP11_MFPT 8 /* move from processor type */ +#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, + wrtlck */ +#define PDP11_MXPS 10 /* move from/to processor status */ +#define PDP11_SPL 11 /* set priority level */ +#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ +#define PDP11_EXT_NUM 13 /* total number of extension types */ + +struct pdp11_opcode +{ + const char *name; + int opcode; + int mask; + int type; + int extension; +}; + +extern const struct pdp11_opcode pdp11_opcodes[]; +extern const struct pdp11_opcode pdp11_aliases[]; +extern const int pdp11_num_opcodes, pdp11_num_aliases; + +/* end of pdp11.h */ diff --git a/include/opcode/s390.h b/include/opcode/s390.h new file mode 100644 index 000000000..8a7c00eff --- /dev/null +++ b/include/opcode/s390.h @@ -0,0 +1,130 @@ +/* s390.h -- Header file for S390 opcode table + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef S390_H +#define S390_H + +/* List of instruction sets variations. */ + +enum s390_opcode_arch_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ESAME + }; + +/* The opcode table is an array of struct s390_opcode. */ + +struct s390_opcode + { + /* The opcode name. */ + const char * name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned char opcode[6]; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned char mask[6]; + + /* The opcode length in bytes. */ + int oplen; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; + + /* Bitmask of architectures this opcode is available for. */ + unsigned int architecture; + }; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct s390_opcode s390_opcodes[]; +extern const int s390_num_opcodes; + +/* A opcode format table for the .insn pseudo mnemonic. */ +extern const struct s390_opcode s390_opformats[]; +extern const int s390_num_opformats; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* The operands table is an array of struct s390_operand. */ + +struct s390_operand + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + unsigned long flags; + }; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct s390_operand s390_operands[]; + +/* Values defined for the flags field of a struct s390_operand. */ + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define S390_OPERAND_GPR 0x1 + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define S390_OPERAND_FPR 0x2 + +/* This operand names an access register. The disassembler + prints these with a leading 'a'. */ +#define S390_OPERAND_AR 0x4 + +/* This operand names a control register. The disassembler + prints these with a leading 'c'. */ +#define S390_OPERAND_CR 0x8 + +/* This operand is a displacement. */ +#define S390_OPERAND_DISP 0x10 + +/* This operand names a base register. */ +#define S390_OPERAND_BASE 0x20 + +/* This operand names an index register, it can be skipped. */ +#define S390_OPERAND_INDEX 0x40 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define S390_OPERAND_PCREL 0x80 + +/* This operand takes signed values. */ +#define S390_OPERAND_SIGNED 0x100 + +/* This operand is a length. */ +#define S390_OPERAND_LENGTH 0x200 + +#endif /* S390_H */ |