diff options
Diffstat (limited to 'include/opcode')
46 files changed, 0 insertions, 24882 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog deleted file mode 100644 index 728230274..000000000 --- a/include/opcode/ChangeLog +++ /dev/null @@ -1,381 +0,0 @@ -2005-09-06 Chao-ying Fu <fu@mips.com> - - * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, - OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New - define. - Document !, $, *, &, g, +t, +T operand formats for MT instructions. - (INSN_ASE_MASK): Update to include INSN_MT. - (INSN_MT): New define for MT ASE. - -2005-08-25 Chao-ying Fu <fu@mips.com> - - * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, - OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, - OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, - OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, - OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. - Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP - instructions. - (INSN_DSP): New define for DSP ASE. - -2005-08-18 Alan Modra <amodra@bigpond.net.au> - - * a29k.h: Delete. - -2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> - - * ppc.h (PPC_OPCODE_E300): Define. - -2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. - -2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - PR gas/336 - * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb - and pitlb. - -2005-07-27 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add comment to movd. Use LongMem for all - movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. - Add movq-s as 64-bit variants of movd-s. - -2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h: Fix punctuation in comment. - - * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for - implicit space-register addressing. Set space-register bits on opcodes - using implicit space-register addressing. Add various missing pa20 - long-immediate opcodes. Remove various opcodes using implicit 3-bit - space-register addressing. Use "fE" instead of "fe" in various - fstw opcodes. - -2005-07-18 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Operands of aam and aad are unsigned. - -2007-07-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel VMX Instructions. - -2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. - -2005-07-05 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add new insns. - -2005-07-01 Nick Clifton <nickc@redhat.com> - - * sparc.h: Add typedefs to structure declarations. - -2005-06-20 H.J. Lu <hongjiu.lu@intel.com> - - PR 1013 - * i386.h (i386_optab): Update comments for 64bit addressing on - mov. Allow 64bit addressing for mov and movq. - -2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, - respectively, in various floating-point load and store patterns. - -2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (FLAG_STRICT): Correct comment. - (pa_opcodes): Update load and store entries to allow both PA 1.X and - PA 2.0 mneumonics when equivalent. Entries with cache control - completers now require PA 1.1. Adjust whitespace. - -2005-05-19 Anton Blanchard <anton@samba.org> - - * ppc.h (PPC_OPCODE_POWER5): Define. - -2005-05-10 Nick Clifton <nickc@redhat.com> - - * Update the address and phone number of the FSF organization in - the GPL notices in the following files: - a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, - crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, - i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, - mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, - pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, - tic54x.h, tic80.h, v850.h, vax.h - -2005-05-09 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add ht and hnt. - -2005-04-18 Mark Kettenis <kettenis@gnu.org> - - * i386.h: Insert hyphens into selected VIA PadLock extensions. - Add xcrypt-ctr. Provide aliases without hyphens. - -2005-04-13 H.J. Lu <hongjiu.lu@intel.com> - - Moved from ../ChangeLog - - 2005-04-12 Paul Brook <paul@codesourcery.com> - * m88k.h: Rename psr macros to avoid conflicts. - - 2005-03-12 Zack Weinberg <zack@codesourcery.com> - * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. - Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, - and ARM_ARCH_V6ZKT2. - - 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. - Remove redundant instruction types. - (struct argument): X_op - new field. - (struct cst4_entry): Remove. - (no_op_insn): Declare. - - 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum argtype): Rename types, remove unused types. - - 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. - (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. - (enum operand_type): Rearrange operands, edit comments. - replace us<N> with ui<N> for unsigned immediate. - replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped - displacements (respectively). - replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. - (instruction type): Add NO_TYPE_INS. - (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. - (operand_entry): New field - 'flags'. - (operand flags): New. - - 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (operand_type): Remove redundant types i3, i4, - i5, i8, i12. - Add new unsigned immediate types us3, us4, us5, us16. - -2005-04-12 Mark Kettenis <kettenis@gnu.org> - - * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and - adjust them accordingly. - -2005-04-01 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add rdtscp. - -2005-03-29 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Don't allow the `l' suffix for moving - between memory and segment register. Allow movq for moving between - general-purpose register and segment register. - -2005-02-09 Jan Beulich <jbeulich@novell.com> - - PR gas/707 - * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and - FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and - fnstsw. - -2005-01-25 Alexandre Oliva <aoliva@redhat.com> - - 2004-11-10 Alexandre Oliva <aoliva@redhat.com> - * cgen.h (enum cgen_parse_operand_type): Add - CGEN_PARSE_OPERAND_SYMBOLIC. - -2005-01-21 Fred Fish <fnf@specifixinc.com> - - * mips.h: Change INSN_ALIAS to INSN2_ALIAS. - Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. - Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. - -2005-01-19 Fred Fish <fnf@specifixinc.com> - - * mips.h (struct mips_opcode): Add new pinfo2 member. - (INSN_ALIAS): New define for opcode table entries that are - specific instances of another entry, such as 'move' for an 'or' - with a zero operand. - (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. - (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. - -2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> - - * mips.h (CPU_RM9000): Define. - (OPCODE_IS_MEMBER): Handle CPU_RM9000. - -2004-11-25 Jan Beulich <jbeulich@novell.com> - - * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves - to/from test registers are illegal in 64-bit mode. Add missing - NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix - (previously one had to explicitly encode a rex64 prefix). Re-enable - lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings - support it there. Add cmpxchg16b as per Intel's 64-bit documentation. - -2004-11-23 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): paddq and psubq, even in their MMX form, are - available only with SSE2. Change the MMX additions introduced by SSE - and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A - instructions by their now designated identifier (since combining i686 - and 3DNow! does not really imply 3DNow!A). - -2004-11-19 Alan Modra <amodra@bigpond.net.au> - - * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, - struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. - -2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> - Vineet Sharma <vineets@noida.hcltech.com> - - * maxq.h: New file: Disassembly information for the maxq port. - -2004-11-05 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Put back "movzb". - -2004-11-04 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (enum cris_insn_version_usage): Tweak formatting and - comments. Remove member cris_ver_sim. Add members - cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, - cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. - (struct cris_support_reg, struct cris_cond15): New types. - (cris_conds15): Declare. - (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) - (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) - (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. - (NOP_Z_BITS): Define in terms of NOP_OPCODE. - (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and - SIZE_FIELD_UNSIGNED. - -2004-11-04 Jan Beulich <jbeulich@novell.com> - - * i386.h (sldx_Suf): Remove. - (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. - (q_FP): Define, implying no REX64. - (x_FP, sl_FP): Imply FloatMF. - (i386_optab): Split reg and mem forms of moving from segment registers - so that the memory forms can ignore the 16-/32-bit operand size - distinction. Adjust a few others for Intel mode. Remove *FP uses from - all non-floating-point instructions. Unite 32- and 64-bit forms of - movsx, movzx, and movd. Adjust floating point operations for the above - changes to the *FP macros. Add DefaultSize to floating point control - insns operating on larger memory ranges. Remove left over comments - hinting at certain insns being Intel-syntax ones where the ones - actually meant are already gone. - -2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> - - * crx.h: Add COPS_REG_INS - Coprocessor Special register - instruction type. - -2004-09-30 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. - (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. - -2004-09-11 Theodore A. Roth <troth@openavr.org> - - * avr.h: Add support for - atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. - -2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> - - * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. - -2004-08-24 Dmitry Diky <diwil@spec.ru> - - * msp430.h (msp430_opc): Add new instructions. - (msp430_rcodes): Declare new instructions. - (msp430_hcodes): Likewise.. - -2004-08-13 Nick Clifton <nickc@redhat.com> - - PR/301 - * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX - processors. - -2004-08-30 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. - -2004-07-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. - -2004-07-21 Jan Beulich <jbeulich@novell.com> - - * i386.h: Adjust instruction descriptions to better match the - specification. - -2004-07-16 Richard Earnshaw <rearnsha@arm.com> - - * arm.h: Remove all old content. Replace with architecture defines - from gas/config/tc-arm.c. - -2004-07-09 Andreas Schwab <schwab@suse.de> - - * m68k.h: Fix comment. - -2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> - - * crx.h: New file. - -2004-06-24 Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. - -2004-05-24 Peter Barada <peter@the-baradas.com> - - * m68k.h: Add 'size' to m68k_opcode. - -2004-05-05 Peter Barada <peter@the-baradas.com> - - * m68k.h: Switch from ColdFire chip name to core variant. - -2004-04-22 Peter Barada <peter@the-baradas.com> - - * m68k.h: Add mcfmac/mcfemac definitions. Update operand - descriptions for new EMAC cases. - Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly - handle Motorola MAC syntax. - Allow disassembly of ColdFire V4e object files. - -2004-03-16 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. - -2004-03-12 Jakub Jelinek <jakub@redhat.com> - - * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added xstore as an alias for xstorerng. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added xstore/xcrypt insns. - -2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (32bit ldc/stc): Add relaxing support. - -2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (BITOP): Pass MEMRELAX flag. - -2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 - except for the H8S. - -For older changes see ChangeLog-9103 - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/include/opcode/ChangeLog-9103 b/include/opcode/ChangeLog-9103 deleted file mode 100644 index 9a04bf5f5..000000000 --- a/include/opcode/ChangeLog-9103 +++ /dev/null @@ -1,3121 +0,0 @@ -2005-04-13 H.J. Lu <hongjiu.lu@intel.com> - - 2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. - - 2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> - * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x - - 2002-11-16 Klee Dienes <kdienes@apple.com> - * m88k.h (INSTAB): Remove 'next' field. - (instruction): Remove definition; replace with extern declaration - and mark as const. - - 2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> - * tic4x.h: New file. - - 2002-07-25 Richard Sandiford <rsandifo@redhat.com> - * mips.h (CPU_R2000): Remove. - -2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> - Bernardo Innocenti <bernie@develer.com> - - * m68k.h: Add MCFv4/MCF5528x support. - -2003-10-19 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix.h (JMP_INSN_BYTE): Define. - -2003-09-30 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Document +E, +F, +G, +H, and +I operand types. - Update documentation of I, +B and +C operand types. - (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. - (M_DEXT, M_DINS): New enum values. - -2003-09-04 Nick Clifton <nickc@redhat.com> - - * v850.h (PROCESSOR_V850E1): Define. - -2003-08-19 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other - PPC_OPCODE_* defines. - -2003-08-16 Jason Eckhardt <jle@rice.edu> - - * i860.h (fmov.ds): Expand as famov.ds. - (fmov.sd): Expand as famov.sd. - (pfmov.ds): Expand as pfamov.ds. - -2003-08-07 Michael Meissner <gnu@the-meissners.org> - - * cgen.h: Remove PARAM macro usage in all prototypes. - (CGEN_EXTRACT_INFO): Use void * instead of PTR. - (cgen_print_fn): Ditto. - (CGEN_HW_ENTRY): Ditto. - (CGEN_MAYBE_MULTI_IFLD): Ditto. - (struct cgen_insn): Ditto. - (CGEN_CPU_TABLE): Ditto. - -2003-08-07 Alan Modra <amodra@bigpond.net.au> - - * alpha.h: Remove PARAMS macro. - * arc.h: Likewise. - * d10v.h: Likewise. - * d30v.h: Likewise. - * i370.h: Likewise. - * or32.h: Likewise. - * pj.h: Likewise. - * ppc.h: Likewise. - * sparc.h: Likewise. - * tic80.h: Likewise. - * v850.h: Likewise. - -2003-07-18 Michael Snyder <msnyder@redhat.com> - - * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting. - -2003-07-15 Richard Sandiford <rsandifo@redhat.com> - - * mips.h (CPU_RM7000): New macro. - (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. - -2003-07-09 Alexandre Oliva <aoliva@redhat.com> - - 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> - * mn10300.h (AM33_2): Renamed from AM33. - 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> - * mn10300.h (AM332, FMT_D3): Defined. - (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. - (MN10300_OPERAND_FPCR): Likewise. - -2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. - -2003-06-25 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. - (IMM8U, IMM8U_NS): Define. - (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. - -2003-06-25 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and - mov.l ERs,@(dd:32,ERd) entries. - -2003-06-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel Precott New Instructions. - -2003-06-10 Gary Hade <garyhade@us.ibm.com> - - * ppc.h (PPC_OPERAND_DQ): Define. - -2003-06-10 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (IMM4_NS, IMM8_NS): New. - (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries. - Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - - * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H. - (ldc): Split ccr ops from exr ops (which are only available - on H8S or H8SX). - (stc): Ditto. - (andc, orc, xorc): Ditto. - (ldmac, stmac, clrmac, mac): Change access to AV_H8S. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - and Bernd Schmidt <bernds@redhat.com> - and Alexandre Oliva <aoliva@redhat.com> - * h8300.h: Add support for h8300sx instruction set. - -2003-05-23 Jason Eckhardt <jle@rice.edu> - - * i860.h (expand_type): Add XP_ONLY. - (scyc.b): New XP instruction. - (ldio.l): Likewise. - (ldio.s): Likewise. - (ldio.b): Likewise. - (ldint.l): Likewise. - (ldint.s): Likewise. - (ldint.b): Likewise. - (stio.l): Likewise. - (stio.s): Likewise. - (stio.b): Likewise. - (pfld.q): Likewise. - -2003-05-20 Jason Eckhardt <jle@rice.edu> - - * i860.h (flush): Set lower 3 bits properly and use 'L' - for the immediate operand type instead of 'i'. - -2003-05-20 Jason Eckhardt <jle@rice.edu> - - * i860.h (fzchks): Both S and R bits must be set. - (pfzchks): Likewise. - (faddp): Likewise. - (pfaddp): Likewise. - (fix.ss): Remove (invalid instruction). - (pfix.ss): Likewise. - (ftrunc.ss): Likewise. - (pftrunc.ss): Likewise. - -2003-05-18 Jason Eckhardt <jle@rice.edu> - - * i860.h (form, pform): Add missing .dd suffix. - -2003-05-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000 - -2003-04-07 Michael Snyder <msnyder@redhat.com> - - * h8300.h (ldc/stc): Fix up src/dst swaps. - -2003-04-09 J. Grant <jg-binutils@jguk.org> - - * mips.h: Correct comment typo. - -2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val. - (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH. - (s390_opcode): Remove architecture. Add modes and min_cpu. - -2003-03-17 D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line - processing. - -2003-02-21 Noida D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32. - -2003-01-23 Alan Modra <amodra@bigpond.net.au> - - * m68hc11.h (cpu6812s): Define. - -2003-01-07 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Fix missing space in comment. - (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5) - (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right - by four bits. - -2003-01-02 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Update copyright years to include 2002 (which had - been missed previously) and 2003. Make comments about "+A", - "+B", and "+C" operand types more descriptive. - -2002-12-31 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Note that the "+D" operand type name is now used. - -2002-12-30 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Document "+" as the start of two-character operand - type names, and add new "K", "+A", "+B", and "+C" operand types. - (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) - (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New - defines. - -2002-12-24 Dmitry Diky <diwil@mail.ru> - - * msp430.h: New file. Defines msp430 opcodes. - -2002-12-30 D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h: Added some more pseudo opcodes for system call - processing. - -2002-12-19 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3) - (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2) - (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1) - (OP_OP_SDC2, OP_OP_SDC3): Define. - -2002-12-16 Alan Modra <amodra@bigpond.net.au> - - * hppa.h (completer_chars): #if 0 out. - - * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and - "default_args". - (struct not_wot): Constify "args". - (struct not): Constify "name". - (numopcodes): Delete. - (endop): Delete. - -2002-12-13 Alan Modra <amodra@bigpond.net.au> - - * pj.h (pj_opc_info_t): Add union. - -2002-12-04 David Mosberger <davidm@hpl.hp.com> - - * ia64.h: Fix copyright message. - (IA64_OPND_AR_CSD): New operand kind. - -2002-12-03 Richard Henderson <rth@redhat.com> - - * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. - -2002-12-03 Alan Modra <amodra@bigpond.net.au> - - * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union. - Constify "leaf" and "multi". - -2002-11-19 Klee Dienes <kdienes@apple.com> - - * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size' - fields. - (h8_opcodes). Modify initializer and initializer macros to no - longer initialize the removed fields. - -2002-11-19 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h (c4x_insts): Fixed LDHI constraint - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * h8300.h (h8_opcode): Remove 'length' field. - (h8_opcodes): Mark as 'const' (both the declaration and - definition). Modify initializer and initializer macros to no - longer initialize the length field. - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * arc.h (arc_ext_opcodes): Declare as extern. - (arc_ext_operands): Declare as extern. - * i860.h (i860_opcodes): Declare as const. - -2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: File reordering. Added enhanced opcodes. - -2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: Major rewrite of entire file. Define instruction - classes, and put each instruction into a class. - -2002-11-11 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: Added new opcodes and corrected some bugs. Add support - for new DSP types. - -2002-10-14 Alan Modra <amodra@bigpond.net.au> - - * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE. - -2002-09-30 Gavin Romig-Koch <gavin@redhat.com> - Ken Raeburn <raeburn@cygnus.com> - Aldy Hernandez <aldyh@redhat.com> - Eric Christopher <echristo@redhat.com> - Richard Sandiford <rsandifo@redhat.com> - - * mips.h: Update comment for new opcodes. - (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. - (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. - (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. - (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. - (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. - Don't match CPU_R4111 with INSN_4100. - -2002-08-19 Elena Zannoni <ezannoni@redhat.com> - - From matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 - instructions. - (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, - PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the - e500x2 Integer select, branch locking, performance monitor, - cache locking and machine check APUs, respectively. - (PPC_OPCODE_EFS): New opcode type for efs* instructions. - (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions. - -2002-08-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11.h (M6812_OP_PAGE): Define to identify call operand. - (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, - M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 - memory banks. - (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value. - -2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_MIPS16): New define. - -2002-07-08 Alan Modra <amodra@bigpond.net.au> - - * i386.h: Remove IgnoreSize from movsx and movzx. - -2002-06-08 Alan Modra <amodra@bigpond.net.au> - - * a29k.h: Replace CONST with const. - (CONST): Don't define. - * convex.h: Replace CONST with const. - (CONST): Don't define. - * dlx.h: Replace CONST with const. - * or32.h (CONST): Don't define. - -2002-05-30 Chris G. Demetriou <cgd@broadcom.com> - - * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) - (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) - (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) - (INSN_MDMX): New constants, for MDMX support. - (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. - -2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> - - * dlx.h: New file. - -2002-05-25 Alan Modra <amodra@bigpond.net.au> - - * ia64.h: Use #include "" instead of <> for local header files. - * sparc.h: Likewise. - -2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. - -2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> - - * h8300.h: Corrected defs of all control regs - and eepmov instr. - -2002-04-11 Alan Modra <amodra@bigpond.net.au> - - * i386.h: Add intel mode cmpsd and movsd. - Put them before SSE2 insns, so that rep prefix works. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D - instructions. - (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks - may be passed along with the ISA bitmask. - -2002-03-05 Paul Koning <pkoning@equallogic.com> - - * pdp11.h: Add format codes for float instruction formats. - -2002-02-25 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define. - -Mon Feb 18 17:31:48 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. - -Mon Feb 11 12:53:19 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386.h (push,pop): Allow 16bit operands in 64bit mode. - (xchg): Fix. - (in, out): Disable 64bit operands. - (call, jmp): Avoid REX prefixes. - (jcxz): Prohibit in 64bit mode - (jrcxz, loop): Add 64bit variants. - (movq): Fix patterns. - (movmskps, pextrw, pinstrw): Add 64bit variants. - -2002-01-31 Ivan Guzvinec <ivang@opencores.org> - - * or32.h: New file. - -2002-01-22 Graydon Hoare <graydon@redhat.com> - - * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. - (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. - -2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> - - * h8300.h: Comment typo fix. - -2002-01-03 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. - (PPC_OPCODE_BOOKE64): Likewise. - -Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) - - * hppa.h (call, ret): Move to end of table. - (addb, addib): PA2.0 variants should have been PA2.0W. - (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler - happy. - (fldw, fldd, fstw, fstd, bb): Likewise. - (short loads/stores): Tweak format specifier slightly to keep - disassembler happy. - (indexed loads/stores): Likewise. - (absolute loads/stores): Likewise. - -2001-12-04 Alexandre Oliva <aoliva@redhat.com> - - * d10v.h (OPERAND_NOSP): New macro. - -2001-11-29 Alexandre Oliva <aoliva@redhat.com> - - * d10v.h (OPERAND_SP): New macro. - -2001-11-15 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. - -2001-11-11 Timothy Wall <twall@alum.mit.edu> - - * tic54x.h: Revise opcode layout; don't really need a separate - structure for parallel opcodes. - -2001-11-13 Zack Weinberg <zack@codesourcery.com> - Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to - accept WordReg. - -2001-11-04 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OPCODE_IS_MEMBER): Remove extra space. - -2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix.h: New file. - -2001-10-18 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end - of the expression, to make source code merging easier. - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Sort coprocessor instruction argument characters - in comment, add a few more words of description for "H". - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips.h (INSN_SB1): New cpu-specific instruction bit. - (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 - if cpu is CPU_SB1. - -2001-10-17 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. - -2001-10-12 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New - opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 - instructions, respectively. - -2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> - - * v850.h: Remove spurious comment. - -2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> - - * h8300.h: Fix compile time warning messages - -2001-09-04 Richard Henderson <rth@redhat.com> - - * alpha.h (struct alpha_operand): Pack elements into bitfields. - -2001-08-31 Eric Christopher <echristo@redhat.com> - - * mips.h: Remove CPU_MIPS32_4K. - -2001-08-27 Torbjorn Granlund <tege@swox.com> - - * ppc.h (PPC_OPERAND_DS): Define. - -2001-08-25 Andreas Jaeger <aj@suse.de> - - * d30v.h: Fix declaration of reg_name_cnt. - - * d10v.h: Fix declaration of d10v_reg_name_cnt. - - * arc.h: Add prototypes from opcodes/arc-opc.c. - -2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_10000): Define. - (OPCODE_IS_MEMBER): Check for INSN_10000. - -2001-08-10 Alan Modra <amodra@one.net.au> - - * ppc.h: Revert 2001-08-08. - -2001-08-10 Richard Sandiford <rsandifo@redhat.com> - - * mips.h (INSN_GP32): Remove. - (OPCODE_IS_MEMBER): Remove gp32 parameter. - (M_MOVE): New macro identifier. - -2001-08-08 Alan Modra <amodra@one.net.au> - - 1999-10-25 Torbjorn Granlund <tege@swox.com> - * ppc.h (struct powerpc_operand): New field `reloc'. - -2001-08-01 Aldy Hernandez <aldyh@redhat.com> - - * mips.h (INSN_ISA_MASK): Nuke bits 12-15. - -2001-07-12 Jeff Johnston <jjohnstn@redhat.com> - - * cgen.h (CGEN_INSN): Add regex support. - (build_insn_regex): Declare. - -2001-07-11 Frank Ch. Eigler <fche@redhat.com> - - * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. - (cgen_cpu_desc): Ditto. - -2001-07-07 Ben Elliston <bje@redhat.com> - - * m88k.h: Clean up and reformat. Remove unused code. - -2001-06-14 Geoffrey Keating <geoffk@redhat.com> - - * cgen.h (cgen_keyword): Add nonalpha_chars field. - -2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (CPU_R12000): Define. - -2001-05-23 John Healy <jhealy@redhat.com> - - * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. - -2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_ISA_MASK): Define. - -2001-05-12 Alan Modra <amodra@one.net.au> - - * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg, - not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq, - and use InvMem as these insns must have register operands. - -2001-05-04 Alan Modra <amodra@one.net.au> - - * i386.h (i386_optab): Move InvMem to first operand of pmovmskb - and pextrw to swap reg/rm assignments. - -2001-04-05 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (enum cris_insn_version_usage): Correct comment for - cris_ver_v3p. - -2001-03-24 Alan Modra <alan@linuxcare.com.au> - - * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". - Add InvMem to first operand of "maskmovdqu". - -2001-03-22 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (ADD_PC_INCR_OPCODE): New macro. - -2001-03-21 Kazu Hirata <kazu@hxi.com> - - * h8300.h: Fix formatting. - -2001-03-22 Alan Modra <alan@linuxcare.com.au> - - * i386.h (i386_optab): Add paddq, psubq. - -2001-03-19 Alan Modra <alan@linuxcare.com.au> - - * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. - -2001-02-28 Igor Shevlyakov <igor@windriver.com> - - * m68k.h: new defines for Coldfire V4. Update mcf to know - about mcf5407. - -2001-02-18 lars brinkhoff <lars@nocrew.org> - - * pdp11.h: New file. - -2001-02-12 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): SSE integer converison instructions have - 64bit versions on x86-64. - -2001-02-10 Nick Clifton <nickc@redhat.com> - - * mips.h: Remove extraneous whitespace. Formating change to allow - for future contribution. - -2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h: New file. - -2001-02-02 Patrick Macdonald <patrickm@redhat.com> - - * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. - (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. - (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. - -2001-01-24 Karsten Keil <kkeil@suse.de> - - * i386.h (i386_optab): Fix swapgs - -2001-01-14 Alan Modra <alan@linuxcare.com.au> - - * hppa.h: Describe new '<' and '>' operand types, and tidy - existing comments. - (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. - Remove duplicate "ldw j(s,b),x". Sort some entries. - -2001-01-13 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Fix pusha and ret templates. - -2001-01-11 Peter Targett <peter.targett@arccores.com> - - * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New - definitions for masking cpu type. - (arc_ext_operand_value) New structure for storing extended - operands. - (ARC_OPERAND_*) Flags for operand values. - -2001-01-10 Jan Hubicka <jh@suse.cz> - - * i386.h (pinsrw): Add. - (pshufw): Remove. - (cvttpd2dq): Fix operands. - (cvttps2dq): Likewise. - (movq2q): Rename to movdq2q. - -2001-01-10 Richard Schaal <richard.schaal@intel.com> - - * i386.h: Correct movnti instruction. - -2001-01-09 Jeff Johnston <jjohnstn@redhat.com> - - * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number - of operands (unsigned char or unsigned short). - (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. - (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char. - -2001-01-05 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Make [sml]fence template to use immext field. - -2001-01-03 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Fix 64bit pushf template; Add instructions - introduced by Pentium4 - -2000-12-30 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Add "rex*" instructions; - add swapgs; disable jmp/call far direct instructions for - 64bit mode; add syscall and sysret; disable registers for 0xc6 - template. Add 'q' suffixes to extendable instructions, disable - obsolete instructions, add new sign/zero extension ones. - (i386_regtab): Add extended registers. - (*Suf): Add No_qSuf. - (q_Suf, wlq_Suf, bwlq_Suf): New. - -2000-12-20 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Replace "Imm" with "EncImm". - (i386_regtab): Add flags field. - -2000-12-12 Nick Clifton <nickc@redhat.com> - - * mips.h: Fix formatting. - -2000-12-01 Chris Demetriou <cgd@sibyte.com> - - mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. - (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old - OP_*_SYSCALL definitions. - (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as - 19 bit wait codes. - (MIPS operand specifier comments): Remove 'm', add 'U' and - 'J', and update the meaning of 'B' so that it's more general. - - * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, - INSN_ISA5): Renumber, redefine to mean the ISA at which the - instruction was added. - (INSN_ISA32): New constant. - (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): - Renumber to avoid new and/or renumbered INSN_* constants. - (INSN_MIPS32): Delete. - (ISA_UNKNOWN): New constant to indicate unknown ISA. - (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, - ISA_MIPS32): New constants, defined to be the mask of INSN_* - constants available at that ISA level. - (CPU_UNKNOWN): New constant to indicate unknown CPU. - (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, - define it with a unique value. - (OPCODE_IS_MEMBER): Update for new ISA membership-related - constant meanings. - - * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New - definitions. - - * mips.h (CPU_SB1): New constant. - -2000-10-20 Jakub Jelinek <jakub@redhat.com> - - * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. - Note that '3' is used for siam operand. - -2000-09-22 Jim Wilson <wilson@cygnus.com> - - * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. - -2000-09-13 Anders Norlander <anorland@acc.umu.se> - - * mips.h: Use defines instead of hard-coded processor numbers. - (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, - CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, - CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, - CPU_4KC, CPU_4KM, CPU_4KP): Define.. - (OPCODE_IS_MEMBER): Use new defines. - (OP_MASK_SEL, OP_SH_SEL): Define. - (OP_MASK_CODE20, OP_SH_CODE20): Define. - Add 'P' to used characters. - Use 'H' for coprocessor select field. - Use 'm' for 20 bit breakpoint code. - Document new arg characters and add to used characters. - (INSN_MIPS32): New define for MIPS32 extensions. - (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. - -2000-09-05 Alan Modra <alan@linuxcare.com.au> - - * hppa.h: Mention cz completer. - -2000-08-16 Jim Wilson <wilson@cygnus.com> - - * ia64.h (IA64_OPCODE_POSTINC): New. - -2000-08-15 H.J. Lu <hjl@gnu.org> - - * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the - IgnoreSize change. - -2000-08-08 Jason Eckhardt <jle@cygnus.com> - - * i860.h: Small formatting adjustments. - -2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. - Move related opcodes closer to each other. - Minor changes in comments, list undefined opcodes. - -2000-07-26 Dave Brolley <brolley@redhat.com> - - * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned. - -2000-07-22 Jason Eckhardt <jle@cygnus.com> - - * i860.h (btne, bte, bla): Changed these opcodes - to use sbroff ('r') instead of split16 ('s'). - (J, K, L, M): New operand types for 16-bit aligned fields. - (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to - use I, J, K, L, M instead of just I. - (T, U): New operand types for split 16-bit aligned fields. - (st.x): Changed these opcodes to use S, T, U instead of just S. - (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not - exist on the i860. - (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. - (pfeq.ss, pfeq.dd): New opcodes. - (st.s): Fixed incorrect mask bits. - (fmlow): Fixed incorrect mask bits. - (fzchkl, pfzchkl): Fixed incorrect mask bits. - (faddz, pfaddz): Fixed incorrect mask bits. - (form, pform): Fixed incorrect mask bits. - (pfld.l): Fixed incorrect mask bits. - (fst.q): Fixed incorrect mask bits. - (all floating point opcodes): Fixed incorrect mask bits for - handling of dual bit. - -2000-07-20 Hans-Peter Nilsson <hp@axis.com> - - cris.h: New file. - -2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA. - (AVR_ISA_ESPM): Remove, because ESPM removed in databook update. - (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx. - (AVR_ISA_M83): Define for ATmega83, ATmega85. - (espm): Remove, because ESPM removed in databook update. - (eicall, eijmp): Move to the end of opcode table. - -2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> - - * m68hc11.h: New file for support of Motorola 68hc11. - -Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru> - - * avr.h: clr,lsl,rol, ... moved after add,adc, ... - -Wed Jun 7 21:39:54 2000 Denis Chertykov <denisc@overta.ru> - - * avr.h: New file with AVR opcodes. - -Wed Apr 12 17:11:20 2000 Donald Lindsay <dlindsay@hound.cygnus.com> - - * d10v.h: added ALONE attribute for d10v_opcode.exec_type. - -2000-05-23 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * i386.h: Allow d suffix on iret, and add DefaultSize modifier. - -2000-05-17 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * i386.h: Use sl_FP, not sl_Suf for fild. - -2000-05-16 Frank Ch. Eigler <fche@redhat.com> - - * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that - it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. - (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds - CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set. - -2000-05-13 Alan Modra <alan@linuxcare.com.au>, - - * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore. - -2000-05-13 Alan Modra <alan@linuxcare.com.au>, - Alexander Sokolov <robocop@netlink.ru> - - * i386.h (i386_optab): Add cpu_flags for all instructions. - -2000-05-13 Alan Modra <alan@linuxcare.com.au> - - From Gavin Romig-Koch <gavin@cygnus.com> - * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa. - -2000-05-04 Timothy Wall <twall@cygnus.com> - - * tic54x.h: New. - -2000-05-03 J.T. Conklin <jtc@redback.com> - - * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. - (PPC_OPERAND_VR): New operand flag for vector registers. - -2000-05-01 Kazu Hirata <kazu@hxi.com> - - * h8300.h (EOP): Add missing initializer. - -Fri Apr 21 15:03:37 2000 Jason Eckhardt <jle@cygnus.com> - - * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode - forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). - New operand types l,y,&,fe,fE,fx added to support above forms. - (pa_opcodes): Replaced usage of 'x' as source/target for - floating point double-word loads/stores with 'fx'. - -Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> - David Mosberger <davidm@hpl.hp.com> - Timothy Wall <twall@cygnus.com> - Jim Wilson <wilson@cygnus.com> - - * ia64.h: New file. - -2000-03-27 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_A1): Fix value. - (SHORT_AR): Renumber so that it is at the end of the list of short - instructions, not the end of the list of long instructions. - -2000-03-26 Alan Modra <alan@linuxcare.com> - - * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the - problem isn't really specific to Unixware. - (OLDGCC_COMPAT): Define. - (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with - destination %st(0). - Fix lots of comments. - -2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d30v.h: - (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. - (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. - (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. - (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. - (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. - (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. - (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. - -2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (fild, fistp): Change intel d_Suf form to fildd and - fistpd without suffix. - -2000-02-24 Nick Clifton <nickc@cygnus.com> - - * cgen.h (cgen_cpu_desc): Rename field 'flags' to - 'signed_overflow_ok_p'. - Delete prototypes for cgen_set_flags() and cgen_get_flags(). - -2000-02-24 Andrew Haley <aph@cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - (CGEN_CPU_TABLE): flags: new field. - Add prototypes for new functions. - -2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add some more UNIXWARE_COMPAT comments. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370.h: New file. - -2000-02-22 Chandra Chavva <cchavva@cygnus.com> - - * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation - cannot be combined in parallel with ADD/SUBppp. - -2000-02-22 Andrew Haley <aph@cygnus.com> - - * mips.h: (OPCODE_IS_MEMBER): Add comment. - -1999-12-30 Andrew Haley <aph@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines - whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit - insns. - -2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Qualify intel mode far call and jmp with x_Suf. - -1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add JumpAbsolute qualifier to all non-intel mode - indirect jumps and calls. Add FF/3 call for intel mode. - -Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add new operand types. Add new instruction formats. - -Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" - instruction. - -1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (INSN_ISA5): New. - -1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): New. - -1999-10-29 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_AR): Define. - -1999-10-18 Michael Meissner <meissner@cygnus.com> - - * alpha.h (alpha_num_opcodes): Convert to unsigned. - (alpha_num_operands): Ditto. - -Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> - - * hppa.h (pa_opcodes): Add load and store cache control to - instructions. Add ordered access load and store. - - * hppa.h (pa_opcode): Add new entries for addb and addib. - - * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. - - * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. - -Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> - - * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. - -Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" - and "be" using completer prefixes. - - * hppa.h (pa_opcodes): Add initializers to silence compiler. - - * hppa.h: Update comments about character usage. - -Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning - up the new fstw & bve instructions. - -Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store - instructions. - - * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. - - * hppa.h (pa_opcodes): Add long offset double word load/store - instructions. - - * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and - stores. - - * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. - - * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. - - * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. - - * hppa.h (pa_opcodes): Add new syntax "be" instructions. - - * hppa.h (pa_opcodes): Note use of 'M' and 'L'. - - * hppa.h (pa_opcodes): Add support for "b,l". - - * hppa.h (pa_opcodes): Add support for "b,gate". - -Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Use 'fX' for first register operand - in xmpyu. - - * hppa.h (pa_opcodes): Fix mask for probe and probei. - - * hppa.h (pa_opcodes): Fix mask for depwi. - -Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as - an explicit output argument. - -Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. - Add a few PA2.0 loads and store variants. - -1999-09-04 Steve Chamberlain <sac@pobox.com> - - * pj.h: New file. - -1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_regtab): Move %st to top of table, and split off - other fp reg entries. - (i386_float_regtab): To here. - -Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args - by 'f'. - - * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. - Add supporting args. - - * hppa.h: Document new completers and args. - * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, - uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 - extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions - pmenb and pmdis. - - * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, - hshr, hsub, mixh, mixw, permh. - - * hppa.h (pa_opcodes): Change completers in instructions to - use 'c' prefix. - - * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, - hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. - - * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, - fnegabs to use 'I' instead of 'F'. - -1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. - Document pf2iw and pi2fw as athlon insns. Remove pswapw. - Alphabetically sort PIII insns. - -Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - -Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, - and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. - - * hppa.h: Document 64 bit condition completers. - -Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Change condition args to use '?' prefix. - -1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Add DefaultSize modifier to all insns - that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, - sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. - -Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> - Jeff Law <law@cygnus.com> - - * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". - - * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. - - * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, - and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. - -1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. - -Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (struct pa_opcode): Add new field "flags". - (FLAGS_STRICT): Define. - -Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> - Jeff Law <law@cygnus.com> - - * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. - - * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. - -1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, - lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP - flag to fcomi and friends. - -Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Move integer arithmetic instructions after - integer logical instructions. - -1999-05-28 Linus Nordberg <linus.nordberg@canit.se> - - * m68k.h: Document new formats `E', `G', `H' and new places `N', - `n', `o'. - - * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' - and new places `m', `M', `h'. - -Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com - - * hppa.h (pa_opcodes): Add several processor specific system - instructions. - -Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add second entry for "comb", "comib", - "addb", and "addib" to be used by the disassembler. - -1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> - - * i386.h (ReverseModrm): Remove all occurences. - (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, - movmskps, pextrw, pmovmskb, maskmovq. - Change NoSuf to FP on all MMX, XMM and AMD insns as these all - ignore the data size prefix. - - * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. - Mostly stolen from Doug Ledford <dledford@redhat.com> - -Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> - - * ppc.h (PPC_OPCODE_64_BRIDGE): New. - -1999-04-14 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ATTR): Delete member num_nonbools. - (CGEN_ATTR_TYPE): Update. - (CGEN_ATTR_MASK): Number booleans starting at 0. - (CGEN_ATTR_VALUE): Update. - (CGEN_INSN_ATTR): Update. - -Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0 - instructions. - -Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (bb, bvb): Tweak opcode/mask. - - -1999-03-22 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs. - (struct cgen_cpu_desc): Rename member mach to machs. New member isas. - New members word_bitsize,default_insn_bitsize,base_insn-bitsize, - min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables. - Delete member max_insn_size. - (enum cgen_cpu_open_arg): New enum. - (cpu_open): Update prototype. - (cpu_open_1): Declare. - (cgen_set_cpu): Delete. - -1999-03-11 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member. - (CGEN_OPERAND_NIL): New macro. - (CGEN_OPERAND): New member `type'. - (@arch@_cgen_operand_table): Delete decl. - (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete. - (CGEN_OPERAND_TABLE): New struct. - (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare. - (CGEN_OPINST): Pointer to operand table entry replaced with enum. - (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table', - now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to - {get,set}_{int,vma}_operand. - (@arch@_cgen_cpu_open): New arg `isa'. - (cgen_set_cpu): Ditto. - -Fri Feb 26 02:36:45 1999 Richard Henderson <rth@cygnus.com> - - * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms. - -1999-02-25 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE. - (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to - enum cgen_hw_type. - (CGEN_HW_TABLE): New struct. - (hw_table): Delete declaration. - (CGEN_OPERAND): Change member hw to hw_type, change type from pointer - to table entry to enum. - (CGEN_OPINST): Ditto. - (CGEN_CPU_TABLE): Change member hw_list to hw_table. - -Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> - - * alpha.h (AXP_OPCODE_EV6): New. - (AXP_OPCODE_NOPAL): Include it. - -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC. - All uses updated. New members int_insn_p, max_insn_size, - parse_operand,insert_operand,extract_operand,print_operand, - sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand, - get_vma_operand,set_vma_operand,parse_handlers,insert_handlers, - extract_handlers,print_handlers. - (CGEN_ATTR): Change type of num_nonbools to unsigned int. - (CGEN_ATTR_BOOL_OFFSET): New macro. - (CGEN_ATTR_MASK): Subtract it to compute bit number. - (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation. - (cgen_opcode_handler): Renamed from cgen_base. - (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated. - (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR, - all uses updated. - (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global. - (enum cgen_opinst_type): Renamed from cgen_operand_instance_type. - (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated. - (CGEN_OPCODE,CGEN_IBASE): New types. - (CGEN_INSN): Rewrite. - (CGEN_{ASM,DIS}_HASH*): Delete. - (init_opcode_table,init_ibld_table): Declare. - (CGEN_INSN_ATTR): New type. - -Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> - - * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. - (x_FP, d_FP, dls_FP, sldx_FP): Define. - Change *Suf definitions to include x and d suffixes. - (movsx): Use w_Suf and b_Suf. - (movzx): Likewise. - (movs): Use bwld_Suf. - (fld): Change ordering. Use sld_FP. - (fild): Add Intel Syntax equivalent of fildq. - (fst): Use sld_FP. - (fist): Use sld_FP. - (fstp): Use sld_FP. Add x_FP version. - (fistp): LLongMem version for Intel Syntax. - (fcom, fcomp): Use sld_FP. - (fadd, fiadd, fsub): Use sld_FP. - (fsubr): Use sld_FP. - (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP. - -1999-01-27 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, - CGEN_MODE_UINT. - -1999-01-16 Jeffrey A Law (law@cygnus.com) - - * hppa.h (bv): Fix mask. - -1999-01-05 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef. - (CGEN_ATTR): Use it. - (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto. - (CGEN_ATTR_TABLE): New member dfault. - -1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (MIPS16_INSN_BRANCH): New. - -Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> - - The following is part of a change made by Edith Epstein - <eepstein@sophia.cygnus.com> as part of a project to merge in - changes by HP; HP did not create ChangeLog entries. - - * hppa.h (completer_chars): list of chars to not put a space - after. - -Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> - - * i386.h (i386_optab): Permit w suffix on processor control and - status word instructions. - -1998-11-30 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (struct cgen_hw_entry): Delete const on attrs member. - (struct cgen_keyword_entry): Ditto. - (struct cgen_operand): Ditto. - (CGEN_IFLD): New typedef, with associated access macros. - (CGEN_IFMT): New typedef, with associated access macros. - (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'. - (CGEN_IVALUE): New typedef. - (struct cgen_insn): Delete const on syntax,attrs members. - `format' now points to format data. Type of `value' is now - CGEN_IVALUE. - (struct cgen_opcode_table): New member ifld_table. - -1998-11-18 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (cgen_extract_fn): Update type of `base_insn' arg. - (CGEN_OPERAND_INSTANCE): New member `attrs'. - (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros. - (cgen_dis_lookup_insn): Update type of `base_insn' arg. - (cgen_opcode_table): Update type of dis_hash fn. - (extract_operand): Update type of `insn_value' arg. - -Thu Oct 29 11:38:36 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete. - -Tue Oct 27 08:57:59 1998 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (INSN_MULT): Added. - -Tue Oct 20 11:31:34 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE. - -Mon Oct 19 12:50:00 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_INSN_INT): New typedef. - (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN. - (CGEN_INSN_BYTES): Renamed from cgen_insn_t. - (CGEN_INSN_BYTES_PTR): New typedef. - (CGEN_EXTRACT_INFO): New typedef. - (cgen_insert_fn,cgen_extract_fn): Update. - (cgen_opcode_table): New member `insn_endian'. - (assemble_insn,lookup_insn,lookup_get_insn_operands): Update. - (insert_operand,extract_operand): Update. - (cgen_get_insn_value,cgen_put_insn_value): Add prototypes. - -Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_ATTR_BOOLS): New macro. - (struct CGEN_HW_ENTRY): New member `attrs'. - (CGEN_HW_ATTR): New macro. - (struct CGEN_OPERAND_INSTANCE): New member `name'. - (CGEN_INSN_INVALID_P): New macro. - -Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add "fid". - -Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - From Robert Andrew Dale <rob@nb.net> - * i386.h (i386_optab): Add AMD 3DNow! instructions. - (AMD_3DNOW_OPCODE): Define. - -Tue Sep 22 17:53:47 1998 Nick Clifton <nickc@cygnus.com> - - * d30v.h (EITHER_BUT_PREFER_MU): Define. - -Mon Aug 10 14:09:38 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (cgen_insn): #if 0 out element `cdx'. - -Mon Aug 3 12:21:57 1998 Doug Evans <devans@seba.cygnus.com> - - Move all global state data into opcode table struct, and treat - opcode table as something that is "opened/closed". - * cgen.h (CGEN_OPCODE_DESC): New type. - (all fns): New first arg of opcode table descriptor. - (cgen_set_parse_operand_fn): Add prototype. - (cgen_current_machine,cgen_current_endian): Delete. - (CGEN_OPCODE_TABLE): New members mach,endian,operand_table, - parse_operand_fn,asm_hash_table,asm_hash_table_entries, - dis_hash_table,dis_hash_table_entries. - (opcode_open,opcode_close): Add prototypes. - - * cgen.h (cgen_insn): New element `cdx'. - -Thu Jul 30 21:44:25 1998 Frank Ch. Eigler <fche@cygnus.com> - - * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions. - -Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add "no_match_operands" field for instructions. - (MN10300_MAX_OPERANDS): Define. - -Fri Jul 24 11:44:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (cgen_macro_insn_count): Declare. - -Tue Jul 21 13:12:13 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define. - (cgen_insert_fn,cgen_extract_fn): New arg `pc'. - (get_operand,put_operand): Replaced with get_{int,vma}_operand, - set_{int,vma}_operand. - -Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add "machine" field for instructions. - (MN103, AM30): Define machine types. - -Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. - -1998-06-18 Ulrich Drepper <drepper@cygnus.com> - - * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit. - -Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Add general form of aad and aam. Add ud2a - and ud2b. - (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just - those that happen to be implemented on pentiums. - -Tue Jun 9 12:16:01 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Change occurences of Data16 to Size16, Data32 to Size32, - IgnoreDataSize to IgnoreSize. Flag address and data size prefixes - with Size16|IgnoreSize or Size32|IgnoreSize. - -Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. - (REPE): Rename to REPE_PREFIX_OPCODE. - (i386_regtab_end): Remove. - (i386_prefixtab, i386_prefixtab_end): Remove. - (i386_optab): Use NULL as sentinel rather than "" to suit rewrite - of md_begin. - (MAX_OPCODE_SIZE): Define. - (i386_optab_end): Remove. - (sl_Suf): Define. - (sl_FP): Use sl_Suf. - - * i386.h (i386_optab): Allow 16 bit displacement for `mov - mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 - bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, - data32, dword, and adword prefixes. - (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index - regs. - -Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_regtab): Remove BaseIndex modifier from esp. - - * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with - register operands, because this is a common idiom. Flag them with - a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp, - fdivrp because gcc erroneously generates them. Also flag with a - warning. - - * i386.h: Add suffix modifiers to most insns, and tighter operand - checks in some cases. Fix a number of UnixWare compatibility - issues with float insns. Merge some floating point opcodes, using - new FloatMF modifier. - (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for - consistency. - - * i386.h: Change occurence of ShortformW to W|ShortForm. Add - IgnoreDataSize where appropriate. - -Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: (one_byte_segment_defaults): Remove. - (two_byte_segment_defaults): Remove. - (i386_regtab): Add BaseIndex to 32 bit regs reg_type. - -Fri May 15 15:59:04 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. - (cgen_hw_lookup_by_num): Declare. - -Thu May 7 09:27:58 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower - ten bits of MIPS ISA1 "break" instruction, and for "sdbbp" - -Thu May 7 02:14:08 1998 Doug Evans <devans@charmed.cygnus.com> - - * cgen.h (cgen_asm_init_parse): Delete. - (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete. - (cgen_asm_record_register,cgen_asm_finish_insn): Delete. - -Mon Apr 27 10:13:11 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses. - (cgen_asm_finish_insn): Update prototype. - (cgen_insn): New members num, data. - (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size, - dis_hash, dis_hash_table_size moved to ... - (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA. - All uses updated. New members asm_hash_p, dis_hash_p. - (CGEN_MINSN_EXPANSION): New struct. - (cgen_expand_macro_insn): Declare. - (cgen_macro_insn_count): Declare. - (get_insn_operands): Update prototype. - (lookup_get_insn_operands): Declare. - -Tue Apr 21 17:11:32 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Change iclrKludge and imulKludge to - regKludge. Add operands types for string instructions. - -Mon Apr 20 14:40:29 1998 Tom Tromey <tromey@cygnus.com> - - * i386.h (X): Renamed from `Z_' to preserve formatting of opcode - table. - -Sun Apr 19 13:54:06 1998 Tom Tromey <tromey@cygnus.com> - - * i386.h (Z_): Renamed from `_' to avoid clash with common alias - for `gettext'. - -Fri Apr 3 12:04:48 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Remove NoModrm flag from all insns: it's never checked. - Add IsString flag to string instructions. - (IS_STRING): Don't define. - (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define. - (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define. - (SS_PREFIX_OPCODE): Define. - -Mon Mar 30 21:31:56 1998 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Revert March 24 patch; no more LinearAddress. - -Mon Mar 30 10:25:54 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Remove fwait (9b) from all floating point - instructions, and instead add FWait opcode modifier. Add short - form of fldenv and fstenv. - (FWAIT_OPCODE): Define. - - * i386.h (i386_optab): Change second operand constraint of `mov - sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to - allow legal instructions such as `movl %gs,%esi' - -Fri Mar 27 18:30:52 1998 Ian Lance Taylor <ian@cygnus.com> - - * h8300.h: Various changes to fully bracket initializers. - -Tue Mar 24 18:32:47 1998 H.J. Lu <hjl@gnu.org> - - * i386.h: Set LinearAddress for lidt and lgdt. - -Mon Mar 2 10:44:07 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_BOOL_ATTR): New macro. - -Thu Feb 26 15:54:31 1998 Michael Meissner <meissner@cygnus.com> - - * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps. - -Mon Feb 23 10:38:21 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. - (cgen_insn): Record syntax and format entries here, rather than - separately. - -Tue Feb 17 21:42:56 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro. - -Tue Feb 17 16:00:56 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (cgen_insert_fn): Change type of result to const char *. - (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. - (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS. - -Thu Feb 12 18:30:41 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (lookup_insn): New argument alias_p. - -Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> - -Fix rac to accept only a0: - * d10v.h (OPERAND_ACC): Split into: - (OPERAND_ACC0, OPERAND_ACC1) . - (OPERAND_GPR): Define. - -Wed Feb 11 17:31:53 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_FIELDS): Define here. - (CGEN_HW_ENTRY): New member `type'. - (hw_list): Delete decl. - (enum cgen_mode): Declare. - (CGEN_OPERAND): New member `hw'. - (enum cgen_operand_instance_type): Declare. - (CGEN_OPERAND_INSTANCE): New type. - (CGEN_INSN): New member `operands'. - (CGEN_OPCODE_DATA): Make hw_list const. - (get_insn_operands,lookup_insn): Add prototypes for. - -Tue Feb 3 17:11:23 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS. - (CGEN_HW_ENTRY): Move `next' entry to end of struct. - (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS. - (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS. - -Mon Feb 2 19:19:15 1998 Ian Lance Taylor <ian@cygnus.com> - - * cgen.h: Correct typo in comment end marker. - -Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> - - * tic30.h: New file. - -Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h: Add prototypes for cgen_save_fixups(), - cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype - of cgen_asm_finish_insn() to return a char *. - -Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h: Formatting changes to improve readability. - -Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (*): Clean up pass over `struct foo' usage. - (CGEN_ATTR): Make unsigned char. - (CGEN_ATTR_TYPE): Update. - (CGEN_ATTR_{ENTRY,TABLE}): New types. - (cgen_base): Move member `attrs' to cgen_insn. - (CGEN_KEYWORD): New member `null_entry'. - (CGEN_{SYNTAX,FORMAT}): New types. - (cgen_insn): Format and syntax separated from each other. - -Tue Dec 16 15:15:52 1997 Michael Meissner <meissner@cygnus.com> - - * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for - 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make - flags_{used,set} long. - (d30v_operand): Make flags field long. - -Mon Dec 1 12:24:44 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k.h: Fix comment describing operand types. - -Sun Nov 23 22:31:27 1997 Michael Meissner <meissner@cygnus.com> - - * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move - everything else after down. - -Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v.h (OPERAND_FLAG): Split into: - (OPERAND_FFLAG, OPERAND_CFLAG) . - -Thu Nov 13 11:04:24 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h (struct mips_opcode): Changed comments to reflect new - field usage. - -Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips.h: Added to comments a quick-ref list of all assigned - operand type characters. - (OP_{MASK,SH}_PERFREG): New macros. - -Wed Oct 22 17:28:33 1997 Richard Henderson <rth@cygnus.com> - - * sparc.h: Add '_' and '/' for v9a asr's. - Patch from David Miller <davem@vger.rutgers.edu> - -Tue Oct 14 13:22:29 1997 Jeffrey A Law (law@cygnus.com) - - * h8300.h: Bit ops with absolute addresses not in the 8 bit - area are not available in the base model (H8/300). - -Thu Sep 25 13:03:41 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Remove documentation of ` operand specifier. - -Wed Sep 24 19:00:34 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Document q and v operand specifiers. - -Mon Sep 15 18:28:37 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Add processors field. - (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. - (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants. - (PROCESSOR_V850EA): New bit constants. - -Mon Sep 15 11:29:43 1997 Ken Raeburn <raeburn@cygnus.com> - - Merge changes from Martin Hunt: - - * d30v.h: Allow up to 64 control registers. Add - SHORT_A5S format. - - * d30v.h (LONG_Db): New form for delayed branches. - - * d30v.h: (LONG_Db): New form for repeati. - - * d30v.h (SHORT_D2B): New form. - - * d30v.h (SHORT_A2): New form. - - * d30v.h (OPERAND_2REG): Add new operand to indicate 2 - registers are used. Needed for VLIW optimization. - -Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h: Move assembler interface section - up so cgen_parse_operand_result is defined for cgen_parse_address. - (cgen_parse_address): Update prototype. - -Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. - -Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h (two_byte_segment_defaults): Correct base register 5 in - modes 1 and 2 to be ss rather than ds. From Gabriel Paubert - <paubert@iram.es>. - - * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert - <paubert@iram.es>. - - * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert - <paubert@iram.es>. - - * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again). - (JUMP_ON_ECX_ZERO): Remove commented out macro. - -Fri Aug 22 10:38:29 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (V850_NOT_R0): New flag. - -Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Remove flags field. - -Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Add flags field. - (struct v850_operand): Extend meaning of 'bits' and 'shift' - fields. - (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags. - (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags. - -Fri Aug 8 16:58:42 1997 Doug Evans <dje@canuck.cygnus.com> - - * arc.h: New file. - -Thu Jul 24 21:16:58 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_opcodes): Declare as const. - -Thu Jul 10 12:53:25 1997 Jeffrey A Law (law@cygnus.com) - - * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn - uses single or double precision floating point resources. - (INSN_NO_ISA, INSN_ISA1): Define. - (cpu specific INSN macros): Tweak into bitmasks outside the range - of INSN_ISA field. - -Mon Jun 16 14:10:00 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h: Fix pand opcode. - -Mon Jun 2 11:35:09 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h: Widen INSN_ISA and move it to a more convenient - bit position. Add INSN_3900. - -Tue May 20 11:25:29 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h (struct mips_opcode): added new field membership. - -Mon May 12 16:26:50 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h (movd): only Reg32 is allowed. - - * i386.h: add fcomp and ud2. From Wayne Scott - <wscott@ichips.intel.com>. - -Mon May 5 17:16:21 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Add MMX instructions. - -Mon May 5 12:45:19 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h: Remove W modifier from conditional move instructions. - -Mon Apr 14 14:56:58 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp - with no arguments to match that generated by the UnixWare - assembler. - -Thu Apr 10 14:35:00 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg. - (cgen_parse_operand_fn): Declare. - (cgen_init_parse_operand): Declare. - (cgen_parse_operand): Renamed from cgen_asm_parse_operand, - new argument `want'. - (enum cgen_parse_operand_result): Renamed from cgen_asm_result. - (enum cgen_parse_operand_type): New enum. - -Sat Apr 5 13:14:05 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases. - -Fri Apr 4 11:46:11 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h: New file. - -Fri Apr 4 14:02:32 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and - fdivrp. - -Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com) - - * v850.h (extract): Make unsigned. - -Mon Mar 24 14:38:15 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Add iclr. - -Thu Mar 20 19:49:10 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Change DW to W for cmpxchg and xadd, since they don't - take a direction bit. - -Sat Mar 15 19:03:29 1997 H.J. Lu <hjl@lucon.org> - - * sparc.h (sparc_opcode_lookup_arch): Use full prototype. - -Fri Mar 14 15:22:01 1997 Ian Lance Taylor <ian@cygnus.com> - - * sparc.h: Include <ansidecl.h>. Update function declarations to - use prototypes, and to use const when appropriate. - -Thu Mar 6 14:18:30 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_RELAX): Define. - -Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Change pre_defined_registers to - d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. - -Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> - - * mips.h: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, - and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table - dynamically. - -Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v.h (FLAG_X): Remove unused flag. - -Tue Feb 18 17:37:20 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v.h: New file. - -Fri Feb 14 13:16:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (PDS_NAME): Macro to access name field of predefined symbols. - (PDS_VALUE): Macro to access value field of predefined symbols. - (tic80_next_predefined_symbol): Add prototype. - -Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (tic80_symbol_to_value): Change prototype to match - change in function, added class parameter. - -Thu Feb 6 17:30:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80 - endmask fields, which are somewhat weird in that 0 and 32 are - treated exactly the same. - -Thu Jan 30 13:46:18 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h: Change all the OPERAND defines to use the form (1 << X) - rather than a constant that is 2**X. Reorder them to put bits for - operands that have symbolic names in the upper bits, so they can - be packed into an int where the lower bits contain the value that - corresponds to that symbolic name. - (predefined_symbo): Add struct. - (tic80_predefined_symbols): Declare array of translations. - (tic80_num_predefined_symbols): Declare size of that array. - (tic80_value_to_symbol): Declare function. - (tic80_symbol_to_value): Declare function. - -Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200.h (MN10200_OPERAND_RELAX): Define. - -Sat Jan 18 15:18:59 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot - be the destination register. - -Thu Jan 16 20:48:55 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (struct tic80_opcode): Change "format" field to "flags". - (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete. - (TIC80_VECTOR): Define a flag bit for the flags. This one means - that the opcode can have two vector instructions in a single - 32 bit word and we have to encode/decode both. - -Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_PCREL): Renamed from - TIC80_OPERAND_RELATIVE for PC relative. - (TIC80_OPERAND_BASEREL): New flag bit for register - base relative. - -Mon Jan 13 15:56:38 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands. - -Mon Jan 6 10:51:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional - ":s" modifier for scaling. - -Sun Jan 5 12:12:19 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m". - (TIC80_OPERAND_M_LI): Ditto - -Sat Jan 4 19:02:44 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ. - (TIC80_OPERAND_CC): New define for condition code operand. - (TIC80_OPERAND_CR): New define for control register operand. - -Fri Jan 3 16:22:23 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (struct tic80_opcode): Name changed. - (struct tic80_opcode): Remove format field. - (struct tic80_operand): Add insertion and extraction functions. - (TIC80_OPERAND_*): Remove old bogus values, start adding new - correct ones. - (FMT_*): Ditto. - -Tue Dec 31 15:05:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust - type IV instruction offsets. - -Fri Dec 27 22:23:10 1996 Fred Fish <fnf@cygnus.com> - - * tic80.h: New file. - -Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200.h (MN10200_OPERAND_NOCHECK): Define. - -Sat Dec 14 10:48:31 1996 Fred Fish <fnf@ninemoons.com> - - * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. - * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. - * v850.h: Fix comment, v850_operand not powerpc_operand. - -Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200.h: Flesh out structures and definitions needed by - the mn10200 assembler & disassembler. - -Tue Nov 26 10:46:56 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips.h: Add mips16 definitions. - -Mon Nov 25 17:56:54 1996 J.T. Conklin <jtc@cygnus.com> - - * m68k.h: Document new <, >, m, n, o and p operand specifiers. - -Wed Nov 20 10:59:41 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_PCREL): Define. - (MN10300_OPERAND_MEMADDR): Define. - -Tue Nov 19 13:30:40 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_REG_LIST): Define. - -Wed Nov 6 13:41:08 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_SPLIT): Define. - -Tue Nov 5 13:26:12 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_EXTENDED): Define. - -Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_REPEATED): Define. - -Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> - - * alpha.h: Don't include "bfd.h"; private relocation types are now - negative to minimize problems with shared libraries. Organize - instruction subsets by AMASK extensions and PALcode - implementation. - (struct alpha_operand): Move flags slot for better packing. - -Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (V850_OPERAND_RELAX): New operand flag. - -Thu Oct 10 14:29:11 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (FMT_*): Move operand format definitions - here. - -Tue Oct 8 14:48:07 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_PAREN): Define. - -Mon Oct 7 16:52:11 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (mn10300_opcode): Add "format" field. - (MN10300_OPERAND_*): Define. - -Thu Oct 3 10:33:46 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00.h: Delete. - * mn10200.h, mn10300.h: New files. - -Wed Oct 2 21:31:26 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00.h: New file. - -Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com) - - * v850.h: Add new flag to indicate this instruction uses a PC - displacement. - -Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (stmac): Add missing instruction. - -Sat Aug 31 16:02:03 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (v850_opcode): Remove "size" field. Add "memop" - field. - -Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (V850_OPERAND_EP): Define. - - * v850.h (v850_opcode): Add size field. - -Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h (v850_operands): Add insert and extract fields, pointers - to functions used to handle unusual operand encoding. - (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, - V850_OPERAND_SIGNED): Defined. - -Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h (v850_operands): Add flags field. - (OPERAND_REG, OPERAND_NUM): Defined. - -Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h: New file. - -Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> - - * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, - OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, - OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, - OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, - OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): - Defined. - -Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept - a 3 bit space id instead of a 2 bit space id. - -Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Add some additional defines to support the - assembler in determining which operations can be done in parallel. - -Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (SN): Define. - (eepmov.b): Renamed from "eepmov" - (nop, bpt, rte, rts, sleep, clrmac): These have no size associated - with them. - -Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h (OPERAND_SHIFT): New operand flag. - -Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Changes for divs, parallel-only instructions, and - signed numbers. - -Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h (pd_reg): Define. Putting the definition here allows - the assembler and disassembler to share the same struct. - -Mon Jul 22 12:15:25 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960.h (i960_opcodes): "halt" takes an argument. From Stephen - Williams <steve@icarus.com>. - -Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: New file. - -Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (band, bclr): Force high bit of immediate nibble to zero. - -Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k.h (mcf5200): New macro. - Document names of coldfire control registers. - -Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (SRC_IN_DST): Define. - - * h8300.h (UNOP3): Mark the register operand in this insn - as a source operand, not a destination operand. - (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references. - (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark - register operand with SRC_IN_DST. - -Fri Jun 21 13:52:17 1996 Richard Henderson <rth@tamu.edu> - - * alpha.h: New file. - -Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com> - - * rs6k.h: Remove obsolete file. - -Wed Jun 19 15:29:38 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp, - fdivp, and fdivrp. Add ffreep. - -Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com> - - * h8300.h: Reorder various #defines for readability. - (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define. - (BITOP): Accept additional (unused) argument. All callers changed. - (EBITOP): Likewise. - (O_LAST): Bump. - (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes. - - * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define. - (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define. - (BITOP, EBITOP): Handle new H8/S addressing modes for - bit insns. - (UNOP3): Handle new shift/rotate insns on the H8/S. - (insns using exr): New instructions. - (tas, mac, ldmac, clrmac, ldm, stm): New instructions. - -Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (add.l): Undo Apr 5th change. The manual I had - was incorrect. - -Mon May 6 23:38:22 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (START): Remove. - (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w - and mov.l insns that can be relaxed. - -Tue Apr 30 18:30:58 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Remove Abs32 from lcall. - -Mon Apr 22 17:09:23 1996 Doug Evans <dje@blues.cygnus.com> - - * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro. - (SLCPOP): New macro. - Mark X,Y opcode letters as in use. - -Thu Apr 11 17:28:18 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc.h (F_FLOAT, F_FBR): Define. - -Fri Apr 5 16:55:34 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV - from all insns. - (ABS8SRC,ABS8DST): Add ABS8MEM. - (add.l): Fix reg+reg variant. - (eepmov.w): Renamed from eepmovw. - (ldc,stc): Fix many cases. - -Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro. - -Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (O): Mark operand letter as in use. - -Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare. - Mark operand letters uU as in use. - -Mon Feb 19 01:59:08 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET. - (sparc_opcode_arch): Delete member `conflicts'. Add `supported'. - (SPARC_OPCODE_SUPPORTED): New macro. - (SPARC_OPCODE_CONFLICT_P): Rewrite. - (F_NOTV9): Delete. - -Fri Feb 16 12:23:34 1996 Jeffrey A Law (law@cygnus.com) - - * sparc.h (sparc_opcode_lookup_arch) Make return type in - declaration consistent with return type in definition. - -Wed Feb 14 18:14:11 1996 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Remove Data32 from pushf and popf. - -Thu Feb 8 14:27:21 1996 James Carlson <carlson@xylogics.com> - - * i386.h (i386_regtab): Add 80486 test registers. - -Mon Feb 5 18:35:46 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960.h (I_HX): Define. - (i960_opcodes): Add HX instruction. - -Mon Jan 29 12:43:39 1996 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw, - and fclex. - -Wed Jan 24 22:36:59 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture. - (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P. - (bfd_* defines): Delete. - (sparc_opcode_archs): Replaces architecture_pname. - (sparc_opcode_lookup_arch): Declare. - (NUMOPCODES): Delete. - -Mon Jan 22 08:24:32 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (enum sparc_architecture): Add v9a. - (ARCHITECTURES_CONFLICT_P): Update. - -Thu Dec 28 13:27:53 1995 John Hassey <hassey@rtp.dg.com> - - * i386.h: Added Pentium Pro instructions. - -Thu Nov 2 22:59:22 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Document new 'W' operand place. - -Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add lci and syncdma instructions. - -Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> - - * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific - instructions. - -Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for - assembler's -mcom and -many switches. - -Wed Oct 11 16:56:33 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Fix cmpxchg8b extension opcode description. - -Thu Oct 5 18:03:36 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b, - and register cr4. - -Tue Sep 19 15:26:43 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Change comment: split type P into types 0, 1 and 2. - -Wed Aug 30 13:50:55 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_{encode,decode}_prefetch): Declare. - -Tue Aug 29 15:34:58 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare. - -Wed Aug 2 18:32:19 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68kmri.h: Remove. - - * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the - declarations. Remove F_ALIAS and flag field of struct - m68k_opcode. Change arch field of struct m68k_opcode to unsigned - int. Make name and args fields of struct m68k_opcode const. - -Wed Aug 2 08:16:46 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (F_NOTV9): Define. - -Tue Jul 11 14:20:42 1995 Jeff Spiegel <jeffs@lsil.com> - - * mips.h (INSN_4010): Define. - -Wed Jun 21 18:49:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h (TBL1): Reverse sense of "round" argument in result. - - Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>: - * m68k.h: Fix argument descriptions of coprocessor - instructions to allow only alterable operands where appropriate. - [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'. - (m68k_opcode_aliases): Add more aliases. - -Fri Apr 14 22:15:34 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h: Added explcitly short-sized conditional branches, and a - bunch of aliases (fmov*, ftest*, tdivul) to support gcc's - svr4-based configurations. - -Mon Mar 13 21:30:01 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Mon Feb 27 08:36:39 1995 Bryan Ford <baford@cs.utah.edu> - * i386.h: added missing Data16/Data32 flags to a few instructions. - -Wed Mar 8 15:19:53 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (OP_MASK_FR, OP_SH_FR): Define. - (OP_MASK_BCC, OP_SH_BCC): Define. - (OP_MASK_PREFX, OP_SH_PREFX): Define. - (OP_MASK_CCC, OP_SH_CCC): Define. - (INSN_READ_FPR_R): Define. - (INSN_RFE): Delete. - -Wed Mar 8 03:13:23 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h (enum m68k_architecture): Deleted. - (struct m68k_opcode_alias): New type. - (m68k_opcodes): Now const. Deleted opcode aliases with exactly - matching constraints, values and flags. As a side effect of this, - the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far - as I know were never used, now may need re-examining. - (numopcodes): Now const. - (m68k_opcode_aliases, numaliases): New variables. - (endop): Deleted. - [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and - m68k_opcode_aliases; update declaration of m68k_opcodes. - -Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa.h (delay_type): Delete unused enumeration. - (pa_opcode): Replace unused delayed field with an architecture - field. - (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1. - -Fri Mar 3 16:10:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (INSN_ISA4): Define. - -Fri Feb 24 19:13:37 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (M_DLA_AB, M_DLI): Define. - -Thu Feb 23 17:33:09 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa.h (fstwx): Fix single-bit error. - -Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. - -Mon Feb 6 10:35:23 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386.h: added cpuid instruction , and dr[0-7] aliases for the - debug registers. From Charles Hannum (mycroft@netbsd.org). - -Mon Feb 6 03:31:54 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit - i386 support: - * i386.h (MOV_AX_DISP32): New macro. - (i386_optab): Added Data16 and Data32 as needed. Added "w" forms - of several call/return instructions. - (ADDR_PREFIX_OPCODE): New macro. - -Mon Jan 23 16:45:43 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Sat Jan 21 17:50:38 1995 Pat Rankin (rankin@eql.caltech.edu) - - * vax.h (struct vot_wot, field `args'): Make it pointer to const - char. - (struct vot, field `name'): ditto. - -Thu Jan 19 14:47:53 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * vax.h: Supply and properly group all values in end sentinel. - -Tue Jan 17 10:55:30 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips.h (INSN_ISA, INSN_4650): Define. - -Wed Oct 19 13:34:17 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On - systems with a separate instruction and data cache, such as the - 29040, these instructions take an optional argument. - -Wed Sep 14 17:44:20 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with - INSN_TRAP. - -Tue Sep 6 11:39:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips.h (INSN_STORE_MEMORY): Define. - -Thu Jul 28 19:28:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc.h: Document new operand type 'x'. - -Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i960.h (I_CX2): New instruction category. It includes - instructions available on Cx and Jx processors. - (I_JX): New instruction category, for JX-only instructions. - (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added - Jx-only instructions, in I_JX category. - -Wed Jul 13 18:43:47 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * ns32k.h (endop): Made pointer const too. - -Sun Jul 10 11:01:09 1994 Ian Dall (dall@hfrd.dsto.gov.au) - - * ns32k.h: Drop Q operand type as there is no correct use - for it. Add I and Z operand types which allow better checking. - -Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * h8300.h (xor.l) :fix bit pattern. - (L_2): New size of operand. - (trapa): Use it. - -Fri Jun 10 16:38:11 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68k.h: Move "trap" before "tpcc" to change disassembly. - -Fri Jun 3 15:57:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc.h: Include v9 definitions. - -Thu Jun 2 12:23:17 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * m68k.h (m68060): Defined. - (m68040up, mfloat, mmmu): Include it. - (struct m68k_opcode): Widen `arch' field. - (m68k_opcodes): Updated for M68060. Removed comments that were - instructions commented out by "JF" years ago. - -Thu Apr 28 18:31:14 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and - add a one-bit `flags' field. - (F_ALIAS): New macro. - -Wed Apr 27 11:29:52 1994 Steve Chamberlain (sac@cygnus.com) - - * h8300.h (dec, inc): Get encoding right. - -Mon Apr 4 13:12:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (struct powerpc_operand): Removed signedp field; just use - a flag instead. - (PPC_OPERAND_SIGNED): Define. - (PPC_OPERAND_SIGNOPT): Define. - -Thu Mar 31 19:34:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size - prefix is 0x66, not 0x67. Patch from H.J. Lu (hlu@nynexst.com). - -Thu Mar 3 15:51:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h: Reverse last change. It'll be handled in gas instead. - -Thu Feb 24 15:29:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (sar): Disabled the two-operand Imm1 form, since it was - slower on the 486 and used the implicit shift count despite the - explicit operand. The one-operand form is still available to get - the shorter form with the implicit shift count. - -Thu Feb 17 12:27:52 1994 Torbjorn Granlund (tege@mexican.cygnus.com) - - * hppa.h: Fix typo in fstws arg string. - -Wed Feb 9 21:23:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (struct powerpc_opcode): Make operands field unsigned. - -Mon Feb 7 19:14:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (PPC_OPCODE_601): Define. - -Fri Feb 4 23:43:50 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h (addb): Use '@' for addb and addib pseudo ops. - (so we can determine valid completers for both addb and addb[tf].) - - * hppa.h (xmpyu): No floating point format specifier for the - xmpyu instruction. - -Fri Feb 4 23:36:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (PPC_OPERAND_NEXT): Define. - (PPC_OPERAND_NEGATIVE): Change value to make room for above. - (struct powerpc_macro): Define. - (powerpc_macros, powerpc_num_macros): Declare. - -Fri Jan 21 19:13:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h: New file. Header file for PowerPC opcode table. - -Mon Jan 17 00:14:23 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: More minor template fixes for sfu and copr (to allow - for easier disassembly). - - * hppa.h: Fix templates for all the sfu and copr instructions. - -Wed Dec 15 15:12:42 1993 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (push): Permit Imm16 operand too. - -Sat Dec 11 16:14:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8300.h (andc): Exists in base arch. - -Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp> - * hppa.h: #undef NONE to avoid conflict with hiux include files. - -Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: Add FP quadword store instructions. - -Wed Nov 17 17:13:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: (M_J_A): Added. - (M_LA): Removed. - -Mon Nov 8 12:12:47 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon - <mellon@pepper.ncd.com>. - -Sun Nov 7 00:30:11 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: Immediate field in probei instructions is unsigned, - not low-sign extended. - -Wed Nov 3 10:30:00 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00. - -Tue Nov 2 12:41:30 1993 Ken Raeburn (raeburn@rover.cygnus.com) - - * i386.h: Add "fxch" without operand. - -Mon Nov 1 18:13:03 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added. - -Sat Oct 2 22:26:11 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa.h: Add gfw and gfr to the opcode table. - -Wed Sep 29 16:23:00 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k.h: extended to handle m88110. - -Tue Sep 28 19:19:08 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa.h (be, ble): Use operand type 'z' to denote absolute branch - addresses. - -Tue Sep 14 14:04:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960.h (i960_opcodes): Properly bracket initializers. - -Mon Sep 13 12:50:52 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k.h (BOFLAG): rewrite to avoid nested comment. - -Mon Sep 13 15:46:06 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68k.h (two): Protect second argument with parentheses. - -Fri Sep 10 16:29:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * i386.h (i386_optab): Added new instruction "rsm" (for i386sl). - Deleted old in/out instructions in "#if 0" section. - -Thu Sep 9 17:42:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i386.h (i386_optab): Properly bracket initializers. - -Wed Aug 25 13:50:56 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From - Jeff Law, law@cs.utah.edu). - -Mon Aug 23 16:55:03 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * i386.h (lcall): Accept Imm32 operand also. - -Mon Aug 23 12:43:11 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (M_ABSU): Removed (absolute value of unsigned number??). - (M_DABS): Added. - -Thu Aug 19 15:08:37 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (INSN_*): Changed values. Removed unused definitions. - Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split - INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and - INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into - INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY. - (M_*): Added new values for r6000 and r4000 macros. - (ANY_DELAY): Removed. - -Wed Aug 18 15:37:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: Added M_LI_S and M_LI_SS. - -Tue Aug 17 07:08:08 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300.h: Get some rare mov.bs correct. - -Thu Aug 5 09:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc.h: Don't define const ourself; rely on ansidecl.h having - been included. - -Fri Jul 30 18:41:11 1993 John Gilmore (gnu@cygnus.com) - - * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark - jump instructions, for use in disassemblers. - -Thu Jul 22 07:25:27 1993 Ian Lance Taylor (ian@cygnus.com) - - * m88k.h: Make bitfields just unsigned, not unsigned long or - unsigned short. - -Wed Jul 21 11:55:31 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa.h: New argument type 'y'. Use in various float instructions. - -Mon Jul 19 17:17:03 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa.h (break): First immediate field is unsigned. - - * hppa.h: Add rfir instruction. - -Sun Jul 18 16:28:08 1993 Jim Kingdon (kingdon@rtl.cygnus.com) - - * mips.h: Split the actual table out into ../../opcodes/mips-opc.c. - -Fri Jul 16 09:59:29 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips.h: Reworked the hazard information somewhat, and fixed some - bugs in the instruction hazard descriptions. - -Thu Jul 15 12:42:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k.h: Corrected a couple of opcodes. - -Tue Jul 6 15:17:35 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips.h: Replaced with version from Ralph Campbell and OSF. The - new version includes instruction hazard information, but is - otherwise reasonably similar. - -Thu Jul 1 20:36:17 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l). - -Fri Jun 11 18:38:44 1993 Ken Raeburn (raeburn@cygnus.com) - - Patches from Jeff Law, law@cs.utah.edu: - * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage. - Make the tables be the same for the following instructions: - "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", - "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o", - "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", - "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", - "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", - "fcmp", and "ftest". - - * hppa.h: Make new and old tables the same for "break", "mtctl", - "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub". - Fix typo in last patch. Collapse several #ifdefs into a - single #ifdef. - - * hppa.h: Delete remaining OLD_TABLE code. Bring some - of the comments up-to-date. - - * hppa.h: Update "free list" of letters and update - comments describing each letter's function. - -Thu Jul 8 09:05:26 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300.h: Lots of little fixes for the h8/300h. - -Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - Support for H8/300-H - * h8300.h: Lots of new opcodes. - -Fri Jun 4 15:41:37 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300.h: checkpoint, includes H8/300-H opcodes. - -Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com) - - * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa.h: Rework single precision FP - instructions so that they correctly disassemble code - PA1.1 code. - -Thu May 27 19:21:22 1993 Bruce Bauman (boot@osf.org) - - * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from - mov to allow instructions like mov ss,xyz(ecx) to assemble. - -Tue May 25 00:39:40 1993 Ken Raeburn (raeburn@cygnus.com) - - * hppa.h: Use new version from Utah if OLD_TABLE isn't defined; - gdb will define it for now. - -Mon May 24 15:20:06 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * sparc.h: Don't end enumerator list with comma. - -Fri May 14 15:15:50 1993 Ian Lance Taylor (ian@cygnus.com) - - * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): - * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define. - ("bc2t"): Correct typo. - ("[ls]wc[023]"): Use T rather than t. - ("c[0123]"): Define general coprocessor instructions. - -Mon May 10 06:02:25 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) - - * m68k.h: Move split point for gcc compilation more towards - middle. - -Fri Apr 9 13:26:16 1993 Jim Kingdon (kingdon@cygnus.com) - - * rs6k.h: Clean up instructions for primary opcode 19 (many were - simply wrong, ics, rfi, & rfsvc were missing). - Add "a" to opr_ext for "bb". Doc fix. - -Thu Mar 18 13:45:31 1993 Per Bothner (bothner@rtl.cygnus.com) - - * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com). - * mips.h: Add casts, to suppress warnings about shifting too much. - * m68k.h: Document the placement code '9'. - -Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com) - - * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which - allows callers to break up the large initialized struct full of - opcodes into two half-sized ones. This permits GCC to compile - this module, since it takes exponential space for initializers. - (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs. - -Thu Feb 4 02:06:56 1993 John Gilmore (gnu@cygnus.com) - - * a29k.h: Remove RCS crud, update GPL to v2, update copyrights. - * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all - initialized structs in it. - -Thu Jan 28 21:32:22 1993 John Gilmore (gnu@cygnus.com) - - Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>: - * m88k.h (PMEM): Avoid previous definition from <sys/param.h>. - (AND): Change to AND_ to avoid ansidecl.h `AND' conflict. - -Sat Jan 23 18:10:49 PST 1993 Ralph Campbell (ralphc@pyramid.com) - - * mips.h: document "i" and "j" operands correctly. - -Thu Jan 7 15:58:13 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: Removed endianness dependency. - -Sun Jan 3 14:13:35 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8300.h: include info on number of cycles per instruction. - -Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com) - - * hppa.h: Move handy aliases to the front. Fix masks for extract - and deposit instructions. - -Sat Dec 12 16:09:48 1992 Ian Lance Taylor (ian@cygnus.com) - - * i386.h: accept shld and shrd both with and without the shift - count argument, which is always %cl. - -Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com) - - * i386.h (i386_optab_end, i386_regtab_end): Now const. - (one_byte_segment_defaults, two_byte_segment_defaults, - i386_prefixtab_end): Ditto. - -Mon Nov 23 10:47:25 1992 Ken Raeburn (raeburn@cygnus.com) - - * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand) - for operand 2; from John Carr, jfc@dsg.dec.com. - -Wed Nov 4 07:36:49 1992 Ken Raeburn (raeburn@cygnus.com) - - * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions - always use 16-bit offsets. Makes calculated-size jump tables - feasible. - -Fri Oct 16 22:52:43 1992 Ken Raeburn (raeburn@cygnus.com) - - * i386.h: Fix one-operand forms of in* and out* patterns. - -Tue Sep 22 14:08:14 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * m68k.h: Added CPU32 support. - -Tue Sep 22 00:38:41 1992 John Gilmore (gnu@cygnus.com) - - * mips.h (break): Disassemble the argument. Patch from - jonathan@cs.stanford.edu (Jonathan Stone). - -Wed Sep 9 11:25:28 1992 Ian Lance Taylor (ian@cygnus.com) - - * m68k.h: merged Motorola and MIT syntax. - -Thu Sep 3 09:33:22 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68k.h (pmove): make the tests less strict, the 68k book is - wrong. - -Tue Aug 25 23:25:19 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * m68k.h (m68ec030): Defined as alias for 68030. - (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t" - for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use - them. Tightened description of "fmovex" to distinguish it from - some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned - up descriptions that claimed versions were available for chips not - supporting them. Added "pmovefd". - -Mon Aug 24 12:04:51 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68k.h: fix where the . goes in divull - -Wed Aug 19 11:22:24 1992 Ian Lance Taylor (ian@cygnus.com) - - * m68k.h: the cas2 instruction is supposed to be written with - indirection on the last two operands, which can be either data or - address registers. Added a new operand type 'r' which accepts - either register type. Added new cases for cas2l and cas2w which - use them. Corrected masks for cas2 which failed to recognize use - of address register. - -Fri Aug 14 14:20:38 1992 Per Bothner (bothner@cygnus.com) - - * m68k.h: Merged in patches (mostly m68040-specific) from - Colin Smith <colin@wrs.com>. - - * m68k.h: Merged m68kmri.h and m68k.h (using the former as a - base). Also cleaned up duplicates, re-ordered instructions for - the sake of dis-assembling (so aliases come after standard names). - * m68kmri.h: Now just defines some macros, and #includes m68k.h. - -Wed Aug 12 16:38:15 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in - all missing .s - -Mon Aug 10 23:22:33 1992 Ken Raeburn (raeburn@cygnus.com) - - * sparc.h: Moved tables to BFD library. - - * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc. - -Sun Jun 28 13:29:03 1992 Fred Fish (fnf@cygnus.com) - - * h8300.h: Finish filling in all the holes in the opcode table, - so that the Lucid C compiler can digest this as well... - -Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com) - - * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases. - Fix opcodes on various sizes of fild/fist instructions - (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix). - Use tabs to indent for comments. Fixes suggested by Minh Tran-Le. - -Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com) - - * h8300.h: Fill in all the holes in the opcode table so that the - losing HPUX C compiler can digest this... - -Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com) - - * mips.h: Fix decoding of coprocessor instructions, somewhat. - (Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.) - -Thu May 28 11:17:44 1992 Jim Wilson (wilson@sphagnum.cygnus.com) - - * sparc.h: Add new architecture variant sparclite; add its scan - and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro. - -Tue May 5 14:23:27 1992 Per Bothner (bothner@rtl.cygnus.com) - - * mips.h: Add some more opcode synonyms (from Frank Yellin, - fy@lucid.com). - -Thu Apr 16 18:25:26 1992 Per Bothner (bothner@cygnus.com) - - * rs6k.h: New version from IBM (Metin). - -Thu Apr 9 00:31:19 1992 Per Bothner (bothner@rtl.cygnus.com) - - * rs6k.h: Fix incorrect extended opcode for instructions `fm' - and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).) - -Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com) - - * rs6k.h: Move from ../../gdb/rs6k-opcode.h. - -Fri Apr 3 11:30:20 1992 Fred Fish (fnf@cygnus.com) - - * m68k.h (one, two): Cast macro args to unsigned to suppress - complaints from compiler and lint about integer overflow during - shift. - -Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com) - - * sparc.h (OP): Avoid signed overflow when shifting to high order bit. - -Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com) - - * mips.h: Make bitfield layout depend on the HOST compiler, - not on the TARGET system. - -Fri Feb 21 01:29:51 1992 K. Richard Pixley (rich@cygnus.com) - - * i386.h: added inb, inw, outb, outw opcodes, added att syntax for - scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le - <TRANLE@INTELLICORP.COM>. - -Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com) - - * h8300.h: turned op_type enum into #define list - -Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com) - - * sparc.h: Remove "cypress" architecture. Remove "fitox" and - similar instructions -- they've been renamed to "fitoq", etc. - REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong - number of arguments. - * h8300.h: Remove extra ; which produces compiler warning. - -Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com) - - * sparc.h: fix opcode for tsubcctv. - -Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com) - - * sparc.h: fba and cba are now aliases for fb and cb respectively. - -Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com) - - * sparc.h (nop): Made the 'lose' field be even tighter, - so only a standard 'nop' is disassembled as a nop. - -Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com) - - * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is - disassembled as a nop. - -Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) - - * m68k.h, sparc.h: ANSIfy enums. - -Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) - - * sparc.h: fix a typo. - -Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com) - - * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, - m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h, - vax.h: Renamed from ../<foo>-opcode.h. - - -Local Variables: -version-control: never -End: diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h deleted file mode 100644 index 22c85a1f5..000000000 --- a/include/opcode/alpha.h +++ /dev/null @@ -1,237 +0,0 @@ -/* alpha.h -- Header file for Alpha opcode table - Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@tamu.edu>, - patterned after the PPC opcode table written by Ian Lance Taylor. - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef OPCODE_ALPHA_H -#define OPCODE_ALPHA_H - -/* The opcode table is an array of struct alpha_opcode. */ - -struct alpha_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned mask; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[4]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct alpha_opcode alpha_opcodes[]; -extern const unsigned alpha_num_opcodes; - -/* Values defined for the flags field of a struct alpha_opcode. */ - -/* CPU Availability */ -#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ -#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ -#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ -#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ -#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ -#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ -#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ - -#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) - -/* A macro to extract the major opcode from an instruction. */ -#define AXP_OP(i) (((i) >> 26) & 0x3F) - -/* The total number of major opcodes. */ -#define AXP_NOPS 0x40 - - -/* The operands table is an array of struct alpha_operand. */ - -struct alpha_operand -{ - /* The number of bits in the operand. */ - unsigned int bits : 5; - - /* How far the operand is left shifted in the instruction. */ - unsigned int shift : 5; - - /* The default relocation type for this operand. */ - signed int default_reloc : 16; - - /* One bit syntax flags. */ - unsigned int flags : 16; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned (*insert) (unsigned instruction, int op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & AXP_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - int (*extract) (unsigned instruction, int *invalid); -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the alpha_opcodes table. */ - -extern const struct alpha_operand alpha_operands[]; -extern const unsigned alpha_num_operands; - -/* Values defined for the flags field of a struct alpha_operand. */ - -/* Mask for selecting the type for typecheck purposes */ -#define AXP_OPERAND_TYPECHECK_MASK \ - (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ - AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ - AXP_OPERAND_UNSIGNED) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics, for which two operands fields - are identical. The assembler should call the insert function with - any op value. The disassembler should call the extract function, - ignore the return value, and check the value placed in the invalid - argument. */ -#define AXP_OPERAND_FAKE 01 - -/* The operand should be wrapped in parentheses rather than separated - from the previous by a comma. This is used for the load and store - instructions which want their operands to look like "Ra,disp(Rb)". */ -#define AXP_OPERAND_PARENS 02 - -/* Used in combination with PARENS, this supresses the supression of - the comma. This is used for "jmp Ra,(Rb),hint". */ -#define AXP_OPERAND_COMMA 04 - -/* This operand names an integer register. */ -#define AXP_OPERAND_IR 010 - -/* This operand names a floating point register. */ -#define AXP_OPERAND_FPR 020 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define AXP_OPERAND_RELATIVE 040 - -/* This operand takes signed values. */ -#define AXP_OPERAND_SIGNED 0100 - -/* This operand takes unsigned values. This exists primarily so that - a flags value of 0 can be treated as end-of-arguments. */ -#define AXP_OPERAND_UNSIGNED 0200 - -/* Supress overflow detection on this field. This is used for hints. */ -#define AXP_OPERAND_NOOVERFLOW 0400 - -/* Mask for optional argument default value. */ -#define AXP_OPERAND_OPTIONAL_MASK 07000 - -/* This operand defaults to zero. This is used for jump hints. */ -#define AXP_OPERAND_DEFAULT_ZERO 01000 - -/* This operand should default to the first (real) operand and is used - in conjunction with AXP_OPERAND_OPTIONAL. This allows - "and $0,3,$0" to be written as "and $0,3", etc. I don't like - it, but it's what DEC does. */ -#define AXP_OPERAND_DEFAULT_FIRST 02000 - -/* Similarly, this operand should default to the second (real) operand. - This allows "negl $0" instead of "negl $0,$0". */ -#define AXP_OPERAND_DEFAULT_SECOND 04000 - - -/* Register common names */ - -#define AXP_REG_V0 0 -#define AXP_REG_T0 1 -#define AXP_REG_T1 2 -#define AXP_REG_T2 3 -#define AXP_REG_T3 4 -#define AXP_REG_T4 5 -#define AXP_REG_T5 6 -#define AXP_REG_T6 7 -#define AXP_REG_T7 8 -#define AXP_REG_S0 9 -#define AXP_REG_S1 10 -#define AXP_REG_S2 11 -#define AXP_REG_S3 12 -#define AXP_REG_S4 13 -#define AXP_REG_S5 14 -#define AXP_REG_FP 15 -#define AXP_REG_A0 16 -#define AXP_REG_A1 17 -#define AXP_REG_A2 18 -#define AXP_REG_A3 19 -#define AXP_REG_A4 20 -#define AXP_REG_A5 21 -#define AXP_REG_T8 22 -#define AXP_REG_T9 23 -#define AXP_REG_T10 24 -#define AXP_REG_T11 25 -#define AXP_REG_RA 26 -#define AXP_REG_PV 27 -#define AXP_REG_T12 27 -#define AXP_REG_AT 28 -#define AXP_REG_GP 29 -#define AXP_REG_SP 30 -#define AXP_REG_ZERO 31 - -#endif /* OPCODE_ALPHA_H */ diff --git a/include/opcode/arc.h b/include/opcode/arc.h deleted file mode 100644 index 8ddcf5433..000000000 --- a/include/opcode/arc.h +++ /dev/null @@ -1,323 +0,0 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 2001, 2002, 2003 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* List of the various cpu types. - The tables currently use bit masks to say whether the instruction or - whatever is supported by a particular cpu. This lets us have one entry - apply to several cpus. - - The `base' cpu must be 0. The cpu type is treated independently of - endianness. The complete `mach' number includes endianness. - These values are internal to opcodes/bfd/binutils/gas. */ -#define ARC_MACH_5 0 -#define ARC_MACH_6 1 -#define ARC_MACH_7 2 -#define ARC_MACH_8 4 - -/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ -#define ARC_MACH_BIG 16 - -/* Mask of number of bits necessary to record cpu type. */ -#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) - -/* Mask of number of bits necessary to record cpu type + endianness. */ -#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) - -/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ - -typedef unsigned int arc_insn; - -struct arc_opcode { - char *syntax; /* syntax of insn */ - unsigned long mask, value; /* recognize insn if (op&mask) == value */ - int flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) - -/* Return MACH number, given flag bits. */ -#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* First opcode flag bit available after machine mask. */ -#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) - -/* This insn is a conditional branch. */ -#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) -#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) -#define SYNTAX_LENGTH (SYNTAX_3OP ) -#define SYNTAX_2OP (SYNTAX_3OP << 1) -#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) -#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) -#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* These values are used to optimize assembly and disassembly. Each insn - is on a list of related insns (same first letter for assembly, same - insn code for disassembly). */ - - struct arc_opcode *next_asm; /* Next instr to try during assembly. */ - struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ - -/* Macros to create the hash values for the lists. */ -#define ARC_HASH_OPCODE(string) \ - ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) -#define ARC_HASH_ICODE(insn) \ - ((unsigned int) (insn) >> 27) - - /* Macros to access `next_asm', `next_dis' so users needn't care about the - underlying mechanism. */ -#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) -#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) -}; - -/* this is an "insert at front" linked list per Metaware spec - that new definitions override older ones. */ -extern struct arc_opcode *arc_ext_opcodes; - -struct arc_operand_value { - char *name; /* eg: "eq" */ - short value; /* eg: 1 */ - unsigned char type; /* index into `arc_operands' */ - unsigned char flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* Return MACH number, given flag bits. */ -#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) -}; - -struct arc_ext_operand_value { - struct arc_ext_operand_value *next; - struct arc_operand_value operand; -}; - -extern struct arc_ext_operand_value *arc_ext_operands; - -struct arc_operand { -/* One of the insn format chars. */ - unsigned char fmt; - -/* The number of bits in the operand (may be unused for a modifier). */ - unsigned char bits; - -/* How far the operand is left shifted in the instruction, or - the modifier's flag bit (may be unused for a modifier. */ - unsigned char shift; - -/* Various flag bits. */ - int flags; - -/* Values for `flags'. */ - -/* This operand is a suffix to the opcode. */ -#define ARC_OPERAND_SUFFIX 1 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_RELATIVE_BRANCH 2 - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ABSOLUTE_BRANCH 4 - -/* This operand is an address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ADDRESS 8 - -/* This operand is a long immediate value. */ -#define ARC_OPERAND_LIMM 0x10 - -/* This operand takes signed values. */ -#define ARC_OPERAND_SIGNED 0x20 - -/* This operand takes signed values, but also accepts a full positive - range of values. That is, if bits is 16, it takes any value from - -0x8000 to 0xffff. */ -#define ARC_OPERAND_SIGNOPT 0x40 - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define ARC_OPERAND_NEGATIVE 0x80 - -/* This operand doesn't really exist. The program uses these operands - in special ways. */ -#define ARC_OPERAND_FAKE 0x100 - -/* separate flags operand for j and jl instructions */ -#define ARC_OPERAND_JUMPFLAGS 0x200 - -/* allow warnings and errors to be issued after call to insert_xxxxxx */ -#define ARC_OPERAND_WARN 0x400 -#define ARC_OPERAND_ERROR 0x800 - -/* this is a load operand */ -#define ARC_OPERAND_LOAD 0x8000 - -/* this is a store operand */ -#define ARC_OPERAND_STORE 0x10000 - -/* Modifier values. */ -/* A dot is required before a suffix. Eg: .le */ -#define ARC_MOD_DOT 0x1000 - -/* A normal register is allowed (not used, but here for completeness). */ -#define ARC_MOD_REG 0x2000 - -/* An auxiliary register name is expected. */ -#define ARC_MOD_AUXREG 0x4000 - -/* Sum of all ARC_MOD_XXX bits. */ -#define ARC_MOD_BITS 0x7000 - -/* Non-zero if the operand type is really a modifier. */ -#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) - -/* enforce read/write only register restrictions */ -#define ARC_REGISTER_READONLY 0x01 -#define ARC_REGISTER_WRITEONLY 0x02 -#define ARC_REGISTER_NOSHORT_CUT 0x04 - -/* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (p & ((1 << o->bits) - 1)) << o->shift; - (I is the instruction which we are filling in, O is a pointer to - this structure, and OP is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged. - - REG is non-NULL when inserting a register value. */ - - arc_insn (*insert) - (arc_insn insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value *reg, long value, const char **errmsg); - -/* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & ARC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (I is the instruction, O is a pointer to this structure, and OP - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. - - INSN is a pointer to an array of two `arc_insn's. The first element is - the insn, the second is the limm if present. - - Operands that have a printable form like registers and suffixes have - their struct arc_operand_value pointer stored in OPVAL. */ - - long (*extract) - (arc_insn *insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value **opval, int *invalid); -}; - -/* Bits that say what version of cpu we have. These should be passed to - arc_init_opcode_tables. At present, all there is is the cpu type. */ - -/* CPU number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* MACH number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* Special register values: */ -#define ARC_REG_SHIMM_UPDATE 61 -#define ARC_REG_SHIMM 63 -#define ARC_REG_LIMM 62 - -/* Non-zero if REG is a constant marker. */ -#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) - -/* Positions and masks of various fields: */ -#define ARC_SHIFT_REGA 21 -#define ARC_SHIFT_REGB 15 -#define ARC_SHIFT_REGC 9 -#define ARC_MASK_REG 63 - -/* Delay slot types. */ -#define ARC_DELAY_NONE 0 /* no delay slot */ -#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ -#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ - -/* Non-zero if X will fit in a signed 9 bit field. */ -#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) - -extern const struct arc_operand arc_operands[]; -extern const int arc_operand_count; -extern struct arc_opcode arc_opcodes[]; -extern const int arc_opcodes_count; -extern const struct arc_operand_value arc_suffixes[]; -extern const int arc_suffixes_count; -extern const struct arc_operand_value arc_reg_names[]; -extern const int arc_reg_names_count; -extern unsigned char arc_operand_map[]; - -/* Utility fns in arc-opc.c. */ -int arc_get_opcode_mach (int, int); - -/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ -void arc_opcode_init_tables (int); -void arc_opcode_init_insert (void); -void arc_opcode_init_extract (void); -const struct arc_opcode *arc_opcode_lookup_asm (const char *); -const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); -int arc_opcode_limm_p (long *); -const struct arc_operand_value *arc_opcode_lookup_suffix - (const struct arc_operand *type, int value); -int arc_opcode_supported (const struct arc_opcode *); -int arc_opval_supported (const struct arc_operand_value *); -int arc_limm_fixup_adjust (arc_insn); -int arc_insn_is_j (arc_insn); -int arc_insn_not_jl (arc_insn); -int arc_operand_type (int); -struct arc_operand_value *get_ext_suffix (char *); -int arc_get_noshortcut_flag (void); diff --git a/include/opcode/arm.h b/include/opcode/arm.h deleted file mode 100644 index d98f038c9..000000000 --- a/include/opcode/arm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* ARM assembler/disassembler support. - Copyright 2004 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - GDB and GAS are free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 1, or (at - your option) any later version. - - GDB and GAS are distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or GAS; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* The following bitmasks control CPU extensions: */ -#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ -#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ -#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ -#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ -#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ -#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ -#define ARM_EXT_V4T 0x00000040 /* Thumb. */ -#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ -#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ -#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ -#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ -#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ -#define ARM_EXT_V6 0x00001000 /* ARM V6. */ -#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ -#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ -#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ - -/* Co-processor space extensions. */ -#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */ -#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */ -#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */ - -/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) - defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, - ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add - three more to cover cores prior to ARM6. Finally, there are cores which - implement further extensions in the co-processor space. */ -#define ARM_ARCH_V1 ARM_EXT_V1 -#define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2) -#define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S) -#define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3) -#define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M) -#define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4) -#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4) -#define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T) -#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T) -#define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5) -#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5) -#define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP) -#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E) -#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J) -#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6) -#define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K) -#define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z) -#define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) -#define ARM_ARCH_V6T2 (ARM_ARCH_V6 | ARM_EXT_V6T2) -#define ARM_ARCH_V6KT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K) -#define ARM_ARCH_V6ZT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6Z) -#define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) - -/* Processors with specific extensions in the co-processor space. */ -#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE) -#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT) - -#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */ -#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */ -#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */ -#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */ -#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */ -#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */ -#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */ -#define FPU_NONE 0 - -#define FPU_ARCH_FPE FPU_FPA_EXT_V1 -#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2) - -#define FPU_ARCH_VFP FPU_VFP_EXT_NONE -#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE) -#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1) -#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2) - -#define FPU_ARCH_MAVERICK FPU_MAVERICK - -/* Some useful combinations: */ -#define ARM_ANY 0x0000ffff /* Any basic core. */ -#define ARM_ALL 0x00ffffff /* Any core + co-processor */ -#define CPROC_ANY 0x00ff0000 /* Any co-processor */ -#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */ diff --git a/include/opcode/avr.h b/include/opcode/avr.h deleted file mode 100644 index b7a80b096..000000000 --- a/include/opcode/avr.h +++ /dev/null @@ -1,265 +0,0 @@ -/* Opcode table for the Atmel AVR micro controllers. - - Copyright 2000, 2001, 2004 Free Software Foundation, Inc. - Contributed by Denis Chertykov <denisc@overta.ru> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#define AVR_ISA_1200 0x0001 /* in the beginning there was ... */ -#define AVR_ISA_LPM 0x0002 /* device has LPM */ -#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ -#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ -#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL - supported, no 8K wrap on RJMP and RCALL) */ -#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ -#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ -#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ -#define AVR_ISA_SPM 0x0200 /* device can program itself */ -#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ -#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ -#define AVR_ISA_MOVW 0x1000 /* device has MOVW */ - -#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) -#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) -#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \ - AVR_ISA_SPM | AVR_ISA_BRK) -#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \ - AVR_ISA_LPMX | AVR_ISA_SPM) -#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) -#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) -#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \ - AVR_ISA_LPMX | AVR_ISA_SPM) -#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX) -#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) -#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) - -#define AVR_ISA_ALL 0xFFFF - -#define REGISTER_P(x) ((x) == 'r' \ - || (x) == 'd' \ - || (x) == 'w' \ - || (x) == 'a' \ - || (x) == 'v') - -/* Undefined combination of operands - does the register - operand overlap with pre-decremented or post-incremented - pointer register (like ld r31,Z+)? */ -#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \ - ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \ - ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \ - ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2) - -/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */ -#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \ - ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00) - -/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as - `ld r,b' or `st b,r' respectively - next opcode entry)? */ -#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) - -/* constraint letters - r - any register - d - `ldi' register (r16-r31) - v - `movw' even register (r0, r2, ..., r28, r30) - a - `fmul' register (r16-r23) - w - `adiw' register (r24,r26,r28,r30) - e - pointer registers (X,Y,Z) - b - base pointer register and displacement ([YZ]+disp) - z - Z pointer register (for [e]lpm Rd,Z[+]) - M - immediate value from 0 to 255 - n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible - s - immediate value from 0 to 7 - P - Port address value from 0 to 63. (in, out) - p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) - K - immediate value from 0 to 63 (used in `adiw', `sbiw') - i - immediate value - l - signed pc relative offset from -64 to 63 - L - signed pc relative offset from -2048 to 2047 - h - absolute code address (call, jmp) - S - immediate value from 0 to 7 (S = s << 4) - ? - use this opcode entry if no parameters, else use next opcode entry - - Order is important - some binary opcodes have more than one name, - the disassembler will only see the first match. - - Remaining undefined opcodes (1699 total - some of them might work - as normal instructions if not all of the bits are decoded): - - 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) - "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] - "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 - "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7] - "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 - "1001010x001x1001" (4) 0x9[45][23]9 - "1001010x01xx1001" (8) 0x9[45][4-7]9 - "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9 - "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b - "10010101001x1000" (2) 0x95[23]8 - "1001010101xx1000" (4) 0x95[4-7]8 - "1001010110111000" (1) 0x95b8 - "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) - "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] - */ - -AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488) -AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8) -AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8) -AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8) -AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8) -AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8) -AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8) -AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498) - -AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408) -AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458) -AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478) -AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428) -AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448) -AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) -AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) -AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) - - /* Same as {cl,se}[chinstvz] above. */ -AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) -AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) - -AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) -AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) - -AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) -AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) -AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8) -AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006) - -AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) -AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) -AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) -AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) -AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) -AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) -AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) - -AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) -AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) -AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) -AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400) -AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400) -AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000) -AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) -AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00) -AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00) -AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) -AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) -AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) - - /* Shorthand for {eor,add,adc,and} r,r above. */ -AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) -AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) -AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) -AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) - -AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) - /*XXX special case*/ -AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) - -AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000) -AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f) - -AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) -AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) - -AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000) -AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000) -AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000) - -AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00) -AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00) -AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800) -AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00) - -AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000) -AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800) - -AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600) -AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700) - -AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800) -AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00) -AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900) -AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00) - -AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) -AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) -AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001) -AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404) -AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405) -AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005) -AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407) -AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007) -AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) -AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004) -AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002) -AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401) -AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402) -AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) -AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406) -AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) -AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) -AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) - - /* Same as br?? above. */ -AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) -AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) - -AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000) -AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000) - -AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e) -AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c) - -AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405) -AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400) -AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) -AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) -AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) -AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) -AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) -AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) -AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) -AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) - - /* Known to be decoded as `nop' by the old core. */ -AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) -AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) -AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) -AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) -AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) -AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) - -AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) -AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) - - /* Special case for b+0, `e' must be next entry after `b', - b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ -AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) -AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) -AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) -AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) - - /* These are for devices that don't exist yet - (>128K program memory, PC = EIND:Z). */ -AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) -AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) - diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h deleted file mode 100644 index efebadb67..000000000 --- a/include/opcode/cgen.h +++ /dev/null @@ -1,1461 +0,0 @@ -/* Header file for targets using CGEN: Cpu tools GENerator. - -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 -Free Software Foundation, Inc. - -This file is part of GDB, the GNU debugger, and the GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef CGEN_H -#define CGEN_H - -/* ??? This file requires bfd.h but only to get bfd_vma. - Seems like an awful lot to require just to get such a fundamental type. - Perhaps the definition of bfd_vma can be moved outside of bfd.h. - Or perhaps one could duplicate its definition in another file. - Until such time, this file conditionally compiles definitions that require - bfd_vma using __BFD_H_SEEN__. */ - -/* Enums must be defined before they can be used. - Allow them to be used in struct definitions, even though the enum must - be defined elsewhere. - If CGEN_ARCH isn't defined, this file is being included by something other - than <arch>-desc.h. */ - -/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. - The lack of spaces in the arg list is important for non-stdc systems. - This file is included by <arch>-desc.h. - It can be included independently of <arch>-desc.h, in which case the arch - dependent portions will be declared as "unknown_cgen_foo". */ - -#ifndef CGEN_SYM -#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) -#endif - -/* This file contains the static (unchanging) pieces and as much other stuff - as we can reasonably put here. It's generally cleaner to put stuff here - rather than having it machine generated if possible. */ - -/* The assembler syntax is made up of expressions (duh...). - At the lowest level the values are mnemonics, register names, numbers, etc. - Above that are subexpressions, if any (an example might be the - "effective address" in m68k cpus). Subexpressions are wip. - At the second highest level are the insns themselves. Above that are - pseudo-insns, synthetic insns, and macros, if any. */ - -/* Lots of cpu's have a fixed insn size, or one which rarely changes, - and it's generally easier to handle these by treating the insn as an - integer type, rather than an array of characters. So we allow targets - to control this. When an integer type the value is in host byte order, - when an array of characters the value is in target byte order. */ - -typedef unsigned int CGEN_INSN_INT; -#if CGEN_INT_INSN_P -typedef CGEN_INSN_INT CGEN_INSN_BYTES; -typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; -#else -typedef unsigned char *CGEN_INSN_BYTES; -typedef unsigned char *CGEN_INSN_BYTES_PTR; -#endif - -#ifdef __GNUC__ -#define CGEN_INLINE __inline__ -#else -#define CGEN_INLINE -#endif - -enum cgen_endian -{ - CGEN_ENDIAN_UNKNOWN, - CGEN_ENDIAN_LITTLE, - CGEN_ENDIAN_BIG -}; - -/* Forward decl. */ - -typedef struct cgen_insn CGEN_INSN; - -/* Opaque pointer version for use by external world. */ - -typedef struct cgen_cpu_desc *CGEN_CPU_DESC; - -/* Attributes. - Attributes are used to describe various random things associated with - an object (ifield, hardware, operand, insn, whatever) and are specified - as name/value pairs. - Integer attributes computed at compile time are currently all that's - supported, though adding string attributes and run-time computation is - straightforward. Integer attribute values are always host int's - (signed or unsigned). For portability, this means 32 bits. - Integer attributes are further categorized as boolean, bitset, integer, - and enum types. Boolean attributes appear frequently enough that they're - recorded in one host int. This limits the maximum number of boolean - attributes to 32, though that's a *lot* of attributes. */ - -/* Type of attribute values. */ - -typedef int CGEN_ATTR_VALUE_TYPE; - -/* Struct to record attribute information. */ - -typedef struct -{ - /* Boolean attributes. */ - unsigned int bool; - /* Non-boolean integer attributes. */ - CGEN_ATTR_VALUE_TYPE nonbool[1]; -} CGEN_ATTR; - -/* Define a structure member for attributes with N non-boolean entries. - There is no maximum number of non-boolean attributes. - There is a maximum of 32 boolean attributes (since they are all recorded - in one host int). */ - -#define CGEN_ATTR_TYPE(n) \ -struct { unsigned int bool; \ - CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } - -/* Return the boolean attributes. */ - -#define CGEN_ATTR_BOOLS(a) ((a)->bool) - -/* Non-boolean attribute numbers are offset by this much. */ - -#define CGEN_ATTR_NBOOL_OFFSET 32 - -/* Given a boolean attribute number, return its mask. */ - -#define CGEN_ATTR_MASK(attr) (1 << (attr)) - -/* Return the value of boolean attribute ATTR in ATTRS. */ - -#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) - -/* Return value of attribute ATTR in ATTR_TABLE for OBJ. - OBJ is a pointer to the entity that has the attributes - (??? not used at present but is reserved for future purposes - eventually - the goal is to allow recording attributes in source form and computing - them lazily at runtime, not sure of the details yet). */ - -#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ -((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ - ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ - : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET])) - -/* Attribute name/value tables. - These are used to assist parsing of descriptions at run-time. */ - -typedef struct -{ - const char * name; - CGEN_ATTR_VALUE_TYPE value; -} CGEN_ATTR_ENTRY; - -/* For each domain (ifld,hw,operand,insn), list of attributes. */ - -typedef struct -{ - const char * name; - const CGEN_ATTR_ENTRY * dfault; - const CGEN_ATTR_ENTRY * vals; -} CGEN_ATTR_TABLE; - -/* Instruction set variants. */ - -typedef struct { - const char *name; - - /* Default instruction size (in bits). - This is used by the assembler when it encounters an unknown insn. */ - unsigned int default_insn_bitsize; - - /* Base instruction size (in bits). - For non-LIW cpus this is generally the length of the smallest insn. - For LIW cpus its wip (work-in-progress). For the m32r its 32. */ - unsigned int base_insn_bitsize; - - /* Minimum/maximum instruction size (in bits). */ - unsigned int min_insn_bitsize; - unsigned int max_insn_bitsize; -} CGEN_ISA; - -/* Machine variants. */ - -typedef struct { - const char *name; - /* The argument to bfd_arch_info->scan. */ - const char *bfd_name; - /* one of enum mach_attr */ - int num; - /* parameter from mach->cpu */ - unsigned int insn_chunk_bitsize; -} CGEN_MACH; - -/* Parse result (also extraction result). - - The result of parsing an insn is stored here. - To generate the actual insn, this is passed to the insert handler. - When printing an insn, the result of extraction is stored here. - To print the insn, this is passed to the print handler. - - It is machine generated so we don't define it here, - but we do need a forward decl for the handler fns. - - There is one member for each possible field in the insn. - The type depends on the field. - Also recorded here is the computed length of the insn for architectures - where it varies. -*/ - -typedef struct cgen_fields CGEN_FIELDS; - -/* Total length of the insn, as recorded in the `fields' struct. */ -/* ??? The field insert handler has lots of opportunities for optimization - if it ever gets inlined. On architectures where insns all have the same - size, may wish to detect that and make this macro a constant - to allow - further optimizations. */ - -#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) - -/* Extraction support for variable length insn sets. */ - -/* When disassembling we don't know the number of bytes to read at the start. - So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest - are read when needed. This struct controls this. It is basically the - disassemble_info stuff, except that we provide a cache for values already - read (since bytes can typically be read several times to fetch multiple - operands that may be in them), and that extraction of fields is needed - in contexts other than disassembly. */ - -typedef struct { - /* A pointer to the disassemble_info struct. - We don't require dis-asm.h so we use void * for the type here. - If NULL, BYTES is full of valid data (VALID == -1). */ - void *dis_info; - /* Points to a working buffer of sufficient size. */ - unsigned char *insn_bytes; - /* Mask of bytes that are valid in INSN_BYTES. */ - unsigned int valid; -} CGEN_EXTRACT_INFO; - -/* Associated with each insn or expression is a set of "handlers" for - performing operations like parsing, printing, etc. These require a bfd_vma - value to be passed around but we don't want all applications to need bfd.h. - So this stuff is only provided if bfd.h has been included. */ - -/* Parse handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - STRP is a pointer to a pointer to the text being parsed. - FIELDS is a pointer to a cgen_fields struct in which the results are placed. - If the expression is successfully parsed, *STRP is updated. - If not it is left alone. - The result is NULL if success or an error message. */ -typedef const char * (cgen_parse_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - const char **strp_, CGEN_FIELDS *fields_); - -/* Insert handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - FIELDS is a pointer to a cgen_fields struct from which the values - are fetched. - INSNP is a pointer to a buffer in which to place the insn. - PC is the pc value of the insn. - The result is an error message or NULL if success. */ - -#ifdef __BFD_H_SEEN__ -typedef const char * (cgen_insert_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, - bfd_vma pc_); -#else -typedef const char * (cgen_insert_fn) (); -#endif - -/* Extract handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - The second argument is a pointer to a struct controlling extraction - (only used for variable length insns). - EX_INFO is a pointer to a struct for controlling reading of further - bytes for the insn. - BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). - FIELDS is a pointer to a cgen_fields struct in which the results are placed. - PC is the pc value of the insn. - The result is the length of the insn in bits or zero if not recognized. */ - -#ifdef __BFD_H_SEEN__ -typedef int (cgen_extract_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, - CGEN_FIELDS *fields_, bfd_vma pc_); -#else -typedef int (cgen_extract_fn) (); -#endif - -/* Print handler. - CD is a cpu table descriptor. - INFO is a pointer to the disassembly info. - Eg: disassemble_info. It's defined as `PTR' so this file can be included - without dis-asm.h. - INSN is a pointer to a struct describing the insn being printed. - FIELDS is a pointer to a cgen_fields struct. - PC is the pc value of the insn. - LEN is the length of the insn, in bits. */ - -#ifdef __BFD_H_SEEN__ -typedef void (cgen_print_fn) - (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, bfd_vma pc_, int len_); -#else -typedef void (cgen_print_fn) (); -#endif - -/* Parse/insert/extract/print handlers. - - Indices into the handler tables. - We could use pointers here instead, but 90% of them are generally identical - and that's a lot of redundant data. Making these unsigned char indices - into tables of pointers saves a bit of space. - Using indices also keeps assembler code out of the disassembler and - vice versa. */ - -struct cgen_opcode_handler -{ - unsigned char parse, insert, extract, print; -}; - -/* Assembler interface. - - The interface to the assembler is intended to be clean in the sense that - libopcodes.a is a standalone entity and could be used with any assembler. - Not that one would necessarily want to do that but rather that it helps - keep a clean interface. The interface will obviously be slanted towards - GAS, but at least it's a start. - ??? Note that one possible user of the assembler besides GAS is GDB. - - Parsing is controlled by the assembler which calls - CGEN_SYM (assemble_insn). If it can parse and build the entire insn - it doesn't call back to the assembler. If it needs/wants to call back - to the assembler, cgen_parse_operand_fn is called which can either - - - return a number to be inserted in the insn - - return a "register" value to be inserted - (the register might not be a register per pe) - - queue the argument and return a marker saying the expression has been - queued (eg: a fix-up) - - return an error message indicating the expression wasn't recognizable - - The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ - -/* Values for indicating what the caller wants. */ - -enum cgen_parse_operand_type -{ - CGEN_PARSE_OPERAND_INIT, - CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS, - CGEN_PARSE_OPERAND_SYMBOLIC -}; - -/* Values for indicating what was parsed. */ - -enum cgen_parse_operand_result -{ - CGEN_PARSE_OPERAND_RESULT_NUMBER, - CGEN_PARSE_OPERAND_RESULT_REGISTER, - CGEN_PARSE_OPERAND_RESULT_QUEUED, - CGEN_PARSE_OPERAND_RESULT_ERROR -}; - -#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ -typedef const char * (cgen_parse_operand_fn) - (CGEN_CPU_DESC, - enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *); -#else -typedef const char * (cgen_parse_operand_fn) (); -#endif - -/* Set the cgen_parse_operand_fn callback. */ - -extern void cgen_set_parse_operand_fn - (CGEN_CPU_DESC, cgen_parse_operand_fn); - -/* Called before trying to match a table entry with the insn. */ - -extern void cgen_init_parse_operand (CGEN_CPU_DESC); - -/* Operand values (keywords, integers, symbols, etc.) */ - -/* Types of assembler elements. */ - -enum cgen_asm_type -{ - CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX -}; - -#ifndef CGEN_ARCH -enum cgen_hw_type { CGEN_HW_MAX }; -#endif - -/* List of hardware elements. */ - -typedef struct -{ - char *name; - enum cgen_hw_type type; - /* There is currently no example where both index specs and value specs - are required, so for now both are clumped under "asm_data". */ - enum cgen_asm_type asm_type; - void *asm_data; -#ifndef CGEN_HW_NBOOL_ATTRS -#define CGEN_HW_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; -#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) -} CGEN_HW_ENTRY; - -/* Return value of attribute ATTR in HW. */ - -#define CGEN_HW_ATTR_VALUE(hw, attr) \ -CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) - -/* Table of hardware elements for selected mach, computed at runtime. - enum cgen_hw_type is an index into this table (specifically `entries'). */ - -typedef struct { - /* Pointer to null terminated table of all compiled in entries. */ - const CGEN_HW_ENTRY *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - /* Array of all entries, initial and run-time added. */ - const CGEN_HW_ENTRY **entries; - /* Number of elements in `entries'. */ - unsigned int num_entries; - /* For now, xrealloc is called each time a new entry is added at runtime. - ??? May wish to keep track of some slop to reduce the number of calls to - xrealloc, except that there's unlikely to be many and not expected to be - in speed critical code. */ -} CGEN_HW_TABLE; - -extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name - (CGEN_CPU_DESC, const char *); -extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num - (CGEN_CPU_DESC, unsigned int); - -/* This struct is used to describe things like register names, etc. */ - -typedef struct cgen_keyword_entry -{ - /* Name (as in register name). */ - char * name; - - /* Value (as in register number). - The value cannot be -1 as that is used to indicate "not found". - IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ - int value; - - /* Attributes. - This should, but technically needn't, appear last. It is a variable sized - array in that one architecture may have 1 nonbool attribute and another - may have more. Having this last means the non-architecture specific code - needn't care. The goal is to eventually record - attributes in their raw form, evaluate them at run-time, and cache the - values, so this worry will go away anyway. */ - /* ??? Moving this last should be done by treating keywords like insn lists - and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ - /* FIXME: Not used yet. */ -#ifndef CGEN_KEYWORD_NBOOL_ATTRS -#define CGEN_KEYWORD_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; - - /* ??? Putting these here means compiled in entries can't be const. - Not a really big deal, but something to consider. */ - /* Next name hash table entry. */ - struct cgen_keyword_entry *next_name; - /* Next value hash table entry. */ - struct cgen_keyword_entry *next_value; -} CGEN_KEYWORD_ENTRY; - -/* Top level struct for describing a set of related keywords - (e.g. register names). - - This struct supports run-time entry of new values, and hashed lookups. */ - -typedef struct cgen_keyword -{ - /* Pointer to initial [compiled in] values. */ - CGEN_KEYWORD_ENTRY *init_entries; - - /* Number of entries in `init_entries'. */ - unsigned int num_init_entries; - - /* Hash table used for name lookup. */ - CGEN_KEYWORD_ENTRY **name_hash_table; - - /* Hash table used for value lookup. */ - CGEN_KEYWORD_ENTRY **value_hash_table; - - /* Number of entries in the hash_tables. */ - unsigned int hash_table_size; - - /* Pointer to null keyword "" entry if present. */ - const CGEN_KEYWORD_ENTRY *null_entry; - - /* String containing non-alphanumeric characters used - in keywords. - At present, the highest number of entries used is 1. */ - char nonalpha_chars[8]; -} CGEN_KEYWORD; - -/* Structure used for searching. */ - -typedef struct -{ - /* Table being searched. */ - const CGEN_KEYWORD *table; - - /* Specification of what is being searched for. */ - const char *spec; - - /* Current index in hash table. */ - unsigned int current_hash; - - /* Current element in current hash chain. */ - CGEN_KEYWORD_ENTRY *current_entry; -} CGEN_KEYWORD_SEARCH; - -/* Lookup a keyword from its name. */ - -const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name - (CGEN_KEYWORD *, const char *); - -/* Lookup a keyword from its value. */ - -const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value - (CGEN_KEYWORD *, int); - -/* Add a keyword. */ - -void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); - -/* Keyword searching. - This can be used to retrieve every keyword, or a subset. */ - -CGEN_KEYWORD_SEARCH cgen_keyword_search_init - (CGEN_KEYWORD *, const char *); -const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next - (CGEN_KEYWORD_SEARCH *); - -/* Operand value support routines. */ - -extern const char *cgen_parse_keyword - (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); -#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ -extern const char *cgen_parse_signed_integer - (CGEN_CPU_DESC, const char **, int, long *); -extern const char *cgen_parse_unsigned_integer - (CGEN_CPU_DESC, const char **, int, unsigned long *); -extern const char *cgen_parse_address - (CGEN_CPU_DESC, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *); -extern const char *cgen_validate_signed_integer - (long, long, long); -extern const char *cgen_validate_unsigned_integer - (unsigned long, unsigned long, unsigned long); -#endif - -/* Operand modes. */ - -/* ??? This duplicates the values in arch.h. Revisit. - These however need the CGEN_ prefix [as does everything in this file]. */ -/* ??? Targets may need to add their own modes so we may wish to move this - to <arch>-opc.h, or add a hook. */ - -enum cgen_mode { - CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ - CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, - CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, - CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, - CGEN_MODE_TARGET_MAX, - CGEN_MODE_INT, CGEN_MODE_UINT, - CGEN_MODE_MAX -}; - -/* FIXME: Until simulator is updated. */ - -#define CGEN_MODE_VM CGEN_MODE_VOID - -/* Operands. */ - -#ifndef CGEN_ARCH -enum cgen_operand_type { CGEN_OPERAND_MAX }; -#endif - -/* "nil" indicator for the operand instance table */ -#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX - -/* A tree of these structs represents the multi-ifield - structure of an operand's hw-index value, if it exists. */ - -struct cgen_ifld; - -typedef struct cgen_maybe_multi_ifield -{ - int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); - n: indexed by array of more cgen_maybe_multi_ifields. */ - union - { - const void *p; - const struct cgen_maybe_multi_ifield * multi; - const struct cgen_ifld * leaf; - } val; -} -CGEN_MAYBE_MULTI_IFLD; - -/* This struct defines each entry in the operand table. */ - -typedef struct -{ - /* Name as it appears in the syntax string. */ - char *name; - - /* Operand type. */ - enum cgen_operand_type type; - - /* The hardware element associated with this operand. */ - enum cgen_hw_type hw_type; - - /* FIXME: We don't yet record ifield definitions, which we should. - When we do it might make sense to delete start/length (since they will - be duplicated in the ifield's definition) and replace them with a - pointer to the ifield entry. */ - - /* Bit position. - This is just a hint, and may be unused in more complex operands. - May be unused for a modifier. */ - unsigned char start; - - /* The number of bits in the operand. - This is just a hint, and may be unused in more complex operands. - May be unused for a modifier. */ - unsigned char length; - - /* The (possibly-multi) ifield used as an index for this operand, if it - is indexed by a field at all. This substitutes / extends the start and - length fields above, but unsure at this time whether they are used - anywhere. */ - CGEN_MAYBE_MULTI_IFLD index_fields; -#if 0 /* ??? Interesting idea but relocs tend to get too complicated, - and ABI dependent, for simple table lookups to work. */ - /* Ideally this would be the internal (external?) reloc type. */ - int reloc_type; -#endif - - /* Attributes. - This should, but technically needn't, appear last. It is a variable sized - array in that one architecture may have 1 nonbool attribute and another - may have more. Having this last means the non-architecture specific code - needn't care, now or tomorrow. The goal is to eventually record - attributes in their raw form, evaluate them at run-time, and cache the - values, so this worry will go away anyway. */ -#ifndef CGEN_OPERAND_NBOOL_ATTRS -#define CGEN_OPERAND_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; -#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) -} CGEN_OPERAND; - -/* Return value of attribute ATTR in OPERAND. */ - -#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ -CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) - -/* Table of operands for selected mach/isa, computed at runtime. - enum cgen_operand_type is an index into this table (specifically - `entries'). */ - -typedef struct { - /* Pointer to null terminated table of all compiled in entries. */ - const CGEN_OPERAND *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - /* Array of all entries, initial and run-time added. */ - const CGEN_OPERAND **entries; - /* Number of elements in `entries'. */ - unsigned int num_entries; - /* For now, xrealloc is called each time a new entry is added at runtime. - ??? May wish to keep track of some slop to reduce the number of calls to - xrealloc, except that there's unlikely to be many and not expected to be - in speed critical code. */ -} CGEN_OPERAND_TABLE; - -extern const CGEN_OPERAND * cgen_operand_lookup_by_name - (CGEN_CPU_DESC, const char *); -extern const CGEN_OPERAND * cgen_operand_lookup_by_num - (CGEN_CPU_DESC, int); - -/* Instruction operand instances. - - For each instruction, a list of the hardware elements that are read and - written are recorded. */ - -/* The type of the instance. */ - -enum cgen_opinst_type { - /* End of table marker. */ - CGEN_OPINST_END = 0, - CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT -}; - -typedef struct -{ - /* Input or output indicator. */ - enum cgen_opinst_type type; - - /* Name of operand. */ - const char *name; - - /* The hardware element referenced. */ - enum cgen_hw_type hw_type; - - /* The mode in which the operand is being used. */ - enum cgen_mode mode; - - /* The operand table entry CGEN_OPERAND_NIL if there is none - (i.e. an explicit hardware reference). */ - enum cgen_operand_type op_type; - - /* If `operand' is "nil", the index (e.g. into array of registers). */ - int index; - - /* Attributes. - ??? This perhaps should be a real attribute struct but there's - no current need, so we save a bit of space and just have a set of - flags. The interface is such that this can easily be made attributes - should it prove useful. */ - unsigned int attrs; -#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) -/* Return value of attribute ATTR in OPINST. */ -#define CGEN_OPINST_ATTR(opinst, attr) \ -((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) -/* Operand is conditionally referenced (read/written). */ -#define CGEN_OPINST_COND_REF 1 -} CGEN_OPINST; - -/* Syntax string. - - Each insn format and subexpression has one of these. - - The syntax "string" consists of characters (n > 0 && n < 128), and operand - values (n >= 128), and is terminated by 0. Operand values are 128 + index - into the operand table. The operand table doesn't exist in C, per se, as - the data is recorded in the parse/insert/extract/print switch statements. */ - -/* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_ELEMENTS 48 - -/* A target may know its own precise maximum. Assert that it falls below - the above limit. */ -#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS -#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS -#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" -#endif -#endif - -typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; - -typedef struct -{ - CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; -} CGEN_SYNTAX; - -#define CGEN_SYNTAX_STRING(syn) (syn->syntax) -#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) -#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) -#define CGEN_SYNTAX_FIELD(c) ((c) - 128) -#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) - -/* ??? I can't currently think of any case where the mnemonic doesn't come - first [and if one ever doesn't building the hash tables will be tricky]. - However, we treat mnemonics as just another operand of the instruction. - A value of 1 means "this is where the mnemonic appears". 1 isn't - special other than it's a non-printable ASCII char. */ - -#define CGEN_SYNTAX_MNEMONIC 1 -#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) - -/* Instruction fields. - - ??? We currently don't allow adding fields at run-time. - Easy to fix when needed. */ - -typedef struct cgen_ifld { - /* Enum of ifield. */ - int num; -#define CGEN_IFLD_NUM(f) ((f)->num) - - /* Name of the field, distinguishes it from all other fields. */ - const char *name; -#define CGEN_IFLD_NAME(f) ((f)->name) - - /* Default offset, in bits, from the start of the insn to the word - containing the field. */ - int word_offset; -#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) - - /* Default length of the word containing the field. */ - int word_size; -#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) - - /* Default starting bit number. - Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ - int start; -#define CGEN_IFLD_START(f) ((f)->start) - - /* Length of the field, in bits. */ - int length; -#define CGEN_IFLD_LENGTH(f) ((f)->length) - -#ifndef CGEN_IFLD_NBOOL_ATTRS -#define CGEN_IFLD_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; -#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) -} CGEN_IFLD; - -/* Return value of attribute ATTR in IFLD. */ -#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ -CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) - -/* Instruction data. */ - -/* Instruction formats. - - Instructions are grouped by format. Associated with an instruction is its - format. Each insn's opcode table entry contains a format table entry. - ??? There is usually very few formats compared with the number of insns, - so one can reduce the size of the opcode table by recording the format table - as a separate entity. Given that we currently don't, format table entries - are also distinguished by their operands. This increases the size of the - table, but reduces the number of tables. It's all minutiae anyway so it - doesn't really matter [at this point in time]. - - ??? Support for variable length ISA's is wip. */ - -/* Accompanying each iformat description is a list of its fields. */ - -typedef struct { - const CGEN_IFLD *ifld; -#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) -} CGEN_IFMT_IFLD; - -/* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_IFMT_OPERANDS 16 - -/* A target may know its own precise maximum. Assert that it falls below - the above limit. */ -#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS -#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS -#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" -#endif -#endif - - -typedef struct -{ - /* Length that MASK and VALUE have been calculated to - [VALUE is recorded elsewhere]. - Normally it is base_insn_bitsize. On [V]LIW architectures where the base - insn size may be larger than the size of an insn, this field is less than - base_insn_bitsize. */ - unsigned char mask_length; -#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) - - /* Total length of instruction, in bits. */ - unsigned char length; -#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) - - /* Mask to apply to the first MASK_LENGTH bits. - Each insn's value is stored with the insn. - The first step in recognizing an insn for disassembly is - (opcode & mask) == value. */ - CGEN_INSN_INT mask; -#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) - - /* Instruction fields. - +1 for trailing NULL. */ - CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; -#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) -} CGEN_IFMT; - -/* Instruction values. */ - -typedef struct -{ - /* The opcode portion of the base insn. */ - CGEN_INSN_INT base_value; - -#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS - /* Extra opcode values beyond base_value. */ - unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; -#endif -} CGEN_IVALUE; - -/* Instruction opcode table. - This contains the syntax and format data of an instruction. */ - -/* ??? Some ports already have an opcode table yet still need to use the rest - of what cgen_insn has. Plus keeping the opcode data with the operand - instance data can create a pretty big file. So we keep them separately. - Not sure this is a good idea in the long run. */ - -typedef struct -{ - /* Indices into parse/insert/extract/print handler tables. */ - struct cgen_opcode_handler handlers; -#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) - - /* Syntax string. */ - CGEN_SYNTAX syntax; -#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) - - /* Format entry. */ - const CGEN_IFMT *format; -#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) -#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) -#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) -#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) - - /* Instruction opcode value. */ - CGEN_IVALUE value; -#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) -#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) -#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) -} CGEN_OPCODE; - -/* Instruction attributes. - This is made a published type as applications can cache a pointer to - the attributes for speed. */ - -#ifndef CGEN_INSN_NBOOL_ATTRS -#define CGEN_INSN_NBOOL_ATTRS 1 -#endif -typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; - -/* Enum of architecture independent attributes. */ - -#ifndef CGEN_ARCH -/* ??? Numbers here are recorded in two places. */ -typedef enum cgen_insn_attr { - CGEN_INSN_ALIAS = 0 -} CGEN_INSN_ATTR; -#endif - -/* This struct defines each entry in the instruction table. */ - -typedef struct -{ - /* Each real instruction is enumerated. */ - /* ??? This may go away in time. */ - int num; -#define CGEN_INSN_NUM(insn) ((insn)->base->num) - - /* Name of entry (that distinguishes it from all other entries). */ - /* ??? If mnemonics have operands, try to print full mnemonic. */ - const char *name; -#define CGEN_INSN_NAME(insn) ((insn)->base->name) - - /* Mnemonic. This is used when parsing and printing the insn. - In the case of insns that have operands on the mnemonics, this is - only the constant part. E.g. for conditional execution of an `add' insn, - where the full mnemonic is addeq, addne, etc., and the condition is - treated as an operand, this is only "add". */ - const char *mnemonic; -#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) - - /* Total length of instruction, in bits. */ - int bitsize; -#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) - -#if 0 /* ??? Disabled for now as there is a problem with embedded newlines - and the table is already pretty big. Should perhaps be moved - to a file of its own. */ - /* Semantics, as RTL. */ - /* ??? Plain text or bytecodes? */ - /* ??? Note that the operand instance table could be computed at run-time - if we parse this and cache the results. Something to eventually do. */ - const char *rtx; -#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) -#endif - - /* Attributes. - This must appear last. It is a variable sized array in that one - architecture may have 1 nonbool attribute and another may have more. - Having this last means the non-architecture specific code needn't - care. The goal is to eventually record attributes in their raw form, - evaluate them at run-time, and cache the values, so this worry will go - away anyway. */ - CGEN_INSN_ATTR_TYPE attrs; -#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) -/* Return value of attribute ATTR in INSN. */ -#define CGEN_INSN_ATTR_VALUE(insn, attr) \ -CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) -} CGEN_IBASE; - -/* Return non-zero if INSN is the "invalid" insn marker. */ - -#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) - -/* Main struct contain instruction information. - BASE is always present, the rest is present only if asked for. */ - -struct cgen_insn -{ - /* ??? May be of use to put a type indicator here. - Then this struct could different info for different classes of insns. */ - /* ??? A speedup can be had by moving `base' into this struct. - Maybe later. */ - const CGEN_IBASE *base; - const CGEN_OPCODE *opcode; - const CGEN_OPINST *opinst; - - /* Regex to disambiguate overloaded opcodes */ - void *rx; -#define CGEN_INSN_RX(insn) ((insn)->rx) -#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) -}; - -/* Instruction lists. - This is used for adding new entries and for creating the hash lists. */ - -typedef struct cgen_insn_list -{ - struct cgen_insn_list *next; - const CGEN_INSN *insn; -} CGEN_INSN_LIST; - -/* Table of instructions. */ - -typedef struct -{ - const CGEN_INSN *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - unsigned int num_init_entries; - CGEN_INSN_LIST *new_entries; -} CGEN_INSN_TABLE; - -/* Return number of instructions. This includes any added at run-time. */ - -extern int cgen_insn_count (CGEN_CPU_DESC); -extern int cgen_macro_insn_count (CGEN_CPU_DESC); - -/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ - -/* Fetch INSN's operand instance table. */ -/* ??? Doesn't handle insns added at runtime. */ -#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) - -/* Return INSN's opcode table entry. */ -#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) - -/* Return INSN's handler data. */ -#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) - -/* Return INSN's syntax. */ -#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) - -/* Return size of base mask in bits. */ -#define CGEN_INSN_MASK_BITSIZE(insn) \ - CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) - -/* Return mask of base part of INSN. */ -#define CGEN_INSN_BASE_MASK(insn) \ - CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) - -/* Return value of base part of INSN. */ -#define CGEN_INSN_BASE_VALUE(insn) \ - CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) - -/* Standard way to test whether INSN is supported by MACH. - MACH is one of enum mach_attr. - The "|1" is because the base mach is always selected. */ -#define CGEN_INSN_MACH_HAS_P(insn, mach) \ -((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) - -/* Macro instructions. - Macro insns aren't real insns, they map to one or more real insns. - E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or - some such. - - Macro insns can expand to nothing (e.g. a nop that is optimized away). - This is useful in multi-insn macros that build a constant in a register. - Of course this isn't the default behaviour and must be explicitly enabled. - - Assembly of macro-insns is relatively straightforward. Disassembly isn't. - However, disassembly of at least some kinds of macro insns is important - in order that the disassembled code preserve the readability of the original - insn. What is attempted here is to disassemble all "simple" macro-insns, - where "simple" is currently defined to mean "expands to one real insn". - - Simple macro-insns are handled specially. They are emitted as ALIAS's - of real insns. This simplifies their handling since there's usually more - of them than any other kind of macro-insn, and proper disassembly of them - falls out for free. */ - -/* For each macro-insn there may be multiple expansion possibilities, - depending on the arguments. This structure is accessed via the `data' - member of CGEN_INSN. */ - -typedef struct cgen_minsn_expansion { - /* Function to do the expansion. - If the expansion fails (e.g. "no match") NULL is returned. - Space for the expansion is obtained with malloc. - It is up to the caller to free it. */ - const char * (* fn) - (const struct cgen_minsn_expansion *, - const char *, const char **, int *, - CGEN_OPERAND **); -#define CGEN_MIEXPN_FN(ex) ((ex)->fn) - - /* Instruction(s) the macro expands to. - The format of STR is defined by FN. - It is typically the assembly code of the real insn, but it could also be - the original Scheme expression or a tokenized form of it (with FN being - an appropriate interpreter). */ - const char * str; -#define CGEN_MIEXPN_STR(ex) ((ex)->str) -} CGEN_MINSN_EXPANSION; - -/* Normal expander. - When supported, this function will convert the input string to another - string and the parser will be invoked recursively. The output string - may contain further macro invocations. */ - -extern const char * cgen_expand_macro_insn - (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, - const char *, const char **, int *, CGEN_OPERAND **); - -/* The assembler insn table is hashed based on some function of the mnemonic - (the actually hashing done is up to the target, but we provide a few - examples like the first letter or a function of the entire mnemonic). */ - -extern CGEN_INSN_LIST * cgen_asm_lookup_insn - (CGEN_CPU_DESC, const char *); -#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) -#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) - -/* The disassembler insn table is hashed based on some function of machine - instruction (the actually hashing done is up to the target). */ - -extern CGEN_INSN_LIST * cgen_dis_lookup_insn - (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); -/* FIXME: delete these two */ -#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) -#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) - -/* The CPU description. - A copy of this is created when the cpu table is "opened". - All global state information is recorded here. - Access macros are provided for "public" members. */ - -typedef struct cgen_cpu_desc -{ - /* Bitmap of selected machine(s) (a la BFD machine number). */ - int machs; - - /* Bitmap of selected isa(s). - ??? Simultaneous multiple isas might not make sense, but it's not (yet) - precluded. */ - int isas; - - /* Current endian. */ - enum cgen_endian endian; -#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) - - /* Current insn endian. */ - enum cgen_endian insn_endian; -#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) - - /* Word size (in bits). */ - /* ??? Or maybe maximum word size - might we ever need to allow a cpu table - to be opened for both sparc32/sparc64? - ??? Another alternative is to create a table of selected machs and - lazily fetch the data from there. */ - unsigned int word_bitsize; - - /* Instruction chunk size (in bits), for purposes of endianness - conversion. */ - unsigned int insn_chunk_bitsize; - - /* Indicator if sizes are unknown. - This is used by default_insn_bitsize,base_insn_bitsize if there is a - difference between the selected isa's. */ -#define CGEN_SIZE_UNKNOWN 65535 - - /* Default instruction size (in bits). - This is used by the assembler when it encounters an unknown insn. */ - unsigned int default_insn_bitsize; - - /* Base instruction size (in bits). - For non-LIW cpus this is generally the length of the smallest insn. - For LIW cpus its wip (work-in-progress). For the m32r its 32. */ - unsigned int base_insn_bitsize; - - /* Minimum/maximum instruction size (in bits). */ - unsigned int min_insn_bitsize; - unsigned int max_insn_bitsize; - - /* Instruction set variants. */ - const CGEN_ISA *isa_table; - - /* Machine variants. */ - const CGEN_MACH *mach_table; - - /* Hardware elements. */ - CGEN_HW_TABLE hw_table; - - /* Instruction fields. */ - const CGEN_IFLD *ifld_table; - - /* Operands. */ - CGEN_OPERAND_TABLE operand_table; - - /* Main instruction table. */ - CGEN_INSN_TABLE insn_table; -#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) - - /* Macro instructions are defined separately and are combined with real - insns during hash table computation. */ - CGEN_INSN_TABLE macro_insn_table; - - /* Copy of CGEN_INT_INSN_P. */ - int int_insn_p; - - /* Called to rebuild the tables after something has changed. */ - void (*rebuild_tables) (CGEN_CPU_DESC); - - /* Operand parser callback. */ - cgen_parse_operand_fn * parse_operand_fn; - - /* Parse/insert/extract/print cover fns for operands. */ - const char * (*parse_operand) - (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); -#ifdef __BFD_H_SEEN__ - const char * (*insert_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, - CGEN_INSN_BYTES_PTR, bfd_vma pc_); - int (*extract_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *fields_, bfd_vma pc_); - void (*print_operand) - (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, - void const *attrs_, bfd_vma pc_, int length_); -#else - const char * (*insert_operand) (); - int (*extract_operand) (); - void (*print_operand) (); -#endif -#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) -#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) -#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) -#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) - - /* Size of CGEN_FIELDS struct. */ - unsigned int sizeof_fields; -#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) - - /* Set the bitsize field. */ - void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); -#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) - - /* CGEN_FIELDS accessors. */ - int (*get_int_operand) - (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); - void (*set_int_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); -#ifdef __BFD_H_SEEN__ - bfd_vma (*get_vma_operand) - (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); - void (*set_vma_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); -#else - long (*get_vma_operand) (); - void (*set_vma_operand) (); -#endif -#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) -#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) -#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) -#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) - - /* Instruction parse/insert/extract/print handlers. */ - /* FIXME: make these types uppercase. */ - cgen_parse_fn * const *parse_handlers; - cgen_insert_fn * const *insert_handlers; - cgen_extract_fn * const *extract_handlers; - cgen_print_fn * const *print_handlers; -#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) -#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) -#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) -#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) - - /* Return non-zero if insn should be added to hash table. */ - int (* asm_hash_p) (const CGEN_INSN *); - - /* Assembler hash function. */ - unsigned int (* asm_hash) (const char *); - - /* Number of entries in assembler hash table. */ - unsigned int asm_hash_size; - - /* Return non-zero if insn should be added to hash table. */ - int (* dis_hash_p) (const CGEN_INSN *); - - /* Disassembler hash function. */ - unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); - - /* Number of entries in disassembler hash table. */ - unsigned int dis_hash_size; - - /* Assembler instruction hash table. */ - CGEN_INSN_LIST **asm_hash_table; - CGEN_INSN_LIST *asm_hash_table_entries; - - /* Disassembler instruction hash table. */ - CGEN_INSN_LIST **dis_hash_table; - CGEN_INSN_LIST *dis_hash_table_entries; - - /* This field could be turned into a bitfield if room for other flags is needed. */ - unsigned int signed_overflow_ok_p; - -} CGEN_CPU_TABLE; - -/* wip */ -#ifndef CGEN_WORD_ENDIAN -#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) -#endif -#ifndef CGEN_INSN_WORD_ENDIAN -#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) -#endif - -/* Prototypes of major functions. */ -/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. - Not the init fns though, as that would drag in things that mightn't be - used and might not even exist. */ - -/* Argument types to cpu_open. */ - -enum cgen_cpu_open_arg { - CGEN_CPU_OPEN_END, - /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ - CGEN_CPU_OPEN_ISAS, - /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ - CGEN_CPU_OPEN_MACHS, - /* Select machine, arg is mach's bfd name. - Multiple machines can be specified by repeated use. */ - CGEN_CPU_OPEN_BFDMACH, - /* Select endian, arg is CGEN_ENDIAN_*. */ - CGEN_CPU_OPEN_ENDIAN -}; - -/* Open a cpu descriptor table for use. - ??? We only support ISO C stdargs here, not K&R. - Laziness, plus experiment to see if anything requires K&R - eventually - K&R will no longer be supported - e.g. GDB is currently trying this. */ - -extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); - -/* Cover fn to handle simple case. */ - -extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) - (const char *mach_name_, enum cgen_endian endian_); - -/* Close it. */ - -extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); - -/* Initialize the opcode table for use. - Called by init_asm/init_dis. */ - -extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); - -/* build the insn selection regex. - called by init_opcode_table */ - -extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); - -/* Initialize the ibld table for use. - Called by init_asm/init_dis. */ - -extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); - -/* Initialize an cpu table for assembler or disassembler use. - These must be called immediately after cpu_open. */ - -extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); -extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); - -/* Initialize the operand instance table for use. */ - -extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); - -/* Assemble an instruction. */ - -extern const CGEN_INSN * CGEN_SYM (assemble_insn) - (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, - CGEN_INSN_BYTES_PTR, char **); - -extern const CGEN_KEYWORD CGEN_SYM (operand_mach); -extern int CGEN_SYM (get_mach) (const char *); - -/* Operand index computation. */ -extern const CGEN_INSN * cgen_lookup_insn - (CGEN_CPU_DESC, const CGEN_INSN * insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, CGEN_FIELDS *fields_, int alias_p_); -extern void cgen_get_insn_operands - (CGEN_CPU_DESC, const CGEN_INSN * insn_, - const CGEN_FIELDS *fields_, int *indices_); -extern const CGEN_INSN * cgen_lookup_get_insn_operands - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, int *indices_, CGEN_FIELDS *fields_); - -/* Cover fns to bfd_get/set. */ - -extern CGEN_INSN_INT cgen_get_insn_value - (CGEN_CPU_DESC, unsigned char *, int); -extern void cgen_put_insn_value - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); - -/* Read in a cpu description file. - ??? For future concerns, including adding instructions to the assembler/ - disassembler at run-time. */ - -extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); - -/* Allow signed overflow of instruction fields. */ -extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); - -/* Generate an error message if a signed field in an instruction overflows. */ -extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); - -#endif /* CGEN_H */ diff --git a/include/opcode/convex.h b/include/opcode/convex.h deleted file mode 100644 index 7843dce8b..000000000 --- a/include/opcode/convex.h +++ /dev/null @@ -1,1707 +0,0 @@ -/* Information for instruction disassembly on the Convex. - Copyright 1989, 1993, 2002 Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#define xxx 0 -#define rrr 1 -#define rr 2 -#define rxr 3 -#define r 4 -#define nops 5 -#define nr 6 -#define pcrel 7 -#define lr 8 -#define rxl 9 -#define rlr 10 -#define rrl 11 -#define iml 12 -#define imr 13 -#define a1r 14 -#define a1l 15 -#define a2r 16 -#define a2l 17 -#define a3 18 -#define a4 19 -#define a5 20 -#define V 1 -#define S 2 -#define VM 3 -#define A 4 -#define VL 5 -#define VS 6 -#define VLS 7 -#define PSW 8 -/* Prevent an error during "make depend". */ -#if !defined (PC) -#define PC 9 -#endif -#define ITR 10 -#define VV 11 -#define ITSR 12 -#define TOC 13 -#define CIR 14 -#define TTR 15 -#define VMU 16 -#define VML 17 -#define ICR 18 -#define TCPU 19 -#define CPUID 20 -#define TID 21 - -const char *op[] = { - "", - "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", - "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", - "vm", - "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp", - "vl", - "vs", - "vls", - "psw", - "pc", - "itr", - "vv", - "itsr", - "toc", - "cir", - "ttr", - "vmu", - "vml", - "icr", - "tcpu", - "cpuid", - "tid", -}; - -const struct formstr format0[] = { - {0,0,rrr,V,S,S}, /* mov */ - {0,0,rrr,S,S,V}, /* mov */ - {1,1,rrr,V,V,V}, /* merg.t */ - {2,1,rrr,V,V,V}, /* mask.t */ - {1,2,rrr,V,S,V}, /* merg.f */ - {2,2,rrr,V,S,V}, /* mask.f */ - {1,1,rrr,V,S,V}, /* merg.t */ - {2,1,rrr,V,S,V}, /* mask.t */ - {3,3,rrr,V,V,V}, /* mul.s */ - {3,4,rrr,V,V,V}, /* mul.d */ - {4,3,rrr,V,V,V}, /* div.s */ - {4,4,rrr,V,V,V}, /* div.d */ - {3,3,rrr,V,S,V}, /* mul.s */ - {3,4,rrr,V,S,V}, /* mul.d */ - {4,3,rrr,V,S,V}, /* div.s */ - {4,4,rrr,V,S,V}, /* div.d */ - {5,0,rrr,V,V,V}, /* and */ - {6,0,rrr,V,V,V}, /* or */ - {7,0,rrr,V,V,V}, /* xor */ - {8,0,rrr,V,V,V}, /* shf */ - {5,0,rrr,V,S,V}, /* and */ - {6,0,rrr,V,S,V}, /* or */ - {7,0,rrr,V,S,V}, /* xor */ - {8,0,rrr,V,S,V}, /* shf */ - {9,3,rrr,V,V,V}, /* add.s */ - {9,4,rrr,V,V,V}, /* add.d */ - {10,3,rrr,V,V,V}, /* sub.s */ - {10,4,rrr,V,V,V}, /* sub.d */ - {9,3,rrr,V,S,V}, /* add.s */ - {9,4,rrr,V,S,V}, /* add.d */ - {10,3,rrr,V,S,V}, /* sub.s */ - {10,4,rrr,V,S,V}, /* sub.d */ - {9,5,rrr,V,V,V}, /* add.b */ - {9,6,rrr,V,V,V}, /* add.h */ - {9,7,rrr,V,V,V}, /* add.w */ - {9,8,rrr,V,V,V}, /* add.l */ - {9,5,rrr,V,S,V}, /* add.b */ - {9,6,rrr,V,S,V}, /* add.h */ - {9,7,rrr,V,S,V}, /* add.w */ - {9,8,rrr,V,S,V}, /* add.l */ - {10,5,rrr,V,V,V}, /* sub.b */ - {10,6,rrr,V,V,V}, /* sub.h */ - {10,7,rrr,V,V,V}, /* sub.w */ - {10,8,rrr,V,V,V}, /* sub.l */ - {10,5,rrr,V,S,V}, /* sub.b */ - {10,6,rrr,V,S,V}, /* sub.h */ - {10,7,rrr,V,S,V}, /* sub.w */ - {10,8,rrr,V,S,V}, /* sub.l */ - {3,5,rrr,V,V,V}, /* mul.b */ - {3,6,rrr,V,V,V}, /* mul.h */ - {3,7,rrr,V,V,V}, /* mul.w */ - {3,8,rrr,V,V,V}, /* mul.l */ - {3,5,rrr,V,S,V}, /* mul.b */ - {3,6,rrr,V,S,V}, /* mul.h */ - {3,7,rrr,V,S,V}, /* mul.w */ - {3,8,rrr,V,S,V}, /* mul.l */ - {4,5,rrr,V,V,V}, /* div.b */ - {4,6,rrr,V,V,V}, /* div.h */ - {4,7,rrr,V,V,V}, /* div.w */ - {4,8,rrr,V,V,V}, /* div.l */ - {4,5,rrr,V,S,V}, /* div.b */ - {4,6,rrr,V,S,V}, /* div.h */ - {4,7,rrr,V,S,V}, /* div.w */ - {4,8,rrr,V,S,V}, /* div.l */ -}; - -const struct formstr format1[] = { - {11,0,xxx,0,0,0}, /* exit */ - {12,0,a3,0,0,0}, /* jmp */ - {13,2,a3,0,0,0}, /* jmpi.f */ - {13,1,a3,0,0,0}, /* jmpi.t */ - {14,2,a3,0,0,0}, /* jmpa.f */ - {14,1,a3,0,0,0}, /* jmpa.t */ - {15,2,a3,0,0,0}, /* jmps.f */ - {15,1,a3,0,0,0}, /* jmps.t */ - {16,0,a3,0,0,0}, /* tac */ - {17,0,a1r,A,0,0}, /* ldea */ - {18,8,a1l,VLS,0,0}, /* ld.l */ - {18,9,a1l,VM,0,0}, /* ld.x */ - {19,0,a3,0,0,0}, /* tas */ - {20,0,a3,0,0,0}, /* pshea */ - {21,8,a2l,VLS,0,0}, /* st.l */ - {21,9,a2l,VM,0,0}, /* st.x */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {22,0,a3,0,0,0}, /* call */ - {23,0,a3,0,0,0}, /* calls */ - {24,0,a3,0,0,0}, /* callq */ - {25,0,a1r,A,0,0}, /* pfork */ - {26,5,a2r,S,0,0}, /* ste.b */ - {26,6,a2r,S,0,0}, /* ste.h */ - {26,7,a2r,S,0,0}, /* ste.w */ - {26,8,a2r,S,0,0}, /* ste.l */ - {18,5,a1r,A,0,0}, /* ld.b */ - {18,6,a1r,A,0,0}, /* ld.h */ - {18,7,a1r,A,0,0}, /* ld.w */ - {27,7,a1r,A,0,0}, /* incr.w */ - {21,5,a2r,A,0,0}, /* st.b */ - {21,6,a2r,A,0,0}, /* st.h */ - {21,7,a2r,A,0,0}, /* st.w */ - {27,8,a1r,S,0,0}, /* incr.l */ - {18,5,a1r,S,0,0}, /* ld.b */ - {18,6,a1r,S,0,0}, /* ld.h */ - {18,7,a1r,S,0,0}, /* ld.w */ - {18,8,a1r,S,0,0}, /* ld.l */ - {21,5,a2r,S,0,0}, /* st.b */ - {21,6,a2r,S,0,0}, /* st.h */ - {21,7,a2r,S,0,0}, /* st.w */ - {21,8,a2r,S,0,0}, /* st.l */ - {18,5,a1r,V,0,0}, /* ld.b */ - {18,6,a1r,V,0,0}, /* ld.h */ - {18,7,a1r,V,0,0}, /* ld.w */ - {18,8,a1r,V,0,0}, /* ld.l */ - {21,5,a2r,V,0,0}, /* st.b */ - {21,6,a2r,V,0,0}, /* st.h */ - {21,7,a2r,V,0,0}, /* st.w */ - {21,8,a2r,V,0,0}, /* st.l */ -}; - -const struct formstr format2[] = { - {28,5,rr,A,A,0}, /* cvtw.b */ - {28,6,rr,A,A,0}, /* cvtw.h */ - {29,7,rr,A,A,0}, /* cvtb.w */ - {30,7,rr,A,A,0}, /* cvth.w */ - {28,5,rr,S,S,0}, /* cvtw.b */ - {28,6,rr,S,S,0}, /* cvtw.h */ - {29,7,rr,S,S,0}, /* cvtb.w */ - {30,7,rr,S,S,0}, /* cvth.w */ - {28,3,rr,S,S,0}, /* cvtw.s */ - {31,7,rr,S,S,0}, /* cvts.w */ - {32,3,rr,S,S,0}, /* cvtd.s */ - {31,4,rr,S,S,0}, /* cvts.d */ - {31,8,rr,S,S,0}, /* cvts.l */ - {32,8,rr,S,S,0}, /* cvtd.l */ - {33,3,rr,S,S,0}, /* cvtl.s */ - {33,4,rr,S,S,0}, /* cvtl.d */ - {34,0,rr,A,A,0}, /* ldpa */ - {8,0,nr,A,0,0}, /* shf */ - {18,6,nr,A,0,0}, /* ld.h */ - {18,7,nr,A,0,0}, /* ld.w */ - {33,7,rr,S,S,0}, /* cvtl.w */ - {28,8,rr,S,S,0}, /* cvtw.l */ - {35,1,rr,S,S,0}, /* plc.t */ - {36,0,rr,S,S,0}, /* tzc */ - {37,6,rr,A,A,0}, /* eq.h */ - {37,7,rr,A,A,0}, /* eq.w */ - {37,6,nr,A,0,0}, /* eq.h */ - {37,7,nr,A,0,0}, /* eq.w */ - {37,5,rr,S,S,0}, /* eq.b */ - {37,6,rr,S,S,0}, /* eq.h */ - {37,7,rr,S,S,0}, /* eq.w */ - {37,8,rr,S,S,0}, /* eq.l */ - {38,6,rr,A,A,0}, /* leu.h */ - {38,7,rr,A,A,0}, /* leu.w */ - {38,6,nr,A,0,0}, /* leu.h */ - {38,7,nr,A,0,0}, /* leu.w */ - {38,5,rr,S,S,0}, /* leu.b */ - {38,6,rr,S,S,0}, /* leu.h */ - {38,7,rr,S,S,0}, /* leu.w */ - {38,8,rr,S,S,0}, /* leu.l */ - {39,6,rr,A,A,0}, /* ltu.h */ - {39,7,rr,A,A,0}, /* ltu.w */ - {39,6,nr,A,0,0}, /* ltu.h */ - {39,7,nr,A,0,0}, /* ltu.w */ - {39,5,rr,S,S,0}, /* ltu.b */ - {39,6,rr,S,S,0}, /* ltu.h */ - {39,7,rr,S,S,0}, /* ltu.w */ - {39,8,rr,S,S,0}, /* ltu.l */ - {40,6,rr,A,A,0}, /* le.h */ - {40,7,rr,A,A,0}, /* le.w */ - {40,6,nr,A,0,0}, /* le.h */ - {40,7,nr,A,0,0}, /* le.w */ - {40,5,rr,S,S,0}, /* le.b */ - {40,6,rr,S,S,0}, /* le.h */ - {40,7,rr,S,S,0}, /* le.w */ - {40,8,rr,S,S,0}, /* le.l */ - {41,6,rr,A,A,0}, /* lt.h */ - {41,7,rr,A,A,0}, /* lt.w */ - {41,6,nr,A,0,0}, /* lt.h */ - {41,7,nr,A,0,0}, /* lt.w */ - {41,5,rr,S,S,0}, /* lt.b */ - {41,6,rr,S,S,0}, /* lt.h */ - {41,7,rr,S,S,0}, /* lt.w */ - {41,8,rr,S,S,0}, /* lt.l */ - {9,7,rr,S,A,0}, /* add.w */ - {8,0,rr,A,A,0}, /* shf */ - {0,0,rr,A,A,0}, /* mov */ - {0,0,rr,S,A,0}, /* mov */ - {0,7,rr,S,S,0}, /* mov.w */ - {8,0,rr,S,S,0}, /* shf */ - {0,0,rr,S,S,0}, /* mov */ - {0,0,rr,A,S,0}, /* mov */ - {5,0,rr,A,A,0}, /* and */ - {6,0,rr,A,A,0}, /* or */ - {7,0,rr,A,A,0}, /* xor */ - {42,0,rr,A,A,0}, /* not */ - {5,0,rr,S,S,0}, /* and */ - {6,0,rr,S,S,0}, /* or */ - {7,0,rr,S,S,0}, /* xor */ - {42,0,rr,S,S,0}, /* not */ - {40,3,rr,S,S,0}, /* le.s */ - {40,4,rr,S,S,0}, /* le.d */ - {41,3,rr,S,S,0}, /* lt.s */ - {41,4,rr,S,S,0}, /* lt.d */ - {9,3,rr,S,S,0}, /* add.s */ - {9,4,rr,S,S,0}, /* add.d */ - {10,3,rr,S,S,0}, /* sub.s */ - {10,4,rr,S,S,0}, /* sub.d */ - {37,3,rr,S,S,0}, /* eq.s */ - {37,4,rr,S,S,0}, /* eq.d */ - {43,6,rr,A,A,0}, /* neg.h */ - {43,7,rr,A,A,0}, /* neg.w */ - {3,3,rr,S,S,0}, /* mul.s */ - {3,4,rr,S,S,0}, /* mul.d */ - {4,3,rr,S,S,0}, /* div.s */ - {4,4,rr,S,S,0}, /* div.d */ - {9,6,rr,A,A,0}, /* add.h */ - {9,7,rr,A,A,0}, /* add.w */ - {9,6,nr,A,0,0}, /* add.h */ - {9,7,nr,A,0,0}, /* add.w */ - {9,5,rr,S,S,0}, /* add.b */ - {9,6,rr,S,S,0}, /* add.h */ - {9,7,rr,S,S,0}, /* add.w */ - {9,8,rr,S,S,0}, /* add.l */ - {10,6,rr,A,A,0}, /* sub.h */ - {10,7,rr,A,A,0}, /* sub.w */ - {10,6,nr,A,0,0}, /* sub.h */ - {10,7,nr,A,0,0}, /* sub.w */ - {10,5,rr,S,S,0}, /* sub.b */ - {10,6,rr,S,S,0}, /* sub.h */ - {10,7,rr,S,S,0}, /* sub.w */ - {10,8,rr,S,S,0}, /* sub.l */ - {3,6,rr,A,A,0}, /* mul.h */ - {3,7,rr,A,A,0}, /* mul.w */ - {3,6,nr,A,0,0}, /* mul.h */ - {3,7,nr,A,0,0}, /* mul.w */ - {3,5,rr,S,S,0}, /* mul.b */ - {3,6,rr,S,S,0}, /* mul.h */ - {3,7,rr,S,S,0}, /* mul.w */ - {3,8,rr,S,S,0}, /* mul.l */ - {4,6,rr,A,A,0}, /* div.h */ - {4,7,rr,A,A,0}, /* div.w */ - {4,6,nr,A,0,0}, /* div.h */ - {4,7,nr,A,0,0}, /* div.w */ - {4,5,rr,S,S,0}, /* div.b */ - {4,6,rr,S,S,0}, /* div.h */ - {4,7,rr,S,S,0}, /* div.w */ - {4,8,rr,S,S,0}, /* div.l */ -}; - -const struct formstr format3[] = { - {32,3,rr,V,V,0}, /* cvtd.s */ - {31,4,rr,V,V,0}, /* cvts.d */ - {33,4,rr,V,V,0}, /* cvtl.d */ - {32,8,rr,V,V,0}, /* cvtd.l */ - {0,0,rrl,S,S,VM}, /* mov */ - {0,0,rlr,S,VM,S}, /* mov */ - {0,0,0,0,0,0}, - {44,0,rr,S,S,0}, /* lop */ - {36,0,rr,V,V,0}, /* tzc */ - {44,0,rr,V,V,0}, /* lop */ - {0,0,0,0,0,0}, - {42,0,rr,V,V,0}, /* not */ - {8,0,rr,S,V,0}, /* shf */ - {35,1,rr,V,V,0}, /* plc.t */ - {45,2,rr,V,V,0}, /* cprs.f */ - {45,1,rr,V,V,0}, /* cprs.t */ - {37,3,rr,V,V,0}, /* eq.s */ - {37,4,rr,V,V,0}, /* eq.d */ - {43,3,rr,V,V,0}, /* neg.s */ - {43,4,rr,V,V,0}, /* neg.d */ - {37,3,rr,S,V,0}, /* eq.s */ - {37,4,rr,S,V,0}, /* eq.d */ - {43,3,rr,S,S,0}, /* neg.s */ - {43,4,rr,S,S,0}, /* neg.d */ - {40,3,rr,V,V,0}, /* le.s */ - {40,4,rr,V,V,0}, /* le.d */ - {41,3,rr,V,V,0}, /* lt.s */ - {41,4,rr,V,V,0}, /* lt.d */ - {40,3,rr,S,V,0}, /* le.s */ - {40,4,rr,S,V,0}, /* le.d */ - {41,3,rr,S,V,0}, /* lt.s */ - {41,4,rr,S,V,0}, /* lt.d */ - {37,5,rr,V,V,0}, /* eq.b */ - {37,6,rr,V,V,0}, /* eq.h */ - {37,7,rr,V,V,0}, /* eq.w */ - {37,8,rr,V,V,0}, /* eq.l */ - {37,5,rr,S,V,0}, /* eq.b */ - {37,6,rr,S,V,0}, /* eq.h */ - {37,7,rr,S,V,0}, /* eq.w */ - {37,8,rr,S,V,0}, /* eq.l */ - {40,5,rr,V,V,0}, /* le.b */ - {40,6,rr,V,V,0}, /* le.h */ - {40,7,rr,V,V,0}, /* le.w */ - {40,8,rr,V,V,0}, /* le.l */ - {40,5,rr,S,V,0}, /* le.b */ - {40,6,rr,S,V,0}, /* le.h */ - {40,7,rr,S,V,0}, /* le.w */ - {40,8,rr,S,V,0}, /* le.l */ - {41,5,rr,V,V,0}, /* lt.b */ - {41,6,rr,V,V,0}, /* lt.h */ - {41,7,rr,V,V,0}, /* lt.w */ - {41,8,rr,V,V,0}, /* lt.l */ - {41,5,rr,S,V,0}, /* lt.b */ - {41,6,rr,S,V,0}, /* lt.h */ - {41,7,rr,S,V,0}, /* lt.w */ - {41,8,rr,S,V,0}, /* lt.l */ - {43,5,rr,V,V,0}, /* neg.b */ - {43,6,rr,V,V,0}, /* neg.h */ - {43,7,rr,V,V,0}, /* neg.w */ - {43,8,rr,V,V,0}, /* neg.l */ - {43,5,rr,S,S,0}, /* neg.b */ - {43,6,rr,S,S,0}, /* neg.h */ - {43,7,rr,S,S,0}, /* neg.w */ - {43,8,rr,S,S,0}, /* neg.l */ -}; - -const struct formstr format4[] = { - {46,0,nops,0,0,0}, /* nop */ - {47,0,pcrel,0,0,0}, /* br */ - {48,2,pcrel,0,0,0}, /* bri.f */ - {48,1,pcrel,0,0,0}, /* bri.t */ - {49,2,pcrel,0,0,0}, /* bra.f */ - {49,1,pcrel,0,0,0}, /* bra.t */ - {50,2,pcrel,0,0,0}, /* brs.f */ - {50,1,pcrel,0,0,0}, /* brs.t */ -}; - -const struct formstr format5[] = { - {51,5,rr,V,V,0}, /* ldvi.b */ - {51,6,rr,V,V,0}, /* ldvi.h */ - {51,7,rr,V,V,0}, /* ldvi.w */ - {51,8,rr,V,V,0}, /* ldvi.l */ - {28,3,rr,V,V,0}, /* cvtw.s */ - {31,7,rr,V,V,0}, /* cvts.w */ - {28,8,rr,V,V,0}, /* cvtw.l */ - {33,7,rr,V,V,0}, /* cvtl.w */ - {52,5,rxr,V,V,0}, /* stvi.b */ - {52,6,rxr,V,V,0}, /* stvi.h */ - {52,7,rxr,V,V,0}, /* stvi.w */ - {52,8,rxr,V,V,0}, /* stvi.l */ - {52,5,rxr,S,V,0}, /* stvi.b */ - {52,6,rxr,S,V,0}, /* stvi.h */ - {52,7,rxr,S,V,0}, /* stvi.w */ - {52,8,rxr,S,V,0}, /* stvi.l */ -}; - -const struct formstr format6[] = { - {53,0,r,A,0,0}, /* ldsdr */ - {54,0,r,A,0,0}, /* ldkdr */ - {55,3,r,S,0,0}, /* ln.s */ - {55,4,r,S,0,0}, /* ln.d */ - {56,0,nops,0,0,0}, /* patu */ - {57,0,r,A,0,0}, /* pate */ - {58,0,nops,0,0,0}, /* pich */ - {59,0,nops,0,0,0}, /* plch */ - {0,0,lr,PSW,A,0}, /* mov */ - {0,0,rxl,A,PSW,0}, /* mov */ - {0,0,lr,PC,A,0}, /* mov */ - {60,0,r,S,0,0}, /* idle */ - {0,0,lr,ITR,S,0}, /* mov */ - {0,0,rxl,S,ITR,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,rxl,S,ITSR,0}, /* mov */ - {61,0,nops,0,0,0}, /* rtnq */ - {62,0,nops,0,0,0}, /* cfork */ - {63,0,nops,0,0,0}, /* rtn */ - {64,0,nops,0,0,0}, /* wfork */ - {65,0,nops,0,0,0}, /* join */ - {66,0,nops,0,0,0}, /* rtnc */ - {67,3,r,S,0,0}, /* exp.s */ - {67,4,r,S,0,0}, /* exp.d */ - {68,3,r,S,0,0}, /* sin.s */ - {68,4,r,S,0,0}, /* sin.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {69,3,r,S,0,0}, /* cos.s */ - {69,4,r,S,0,0}, /* cos.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {70,7,r,A,0,0}, /* psh.w */ - {0,0,0,0,0,0}, - {71,7,r,A,0,0}, /* pop.w */ - {0,0,0,0,0,0}, - {70,7,r,S,0,0}, /* psh.w */ - {70,8,r,S,0,0}, /* psh.l */ - {71,7,r,S,0,0}, /* pop.w */ - {71,8,r,S,0,0}, /* pop.l */ - {72,0,nops,0,0,0}, /* eni */ - {73,0,nops,0,0,0}, /* dsi */ - {74,0,nops,0,0,0}, /* bkpt */ - {75,0,nops,0,0,0}, /* msync */ - {76,0,r,S,0,0}, /* mski */ - {77,0,r,S,0,0}, /* xmti */ - {0,0,rxl,S,VV,0}, /* mov */ - {78,0,nops,0,0,0}, /* tstvv */ - {0,0,lr,VS,A,0}, /* mov */ - {0,0,rxl,A,VS,0}, /* mov */ - {0,0,lr,VL,A,0}, /* mov */ - {0,0,rxl,A,VL,0}, /* mov */ - {0,7,lr,VS,S,0}, /* mov.w */ - {0,7,rxl,S,VS,0}, /* mov.w */ - {0,7,lr,VL,S,0}, /* mov.w */ - {0,7,rxl,S,VL,0}, /* mov.w */ - {79,0,r,A,0,0}, /* diag */ - {80,0,nops,0,0,0}, /* pbkpt */ - {81,3,r,S,0,0}, /* sqrt.s */ - {81,4,r,S,0,0}, /* sqrt.d */ - {82,0,nops,0,0,0}, /* casr */ - {0,0,0,0,0,0}, - {83,3,r,S,0,0}, /* atan.s */ - {83,4,r,S,0,0}, /* atan.d */ -}; - -const struct formstr format7[] = { - {84,5,r,V,0,0}, /* sum.b */ - {84,6,r,V,0,0}, /* sum.h */ - {84,7,r,V,0,0}, /* sum.w */ - {84,8,r,V,0,0}, /* sum.l */ - {85,0,r,V,0,0}, /* all */ - {86,0,r,V,0,0}, /* any */ - {87,0,r,V,0,0}, /* parity */ - {0,0,0,0,0,0}, - {88,5,r,V,0,0}, /* max.b */ - {88,6,r,V,0,0}, /* max.h */ - {88,7,r,V,0,0}, /* max.w */ - {88,8,r,V,0,0}, /* max.l */ - {89,5,r,V,0,0}, /* min.b */ - {89,6,r,V,0,0}, /* min.h */ - {89,7,r,V,0,0}, /* min.w */ - {89,8,r,V,0,0}, /* min.l */ - {84,3,r,V,0,0}, /* sum.s */ - {84,4,r,V,0,0}, /* sum.d */ - {90,3,r,V,0,0}, /* prod.s */ - {90,4,r,V,0,0}, /* prod.d */ - {88,3,r,V,0,0}, /* max.s */ - {88,4,r,V,0,0}, /* max.d */ - {89,3,r,V,0,0}, /* min.s */ - {89,4,r,V,0,0}, /* min.d */ - {90,5,r,V,0,0}, /* prod.b */ - {90,6,r,V,0,0}, /* prod.h */ - {90,7,r,V,0,0}, /* prod.w */ - {90,8,r,V,0,0}, /* prod.l */ - {35,2,lr,VM,S,0}, /* plc.f */ - {35,1,lr,VM,S,0}, /* plc.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr formatx[] = { - {0,0,0,0,0,0}, -}; - -const struct formstr format1a[] = { - {91,0,imr,A,0,0}, /* halt */ - {92,0,a4,0,0,0}, /* sysc */ - {18,6,imr,A,0,0}, /* ld.h */ - {18,7,imr,A,0,0}, /* ld.w */ - {5,0,imr,A,0,0}, /* and */ - {6,0,imr,A,0,0}, /* or */ - {7,0,imr,A,0,0}, /* xor */ - {8,0,imr,A,0,0}, /* shf */ - {9,6,imr,A,0,0}, /* add.h */ - {9,7,imr,A,0,0}, /* add.w */ - {10,6,imr,A,0,0}, /* sub.h */ - {10,7,imr,A,0,0}, /* sub.w */ - {3,6,imr,A,0,0}, /* mul.h */ - {3,7,imr,A,0,0}, /* mul.w */ - {4,6,imr,A,0,0}, /* div.h */ - {4,7,imr,A,0,0}, /* div.w */ - {18,7,iml,VL,0,0}, /* ld.w */ - {18,7,iml,VS,0,0}, /* ld.w */ - {0,0,0,0,0,0}, - {8,7,imr,S,0,0}, /* shf.w */ - {93,0,a5,0,0,0}, /* trap */ - {0,0,0,0,0,0}, - {37,6,imr,A,0,0}, /* eq.h */ - {37,7,imr,A,0,0}, /* eq.w */ - {38,6,imr,A,0,0}, /* leu.h */ - {38,7,imr,A,0,0}, /* leu.w */ - {39,6,imr,A,0,0}, /* ltu.h */ - {39,7,imr,A,0,0}, /* ltu.w */ - {40,6,imr,A,0,0}, /* le.h */ - {40,7,imr,A,0,0}, /* le.w */ - {41,6,imr,A,0,0}, /* lt.h */ - {41,7,imr,A,0,0}, /* lt.w */ -}; - -const struct formstr format1b[] = { - {18,4,imr,S,0,0}, /* ld.d */ - {18,10,imr,S,0,0}, /* ld.u */ - {18,8,imr,S,0,0}, /* ld.l */ - {18,7,imr,S,0,0}, /* ld.w */ - {5,0,imr,S,0,0}, /* and */ - {6,0,imr,S,0,0}, /* or */ - {7,0,imr,S,0,0}, /* xor */ - {8,0,imr,S,0,0}, /* shf */ - {9,6,imr,S,0,0}, /* add.h */ - {9,7,imr,S,0,0}, /* add.w */ - {10,6,imr,S,0,0}, /* sub.h */ - {10,7,imr,S,0,0}, /* sub.w */ - {3,6,imr,S,0,0}, /* mul.h */ - {3,7,imr,S,0,0}, /* mul.w */ - {4,6,imr,S,0,0}, /* div.h */ - {4,7,imr,S,0,0}, /* div.w */ - {9,3,imr,S,0,0}, /* add.s */ - {10,3,imr,S,0,0}, /* sub.s */ - {3,3,imr,S,0,0}, /* mul.s */ - {4,3,imr,S,0,0}, /* div.s */ - {40,3,imr,S,0,0}, /* le.s */ - {41,3,imr,S,0,0}, /* lt.s */ - {37,6,imr,S,0,0}, /* eq.h */ - {37,7,imr,S,0,0}, /* eq.w */ - {38,6,imr,S,0,0}, /* leu.h */ - {38,7,imr,S,0,0}, /* leu.w */ - {39,6,imr,S,0,0}, /* ltu.h */ - {39,7,imr,S,0,0}, /* ltu.w */ - {40,6,imr,S,0,0}, /* le.h */ - {40,7,imr,S,0,0}, /* le.w */ - {41,6,imr,S,0,0}, /* lt.h */ - {41,7,imr,S,0,0}, /* lt.w */ -}; - -const struct formstr e0_format0[] = { - {10,3,rrr,S,V,V}, /* sub.s */ - {10,4,rrr,S,V,V}, /* sub.d */ - {4,3,rrr,S,V,V}, /* div.s */ - {4,4,rrr,S,V,V}, /* div.d */ - {10,11,rrr,S,V,V}, /* sub.s.f */ - {10,12,rrr,S,V,V}, /* sub.d.f */ - {4,11,rrr,S,V,V}, /* div.s.f */ - {4,12,rrr,S,V,V}, /* div.d.f */ - {3,11,rrr,V,V,V}, /* mul.s.f */ - {3,12,rrr,V,V,V}, /* mul.d.f */ - {4,11,rrr,V,V,V}, /* div.s.f */ - {4,12,rrr,V,V,V}, /* div.d.f */ - {3,11,rrr,V,S,V}, /* mul.s.f */ - {3,12,rrr,V,S,V}, /* mul.d.f */ - {4,11,rrr,V,S,V}, /* div.s.f */ - {4,12,rrr,V,S,V}, /* div.d.f */ - {5,2,rrr,V,V,V}, /* and.f */ - {6,2,rrr,V,V,V}, /* or.f */ - {7,2,rrr,V,V,V}, /* xor.f */ - {8,2,rrr,V,V,V}, /* shf.f */ - {5,2,rrr,V,S,V}, /* and.f */ - {6,2,rrr,V,S,V}, /* or.f */ - {7,2,rrr,V,S,V}, /* xor.f */ - {8,2,rrr,V,S,V}, /* shf.f */ - {9,11,rrr,V,V,V}, /* add.s.f */ - {9,12,rrr,V,V,V}, /* add.d.f */ - {10,11,rrr,V,V,V}, /* sub.s.f */ - {10,12,rrr,V,V,V}, /* sub.d.f */ - {9,11,rrr,V,S,V}, /* add.s.f */ - {9,12,rrr,V,S,V}, /* add.d.f */ - {10,11,rrr,V,S,V}, /* sub.s.f */ - {10,12,rrr,V,S,V}, /* sub.d.f */ - {9,13,rrr,V,V,V}, /* add.b.f */ - {9,14,rrr,V,V,V}, /* add.h.f */ - {9,15,rrr,V,V,V}, /* add.w.f */ - {9,16,rrr,V,V,V}, /* add.l.f */ - {9,13,rrr,V,S,V}, /* add.b.f */ - {9,14,rrr,V,S,V}, /* add.h.f */ - {9,15,rrr,V,S,V}, /* add.w.f */ - {9,16,rrr,V,S,V}, /* add.l.f */ - {10,13,rrr,V,V,V}, /* sub.b.f */ - {10,14,rrr,V,V,V}, /* sub.h.f */ - {10,15,rrr,V,V,V}, /* sub.w.f */ - {10,16,rrr,V,V,V}, /* sub.l.f */ - {10,13,rrr,V,S,V}, /* sub.b.f */ - {10,14,rrr,V,S,V}, /* sub.h.f */ - {10,15,rrr,V,S,V}, /* sub.w.f */ - {10,16,rrr,V,S,V}, /* sub.l.f */ - {3,13,rrr,V,V,V}, /* mul.b.f */ - {3,14,rrr,V,V,V}, /* mul.h.f */ - {3,15,rrr,V,V,V}, /* mul.w.f */ - {3,16,rrr,V,V,V}, /* mul.l.f */ - {3,13,rrr,V,S,V}, /* mul.b.f */ - {3,14,rrr,V,S,V}, /* mul.h.f */ - {3,15,rrr,V,S,V}, /* mul.w.f */ - {3,16,rrr,V,S,V}, /* mul.l.f */ - {4,13,rrr,V,V,V}, /* div.b.f */ - {4,14,rrr,V,V,V}, /* div.h.f */ - {4,15,rrr,V,V,V}, /* div.w.f */ - {4,16,rrr,V,V,V}, /* div.l.f */ - {4,13,rrr,V,S,V}, /* div.b.f */ - {4,14,rrr,V,S,V}, /* div.h.f */ - {4,15,rrr,V,S,V}, /* div.w.f */ - {4,16,rrr,V,S,V}, /* div.l.f */ -}; - -const struct formstr e0_format1[] = { - {0,0,0,0,0,0}, - {94,0,a3,0,0,0}, /* tst */ - {95,0,a3,0,0,0}, /* lck */ - {96,0,a3,0,0,0}, /* ulk */ - {17,0,a1r,S,0,0}, /* ldea */ - {97,0,a1r,A,0,0}, /* spawn */ - {98,0,a1r,A,0,0}, /* ldcmr */ - {99,0,a2r,A,0,0}, /* stcmr */ - {100,0,a1r,A,0,0}, /* popr */ - {101,0,a2r,A,0,0}, /* pshr */ - {102,7,a1r,A,0,0}, /* rcvr.w */ - {103,7,a2r,A,0,0}, /* matm.w */ - {104,7,a2r,A,0,0}, /* sndr.w */ - {104,8,a2r,S,0,0}, /* sndr.l */ - {102,8,a1r,S,0,0}, /* rcvr.l */ - {103,8,a2r,S,0,0}, /* matm.l */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {105,7,a2r,A,0,0}, /* putr.w */ - {105,8,a2r,S,0,0}, /* putr.l */ - {106,7,a1r,A,0,0}, /* getr.w */ - {106,8,a1r,S,0,0}, /* getr.l */ - {26,13,a2r,S,0,0}, /* ste.b.f */ - {26,14,a2r,S,0,0}, /* ste.h.f */ - {26,15,a2r,S,0,0}, /* ste.w.f */ - {26,16,a2r,S,0,0}, /* ste.l.f */ - {107,7,a2r,A,0,0}, /* matr.w */ - {108,7,a2r,A,0,0}, /* mat.w */ - {109,7,a1r,A,0,0}, /* get.w */ - {110,7,a1r,A,0,0}, /* rcv.w */ - {0,0,0,0,0,0}, - {111,7,a1r,A,0,0}, /* inc.w */ - {112,7,a2r,A,0,0}, /* put.w */ - {113,7,a2r,A,0,0}, /* snd.w */ - {107,8,a2r,S,0,0}, /* matr.l */ - {108,8,a2r,S,0,0}, /* mat.l */ - {109,8,a1r,S,0,0}, /* get.l */ - {110,8,a1r,S,0,0}, /* rcv.l */ - {0,0,0,0,0,0}, - {111,8,a1r,S,0,0}, /* inc.l */ - {112,8,a2r,S,0,0}, /* put.l */ - {113,8,a2r,S,0,0}, /* snd.l */ - {18,13,a1r,V,0,0}, /* ld.b.f */ - {18,14,a1r,V,0,0}, /* ld.h.f */ - {18,15,a1r,V,0,0}, /* ld.w.f */ - {18,16,a1r,V,0,0}, /* ld.l.f */ - {21,13,a2r,V,0,0}, /* st.b.f */ - {21,14,a2r,V,0,0}, /* st.h.f */ - {21,15,a2r,V,0,0}, /* st.w.f */ - {21,16,a2r,V,0,0}, /* st.l.f */ -}; - -const struct formstr e0_format2[] = { - {28,5,rr,V,V,0}, /* cvtw.b */ - {28,6,rr,V,V,0}, /* cvtw.h */ - {29,7,rr,V,V,0}, /* cvtb.w */ - {30,7,rr,V,V,0}, /* cvth.w */ - {28,13,rr,V,V,0}, /* cvtw.b.f */ - {28,14,rr,V,V,0}, /* cvtw.h.f */ - {29,15,rr,V,V,0}, /* cvtb.w.f */ - {30,15,rr,V,V,0}, /* cvth.w.f */ - {31,8,rr,V,V,0}, /* cvts.l */ - {32,7,rr,V,V,0}, /* cvtd.w */ - {33,3,rr,V,V,0}, /* cvtl.s */ - {28,4,rr,V,V,0}, /* cvtw.d */ - {31,16,rr,V,V,0}, /* cvts.l.f */ - {32,15,rr,V,V,0}, /* cvtd.w.f */ - {33,11,rr,V,V,0}, /* cvtl.s.f */ - {28,12,rr,V,V,0}, /* cvtw.d.f */ - {114,0,rr,S,S,0}, /* enal */ - {8,7,rr,S,S,0}, /* shf.w */ - {115,0,rr,S,S,0}, /* enag */ - {0,0,0,0,0,0}, - {28,4,rr,S,S,0}, /* cvtw.d */ - {32,7,rr,S,S,0}, /* cvtd.w */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,S,S,0}, /* frint.s */ - {116,4,rr,S,S,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,V,V,0}, /* frint.s */ - {116,4,rr,V,V,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,11,rr,V,V,0}, /* frint.s.f */ - {116,12,rr,V,V,0}, /* frint.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,3,rr,V,V,0}, /* sqrt.s */ - {81,4,rr,V,V,0}, /* sqrt.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,11,rr,V,V,0}, /* sqrt.s.f */ - {81,12,rr,V,V,0}, /* sqrt.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format3[] = { - {32,11,rr,V,V,0}, /* cvtd.s.f */ - {31,12,rr,V,V,0}, /* cvts.d.f */ - {33,12,rr,V,V,0}, /* cvtl.d.f */ - {32,16,rr,V,V,0}, /* cvtd.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,2,rr,V,V,0}, /* tzc.f */ - {44,2,rr,V,V,0}, /* lop.f */ - {117,2,rr,V,V,0}, /* xpnd.f */ - {42,2,rr,V,V,0}, /* not.f */ - {8,2,rr,S,V,0}, /* shf.f */ - {35,17,rr,V,V,0}, /* plc.t.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,11,rr,V,V,0}, /* eq.s.f */ - {37,12,rr,V,V,0}, /* eq.d.f */ - {43,11,rr,V,V,0}, /* neg.s.f */ - {43,12,rr,V,V,0}, /* neg.d.f */ - {37,11,rr,S,V,0}, /* eq.s.f */ - {37,12,rr,S,V,0}, /* eq.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,11,rr,V,V,0}, /* le.s.f */ - {40,12,rr,V,V,0}, /* le.d.f */ - {41,11,rr,V,V,0}, /* lt.s.f */ - {41,12,rr,V,V,0}, /* lt.d.f */ - {40,11,rr,S,V,0}, /* le.s.f */ - {40,12,rr,S,V,0}, /* le.d.f */ - {41,11,rr,S,V,0}, /* lt.s.f */ - {41,12,rr,S,V,0}, /* lt.d.f */ - {37,13,rr,V,V,0}, /* eq.b.f */ - {37,14,rr,V,V,0}, /* eq.h.f */ - {37,15,rr,V,V,0}, /* eq.w.f */ - {37,16,rr,V,V,0}, /* eq.l.f */ - {37,13,rr,S,V,0}, /* eq.b.f */ - {37,14,rr,S,V,0}, /* eq.h.f */ - {37,15,rr,S,V,0}, /* eq.w.f */ - {37,16,rr,S,V,0}, /* eq.l.f */ - {40,13,rr,V,V,0}, /* le.b.f */ - {40,14,rr,V,V,0}, /* le.h.f */ - {40,15,rr,V,V,0}, /* le.w.f */ - {40,16,rr,V,V,0}, /* le.l.f */ - {40,13,rr,S,V,0}, /* le.b.f */ - {40,14,rr,S,V,0}, /* le.h.f */ - {40,15,rr,S,V,0}, /* le.w.f */ - {40,16,rr,S,V,0}, /* le.l.f */ - {41,13,rr,V,V,0}, /* lt.b.f */ - {41,14,rr,V,V,0}, /* lt.h.f */ - {41,15,rr,V,V,0}, /* lt.w.f */ - {41,16,rr,V,V,0}, /* lt.l.f */ - {41,13,rr,S,V,0}, /* lt.b.f */ - {41,14,rr,S,V,0}, /* lt.h.f */ - {41,15,rr,S,V,0}, /* lt.w.f */ - {41,16,rr,S,V,0}, /* lt.l.f */ - {43,13,rr,V,V,0}, /* neg.b.f */ - {43,14,rr,V,V,0}, /* neg.h.f */ - {43,15,rr,V,V,0}, /* neg.w.f */ - {43,16,rr,V,V,0}, /* neg.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format5[] = { - {51,13,rr,V,V,0}, /* ldvi.b.f */ - {51,14,rr,V,V,0}, /* ldvi.h.f */ - {51,15,rr,V,V,0}, /* ldvi.w.f */ - {51,16,rr,V,V,0}, /* ldvi.l.f */ - {28,11,rr,V,V,0}, /* cvtw.s.f */ - {31,15,rr,V,V,0}, /* cvts.w.f */ - {28,16,rr,V,V,0}, /* cvtw.l.f */ - {33,15,rr,V,V,0}, /* cvtl.w.f */ - {52,13,rxr,V,V,0}, /* stvi.b.f */ - {52,14,rxr,V,V,0}, /* stvi.h.f */ - {52,15,rxr,V,V,0}, /* stvi.w.f */ - {52,16,rxr,V,V,0}, /* stvi.l.f */ - {52,13,rxr,S,V,0}, /* stvi.b.f */ - {52,14,rxr,S,V,0}, /* stvi.h.f */ - {52,15,rxr,S,V,0}, /* stvi.w.f */ - {52,16,rxr,S,V,0}, /* stvi.l.f */ -}; - -const struct formstr e0_format6[] = { - {0,0,rxl,S,CIR,0}, /* mov */ - {0,0,lr,CIR,S,0}, /* mov */ - {0,0,lr,TOC,S,0}, /* mov */ - {0,0,lr,CPUID,S,0}, /* mov */ - {0,0,rxl,S,TTR,0}, /* mov */ - {0,0,lr,TTR,S,0}, /* mov */ - {118,0,nops,0,0,0}, /* ctrsl */ - {119,0,nops,0,0,0}, /* ctrsg */ - {0,0,rxl,S,VMU,0}, /* mov */ - {0,0,lr,VMU,S,0}, /* mov */ - {0,0,rxl,S,VML,0}, /* mov */ - {0,0,lr,VML,S,0}, /* mov */ - {0,0,rxl,S,ICR,0}, /* mov */ - {0,0,lr,ICR,S,0}, /* mov */ - {0,0,rxl,S,TCPU,0}, /* mov */ - {0,0,lr,TCPU,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {120,0,nops,0,0,0}, /* stop */ - {0,0,0,0,0,0}, - {0,0,rxl,S,TID,0}, /* mov */ - {0,0,lr,TID,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format7[] = { - {84,13,r,V,0,0}, /* sum.b.f */ - {84,14,r,V,0,0}, /* sum.h.f */ - {84,15,r,V,0,0}, /* sum.w.f */ - {84,16,r,V,0,0}, /* sum.l.f */ - {85,2,r,V,0,0}, /* all.f */ - {86,2,r,V,0,0}, /* any.f */ - {87,2,r,V,0,0}, /* parity.f */ - {0,0,0,0,0,0}, - {88,13,r,V,0,0}, /* max.b.f */ - {88,14,r,V,0,0}, /* max.h.f */ - {88,15,r,V,0,0}, /* max.w.f */ - {88,16,r,V,0,0}, /* max.l.f */ - {89,13,r,V,0,0}, /* min.b.f */ - {89,14,r,V,0,0}, /* min.h.f */ - {89,15,r,V,0,0}, /* min.w.f */ - {89,16,r,V,0,0}, /* min.l.f */ - {84,11,r,V,0,0}, /* sum.s.f */ - {84,12,r,V,0,0}, /* sum.d.f */ - {90,11,r,V,0,0}, /* prod.s.f */ - {90,12,r,V,0,0}, /* prod.d.f */ - {88,11,r,V,0,0}, /* max.s.f */ - {88,12,r,V,0,0}, /* max.d.f */ - {89,11,r,V,0,0}, /* min.s.f */ - {89,12,r,V,0,0}, /* min.d.f */ - {90,13,r,V,0,0}, /* prod.b.f */ - {90,14,r,V,0,0}, /* prod.h.f */ - {90,15,r,V,0,0}, /* prod.w.f */ - {90,16,r,V,0,0}, /* prod.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format0[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {10,18,rrr,S,V,V}, /* sub.s.t */ - {10,19,rrr,S,V,V}, /* sub.d.t */ - {4,18,rrr,S,V,V}, /* div.s.t */ - {4,19,rrr,S,V,V}, /* div.d.t */ - {3,18,rrr,V,V,V}, /* mul.s.t */ - {3,19,rrr,V,V,V}, /* mul.d.t */ - {4,18,rrr,V,V,V}, /* div.s.t */ - {4,19,rrr,V,V,V}, /* div.d.t */ - {3,18,rrr,V,S,V}, /* mul.s.t */ - {3,19,rrr,V,S,V}, /* mul.d.t */ - {4,18,rrr,V,S,V}, /* div.s.t */ - {4,19,rrr,V,S,V}, /* div.d.t */ - {5,1,rrr,V,V,V}, /* and.t */ - {6,1,rrr,V,V,V}, /* or.t */ - {7,1,rrr,V,V,V}, /* xor.t */ - {8,1,rrr,V,V,V}, /* shf.t */ - {5,1,rrr,V,S,V}, /* and.t */ - {6,1,rrr,V,S,V}, /* or.t */ - {7,1,rrr,V,S,V}, /* xor.t */ - {8,1,rrr,V,S,V}, /* shf.t */ - {9,18,rrr,V,V,V}, /* add.s.t */ - {9,19,rrr,V,V,V}, /* add.d.t */ - {10,18,rrr,V,V,V}, /* sub.s.t */ - {10,19,rrr,V,V,V}, /* sub.d.t */ - {9,18,rrr,V,S,V}, /* add.s.t */ - {9,19,rrr,V,S,V}, /* add.d.t */ - {10,18,rrr,V,S,V}, /* sub.s.t */ - {10,19,rrr,V,S,V}, /* sub.d.t */ - {9,20,rrr,V,V,V}, /* add.b.t */ - {9,21,rrr,V,V,V}, /* add.h.t */ - {9,22,rrr,V,V,V}, /* add.w.t */ - {9,23,rrr,V,V,V}, /* add.l.t */ - {9,20,rrr,V,S,V}, /* add.b.t */ - {9,21,rrr,V,S,V}, /* add.h.t */ - {9,22,rrr,V,S,V}, /* add.w.t */ - {9,23,rrr,V,S,V}, /* add.l.t */ - {10,20,rrr,V,V,V}, /* sub.b.t */ - {10,21,rrr,V,V,V}, /* sub.h.t */ - {10,22,rrr,V,V,V}, /* sub.w.t */ - {10,23,rrr,V,V,V}, /* sub.l.t */ - {10,20,rrr,V,S,V}, /* sub.b.t */ - {10,21,rrr,V,S,V}, /* sub.h.t */ - {10,22,rrr,V,S,V}, /* sub.w.t */ - {10,23,rrr,V,S,V}, /* sub.l.t */ - {3,20,rrr,V,V,V}, /* mul.b.t */ - {3,21,rrr,V,V,V}, /* mul.h.t */ - {3,22,rrr,V,V,V}, /* mul.w.t */ - {3,23,rrr,V,V,V}, /* mul.l.t */ - {3,20,rrr,V,S,V}, /* mul.b.t */ - {3,21,rrr,V,S,V}, /* mul.h.t */ - {3,22,rrr,V,S,V}, /* mul.w.t */ - {3,23,rrr,V,S,V}, /* mul.l.t */ - {4,20,rrr,V,V,V}, /* div.b.t */ - {4,21,rrr,V,V,V}, /* div.h.t */ - {4,22,rrr,V,V,V}, /* div.w.t */ - {4,23,rrr,V,V,V}, /* div.l.t */ - {4,20,rrr,V,S,V}, /* div.b.t */ - {4,21,rrr,V,S,V}, /* div.h.t */ - {4,22,rrr,V,S,V}, /* div.w.t */ - {4,23,rrr,V,S,V}, /* div.l.t */ -}; - -const struct formstr e1_format1[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {26,20,a2r,S,0,0}, /* ste.b.t */ - {26,21,a2r,S,0,0}, /* ste.h.t */ - {26,22,a2r,S,0,0}, /* ste.w.t */ - {26,23,a2r,S,0,0}, /* ste.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {18,20,a1r,V,0,0}, /* ld.b.t */ - {18,21,a1r,V,0,0}, /* ld.h.t */ - {18,22,a1r,V,0,0}, /* ld.w.t */ - {18,23,a1r,V,0,0}, /* ld.l.t */ - {21,20,a2r,V,0,0}, /* st.b.t */ - {21,21,a2r,V,0,0}, /* st.h.t */ - {21,22,a2r,V,0,0}, /* st.w.t */ - {21,23,a2r,V,0,0}, /* st.l.t */ -}; - -const struct formstr e1_format2[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {28,20,rr,V,V,0}, /* cvtw.b.t */ - {28,21,rr,V,V,0}, /* cvtw.h.t */ - {29,22,rr,V,V,0}, /* cvtb.w.t */ - {30,22,rr,V,V,0}, /* cvth.w.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {31,23,rr,V,V,0}, /* cvts.l.t */ - {32,22,rr,V,V,0}, /* cvtd.w.t */ - {33,18,rr,V,V,0}, /* cvtl.s.t */ - {28,19,rr,V,V,0}, /* cvtw.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,18,rr,V,V,0}, /* frint.s.t */ - {116,19,rr,V,V,0}, /* frint.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,18,rr,V,V,0}, /* sqrt.s.t */ - {81,19,rr,V,V,0}, /* sqrt.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format3[] = { - {32,18,rr,V,V,0}, /* cvtd.s.t */ - {31,19,rr,V,V,0}, /* cvts.d.t */ - {33,19,rr,V,V,0}, /* cvtl.d.t */ - {32,23,rr,V,V,0}, /* cvtd.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,1,rr,V,V,0}, /* tzc.t */ - {44,1,rr,V,V,0}, /* lop.t */ - {117,1,rr,V,V,0}, /* xpnd.t */ - {42,1,rr,V,V,0}, /* not.t */ - {8,1,rr,S,V,0}, /* shf.t */ - {35,24,rr,V,V,0}, /* plc.t.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,18,rr,V,V,0}, /* eq.s.t */ - {37,19,rr,V,V,0}, /* eq.d.t */ - {43,18,rr,V,V,0}, /* neg.s.t */ - {43,19,rr,V,V,0}, /* neg.d.t */ - {37,18,rr,S,V,0}, /* eq.s.t */ - {37,19,rr,S,V,0}, /* eq.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,18,rr,V,V,0}, /* le.s.t */ - {40,19,rr,V,V,0}, /* le.d.t */ - {41,18,rr,V,V,0}, /* lt.s.t */ - {41,19,rr,V,V,0}, /* lt.d.t */ - {40,18,rr,S,V,0}, /* le.s.t */ - {40,19,rr,S,V,0}, /* le.d.t */ - {41,18,rr,S,V,0}, /* lt.s.t */ - {41,19,rr,S,V,0}, /* lt.d.t */ - {37,20,rr,V,V,0}, /* eq.b.t */ - {37,21,rr,V,V,0}, /* eq.h.t */ - {37,22,rr,V,V,0}, /* eq.w.t */ - {37,23,rr,V,V,0}, /* eq.l.t */ - {37,20,rr,S,V,0}, /* eq.b.t */ - {37,21,rr,S,V,0}, /* eq.h.t */ - {37,22,rr,S,V,0}, /* eq.w.t */ - {37,23,rr,S,V,0}, /* eq.l.t */ - {40,20,rr,V,V,0}, /* le.b.t */ - {40,21,rr,V,V,0}, /* le.h.t */ - {40,22,rr,V,V,0}, /* le.w.t */ - {40,23,rr,V,V,0}, /* le.l.t */ - {40,20,rr,S,V,0}, /* le.b.t */ - {40,21,rr,S,V,0}, /* le.h.t */ - {40,22,rr,S,V,0}, /* le.w.t */ - {40,23,rr,S,V,0}, /* le.l.t */ - {41,20,rr,V,V,0}, /* lt.b.t */ - {41,21,rr,V,V,0}, /* lt.h.t */ - {41,22,rr,V,V,0}, /* lt.w.t */ - {41,23,rr,V,V,0}, /* lt.l.t */ - {41,20,rr,S,V,0}, /* lt.b.t */ - {41,21,rr,S,V,0}, /* lt.h.t */ - {41,22,rr,S,V,0}, /* lt.w.t */ - {41,23,rr,S,V,0}, /* lt.l.t */ - {43,20,rr,V,V,0}, /* neg.b.t */ - {43,21,rr,V,V,0}, /* neg.h.t */ - {43,22,rr,V,V,0}, /* neg.w.t */ - {43,23,rr,V,V,0}, /* neg.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format5[] = { - {51,20,rr,V,V,0}, /* ldvi.b.t */ - {51,21,rr,V,V,0}, /* ldvi.h.t */ - {51,22,rr,V,V,0}, /* ldvi.w.t */ - {51,23,rr,V,V,0}, /* ldvi.l.t */ - {28,18,rr,V,V,0}, /* cvtw.s.t */ - {31,22,rr,V,V,0}, /* cvts.w.t */ - {28,23,rr,V,V,0}, /* cvtw.l.t */ - {33,22,rr,V,V,0}, /* cvtl.w.t */ - {52,20,rxr,V,V,0}, /* stvi.b.t */ - {52,21,rxr,V,V,0}, /* stvi.h.t */ - {52,22,rxr,V,V,0}, /* stvi.w.t */ - {52,23,rxr,V,V,0}, /* stvi.l.t */ - {52,20,rxr,S,V,0}, /* stvi.b.t */ - {52,21,rxr,S,V,0}, /* stvi.h.t */ - {52,22,rxr,S,V,0}, /* stvi.w.t */ - {52,23,rxr,S,V,0}, /* stvi.l.t */ -}; - -const struct formstr e1_format6[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format7[] = { - {84,20,r,V,0,0}, /* sum.b.t */ - {84,21,r,V,0,0}, /* sum.h.t */ - {84,22,r,V,0,0}, /* sum.w.t */ - {84,23,r,V,0,0}, /* sum.l.t */ - {85,1,r,V,0,0}, /* all.t */ - {86,1,r,V,0,0}, /* any.t */ - {87,1,r,V,0,0}, /* parity.t */ - {0,0,0,0,0,0}, - {88,20,r,V,0,0}, /* max.b.t */ - {88,21,r,V,0,0}, /* max.h.t */ - {88,22,r,V,0,0}, /* max.w.t */ - {88,23,r,V,0,0}, /* max.l.t */ - {89,20,r,V,0,0}, /* min.b.t */ - {89,21,r,V,0,0}, /* min.h.t */ - {89,22,r,V,0,0}, /* min.w.t */ - {89,23,r,V,0,0}, /* min.l.t */ - {84,18,r,V,0,0}, /* sum.s.t */ - {84,19,r,V,0,0}, /* sum.d.t */ - {90,18,r,V,0,0}, /* prod.s.t */ - {90,19,r,V,0,0}, /* prod.d.t */ - {88,18,r,V,0,0}, /* max.s.t */ - {88,19,r,V,0,0}, /* max.d.t */ - {89,18,r,V,0,0}, /* min.s.t */ - {89,19,r,V,0,0}, /* min.d.t */ - {90,20,r,V,0,0}, /* prod.b.t */ - {90,21,r,V,0,0}, /* prod.h.t */ - {90,22,r,V,0,0}, /* prod.w.t */ - {90,23,r,V,0,0}, /* prod.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -char *lop[] = { - "mov", /* 0 */ - "merg", /* 1 */ - "mask", /* 2 */ - "mul", /* 3 */ - "div", /* 4 */ - "and", /* 5 */ - "or", /* 6 */ - "xor", /* 7 */ - "shf", /* 8 */ - "add", /* 9 */ - "sub", /* 10 */ - "exit", /* 11 */ - "jmp", /* 12 */ - "jmpi", /* 13 */ - "jmpa", /* 14 */ - "jmps", /* 15 */ - "tac", /* 16 */ - "ldea", /* 17 */ - "ld", /* 18 */ - "tas", /* 19 */ - "pshea", /* 20 */ - "st", /* 21 */ - "call", /* 22 */ - "calls", /* 23 */ - "callq", /* 24 */ - "pfork", /* 25 */ - "ste", /* 26 */ - "incr", /* 27 */ - "cvtw", /* 28 */ - "cvtb", /* 29 */ - "cvth", /* 30 */ - "cvts", /* 31 */ - "cvtd", /* 32 */ - "cvtl", /* 33 */ - "ldpa", /* 34 */ - "plc", /* 35 */ - "tzc", /* 36 */ - "eq", /* 37 */ - "leu", /* 38 */ - "ltu", /* 39 */ - "le", /* 40 */ - "lt", /* 41 */ - "not", /* 42 */ - "neg", /* 43 */ - "lop", /* 44 */ - "cprs", /* 45 */ - "nop", /* 46 */ - "br", /* 47 */ - "bri", /* 48 */ - "bra", /* 49 */ - "brs", /* 50 */ - "ldvi", /* 51 */ - "stvi", /* 52 */ - "ldsdr", /* 53 */ - "ldkdr", /* 54 */ - "ln", /* 55 */ - "patu", /* 56 */ - "pate", /* 57 */ - "pich", /* 58 */ - "plch", /* 59 */ - "idle", /* 60 */ - "rtnq", /* 61 */ - "cfork", /* 62 */ - "rtn", /* 63 */ - "wfork", /* 64 */ - "join", /* 65 */ - "rtnc", /* 66 */ - "exp", /* 67 */ - "sin", /* 68 */ - "cos", /* 69 */ - "psh", /* 70 */ - "pop", /* 71 */ - "eni", /* 72 */ - "dsi", /* 73 */ - "bkpt", /* 74 */ - "msync", /* 75 */ - "mski", /* 76 */ - "xmti", /* 77 */ - "tstvv", /* 78 */ - "diag", /* 79 */ - "pbkpt", /* 80 */ - "sqrt", /* 81 */ - "casr", /* 82 */ - "atan", /* 83 */ - "sum", /* 84 */ - "all", /* 85 */ - "any", /* 86 */ - "parity", /* 87 */ - "max", /* 88 */ - "min", /* 89 */ - "prod", /* 90 */ - "halt", /* 91 */ - "sysc", /* 92 */ - "trap", /* 93 */ - "tst", /* 94 */ - "lck", /* 95 */ - "ulk", /* 96 */ - "spawn", /* 97 */ - "ldcmr", /* 98 */ - "stcmr", /* 99 */ - "popr", /* 100 */ - "pshr", /* 101 */ - "rcvr", /* 102 */ - "matm", /* 103 */ - "sndr", /* 104 */ - "putr", /* 105 */ - "getr", /* 106 */ - "matr", /* 107 */ - "mat", /* 108 */ - "get", /* 109 */ - "rcv", /* 110 */ - "inc", /* 111 */ - "put", /* 112 */ - "snd", /* 113 */ - "enal", /* 114 */ - "enag", /* 115 */ - "frint", /* 116 */ - "xpnd", /* 117 */ - "ctrsl", /* 118 */ - "ctrsg", /* 119 */ - "stop", /* 120 */ -}; - -char *rop[] = { - "", /* 0 */ - ".t", /* 1 */ - ".f", /* 2 */ - ".s", /* 3 */ - ".d", /* 4 */ - ".b", /* 5 */ - ".h", /* 6 */ - ".w", /* 7 */ - ".l", /* 8 */ - ".x", /* 9 */ - ".u", /* 10 */ - ".s.f", /* 11 */ - ".d.f", /* 12 */ - ".b.f", /* 13 */ - ".h.f", /* 14 */ - ".w.f", /* 15 */ - ".l.f", /* 16 */ - ".t.f", /* 17 */ - ".s.t", /* 18 */ - ".d.t", /* 19 */ - ".b.t", /* 20 */ - ".h.t", /* 21 */ - ".w.t", /* 22 */ - ".l.t", /* 23 */ - ".t.t", /* 24 */ -}; diff --git a/include/opcode/cris.h b/include/opcode/cris.h deleted file mode 100644 index 81590baf9..000000000 --- a/include/opcode/cris.h +++ /dev/null @@ -1,359 +0,0 @@ -/* cris.h -- Header file for CRIS opcode and register tables. - Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc. - Contributed by Axis Communications AB, Lund, Sweden. - Originally written for GAS 1.38.1 by Mikael Asker. - Updated, BFDized and GNUified by Hans-Peter Nilsson. - -This file is part of GAS, GDB and the GNU binutils. - -GAS, GDB, and GNU binutils is free software; you can redistribute it -and/or modify it under the terms of the GNU General Public License as -published by the Free Software Foundation; either version 2, or (at your -option) any later version. - -GAS, GDB, and GNU binutils are distributed in the hope that they will be -useful, but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef __CRIS_H_INCLUDED_ -#define __CRIS_H_INCLUDED_ - -#if !defined(__STDC__) && !defined(const) -#define const -#endif - - -/* Registers. */ -#define MAX_REG (15) -#define REG_SP (14) -#define REG_PC (15) - -/* CPU version control of disassembly and assembly of instructions. - May affect how the instruction is assembled, at least the size of - immediate operands. */ -enum cris_insn_version_usage -{ - /* Any version. */ - cris_ver_version_all=0, - - /* Indeterminate (intended for disassembly only, or obsolete). */ - cris_ver_warning, - - /* Only for v0..3 (Etrax 1..4). */ - cris_ver_v0_3, - - /* Only for v3 or higher (ETRAX 4 and beyond). */ - cris_ver_v3p, - - /* Only for v8 (Etrax 100). */ - cris_ver_v8, - - /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ - cris_ver_v8p, - - /* Only for v0..10. FIXME: Not sure what to do with this. */ - cris_ver_sim_v0_10, - - /* Only for v0..10. */ - cris_ver_v0_10, - - /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */ - cris_ver_v3_10, - - /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */ - cris_ver_v8_10, - - /* Only for v10 (ETRAX 100 LX) and same series. */ - cris_ver_v10, - - /* Only for v10 (ETRAX 100 LX) and same series. */ - cris_ver_v10p, - - /* Only for v32 or higher (codename GUINNESS). - Of course some or all these of may change to cris_ver_v32p if/when - there's a new revision. */ - cris_ver_v32p -}; - - -/* Special registers. */ -struct cris_spec_reg -{ - const char *const name; - unsigned int number; - - /* The size of the register. */ - unsigned int reg_size; - - /* What CPU version the special register of that name is implemented - in. If cris_ver_warning, emit an unimplemented-warning. */ - enum cris_insn_version_usage applicable_version; - - /* There might be a specific warning for using a special register - here. */ - const char *const warning; -}; -extern const struct cris_spec_reg cris_spec_regs[]; - - -/* Support registers (kind of special too, but not named as such). */ -struct cris_support_reg -{ - const char *const name; - unsigned int number; -}; -extern const struct cris_support_reg cris_support_regs[]; - -struct cris_cond15 -{ - /* The name of the condition. */ - const char *const name; - - /* What CPU version this condition name applies to. */ - enum cris_insn_version_usage applicable_version; -}; -extern const struct cris_cond15 cris_conds15[]; - -/* Opcode-dependent constants. */ -#define AUTOINCR_BIT (0x04) - -/* Prefixes. */ -#define BDAP_QUICK_OPCODE (0x0100) -#define BDAP_QUICK_Z_BITS (0x0e00) - -#define BIAP_OPCODE (0x0540) -#define BIAP_Z_BITS (0x0a80) - -#define DIP_OPCODE (0x0970) -#define DIP_Z_BITS (0xf280) - -#define BDAP_INDIR_LOW (0x40) -#define BDAP_INDIR_LOW_Z (0x80) -#define BDAP_INDIR_HIGH (0x09) -#define BDAP_INDIR_HIGH_Z (0x02) - -#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) -#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) -#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC) -#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) - -/* No prefix must have this code for its "match" bits in the - opcode-table. "BCC .+2" will do nicely. */ -#define NO_CRIS_PREFIX 0 - -/* Definitions for condition codes. */ -#define CC_CC 0x0 -#define CC_HS 0x0 -#define CC_CS 0x1 -#define CC_LO 0x1 -#define CC_NE 0x2 -#define CC_EQ 0x3 -#define CC_VC 0x4 -#define CC_VS 0x5 -#define CC_PL 0x6 -#define CC_MI 0x7 -#define CC_LS 0x8 -#define CC_HI 0x9 -#define CC_GE 0xA -#define CC_LT 0xB -#define CC_GT 0xC -#define CC_LE 0xD -#define CC_A 0xE -#define CC_EXT 0xF - -/* A table of strings "cc", "cs"... indexed with condition code - values as above. */ -extern const char *const cris_cc_strings[]; - -/* Bcc quick. */ -#define BRANCH_QUICK_LOW (0) -#define BRANCH_QUICK_HIGH (0) -#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) -#define BRANCH_QUICK_Z_BITS (0x0F00) - -/* BA quick. */ -#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) -#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) - -/* Bcc [PC+]. */ -#define BRANCH_PC_LOW (0xFF) -#define BRANCH_INCR_HIGH (0x0D) -#define BA_PC_INCR_OPCODE \ - ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) - -/* Jump. */ -/* Note that old versions generated special register 8 (in high bits) - and not-that-old versions recognized it as a jump-instruction. - That opcode now belongs to JUMPU. */ -#define JUMP_INDIR_OPCODE (0x0930) -#define JUMP_INDIR_Z_BITS (0xf2c0) -#define JUMP_PC_INCR_OPCODE \ - (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) -#define ADD_PC_INCR_OPCODE \ - (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC) - -#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) - -/* BA DWORD (V32). */ -#define BA_DWORD_OPCODE (0x0EBF) - -/* Nop. */ -#define NOP_OPCODE (0x050F) -#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) - -#define NOP_OPCODE_V32 (0x05B0) -#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) - -/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect - registers or flags. Unfortunately shuts off interrupts for one cycle - for < v32, but there doesn't seem to be any alternative without that - effect. */ -#define NOP_OPCODE_COMMON (0x630) -#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) - -/* LAPC.D */ -#define LAPC_DWORD_OPCODE (0x0D7F) -#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) - -/* Structure of an opcode table entry. */ -enum cris_imm_oprnd_size_type -{ - /* No size is applicable. */ - SIZE_NONE, - - /* Always 32 bits. */ - SIZE_FIX_32, - - /* Indicated by size of special register. */ - SIZE_SPEC_REG, - - /* Indicated by size field, signed. */ - SIZE_FIELD_SIGNED, - - /* Indicated by size field, unsigned. */ - SIZE_FIELD_UNSIGNED, - - /* Indicated by size field, no sign implied. */ - SIZE_FIELD -}; - -/* For GDB. FIXME: Is this the best way to handle opcode - interpretation? */ -enum cris_op_type -{ - cris_not_implemented_op = 0, - cris_abs_op, - cris_addi_op, - cris_asr_op, - cris_asrq_op, - cris_ax_ei_setf_op, - cris_bdap_prefix, - cris_biap_prefix, - cris_break_op, - cris_btst_nop_op, - cris_clearf_di_op, - cris_dip_prefix, - cris_dstep_logshift_mstep_neg_not_op, - cris_eight_bit_offset_branch_op, - cris_move_mem_to_reg_movem_op, - cris_move_reg_to_mem_movem_op, - cris_move_to_preg_op, - cris_muls_op, - cris_mulu_op, - cris_none_reg_mode_add_sub_cmp_and_or_move_op, - cris_none_reg_mode_clear_test_op, - cris_none_reg_mode_jump_op, - cris_none_reg_mode_move_from_preg_op, - cris_quick_mode_add_sub_op, - cris_quick_mode_and_cmp_move_or_op, - cris_quick_mode_bdap_prefix, - cris_reg_mode_add_sub_cmp_and_or_move_op, - cris_reg_mode_clear_op, - cris_reg_mode_jump_op, - cris_reg_mode_move_from_preg_op, - cris_reg_mode_test_op, - cris_scc_op, - cris_sixteen_bit_offset_branch_op, - cris_three_operand_add_sub_cmp_and_or_op, - cris_three_operand_bound_op, - cris_two_operand_bound_op, - cris_xor_op -}; - -struct cris_opcode -{ - /* The name of the insn. */ - const char *name; - - /* Bits that must be 1 for a match. */ - unsigned int match; - - /* Bits that must be 0 for a match. */ - unsigned int lose; - - /* See the table in "opcodes/cris-opc.c". */ - const char *args; - - /* Nonzero if this is a delayed branch instruction. */ - char delayed; - - /* Size of immediate operands. */ - enum cris_imm_oprnd_size_type imm_oprnd_size; - - /* Indicates which version this insn was first implemented in. */ - enum cris_insn_version_usage applicable_version; - - /* What kind of operation this is. */ - enum cris_op_type op; -}; -extern const struct cris_opcode cris_opcodes[]; - - -/* These macros are for the target-specific flags in disassemble_info - used at disassembly. */ - -/* This insn accesses memory. This flag is more trustworthy than - checking insn_type for "dis_dref" which does not work for - e.g. "JSR [foo]". */ -#define CRIS_DIS_FLAG_MEMREF (1 << 0) - -/* The "target" field holds a register number. */ -#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) - -/* The "target2" field holds a register number; add it to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) - -/* Yet another add-on: the register in "target2" must be multiplied - by 2 before adding to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) - -/* Yet another add-on: the register in "target2" must be multiplied - by 4 (mutually exclusive with .._MULT2). */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) - -/* The register in "target2" is an indirect memory reference (of the - register there), add to "target". Assumed size is dword (mutually - exclusive with .._MULT[24]). */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) - -/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; - sign-extended before adding to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) - -/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; - sign-extended before adding to "target". */ -#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) - -#endif /* __CRIS_H_INCLUDED_ */ - -/* - * Local variables: - * eval: (c-set-style "gnu") - * indent-tabs-mode: t - * End: - */ diff --git a/include/opcode/crx.h b/include/opcode/crx.h deleted file mode 100644 index 66def6b39..000000000 --- a/include/opcode/crx.h +++ /dev/null @@ -1,418 +0,0 @@ -/* crx.h -- Header file for CRX opcode and register tables. - Copyright 2004 Free Software Foundation, Inc. - Contributed by Tomer Levi, NSC, Israel. - Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. - Updates, BFDizing, GNUifying and ELF support by Tomer Levi. - - This file is part of GAS, GDB and the GNU binutils. - - GAS, GDB, and GNU binutils is free software; you can redistribute it - and/or modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GAS, GDB, and GNU binutils are distributed in the hope that they will be - useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _CRX_H_ -#define _CRX_H_ - -/* CRX core/debug Registers : - The enums are used as indices to CRX registers table (crx_regtab). - Therefore, order MUST be preserved. */ - -typedef enum - { - /* 32-bit general purpose registers. */ - r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, - r10, r11, r12, r13, r14, r15, ra, sp, - /* 32-bit user registers. */ - u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, - u10, u11, u12, u13, u14, u15, ura, usp, - /* hi and lo registers. */ - hi, lo, - /* hi and lo user registers. */ - uhi, ulo, - /* Processor Status Register. */ - psr, - /* Interrupt Base Register. */ - intbase, - /* Interrupt Stack Pointer Register. */ - isp, - /* Configuration Register. */ - cfg, - /* Coprocessor Configuration Register. */ - cpcfg, - /* Coprocessor Enable Register. */ - cen, - /* Not a register. */ - nullregister, - MAX_REG - } -reg; - -/* CRX Coprocessor registers and special registers : - The enums are used as indices to CRX coprocessor registers table - (crx_copregtab). Therefore, order MUST be preserved. */ - -typedef enum - { - /* Coprocessor registers. */ - c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, - c9, c10, c11, c12, c13, c14, c15, - /* Coprocessor special registers. */ - cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, - cs9, cs10, cs11, cs12, cs13, cs14, cs15, - /* Not a Coprocessor register. */ - nullcopregister, - MAX_COPREG - } -copreg; - -/* CRX Register types. */ - -typedef enum - { - CRX_R_REGTYPE, /* r<N> */ - CRX_U_REGTYPE, /* u<N> */ - CRX_C_REGTYPE, /* c<N> */ - CRX_CS_REGTYPE, /* cs<N> */ - CRX_CFG_REGTYPE /* configuration register */ - } -reg_type; - -/* CRX argument types : - The argument types correspond to instructions operands - - Argument types : - r - register - c - constant - i - immediate - idxr - index register - rbase - register base - s - star ('*') - copr - coprocessor register - copsr - coprocessor special register. */ - -typedef enum - { - arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, - arg_idxr, arg_rbase, arg_copr, arg_copsr, - /* Not an argument. */ - nullargs - } -argtype; - -/* CRX operand types : - The operand types correspond to instructions operands. */ - -typedef enum - { - dummy, - /* 4-bit encoded constant. */ - cst4, - /* N-bit immediate. */ - i16, i32, - /* N-bit unsigned immediate. */ - ui3, ui4, ui5, ui16, - /* N-bit signed displacement. */ - disps9, disps17, disps25, disps32, - /* N-bit unsigned displacement. */ - dispu5, - /* N-bit escaped displacement. */ - dispe9, - /* N-bit absolute address. */ - abs16, abs32, - /* Register relative. */ - rbase, rbase_dispu4, - rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, - /* Register index. */ - rindex_disps6, rindex_disps22, - /* 4-bit genaral-purpose register specifier. */ - regr, - /* 8-bit register address space. */ - regr8, - /* coprocessor register. */ - copregr, - /* coprocessor special register. */ - copsregr, - /* Not an operand. */ - nulloperand, - /* Maximum supported operand. */ - MAX_OPRD - } -operand_type; - -/* CRX instruction types. */ - -#define NO_TYPE_INS 0 -#define ARITH_INS 1 -#define LD_STOR_INS 2 -#define BRANCH_INS 3 -#define ARITH_BYTE_INS 4 -#define CMPBR_INS 5 -#define SHIFT_INS 6 -#define BRANCH_NEQ_INS 7 -#define LD_STOR_INS_INC 8 -#define STOR_IMM_INS 9 -#define CSTBIT_INS 10 -#define COP_BRANCH_INS 11 -#define COP_REG_INS 12 -#define COPS_REG_INS 13 -#define DCR_BRANCH_INS 14 - -/* Maximum value supported for instruction types. */ -#define CRX_INS_MAX (1 << 4) -/* Mask to record an instruction type. */ -#define CRX_INS_MASK (CRX_INS_MAX - 1) -/* Return instruction type, given instruction's attributes. */ -#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) - -/* Indicates whether this instruction has a register list as parameter. */ -#define REG_LIST CRX_INS_MAX -/* The operands in binary and assembly are placed in reverse order. - load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ -#define REVERSE_MATCH (1 << 5) - -/* Kind of displacement map used DISPU[BWD]4. */ -#define DISPUB4 (1 << 6) -#define DISPUW4 (1 << 7) -#define DISPUD4 (1 << 8) -#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) - -/* Printing formats, where the instruction prefix isn't consecutive. */ -#define FMT_1 (1 << 9) /* 0xF0F00000 */ -#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ -#define FMT_3 (1 << 11) /* 0xFFF00F00 */ -#define FMT_4 (1 << 12) /* 0xFFF0F000 */ -#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ -#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) - -/* Indicates whether this instruction can be relaxed. */ -#define RELAXABLE (1 << 14) - -/* Indicates that instruction uses user registers (and not - general-purpose registers) as operands. */ -#define USER_REG (1 << 15) - -/* Indicates that instruction can perfom a cst4 mapping. */ -#define CST4MAP (1 << 16) - -/* Instruction shouldn't allow 'sp' usage. */ -#define NO_SP (1 << 17) - -/* Instruction shouldn't allow to push a register which is used as a rptr. */ -#define NO_RPTR (1 << 18) - -/* Maximum operands per instruction. */ -#define MAX_OPERANDS 5 -/* Maximum register name length. */ -#define MAX_REGNAME_LEN 10 -/* Maximum instruction length. */ -#define MAX_INST_LEN 256 - - -/* Values defined for the flags field of a struct operand_entry. */ - -/* Operand must be an unsigned number. */ -#define OP_UNSIGNED (1 << 0) -/* Operand must be a signed number. */ -#define OP_SIGNED (1 << 1) -/* A special arithmetic 4-bit constant operand. */ -#define OP_CST4 (1 << 2) -/* A special load/stor 4-bit unsigned displacement operand. */ -#define OP_DISPU4 (1 << 3) -/* Operand must be an even number. */ -#define OP_EVEN (1 << 4) -/* Operand is shifted right. */ -#define OP_SHIFT (1 << 5) -/* Operand is shifted right and decremented. */ -#define OP_SHIFT_DEC (1 << 6) -/* Operand has reserved escape sequences. */ -#define OP_ESC (1 << 7) -/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ -#define OP_UPPER_64KB (1 << 8) - -/* Single operand description. */ - -typedef struct - { - /* Operand type. */ - operand_type op_type; - /* Operand location within the opcode. */ - unsigned int shift; - } -operand_desc; - -/* Instruction data structure used in instruction table. */ - -typedef struct - { - /* Name. */ - const char *mnemonic; - /* Size (in words). */ - unsigned int size; - /* Constant prefix (matched by the disassembler). */ - unsigned long match; - /* Match size (in bits). */ - int match_bits; - /* Attributes. */ - unsigned int flags; - /* Operands (always last, so unreferenced operands are initialized). */ - operand_desc operands[MAX_OPERANDS]; - } -inst; - -/* Data structure for a single instruction's arguments (Operands). */ - -typedef struct - { - /* Register or base register. */ - reg r; - /* Index register. */ - reg i_r; - /* Coprocessor register. */ - copreg cr; - /* Constant/immediate/absolute value. */ - long constant; - /* Scaled index mode. */ - unsigned int scale; - /* Argument type. */ - argtype type; - /* Size of the argument (in bits) required to represent. */ - int size; - /* The type of the expression. */ - unsigned char X_op; - } -argument; - -/* Internal structure to hold the various entities - corresponding to the current assembling instruction. */ - -typedef struct - { - /* Number of arguments. */ - int nargs; - /* The argument data structure for storing args (operands). */ - argument arg[MAX_OPERANDS]; -/* The following fields are required only by CRX-assembler. */ -#ifdef TC_CRX - /* Expression used for setting the fixups (if any). */ - expressionS exp; - bfd_reloc_code_real_type rtype; -#endif /* TC_CRX */ - /* Instruction size (in bytes). */ - int size; - } -ins; - -/* Structure to hold information about predefined operands. */ - -typedef struct - { - /* Size (in bits). */ - unsigned int bit_size; - /* Argument type. */ - argtype arg_type; - /* One bit syntax flags. */ - int flags; - } -operand_entry; - -/* Structure to hold trap handler information. */ - -typedef struct - { - /* Trap name. */ - char *name; - /* Index in dispatch table. */ - unsigned int entry; - } -trap_entry; - -/* Structure to hold information about predefined registers. */ - -typedef struct - { - /* Name (string representation). */ - char *name; - /* Value (enum representation). */ - union - { - /* Register. */ - reg reg_val; - /* Coprocessor register. */ - copreg copreg_val; - } value; - /* Register image. */ - int image; - /* Register type. */ - reg_type type; - } -reg_entry; - -/* Structure to hold a cst4 operand mapping. */ - -/* CRX opcode table. */ -extern const inst crx_instruction[]; -extern const int crx_num_opcodes; -#define NUMOPCODES crx_num_opcodes - -/* CRX operands table. */ -extern const operand_entry crx_optab[]; - -/* CRX registers table. */ -extern const reg_entry crx_regtab[]; -extern const int crx_num_regs; -#define NUMREGS crx_num_regs - -/* CRX coprocessor registers table. */ -extern const reg_entry crx_copregtab[]; -extern const int crx_num_copregs; -#define NUMCOPREGS crx_num_copregs - -/* CRX trap/interrupt table. */ -extern const trap_entry crx_traps[]; -extern const int crx_num_traps; -#define NUMTRAPS crx_num_traps - -/* cst4 operand mapping. */ -extern const long cst4_map[]; -extern const int cst4_maps; - -/* Table of instructions with no operands. */ -extern const char* no_op_insn[]; - -/* Current instruction we're assembling. */ -extern const inst *instruction; - -/* A macro for representing the instruction "constant" opcode, that is, - the FIXED part of the instruction. The "constant" opcode is represented - as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) - over that range. */ -#define BIN(OPC,SHIFT) (OPC << SHIFT) - -/* Is the current instruction type is TYPE ? */ -#define IS_INSN_TYPE(TYPE) \ - (CRX_INS_TYPE(instruction->flags) == TYPE) - -/* Is the current instruction mnemonic is MNEMONIC ? */ -#define IS_INSN_MNEMONIC(MNEMONIC) \ - (strcmp(instruction->mnemonic,MNEMONIC) == 0) - -/* Does the current instruction has register list ? */ -#define INST_HAS_REG_LIST \ - (instruction->flags & REG_LIST) - -/* Long long type handling. */ -/* Replace all appearances of 'long long int' with LONGLONG. */ -typedef long long int LONGLONG; -typedef unsigned long long ULONGLONG; - -#endif /* _CRX_H_ */ diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h deleted file mode 100644 index c96ddebf1..000000000 --- a/include/opcode/d10v.h +++ /dev/null @@ -1,208 +0,0 @@ -/* d10v.h -- Header file for D10V opcode table - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 - Free Software Foundation, Inc. - Written by Martin Hunt (hunt@cygnus.com), Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef D10V_H -#define D10V_H - -/* Format Specifier */ -#define FM00 0 -#define FM01 0x40000000 -#define FM10 0x80000000 -#define FM11 0xC0000000 - -#define NOP 0x5e00 -#define OPCODE_DIVS 0x14002800 - -/* The opcode table is an array of struct d10v_opcode. */ - -struct d10v_opcode -{ - /* The opcode name. */ - const char *name; - - /* the opcode format */ - int format; - - /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ -#define SHORT_OPCODE 1 -#define LONG_OPCODE 8 -#define SHORT_2 1 /* short with 2 operands */ -#define SHORT_B 3 /* short with 8-bit branch */ -#define LONG_B 8 /* long with 16-bit branch */ -#define LONG_L 10 /* long with 3 operands */ -#define LONG_R 12 /* reserved */ - - /* just a placeholder for variable-length instructions */ - /* for example, "bra" will be a fake for "bra.s" and bra.l" */ - /* which will immediately follow in the opcode table. */ -#define OPCODE_FAKE 32 - - /* the number of cycles */ - int cycles; - - /* the execution unit(s) used */ - int unit; -#define EITHER 0 -#define IU 1 -#define MU 2 -#define BOTH 3 - - /* execution type; parallel or sequential */ - /* this field is used to decide if two instructions */ - /* can be executed in parallel */ - int exec_type; -#define PARONLY 1 /* parallel only */ -#define SEQ 2 /* must be sequential */ -#define PAR 4 /* may be parallel */ -#define BRANCH_LINK 8 /* subroutine call. must be aligned */ -#define RMEM 16 /* reads memory */ -#define WMEM 32 /* writes memory */ -#define RF0 64 /* reads f0 */ -#define WF0 128 /* modifies f0 */ -#define WCAR 256 /* write Carry */ -#define BRANCH 512 /* branch, no link */ -#define ALONE 1024 /* short but pack with a NOP if on asm line alone */ - - /* the opcode */ - long opcode; - - /* mask. if( (i & mask) == opcode ) then match */ - long mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[6]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct d10v_opcode d10v_opcodes[]; -extern const int d10v_num_opcodes; - -/* The operands table is an array of struct d10v_operand. */ -struct d10v_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the d10v_opcodes table. */ - -extern const struct d10v_operand d10v_operands[]; - -/* Values defined for the flags field of a struct d10v_operand. */ - -/* the operand must be an even number */ -#define OPERAND_EVEN (1) - -/* the operand must be an odd number */ -#define OPERAND_ODD (2) - -/* this is the destination register; it will be modified */ -/* this is used by the optimizer */ -#define OPERAND_DEST (4) - -/* number or symbol */ -#define OPERAND_NUM (8) - -/* address or label */ -#define OPERAND_ADDR (0x10) - -/* register */ -#define OPERAND_REG (0x20) - -/* postincrement + */ -#define OPERAND_PLUS (0x40) - -/* postdecrement - */ -#define OPERAND_MINUS (0x80) - -/* @ */ -#define OPERAND_ATSIGN (0x100) - -/* @( */ -#define OPERAND_ATPAR (0x200) - -/* accumulator 0 */ -#define OPERAND_ACC0 (0x400) - -/* accumulator 1 */ -#define OPERAND_ACC1 (0x800) - -/* f0 / f1 flag register */ -#define OPERAND_FFLAG (0x1000) - -/* c flag register */ -#define OPERAND_CFLAG (0x2000) - -/* control register */ -#define OPERAND_CONTROL (0x4000) - -/* predecrement mode '@-sp' */ -#define OPERAND_ATMINUS (0x8000) - -/* signed number */ -#define OPERAND_SIGNED (0x10000) - -/* special accumulator shifts need a 4-bit number */ -/* 1 <= x <= 16 */ -#define OPERAND_SHIFT (0x20000) - -/* general purpose register */ -#define OPERAND_GPR (0x40000) - -/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ -/* needed for rac/rachi */ -#define RESTRICTED_NUM3 (0x80000) - -/* Pre-decrement is only supported for SP. */ -#define OPERAND_SP (0x100000) - -/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and - unlike OPERAND_SP, this flag doesn't prevent the instruction from - matching, it only fails validation later on. */ -#define OPERAND_NOSP (0x200000) - -/* Structure to hold information about predefined registers. */ -struct pd_reg -{ - char *name; /* name to recognize */ - char *pname; /* name to print for this register */ - int value; -}; - -extern const struct pd_reg d10v_predefined_registers[]; -int d10v_reg_name_cnt (void); - -/* an expressionS only has one register type, so we fake it */ -/* by setting high bits to indicate type */ -#define REGISTER_MASK 0xFF - -#endif /* D10V_H */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h deleted file mode 100644 index 7aa5bb6fe..000000000 --- a/include/opcode/d30v.h +++ /dev/null @@ -1,286 +0,0 @@ -/* d30v.h -- Header file for D30V opcode table - Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. - Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef D30V_H -#define D30V_H - -#define NOP 0x00F00000 - -/* Structure to hold information about predefined registers. */ -struct pd_reg -{ - char *name; /* name to recognize */ - char *pname; /* name to print for this register */ - int value; -}; - -extern const struct pd_reg pre_defined_registers[]; -int reg_name_cnt (void); - -/* the number of control registers */ -#define MAX_CONTROL_REG 64 - -/* define the format specifiers */ -#define FM00 0 -#define FM01 0x80000000 -#define FM10 0x8000000000000000LL -#define FM11 0x8000000080000000LL - -/* define the opcode classes */ -#define BRA 0 -#define LOGIC 1 -#define IMEM 2 -#define IALU1 4 -#define IALU2 5 - -/* define the execution condition codes */ -#define ECC_AL 0 /* ALways (default) */ -#define ECC_TX 1 /* F0=True, F1=Don't care */ -#define ECC_FX 2 /* F0=False, F1=Don't care */ -#define ECC_XT 3 /* F0=Don't care, F1=True */ -#define ECC_XF 4 /* F0=Don't care, F1=False */ -#define ECC_TT 5 /* F0=True, F1=True */ -#define ECC_TF 6 /* F0=True, F1=False */ -#define ECC_RESERVED 7 /* reserved */ -#define ECC_MAX ECC_RESERVED - -extern const char *d30v_ecc_names[]; - -/* condition code table for CMP and CMPU */ -extern const char *d30v_cc_names[]; - -/* The opcode table is an array of struct d30v_opcode. */ -struct d30v_opcode -{ - /* The opcode name. */ - const char *name; - - /* the opcode */ - int op1; /* first part, "IALU1" for example */ - int op2; /* the rest of the opcode */ - - /* opcode format(s). These numbers correspond to entries */ - /* in the d30v_format_table */ - unsigned char format[4]; - -#define SHORT_M 1 -#define SHORT_M2 5 /* for ld2w and st2w */ -#define SHORT_A 9 -#define SHORT_B1 11 -#define SHORT_B2 12 -#define SHORT_B2r 13 -#define SHORT_B3 14 -#define SHORT_B3r 16 -#define SHORT_B3b 18 -#define SHORT_B3br 20 -#define SHORT_D1r 22 -#define SHORT_D2 24 -#define SHORT_D2r 26 -#define SHORT_D2Br 28 -#define SHORT_U 30 /* unary SHORT_A. ABS for example */ -#define SHORT_F 31 /* SHORT_A with flag registers */ -#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ -#define SHORT_T 35 /* for trap instruction */ -#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ -#define SHORT_CMP 38 /* special form for CMPcc */ -#define SHORT_CMPU 40 /* special form for CMPUcc */ -#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ -#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ -#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ -#define SHORT_MODINC 48 -#define SHORT_MODDEC 49 -#define SHORT_C1 50 -#define SHORT_C2 51 -#define SHORT_UF 52 -#define SHORT_A2 53 -#define SHORT_NONE 55 /* no operands */ -#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ -#define LONG 57 -#define LONG_U 58 /* unary LONG */ -#define LONG_Ur 59 /* LONG pc-relative */ -#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ -#define LONG_M 61 /* Memory long for ldb, stb */ -#define LONG_M2 62 /* Memory long for ld2w, st2w */ -#define LONG_2 63 /* LONG with 2 operands; jmptnz */ -#define LONG_2r 64 /* LONG with 2 operands; bratnz */ -#define LONG_2b 65 /* LONG_2 with modifier of 3 */ -#define LONG_2br 66 /* LONG_2r with modifier of 3 */ -#define LONG_D 67 /* for DJMPI */ -#define LONG_Dr 68 /* for DBRAI */ -#define LONG_Dbr 69 /* for repeati */ - - /* the execution unit(s) used */ - int unit; -#define EITHER 0 -#define IU 1 -#define MU 2 -#define EITHER_BUT_PREFER_MU 3 - - /* this field is used to decide if two instructions */ - /* can be executed in parallel */ - long flags_used; - long flags_set; -#define FLAG_0 (1L<<0) -#define FLAG_1 (1L<<1) -#define FLAG_2 (1L<<2) -#define FLAG_3 (1L<<3) -#define FLAG_4 (1L<<4) /* S (saturation) */ -#define FLAG_5 (1L<<5) /* V (overflow) */ -#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ -#define FLAG_7 (1L<<7) /* C (carry/borrow) */ -#define FLAG_SM (1L<<8) /* SM (stack mode) */ -#define FLAG_RP (1L<<9) /* RP (repeat enable) */ -#define FLAG_CONTROL (1L<<10) /* control registers */ -#define FLAG_A0 (1L<<11) /* A0 */ -#define FLAG_A1 (1L<<12) /* A1 */ -#define FLAG_JMP (1L<<13) /* instruction is a branch */ -#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ -#define FLAG_MEM (1L<<15) /* reads/writes memory */ -#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation - New meaning: operation cannot be - combined in parallel with ADD/SUBppp. */ -#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ -#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ -#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ -#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ -#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ -#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) -#define FLAG_C FLAG_7 -#define FLAG_ALL (FLAG_0 | \ - FLAG_1 | \ - FLAG_2 | \ - FLAG_3 | \ - FLAG_4 | \ - FLAG_5 | \ - FLAG_6 | \ - FLAG_7 | \ - FLAG_SM | \ - FLAG_RP | \ - FLAG_CONTROL) - - int reloc_flag; -#define RELOC_PCREL 1 -#define RELOC_ABS 2 -}; - -extern const struct d30v_opcode d30v_opcode_table[]; -extern const int d30v_num_opcodes; - -/* The operands table is an array of struct d30v_operand. */ -struct d30v_operand -{ - /* the length of the field */ - int length; - - /* The number of significant bits in the operand. */ - int bits; - - /* position relative to Ra */ - int position; - - /* syntax flags. */ - long flags; -}; -extern const struct d30v_operand d30v_operand_table[]; - -/* Values defined for the flags field of a struct d30v_operand. */ - -/* this is the destination register; it will be modified */ -/* this is used by the optimizer */ -#define OPERAND_DEST (1) - -/* number or symbol */ -#define OPERAND_NUM (2) - -/* address or label */ -#define OPERAND_ADDR (4) - -/* register */ -#define OPERAND_REG (8) - -/* postincrement + */ -#define OPERAND_PLUS (0x10) - -/* postdecrement - */ -#define OPERAND_MINUS (0x20) - -/* signed number */ -#define OPERAND_SIGNED (0x40) - -/* this operand must be shifted left by 3 */ -#define OPERAND_SHIFT (0x80) - -/* flag register */ -#define OPERAND_FLAG (0x100) - -/* control register */ -#define OPERAND_CONTROL (0x200) - -/* accumulator */ -#define OPERAND_ACC (0x400) - -/* @ */ -#define OPERAND_ATSIGN (0x800) - -/* @( */ -#define OPERAND_ATPAR (0x1000) - -/* predecrement mode '@-sp' */ -#define OPERAND_ATMINUS (0x2000) - -/* this operand changes the instruction name */ -/* for example, CPMcc, CMPUcc */ -#define OPERAND_NAME (0x4000) - -/* fake operand for mvtsys and mvfsys */ -#define OPERAND_SPECIAL (0x8000) - -/* let the optimizer know that two registers are affected */ -#define OPERAND_2REG (0x10000) - -/* This operand is pc-relative. Note that repeati can have two immediate - operands, one of which is pcrel, the other (the IMM6U one) is not. */ -#define OPERAND_PCREL (0x20000) - -/* The format table is an array of struct d30v_format. */ -struct d30v_format -{ - int form; /* SHORT_A, LONG, etc */ - int modifier; /* two bit modifier following opcode */ - unsigned char operands[5]; -}; -extern const struct d30v_format d30v_format_table[]; - - -/* an instruction is defined by an opcode and a format */ -/* for example, "add" has one opcode, but three different */ -/* formats, 2 SHORT_A forms and a LONG form. */ -struct d30v_insn -{ - struct d30v_opcode *op; /* pointer to an entry in the opcode table */ - struct d30v_format *form; /* pointer to an entry in the format table */ - int ecc; /* execution condition code */ -}; - -/* an expressionS only has one register type, so we fake it */ -/* by setting high bits to indicate type */ -#define REGISTER_MASK 0xFF - -#endif /* D30V_H */ diff --git a/include/opcode/dlx.h b/include/opcode/dlx.h deleted file mode 100644 index 278e936cd..000000000 --- a/include/opcode/dlx.h +++ /dev/null @@ -1,282 +0,0 @@ -/* Table of opcodes for the DLX microprocess. - Copyright 2002 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. - - Initially created by Kuang Hwa Lin, 2002. */ - -/* Following are the function codes for the Special OP (ALU). */ -#define ALUOP 0x00000000 -#define SPECIALOP 0x00000000 - -#define NOPF 0x00000000 -#define SLLF 0x00000004 -#define SRLF 0x00000006 -#define SRAF 0x00000007 - -#define SEQUF 0x00000010 -#define SNEUF 0x00000011 -#define SLTUF 0x00000012 -#define SGTUF 0x00000013 -#define SLEUF 0x00000014 -#define SGEUF 0x00000015 - -#define ADDF 0x00000020 -#define ADDUF 0x00000021 -#define SUBF 0x00000022 -#define SUBUF 0x00000023 -#define ANDF 0x00000024 -#define ORF 0x00000025 -#define XORF 0x00000026 - -#define SEQF 0x00000028 -#define SNEF 0x00000029 -#define SLTF 0x0000002A -#define SGTF 0x0000002B -#define SLEF 0x0000002C -#define SGEF 0x0000002D - /* Following special functions was not mentioned in the - Hennessy's book but was implemented in the RTL. */ -#define MVTSF 0x00000030 -#define MVFSF 0x00000031 -#define BSWAPF 0x00000032 -#define LUTF 0x00000033 -/* Following special functions was mentioned in the - Hennessy's book but was not implemented in the RTL. */ -#define MULTF 0x00000005 -#define MULTUF 0x00000006 -#define DIVF 0x00000007 -#define DIVUF 0x00000008 - - -/* Following are the rest of the OPcodes: - JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) - ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) - ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) - RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) - BREAKOP= (0x014 << 26) - SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) - SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) - LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) - LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) - LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), - SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) - SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) - SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ -#define JOP 0x08000000 -#define JALOP 0x0c000000 -#define BEQOP 0x10000000 -#define BNEOP 0x14000000 - -#define ADDIOP 0x20000000 -#define ADDUIOP 0x24000000 -#define SUBIOP 0x28000000 -#define SUBUIOP 0x2c000000 -#define ANDIOP 0x30000000 -#define ORIOP 0x34000000 -#define XORIOP 0x38000000 -#define LHIOP 0x3c000000 -#define RFEOP 0x40000000 -#define TRAPOP 0x44000000 -#define JROP 0x48000000 -#define JALROP 0x4c000000 -#define BREAKOP 0x50000000 - -#define SEQIOP 0x60000000 -#define SNEIOP 0x64000000 -#define SLTIOP 0x68000000 -#define SGTIOP 0x6c000000 -#define SLEIOP 0x70000000 -#define SGEIOP 0x74000000 - -#define LBOP 0x80000000 -#define LHOP 0x84000000 -#define LWOP 0x8c000000 -#define LBUOP 0x90000000 -#define LHUOP 0x94000000 -#define LDSTBU -#define LDSTHU -#define SBOP 0xa0000000 -#define SHOP 0xa4000000 -#define SWOP 0xac000000 -#define LDST - -#define SEQUIOP 0xc0000000 -#define SNEUIOP 0xc4000000 -#define SLTUIOP 0xc8000000 -#define SGTUIOP 0xcc000000 -#define SLEUIOP 0xd0000000 -#define SGEUIOP 0xd4000000 - -#define SLLIOP 0xd8000000 -#define SRLIOP 0xdc000000 -#define SRAIOP 0xe0000000 - -/* Following 3 ops was added to provide the MP atonmic operation. */ -#define LSBUOP 0x98000000 -#define LSHUOP 0x9c000000 -#define LSWOP 0xb0000000 - -/* Following opcode was defined in the Hennessy's book as - "normal" opcode but was implemented in the RTL as special - functions. */ -#if 0 -#define MVTSOP 0x50000000 -#define MVFSOP 0x54000000 -#endif - -struct dlx_opcode -{ - /* Name of the instruction. */ - char *name; - - /* Opcode word. */ - unsigned long opcode; - - /* A string of characters which describe the operands. - Valid characters are: - , Itself. The character appears in the assembly code. - a rs1 The register number is in bits 21-25 of the instruction. - b rs2/rd The register number is in bits 16-20 of the instruction. - c rd. The register number is in bits 11-15 of the instruction. - f FUNC bits 0-10 of the instruction. - i An immediate operand is in bits 0-16 of the instruction. 0 extended - I An immediate operand is in bits 0-16 of the instruction. sign extended - d An 16 bit PC relative displacement. - D An immediate operand is in bits 0-25 of the instruction. - N No opperands needed, for nops. - P it can be a register or a 16 bit operand. */ - char *args; -}; - -static const struct dlx_opcode dlx_opcodes[] = - { - /* Arithmetic and Logic R-TYPE instructions. */ - { "nop", (ALUOP|NOPF), "N" }, /* NOP */ - { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ - { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ - { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ - { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ - { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ - { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ - { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ - { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ - { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ - { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ - { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ - { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ - { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ - { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ - { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ - { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ - { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ - { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ - { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ - { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ - { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ - { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ - { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ - { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ - { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ - { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ - { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ - { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ - { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ - { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ - - /* Arithmetic and Logical Immediate I-TYPE instructions. */ - { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ - { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ - { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ - { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ - { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ - { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ - { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ - { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ - { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ - { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ - { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ - { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ - { "slti", SLTIOP, "b,a,i" }, /* Set if less */ - { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ - { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ - { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ - { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ - { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ - { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ - { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ - { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ - { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ - /* Macros for I type instructions. */ - { "mov", ADDIOP, "b,P" }, /* a move macro */ - { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ - -#if 0 - /* Move special. */ - { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ - { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ -#endif - - /* Load high Immediate I-TYPE instruction. */ - { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ - { "lui", LHIOP, "b,i" }, /* Load High Immediate */ - { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ - - /* LOAD/STORE BYTE 8 bits I-TYPE. */ - { "lb", LBOP, "b,a,I" }, /* Load Byte */ - { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ - { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ - { "sb", SBOP, "b,a,I" }, /* Store Byte */ - - /* LOAD/STORE HALFWORD 16 bits. */ - { "lh", LHOP, "b,a,I" }, /* Load Halfword */ - { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ - { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ - { "sh", SHOP, "b,a,I" }, /* Store Halfword */ - - /* LOAD/STORE WORD 32 bits. */ - { "lw", LWOP, "b,a,I" }, /* Load Word */ - { "sw", SWOP, "b,a,I" }, /* Store Word */ - { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ - - /* Branch PC-relative, 16 bits offset. */ - { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ - { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ - { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ - { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ - - /* Jumps Trap and RFE J-TYPE. */ - { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ - { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ - { "break", BREAKOP, "D" }, /* break to OS */ - { "trap" , TRAPOP, "D" }, /* TRAP to OS */ - { "rfe", RFEOP, "N" }, /* Return From Exception */ - /* Macros. */ - { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ - - /* Jumps Trap and RFE I-TYPE. */ - { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ - { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ - /* Macros. */ - { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ - - { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. - This lets code examine entry i + 1 without - checking if we've run off the end of the table. */ - }; - -const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h deleted file mode 100644 index 10fdf527f..000000000 --- a/include/opcode/h8300.h +++ /dev/null @@ -1,1893 +0,0 @@ -/* Opcode table for the H8/300 - Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002, - 2003, 2004 - Free Software Foundation, Inc. - Written by Steve Chamberlain <sac@cygnus.com>. - - This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* Instructions are stored as a sequence of nibbles. - If the nibble has value 15 or less than the representation is complete. - Otherwise, we record what it contains with several flags. */ - -typedef int op_type; - -enum h8_flags -{ - L_2 = 0x10, - L_3 = 0x20, - /* 3 bit constant, zero not accepted. */ - L_3NZ = 0x30, - L_4 = 0x40, - L_5 = 0x50, - L_8 = 0x60, - L_8U = 0x70, - L_16 = 0x80, - L_16U = 0x90, - L_24 = 0xA0, - L_32 = 0xB0, - L_P = 0xC0, - - /* Mask to isolate the L_x size bits. */ - SIZE = 0xF0, - - REG = 0x0100, - ABS = 0x0200, - MEMIND = 0x0300, - IMM = 0x0400, - DISP = 0x0500, - IND = 0x0600, - POSTINC = 0x0700, - POSTDEC = 0x0800, - PREINC = 0x0900, - PREDEC = 0x0A00, - PCREL = 0x0B00, - KBIT = 0x0C00, - DBIT = 0x0D00, - CONST_2 = 0x0E00, - CONST_4 = 0x0F00, - CONST_8 = 0x1000, - CONST_16 = 0x1100, - INDEXB = 0x1200, - INDEXW = 0x1300, - INDEXL = 0x1400, - PCIDXB = 0x1500, - PCIDXW = 0x1600, - PCIDXL = 0x1700, - VECIND = 0x1800, - LOWREG = 0x1900, - DATA = 0x2000, - - /* Synonyms. */ - INC = POSTINC, - DEC = PREDEC, - /* Control Registers. */ - CCR = 0x4000, - EXR = 0x4100, - MACH = 0x4200, - MACL = 0x4300, - RESERV1 = 0x4400, - RESERV2 = 0x4500, - VBR = 0x4600, - SBR = 0x4700, - MACREG = 0x4800, - CCR_EXR = 0x4900, - VBR_SBR = 0x4A00, - CC_EX_VB_SB = 0x4B00, - RESERV3 = 0x4C00, - RESERV4 = 0x4D00, - RESERV5 = 0x4E00, - RESERV6 = 0x4F00, - - /* Mask to isolate the addressing mode bits (REG .. PREDEC). */ - MODE = 0x7F00, - - CTRL = 0x4000, - - NO_SYMBOLS = 0x8000, - SRC = 0x10000, - DST = 0x20000, - OP3 = 0x40000, - MEMRELAX = 0x80000, /* Move insn which may relax. */ - - DISPREG = 0x100000, - IGNORE = 0x200000, - ABSJMP = 0x400000, - - B00 = 0x800000, /* Bit 0 must be low. */ - B01 = 0x1000000, /* Bit 0 must be high. */ - B10 = 0x2000000, /* Bit 1 must be low. */ - B11 = 0x4000000, /* Bit 1 must be high. */ - B20 = 0x8000000, /* Bit 2 must be low. */ - B21 = 0x10000000, /* Bit 2 must be high. */ - B30 = 0x20000000, /* Bit 3 must be low. */ - B31 = 0x40000000, /* Bit 3 must be high. */ - E = 0x80000000, /* End of nibble sequence. */ - - /* Immediates smaller than 8 bits are always unsigned. */ - IMM3 = IMM | L_3, - IMM4 = IMM | L_4, - IMM5 = IMM | L_5, - IMM3NZ = IMM | L_3NZ, - IMM2 = IMM | L_2, - - IMM8 = IMM | SRC | L_8, - IMM8U = IMM | SRC | L_8U, - IMM16 = IMM | SRC | L_16, - IMM16U = IMM | SRC | L_16U, - IMM32 = IMM | SRC | L_32, - - IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, - IMM4_NS = IMM4 | NO_SYMBOLS, - IMM8U_NS = IMM8U | NO_SYMBOLS, - IMM16U_NS = IMM16U | NO_SYMBOLS, - - RD8 = DST | L_8 | REG, - RD16 = DST | L_16 | REG, - RD32 = DST | L_32 | REG, - R3_8 = OP3 | L_8 | REG, - R3_16 = OP3 | L_16 | REG, - R3_32 = OP3 | L_32 | REG, - RS8 = SRC | L_8 | REG, - RS16 = SRC | L_16 | REG, - RS32 = SRC | L_32 | REG, - - RSP = SRC | L_P | REG, - RDP = DST | L_P | REG, - - PCREL8 = PCREL | L_8, - PCREL16 = PCREL | L_16, - - OP3PCREL8 = OP3 | PCREL | L_8, - OP3PCREL16 = OP3 | PCREL | L_16, - - INDEXB16 = INDEXB | L_16, - INDEXW16 = INDEXW | L_16, - INDEXL16 = INDEXL | L_16, - INDEXB16D = INDEXB | L_16 | DST, - INDEXW16D = INDEXW | L_16 | DST, - INDEXL16D = INDEXL | L_16 | DST, - - INDEXB32 = INDEXB | L_32, - INDEXW32 = INDEXW | L_32, - INDEXL32 = INDEXL | L_32, - INDEXB32D = INDEXB | L_32 | DST, - INDEXW32D = INDEXW | L_32 | DST, - INDEXL32D = INDEXL | L_32 | DST, - - DISP2SRC = DISP | L_2 | SRC, - DISP16SRC = DISP | L_16 | SRC, - DISP32SRC = DISP | L_32 | SRC, - - DISP2DST = DISP | L_2 | DST, - DISP16DST = DISP | L_16 | DST, - DISP32DST = DISP | L_32 | DST, - - DSTDISPREG = DST | DISPREG, - SRCDISPREG = SRC | DISPREG, - - ABS8SRC = SRC | ABS | L_8, - ABS16SRC = SRC | ABS | L_16U, - ABS24SRC = SRC | ABS | L_24, - ABS32SRC = SRC | ABS | L_32, - - ABS8DST = DST | ABS | L_8, - ABS16DST = DST | ABS | L_16U, - ABS24DST = DST | ABS | L_24, - ABS32DST = DST | ABS | L_32, - - ABS8OP3 = OP3 | ABS | L_8, - ABS16OP3 = OP3 | ABS | L_16U, - ABS24OP3 = OP3 | ABS | L_24, - ABS32OP3 = OP3 | ABS | L_32, - - RDDEC = DST | DEC, - RSINC = SRC | INC, - RDINC = DST | INC, - - RSPOSTINC = SRC | POSTINC, - RDPOSTINC = DST | POSTINC, - RSPREINC = SRC | PREINC, - RDPREINC = DST | PREINC, - RSPOSTDEC = SRC | POSTDEC, - RDPOSTDEC = DST | POSTDEC, - RSPREDEC = SRC | PREDEC, - RDPREDEC = DST | PREDEC, - - RSIND = SRC | IND, - RDIND = DST | IND, - R3_IND = OP3 | IND, - -#define MS32 (SRC | L_32 | MACREG) -#define MD32 (DST | L_32 | MACREG) - -#if 1 - OR8 = RS8, /* ??? OR as in One Register. */ - OR16 = RS16, - OR32 = RS32, -#else - OR8 = RD8, - OR16 = RD16, - OR32 = RD32 -#endif -}; - -enum ctrlreg -{ - C_CCR = 0, - C_EXR = 1, - C_MACH = 2, - C_MACL = 3, - C_VBR = 6, - C_SBR = 7 -}; - -enum {MAX_CODE_NIBBLES = 33}; - -struct code -{ - op_type nib[MAX_CODE_NIBBLES]; -}; - -struct arg -{ - op_type nib[3]; -}; - -/* Availability of instructions on processor models. */ -enum h8_model -{ - AV_H8, - AV_H8H, - AV_H8S, - AV_H8SX -}; - -struct h8_opcode -{ - int how; - enum h8_model available; - int time; - char *name; - struct arg args; - struct code data; -}; - -#ifdef DEFINE_TABLE - -#define DATA2 DATA, DATA -#define DATA3 DATA, DATA, DATA -#define DATA5 DATA, DATA, DATA, DATA, DATA -#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA - -#define IMM8LIST IMM8, DATA -#define IMM16LIST IMM16, DATA3 -#define IMM16ULIST IMM16U, DATA3 -#define IMM24LIST IMM24, DATA5 -#define IMM32LIST IMM32, DATA7 - -#define DISP16LIST DISP | L_16, DATA3 -#define DISP24LIST DISP | L_24, DATA5 -#define DISP32LIST DISP | L_32, DATA7 - -#define ABS8LIST ABS | L_8, DATA -#define ABS16LIST ABS | L_16U, DATA3 -#define ABS24LIST ABS | L_24, DATA5 -#define ABS32LIST ABS | L_32, DATA7 - -#define DSTABS8LIST DST | ABS | L_8, DATA -#define DSTABS16LIST DST | ABS | L_16U, DATA3 -#define DSTABS24LIST DST | ABS | L_24, DATA5 -#define DSTABS32LIST DST | ABS | L_32, DATA7 - -#define OP3ABS8LIST OP3 | ABS | L_8, DATA -#define OP3ABS16LIST OP3 | ABS | L_16, DATA3 -#define OP3ABS24LIST OP3 | ABS | L_24, DATA5 -#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 - -#define DSTDISP16LIST DST | DISP | L_16, DATA3 -#define DSTDISP24LIST DST | DISP | L_24, DATA5 -#define DSTDISP32LIST DST | DISP | L_32, DATA7 - -#define A16LIST L_16, DATA3 -#define A24LIST L_24, DATA5 -#define A32LIST L_32, DATA7 - -/* Extended Operand Prefixes: */ - -#define PREFIX_010 0x0, 0x1, 0x0 -#define PREFIX_015 0x0, 0x1, 0x5 -#define PREFIX_017 0x0, 0x1, 0x7 - -#define PREFIX_0100 0x0, 0x1, 0x0, 0x0 -#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC -#define PREFIX_0101 0x0, 0x1, 0x0, 0x1 -#define PREFIX_0102 0x0, 0x1, 0x0, 0x2 -#define PREFIX_0103 0x0, 0x1, 0x0, 0x3 -#define PREFIX_0104 0x0, 0x1, 0x0, 0x4 -#define PREFIX_0105 0x0, 0x1, 0x0, 0x5 -#define PREFIX_0106 0x0, 0x1, 0x0, 0x6 -#define PREFIX_0107 0x0, 0x1, 0x0, 0x7 -#define PREFIX_0108 0x0, 0x1, 0x0, 0x8 -#define PREFIX_0109 0x0, 0x1, 0x0, 0x9 -#define PREFIX_010A 0x0, 0x1, 0x0, 0xa -#define PREFIX_010D 0x0, 0x1, 0x0, 0xd -#define PREFIX_010E 0x0, 0x1, 0x0, 0xe - -#define PREFIX_0150 0x0, 0x1, 0x5, 0x0 -#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC -#define PREFIX_0151 0x0, 0x1, 0x5, 0x1 -#define PREFIX_0152 0x0, 0x1, 0x5, 0x2 -#define PREFIX_0153 0x0, 0x1, 0x5, 0x3 -#define PREFIX_0154 0x0, 0x1, 0x5, 0x4 -#define PREFIX_0155 0x0, 0x1, 0x5, 0x5 -#define PREFIX_0156 0x0, 0x1, 0x5, 0x6 -#define PREFIX_0157 0x0, 0x1, 0x5, 0x7 -#define PREFIX_0158 0x0, 0x1, 0x5, 0x8 -#define PREFIX_0159 0x0, 0x1, 0x5, 0x9 -#define PREFIX_015A 0x0, 0x1, 0x5, 0xa -#define PREFIX_015D 0x0, 0x1, 0x5, 0xd -#define PREFIX_015E 0x0, 0x1, 0x5, 0xe -#define PREFIX_015F 0x0, 0x1, 0x5, 0xf - -#define PREFIX_0170 0x0, 0x1, 0x7, 0x0 -#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC -#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST -#define PREFIX_0171 0x0, 0x1, 0x7, 0x1 -#define PREFIX_0172 0x0, 0x1, 0x7, 0x2 -#define PREFIX_0173 0x0, 0x1, 0x7, 0x3 -#define PREFIX_0174 0x0, 0x1, 0x7, 0x4 -#define PREFIX_0175 0x0, 0x1, 0x7, 0x5 -#define PREFIX_0176 0x0, 0x1, 0x7, 0x6 -#define PREFIX_0177 0x0, 0x1, 0x7, 0x7 -#define PREFIX_0178 0x0, 0x1, 0x7, 0x8 -#define PREFIX_0179 0x0, 0x1, 0x7, 0x9 -#define PREFIX_017A 0x0, 0x1, 0x7, 0xa -#define PREFIX_017D 0x0, 0x1, 0x7, 0xd -#define PREFIX_017E 0x0, 0x1, 0x7, 0xe -#define PREFIX_017F 0x0, 0x1, 0x7, 0xf - -#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5 -#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5 -#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5 -#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5 - -#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4 -#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5 -#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6 -#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7 - -#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4 -#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5 -#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6 -#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7 - -#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4 -#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5 -#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6 -#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7 - -#define PREFIX_7974 0x7, 0x9, 0x7, 0x4 -#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4 -#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc - - -/* Source standard fragment: */ -#define FROM_IND 0, RSIND -#define FROM_POSTINC 8, RSPOSTINC -#define FROM_POSTDEC 10, RSPOSTDEC -#define FROM_PREINC 9, RSPREINC -#define FROM_PREDEC 11, RSPREDEC -#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG -#define FROM_DISP16 12, B30 | DISPREG -#define FROM_DISP32 12, B31 | DISPREG -#define FROM_DISP16B 13, B30 | DISPREG -#define FROM_DISP16W 14, B30 | DISPREG -#define FROM_DISP16L 15, B30 | DISPREG -#define FROM_DISP32B 13, B31 | DISPREG -#define FROM_DISP32W 14, B31 | DISPREG -#define FROM_DISP32L 15, B31 | DISPREG -#define FROM_ABS16 4, B30 | IGNORE -#define FROM_ABS32 4, B31 | IGNORE - -/* Destination standard fragment: */ -#define TO_IND 0, RDIND -#define TO_IND_MOV 0, RDIND | B30 -#define TO_POSTINC 8, RDPOSTINC -#define TO_POSTINC_MOV 8, RDPOSTINC | B30 -#define TO_POSTDEC 10, RDPOSTDEC -#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30 -#define TO_PREINC 9, RDPREINC -#define TO_PREINC_MOV 9, RDPREINC | B30 -#define TO_PREDEC 11, RDPREDEC -#define TO_PREDEC_MOV 11, RDPREDEC | B30 -#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG -#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30 -#define TO_DISP16 12, B30 | DSTDISPREG -#define TO_DISP32 12, B31 | DSTDISPREG -#define TO_DISP16B 13, B30 | DSTDISPREG -#define TO_DISP16W 14, B30 | DSTDISPREG -#define TO_DISP16L 15, B30 | DSTDISPREG -#define TO_DISP32B 13, B31 | DSTDISPREG -#define TO_DISP32W 14, B31 | DSTDISPREG -#define TO_DISP32L 15, B31 | DSTDISPREG -#define TO_ABS16 4, B30 | IGNORE -#define TO_ABS32 4, B31 | IGNORE - -/* Source fragment for three-word instruction: */ -#define TFROM_IND 6, 9, B30 | RSIND, 12 -#define TFROM_DISP2 6, 9, B30 | DISPREG, 12 -#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST -#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST -#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12 -#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12 -#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12 -#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12 -#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST -#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST -#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST -#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST -#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST -#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST - -/* Source fragment for three-word instruction: */ -#define TFROM_IND_B 6, 8, B30 | RSIND, 12 -#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST -#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST - -#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12 -#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12 -#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12 -#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12 -#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12 -#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST -#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST -#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST -#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST -#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST - -#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST -#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST - -/* Extended Operand Class Expanders: */ - -#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}} - -#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}} - -#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}} - -#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}} - -#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ - {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} - -#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ - {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \ - {CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \ - {CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}} - -/* Expansion macros for two-word (plus data) instructions. */ - -/* Expansion from one source to "standard" destinations. */ -#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} - -/* Expansion from one destination to "standard" sources. */ -#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}} - -/* Expansion from immediate source to "standard" destinations. */ -#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}} - -/* Expansion from abs/disp source to "standard" destinations. */ -#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} - -/* Expansion from ind source to "standard" destinations. */ -#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}} - -/* Expansion macros for three word (plus data) instructions. */ - -#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}} - -#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}} - - -#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \ - EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \ - EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE) - - -#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE) - -#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \ - EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE) - - -/* Use the expansion macros to fill out the opcode table. */ - -#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \ - EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \ - {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}} - -#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \ - EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \ - {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}} - -#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \ - EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \ - {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}} - -#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \ - EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \ - {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}} - -#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \ - EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}} - -#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ - EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} - -#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \ - EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}} - -#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \ - EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \ - {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}} - -#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \ - EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \ - {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}} - -#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \ - EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}} - - -#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ - {CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \ - EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \ - EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \ - EXPAND_FROM_IND8 (CODE, NAME, OP4), \ - EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \ - EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \ - EXPAND_FROM_ABS32_B (CODE, NAME, OP4) - -#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \ - {CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \ - EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \ - EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \ - EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \ - EXPAND_FROM_IND16 (CODE, NAME, OP3), \ - EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \ - EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \ - EXPAND_FROM_ABS32_W (CODE, NAME, OP3) - -#define EXPAND_TWOOP_L(CODE, NAME, OP1) \ - {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \ - {CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \ - EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \ - EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \ - EXPAND_FROM_REG32 (CODE, NAME, OP1), \ - EXPAND_TO_REG32 (CODE, NAME, OP1), \ - EXPAND_STD_MATRIX_L (CODE, NAME, OP1) - - -/* Old expanders: */ - -#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - {code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \ - {code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \ - {code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \ - {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \ - {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}} - -#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - {code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \ - {code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \ - {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \ - {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}} - -#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ - BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) - -#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ - BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ - BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) - -#define WTWOP(code, name, op1, op2) \ - {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}} - -#define BRANCH(code, name, op) \ - {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \ - {code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}} - - -#define UNOP(code, name, op1, op2) \ - {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}} - -#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}} - -#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ - {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} - -#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \ - {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ - {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}} - -#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST -#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC - -#define O(op, size) (op * 4 + size) -#define OP_SIZE(HOW) (HOW % 4) -#define OP_KIND(HOW) (HOW / 4) - -enum h8_asm_codes -{ - O_RECOMPILE = 0, - O_ADD, - O_ADDX, - O_AND, - O_BAND, - O_BRA, - O_BRAB, - O_BRAW, - O_BRAL, - O_BRAS, - O_BRABC, - O_BRABS, - O_BSRBC, - O_BSRBS, - O_BRN, - O_BHI, - O_BLS, - O_BCC, - O_BCS, - O_BNE, - O_BVC, - O_BVS, - O_BPL, - O_BMI, - O_BGE, - O_BLT, - O_BGT, - O_BLE, - O_ANDC, - O_BEQ, - O_BCLR, - O_BCLREQ, - O_BCLRNE, - O_BSETEQ, - O_BSETNE, - O_BFLD, - O_BFST, - O_BIAND, - O_BILD, - O_BIOR, - O_BIXOR, - O_BIST, - O_BISTZ, - O_BLD, - O_BNOT, - O_BOR, - O_BSET, - O_BSR, - O_BXOR, - O_CMP, - O_DAA, - O_DAS, - O_DEC, - O_DIVU, - O_DIVS, - O_DIVXU, - O_DIVXS, - O_INC, - O_LDC, - O_MOV, - O_MOVAB, - O_MOVAW, - O_MOVAL, - O_MOVMD, - O_MOVSD, - O_OR, - O_ROTL, - O_ROTR, - O_ROTXL, - O_ROTXR, - O_BPT, - O_SHAL, - O_SHAR, - O_SHLL, - O_SHLR, - O_SUB, - O_SUBS, - O_TRAPA, - O_XOR, - O_XORC, - O_BST, - O_BSTZ, - O_BTST, - O_EEPMOV, - O_EXTS, - O_EXTU, - O_JMP, - O_JSR, - O_MULU, - O_MULUU, - O_MULS, - O_MULSU, - O_MULXU, - O_MULXS, - O_NOP, - O_NOT, - O_ORC, - O_RTE, - O_RTEL, - O_STC, - O_SUBX, - O_NEG, - O_RTS, - O_RTSL, - O_SLEEP, - O_ILL, - O_ADDS, - O_SYSCALL, - O_TAS, - O_CLRMAC, - O_LDMAC, - O_MAC, - O_LDM, - O_STM, - O_STMAC, - O_LAST, - /* Change made for System Call processing. */ - O_SYS_CREAT, - O_SYS_OPEN, - O_SYS_READ, - O_SYS_WRITE, - O_SYS_LSEEK, - O_SYS_CLOSE, - O_SYS_STAT, - O_SYS_FSTAT, -/* Space reserved for future file I/O system calls. */ - O_SYS_CMDLINE - /* End of System Call specific Changes. */ -}; - -enum h8_size -{ - SB = 0, - SW = 1, - SL = 2, - SN = 3 -}; - - -/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. - Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */ - -struct h8_opcode h8_opcodes[] = -{ - {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), - - {O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), - - {O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), - - {O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}}, - - {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, - {O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, - {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, - - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, - {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, - - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, - {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, - - {O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), - - {O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}}, - EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), - - {O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), - - {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}}, - {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}}, - - BRANCH (O (O_BRA, SB), "bra", 0x0), - - {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}}, - {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}}, - {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}}, - - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - - {O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}}, - - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, - - BRANCH (O (O_BRA, SB), "bt", 0x0), - BRANCH (O (O_BRN, SB), "brn", 0x1), - BRANCH (O (O_BRN, SB), "bf", 0x1), - BRANCH (O (O_BHI, SB), "bhi", 0x2), - BRANCH (O (O_BLS, SB), "bls", 0x3), - BRANCH (O (O_BCC, SB), "bcc", 0x4), - BRANCH (O (O_BCC, SB), "bhs", 0x4), - BRANCH (O (O_BCS, SB), "bcs", 0x5), - BRANCH (O (O_BCS, SB), "blo", 0x5), - BRANCH (O (O_BNE, SB), "bne", 0x6), - BRANCH (O (O_BEQ, SB), "beq", 0x7), - BRANCH (O (O_BVC, SB), "bvc", 0x8), - BRANCH (O (O_BVS, SB), "bvs", 0x9), - BRANCH (O (O_BPL, SB), "bpl", 0xA), - BRANCH (O (O_BMI, SB), "bmi", 0xB), - BRANCH (O (O_BGE, SB), "bge", 0xC), - BRANCH (O (O_BLT, SB), "blt", 0xD), - BRANCH (O (O_BGT, SB), "bgt", 0xE), - BRANCH (O (O_BLE, SB), "ble", 0xF), - - EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), - EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), - - EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), - EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), - BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), - - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}}, - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}}, - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}}, - {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}}, - - /* Because the assembler treats SRC, DST and OP3 as ordinals, - I must designate the second argument, an immediate value, as DST. - May God have mercy on my soul. */ - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}}, - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}}, - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}}, - {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}}, - - {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}}, - {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}}, - {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}}, - {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}}, - {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}}, - - {O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), - - {O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, - EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), - - {O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}}, - {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), - - UNOP (O (O_DAA, SB), "daa", 0x0, 0xF), - UNOP (O (O_DAS, SB), "das", 0x1, 0xF), - UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA), - - {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}}, - {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, - - {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}}, - {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, - - {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}}, - {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, - - {O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}}, - {O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}}, - - {O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}}, - {O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}}, - {O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}}, - {O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}}, - - {O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}}, - {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}}, - - EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd), - EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf), - EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0), - EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5), - EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7), - EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0), - - UNOP (O (O_INC, SB), "inc", 0x0, 0xA), - - {O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}}, - {O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, - - {O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}}, - {O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}}, - - {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, - - {O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}}, - {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}}, - - {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}}, - {O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}}, - - {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, - - {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, - {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, - - {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, - {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, - {O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}}, - {O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, - - {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, - - - {O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}}, - {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}}, - {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}}, - MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8), - - {O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}}, - MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), - {O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}}, - MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), - {O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}}, - - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC), - MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST), - MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST), - - {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}}, - {O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}}, - {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, - {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, - - MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), - MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), - - {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, - MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0), - MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0), - - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC), - MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST), - MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST), - - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, - - MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), - MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), - - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, - {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}}, - - MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST), - - {O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}}, - - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}}, - - {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}}, - - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC), - MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST), - MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST), - -#define DO_MOVA1(TYPE, OP0, OP1) \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \ -\ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}} - -#define DO_MOVA2(TYPE, OP0, OP1, OP2) \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \ -\ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \ - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \ - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \ - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}} - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}}, - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}}, - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}}, - - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}}, - {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}}, - {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}}, - {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}}, - - DO_MOVA1 (RDIND, 0x0, B30 | RDIND), - DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC), - DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), - DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), - DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), - DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), - DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST), - DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST), - DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST), - DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST), - - {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, - {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, - - {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}}, - {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}}, - {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}}, - {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}}, - - {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}}, - {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - - {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}}, - {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - - {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, - - {O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}}, - {O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}}, - - {O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}}, - {O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}}, - {O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}}, - {O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}}, - - EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8), - EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9), - EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb), - - {O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}}, - - EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0), - EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1), - EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3), - - {O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), - - {O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, - EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), - - {O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), - - {O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}}, - {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}}, - - {O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}}, - {O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}}, - - EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc), - EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd), - EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30), - EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc), - EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd), - EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30), - EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0), - EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4), - EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1), - EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5), - EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3), - EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30), - EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0), - EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4), - EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1), - EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5), - EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3), - EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30), - - - {O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}}, - {O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}}, - {O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}}, - {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}}, - {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}}, - - EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc), - EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd), - EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30), - EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8), - EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc), - EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9), - EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd), - EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb), - EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30), - - EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0), - - {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}}, - - EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4), - EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa), - {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}}, - - EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1), - - {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}}, - - EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5), - EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2), - EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6), - {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}}, - - EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3), - - {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}}, - - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30), - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31), - {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}}, - - EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0), - - {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}}, - - EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4), - EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa), - {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}}, - - EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1), - - {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}}, - - EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5), - EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2), - EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6), - {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}, - - EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3), - - {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}}, - - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30), - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31), - EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31), - {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}}, - - {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}}, - - {O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}}, - {O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, - {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, - - - EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), - - {O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, - EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), - - {O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), - - {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}}, - - {O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, - {O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, - {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, - - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, - {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, - - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, - {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, - - {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}}, - {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}}, - - {O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}}, - EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), - - {O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, - EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), - - {O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}}, - EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), - - {O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}}, - {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}}, - - {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}}, - {O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}}, - {O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}}, - {O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}}, - {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}}, - {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}}, - {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}} -}; -#else -extern const struct h8_opcode h8_opcodes[]; -#endif - diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h deleted file mode 100644 index 8114c6714..000000000 --- a/include/opcode/hppa.h +++ /dev/null @@ -1,1027 +0,0 @@ -/* Table of opcodes for the PA-RISC. - Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, - 2001, 2002, 2003, 2004, 2005 - Free Software Foundation, Inc. - - Contributed by the Center for Software Science at the - University of Utah (pa-gdb-bugs@cs.utah.edu). - -This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. - -GAS/GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GAS/GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GAS or GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#if !defined(__STDC__) && !defined(const) -#define const -#endif - -/* - * Structure of an opcode table entry. - */ - -/* There are two kinds of delay slot nullification: normal which is - * controled by the nullification bit, and conditional, which depends - * on the direction of the branch and its success or failure. - * - * NONE is unfortunately #defined in the hiux system include files. - * #undef it away. - */ -#undef NONE -struct pa_opcode -{ - const char *name; - unsigned long int match; /* Bits that must be set... */ - unsigned long int mask; /* ... in these bits. */ - char *args; - enum pa_arch arch; - char flags; -}; - -/* Enable/disable strict syntax checking. When strict syntax checking - is not used, out-of-range immediate fields can result in an error, - depending on the specific immediate range being matched. An immediate - value of zero is also accepted as equivalent to index register 0. - As a result, non-strict opcode entries must be ordered from largest - to smallest immediate range. */ -#define FLAG_STRICT 0x1 - -/* - All hppa opcodes are 32 bits. - - The match component is a mask saying which bits must match a - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing one character for each operand of - the instruction. Characters used as a prefix allow any second character to - be used without conflicting with the main operand characters. - - Bit positions in this description follow HP usage of lsb = 31, - "at" is lsb of field. - - In the args field, the following characters must match exactly: - - '+,() ' - - In the args field, the following characters are unused: - - ' " - / 34 6789:; ' - '@ C M [\] ' - '` e g } ' - - Here are all the characters: - - ' !"#$%&'()*+-,./0123456789:;<=>?' - '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_' - '`abcdefghijklmnopqrstuvwxyz{|}~ ' - -Kinds of operands: - x integer register field at 15. - b integer register field at 10. - t integer register field at 31. - a integer register field at 10 and 15 (for PERMH) - 5 5 bit immediate at 15. - s 2 bit space specifier at 17. - S 3 bit space specifier at 18. - V 5 bit immediate value at 31 - i 11 bit immediate value at 31 - j 14 bit immediate value at 31 - k 21 bit immediate value at 31 - l 16 bit immediate value at 31 (wide mode only, unusual encoding). - n nullification for branch instructions - N nullification for spop and copr instructions - w 12 bit branch displacement - W 17 bit branch displacement (PC relative) - X 22 bit branch displacement (PC relative) - z 17 bit branch displacement (just a number, not an address) - -Also these: - - . 2 bit shift amount at 25 - * 4 bit shift amount at 25 - p 5 bit shift count at 26 (to support the SHD instruction) encoded as - 31-p - ~ 6 bit shift count at 20,22:26 encoded as 63-~. - P 5 bit bit position at 26 - q 6 bit bit position at 20,22:26 - T 5 bit field length at 31 (encoded as 32-T) - % 6 bit field length at 23,27:31 (variable extract/deposit) - | 6 bit field length at 19,27:31 (fixed extract/deposit) - A 13 bit immediate at 18 (to support the BREAK instruction) - ^ like b, but describes a control register - ! sar (cr11) register - D 26 bit immediate at 31 (to support the DIAG instruction) - $ 9 bit immediate at 28 (to support POPBTS) - - v 3 bit Special Function Unit identifier at 25 - O 20 bit Special Function Unit operation split between 15 bits at 20 - and 5 bits at 31 - o 15 bit Special Function Unit operation at 20 - 2 22 bit Special Function Unit operation split between 17 bits at 20 - and 5 bits at 31 - 1 15 bit Special Function Unit operation split between 10 bits at 20 - and 5 bits at 31 - 0 10 bit Special Function Unit operation split between 5 bits at 20 - and 5 bits at 31 - u 3 bit coprocessor unit identifier at 25 - F Source Floating Point Operand Format Completer encoded 2 bits at 20 - I Source Floating Point Operand Format Completer encoded 1 bits at 20 - (for 0xe format FP instructions) - G Destination Floating Point Operand Format Completer encoded 2 bits at 18 - H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' - (very similar to 'F') - - r 5 bit immediate value at 31 (for the break instruction) - (very similar to V above, except the value is unsigned instead of - low_sign_ext) - R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) - (same as r above, except the value is in a different location) - U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) - Q 5 bit immediate value at 10 (a bit position specified in - the bb instruction. It's the same as r above, except the - value is in a different location) - B 5 bit immediate value at 10 (a bit position specified in - the bb instruction. Similar to Q, but 64 bit handling is - different. - Z %r1 -- implicit target of addil instruction. - L ,%r2 completer for new syntax branch - { Source format completer for fcnv - _ Destination format completer for fcnv - h cbit for fcmp - = gfx tests for ftest - d 14 bit offset for single precision FP long load/store. - # 14 bit offset for double precision FP load long/store. - J Yet another 14 bit offset for load/store with ma,mb completers. - K Yet another 14 bit offset for load/store with ma,mb completers. - y 16 bit offset for word aligned load/store (PA2.0 wide). - & 16 bit offset for dword aligned load/store (PA2.0 wide). - < 16 bit offset for load/store with ma,mb completers (PA2.0 wide). - > 16 bit offset for load/store with ma,mb completers (PA2.0 wide). - Y %sr0,%r31 -- implicit target of be,l instruction. - @ implicit immediate value of 0 - -Completer operands all have 'c' as the prefix: - - cx indexed load completer. - cX indexed load completer. Like cx, but emits a space after - in disassembler. - cm short load and store completer. - cM short load and store completer. Like cm, but emits a space - after in disassembler. - cq long load and store completer (like cm, but inserted into a - different location in the target instruction). - cs store bytes short completer. - cA store bytes short completer. Like cs, but emits a space - after in disassembler. - ce long load/store completer for LDW/STW with a different encoding - than the others - cc load cache control hint - cd load and clear cache control hint - cC store cache control hint - co ordered access - - cp branch link and push completer - cP branch pop completer - cl branch link completer - cg branch gate completer - - cw read/write completer for PROBE - cW wide completer for MFCTL - cL local processor completer for cache control - cZ System Control Completer (to support LPA, LHA, etc.) - - ci correction completer for DCOR - ca add completer - cy 32 bit add carry completer - cY 64 bit add carry completer - cv signed overflow trap completer - ct trap on condition completer for ADDI, SUB - cT trap on condition completer for UADDCM - cb 32 bit borrow completer for SUB - cB 64 bit borrow completer for SUB - - ch left/right half completer - cH signed/unsigned saturation completer - cS signed/unsigned completer at 21 - cz zero/sign extension completer. - c* permutation completer - -Condition operands all have '?' as the prefix: - - ?f Floating point compare conditions (encoded as 5 bits at 31) - - ?a add conditions - ?A 64 bit add conditions - ?@ add branch conditions followed by nullify - ?d non-negated add branch conditions - ?D negated add branch conditions - ?w wide mode non-negated add branch conditions - ?W wide mode negated add branch conditions - - ?s compare/subtract conditions - ?S 64 bit compare/subtract conditions - ?t non-negated compare and branch conditions - ?n 32 bit compare and branch conditions followed by nullify - ?N 64 bit compare and branch conditions followed by nullify - ?Q 64 bit compare and branch conditions for CMPIB instruction - - ?l logical conditions - ?L 64 bit logical conditions - - ?b branch on bit conditions - ?B 64 bit branch on bit conditions - - ?x shift/extract/deposit conditions - ?X 64 bit shift/extract/deposit conditions - ?y shift/extract/deposit conditions followed by nullify for conditional - branches - - ?u unit conditions - ?U 64 bit unit conditions - -Floating point registers all have 'f' as a prefix: - - ft target register at 31 - fT target register with L/R halves at 31 - fa operand 1 register at 10 - fA operand 1 register with L/R halves at 10 - fX Same as fA, except prints a space before register during disasm - fb operand 2 register at 15 - fB operand 2 register with L/R halves at 15 - fC operand 3 register with L/R halves at 16:18,21:23 - fe Like fT, but encoding is different. - fE Same as fe, except prints a space before register during disasm. - fx target register at 15 (only for PA 2.0 long format FLDD/FSTD). - -Float registers for fmpyadd and fmpysub: - - fi mult operand 1 register at 10 - fj mult operand 2 register at 15 - fk mult target register at 20 - fl add/sub operand register at 25 - fm add/sub target register at 31 - -*/ - - -#if 0 -/* List of characters not to put a space after. Note that - "," is included, as the "spopN" operations use literal - commas in their completer sections. */ -static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}"; -#endif - -/* The order of the opcodes in this table is significant: - - * The assembler requires that all instances of the same mnemonic be - consecutive. If they aren't, the assembler will bomb at runtime. - - * The disassembler does not care about the order of the opcodes - except in cases where implicit addressing is used. - - Strict syntax (FLAG_STRICT) should be used for pa11 opcodes - and later. - - Here are the rules for ordering the opcodes of a mnemonic: - - 1) Opcodes with FLAG_STRICT precede opcodes without FLAG_STRICT, - - 2) Opcodes with FLAG_STRICT should be ordered as follows: - register index opcodes, short immediate opcodes, and finally - long immediate opcodes. Where there are opcodes for more - than one architecture in any of these groups, the opcodes - for the higher architecture should come first, - - 3) Where implicit addressing is available for an opcode, the - implicit opcode should precede the explicit opcode, and - - 4) Opcodes without FLAG_STRICT should be order as follows: long - immediate opcodes, short immediate opcodes and finally register - index opcodes. */ - -static const struct pa_opcode pa_opcodes[] = -{ - -/* Pseudo-instructions. */ - -{ "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ -{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ - -{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, -{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, -{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ -{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, -{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, -{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, -{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, -{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, -{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ -/* This entry is for the disassembler only. It will never be used by - assembler. */ -{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ -{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ -{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ -{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ - -/* Loads and Stores for integer registers. */ - -{ "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, 0}, -{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, 0}, -{ "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, -{ "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldh", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldb", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldb", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, -{ "ldb", 0x40000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldb", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldb", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldb", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "std", 0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "std", 0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, -{ "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, -{ "std", 0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT}, -{ "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, -{ "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT}, -{ "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, -{ "stw", 0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT}, -{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, -{ "stw", 0x6c000000, 0xfc00c000, "cex,J(b)", pa10, 0}, -{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, 0}, -{ "stw", 0x68000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "stw", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stw", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "sth", 0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "sth", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, -{ "sth", 0x64000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "sth", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "sth", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "stb", 0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stb", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, -{ "stb", 0x60000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "stb", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stb", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "ldwm", 0x4c000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "stwm", 0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldwx", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldhx", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldbx", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldwa", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldwa", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldcw", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, -{ "ldcw", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldcw", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldcw", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldcw", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stwa", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stby", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, -{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stby", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0}, -{ "stby", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, -{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, -{ "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, -{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, -{ "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, -{ "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, -{ "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT}, -{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0}, -{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, - -/* Immediate instructions. */ -{ "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, -{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, -{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, -{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, -{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, - -/* Branching instructions. */ -{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, -{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, -{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, -{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, -{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ -{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, -{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, -{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, -{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, -{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, -{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, -{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, -{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, -{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, -{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, -{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, -{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, -{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, -{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, -{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, -{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, -{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, -{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, -{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, -{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, -{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, -{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, -{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, -{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, -{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, -{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, -{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, -{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, -{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, - -/* Computation Instructions. */ - -{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, -{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, -{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, -{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, -{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, -{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, -{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, -{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, -{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, -{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, -{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, -{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, -{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, -{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, -{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, -{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, -{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, -{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, -{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, -{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, -{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, -{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, -{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, -{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, -{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, -{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, -{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, -{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, -{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, -{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, -{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, -{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, -{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, -{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, -{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, -{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, -{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, -{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, - -/* Subword Operation Instructions. */ - -{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, -{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, -{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, -{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, -{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, -{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, -{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, -{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, -{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, -{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, - - -/* Extract and Deposit Instructions. */ - -{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, -{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, -{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, -{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, -{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, -{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, -{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, -{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, -{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, -{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, -{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, -{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, -{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, -{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, -{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, -{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, -{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, -{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, -{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, -{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, -{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, -{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, -{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, -{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, -{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, -{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, -{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, -{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, -{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, -{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, - -/* System Control Instructions. */ - -{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, -{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, -{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, -{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, -{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, -{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, -{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, -{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, -{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, -{ "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, -{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, -{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, -{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, -{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, -{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, -{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, -{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, -{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, -{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, -{ "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT}, -{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, -{ "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT}, -{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, -{ "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0}, -{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, -{ "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0}, -{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, -{ "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0}, -{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, -{ "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, -{ "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0}, -{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, -{ "lha", 0x04001300, 0xfc00ffc0, "cZx(b),t", pa10, 0}, -{ "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, -{ "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa10, 0}, -{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0}, -{ "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, -{ "pitlb", 0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT}, -{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, -{ "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, -{ "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, -{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, -{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, -{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, - -/* These may be specific to certain versions of the PA. Joel claimed - they were 72000 (7200?) specific. However, I'm almost certain the - mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ -{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, -{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, -{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, -{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, -{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, -{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, - -/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either - the Timex FPU or the Mustang ERS (not sure which) manual. */ -{ "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, -{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, -{ "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0}, -{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, - -/* Floating Point Coprocessor Instructions. */ - -{ "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, 0}, -{ "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, 0}, -{ "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0}, -{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, -{ "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, 0}, -{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, 0}, -{ "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0}, -{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, -{ "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, 0}, -{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, 0}, -{ "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, 0}, -{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, 0}, -{ "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0}, -{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0}, -{ "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0}, -{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0}, -{ "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0}, -{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, -{ "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0}, -{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, -{ "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, -{ "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0}, -{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, -{ "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0}, -{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, -{ "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0}, -{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, -{ "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, -{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, -{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, -{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, -{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, -{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, -{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, -{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, -{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, -{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, -{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, -{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, -{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, -{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, -{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, -{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, -{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, -{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, -{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, -{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, -{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, -{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, -{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, -{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, -{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, -{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, -{ "ftest", 0x30002420, 0xffffffff, "", pa10, 0}, -{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, - -/* Performance Monitor Instructions. */ - -{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, -{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, - -/* Assist Instructions. */ - -{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, -{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, -{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, -{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, -{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, -{ "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, -{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, -{ "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, -{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, -{ "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, -{ "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, -{ "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, -{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, -{ "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, -{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, -{ "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, -{ "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, -{ "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, -{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, -{ "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, -{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, - -/* More pseudo instructions which must follow the main table. */ -{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, -{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, -{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, - -}; - -#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) - -/* SKV 12/18/92. Added some denotations for various operands. */ - -#define PA_IMM11_AT_31 'i' -#define PA_IMM14_AT_31 'j' -#define PA_IMM21_AT_31 'k' -#define PA_DISP12 'w' -#define PA_DISP17 'W' - -#define N_HPPA_OPERAND_FORMATS 5 diff --git a/include/opcode/i370.h b/include/opcode/i370.h deleted file mode 100644 index bdbb2f421..000000000 --- a/include/opcode/i370.h +++ /dev/null @@ -1,265 +0,0 @@ -/* i370.h -- Header file for S/390 opcode table - Copyright 1994, 1995, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. - PowerPC version written by Ian Lance Taylor, Cygnus Support - Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef I370_H -#define I370_H - -/* The opcode table is an array of struct i370_opcode. */ -typedef union -{ - unsigned int i[2]; - unsigned short s[4]; - unsigned char b[8]; -} i370_insn_t; - -struct i370_opcode -{ - /* The opcode name. */ - const char *name; - - /* the length of the instruction */ - char len; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - i370_insn_t opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - i370_insn_t mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct i370_opcode i370_opcodes[]; -extern const int i370_num_opcodes; - -/* Values defined for the flags field of a struct i370_opcode. */ - -/* Opcode is defined for the original 360 architecture. */ -#define I370_OPCODE_360 (0x01) - -/* Opcode is defined for the 370 architecture. */ -#define I370_OPCODE_370 (0x02) - -/* Opcode is defined for the 370-XA architecture. */ -#define I370_OPCODE_370_XA (0x04) - -/* Opcode is defined for the ESA/370 architecture. */ -#define I370_OPCODE_ESA370 (0x08) - -/* Opcode is defined for the ESA/390 architecture. */ -#define I370_OPCODE_ESA390 (0x10) - -/* Opcode is defined for the ESA/390 w/ BFP facility. */ -#define I370_OPCODE_ESA390_BF (0x20) - -/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ -#define I370_OPCODE_ESA390_BS (0x40) - -/* Opcode is defined for the ESA/390 w/ checksum facility. */ -#define I370_OPCODE_ESA390_CK (0x80) - -/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ -#define I370_OPCODE_ESA390_CM (0x100) - -/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ -#define I370_OPCODE_ESA390_FX (0x200) - -/* Opcode is defined for the ESA/390 w/ HFP facility. */ -#define I370_OPCODE_ESA390_HX (0x400) - -/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ -#define I370_OPCODE_ESA390_IR (0x800) - -/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ -#define I370_OPCODE_ESA390_MI (0x1000) - -/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ -#define I370_OPCODE_ESA390_PC (0x2000) - -/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ -#define I370_OPCODE_ESA390_PL (0x4000) - -/* Opcode is defined for the ESA/390 w/ square-root facility. */ -#define I370_OPCODE_ESA390_QR (0x8000) - -/* Opcode is defined for the ESA/390 w/ resume-program facility. */ -#define I370_OPCODE_ESA390_RP (0x10000) - -/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ -#define I370_OPCODE_ESA390_SA (0x20000) - -/* Opcode is defined for the ESA/390 w/ subspace group facility. */ -#define I370_OPCODE_ESA390_SG (0x40000) - -/* Opcode is defined for the ESA/390 w/ string facility. */ -#define I370_OPCODE_ESA390_SR (0x80000) - -/* Opcode is defined for the ESA/390 w/ trap facility. */ -#define I370_OPCODE_ESA390_TR (0x100000) - -#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) - - -/* The operands table is an array of struct i370_operand. */ - -struct i370_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - i370_insn_t (*insert) - (i370_insn_t instruction, long op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & I370_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (i370_insn_t instruction, int *invalid); - - /* One bit syntax flags. */ - unsigned long flags; - - /* name -- handy for debugging, otherwise pointless */ - char * name; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the i370_opcodes table. */ - -extern const struct i370_operand i370_operands[]; - -/* Values defined for the flags field of a struct i370_operand. */ - -/* This operand should be wrapped in parentheses rather than - separated from the previous by a comma. This is used for S, RS and - SS form instructions which want their operands to look like - reg,displacement(basereg) */ -#define I370_OPERAND_SBASE (0x01) - -/* This operand is a base register. It may or may not appear next - to an index register, i.e. either of the two forms - reg,displacement(basereg) - reg,displacement(index,basereg) */ -#define I370_OPERAND_BASE (0x02) - -/* This pair of operands should be wrapped in parentheses rather than - separated from the last by a comma. This is used for the RX form - instructions which want their operands to look like - reg,displacement(index,basereg) */ -#define I370_OPERAND_INDEX (0x04) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define I370_OPERAND_GPR (0x08) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define I370_OPERAND_FPR (0x10) - -/* This operand is a displacement. */ -#define I370_OPERAND_RELATIVE (0x20) - -/* This operand is a length, such as that in SS form instructions. */ -#define I370_OPERAND_LENGTH (0x40) - -/* This operand is optional, and is zero if omitted. This is used for - the optional B2 field in the shift-left, shift-right instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define I370_OPERAND_OPTIONAL (0x80) - - -/* Define some misc macros. We keep them with the operands table - for simplicity. The macro table is an array of struct i370_macro. */ - -struct i370_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct i370_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct i370_macro i370_macros[]; -extern const int i370_num_macros; - - -#endif /* I370_H */ diff --git a/include/opcode/i386.h b/include/opcode/i386.h deleted file mode 100644 index 59b5e3c33..000000000 --- a/include/opcode/i386.h +++ /dev/null @@ -1,1670 +0,0 @@ -/* opcode/i386.h -- Intel 80386 opcode table - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004, 2005 - Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived - ix86 Unix assemblers, generate floating point instructions with - reversed source and destination registers in certain cases. - Unfortunately, gcc and possibly many other programs use this - reversed syntax, so we're stuck with it. - - eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but - `fsub %st,%st(3)' results in st(3) = st - st(3), rather than - the expected st(3) = st(3) - st - - This happens with all the non-commutative arithmetic floating point - operations with two register operands, where the source register is - %st, and destination register is %st(i). See FloatDR below. - - The affected opcode map is dceX, dcfX, deeX, defX. */ - -#ifndef SYSV386_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes at your peril. gcc generates SystemV/386 - compatible instructions. */ -#define SYSV386_COMPAT 1 -#endif -#ifndef OLDGCC_COMPAT -/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could - generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands - reversed. */ -#define OLDGCC_COMPAT SYSV386_COMPAT -#endif - -static const template i386_optab[] = -{ - -#define X None -#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) -#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) -#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) -#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) -#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) -#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) -#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) -#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) -#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) -#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) -#define bwlq_Suf (No_sSuf|No_xSuf) -#define FP (NoSuf) -#define l_FP (l_Suf) -#define q_FP (q_Suf|NoRex64) -#define x_FP (x_Suf|FloatMF) -#define sl_FP (sl_Suf|FloatMF) -#if SYSV386_COMPAT -/* Someone forgot that the FloatR bit reverses the operation when not - equal to the FloatD bit. ie. Changing only FloatD results in the - destination being swapped *and* the direction being reversed. */ -#define FloatDR FloatD -#else -#define FloatDR (FloatD|FloatR) -#endif - -/* Move instructions. */ -#define MOV_AX_DISP32 0xa0 -/* We put the 64bit displacement first and we only mark constants - larger than 32bit as Disp64. */ -{ "mov", 2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, -{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, -{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit value. */ -{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, -{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, -{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, -/* The segment register moves accept WordReg so that a segment register - can be copied to a 32 bit register, and vice versa, without using a - size prefix. When moving to a 32 bit register, the upper 16 bits - are set to an implementation defined value (on the Pentium Pro, - the implementation defined value is zero). */ -{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } }, -{ "mov", 2, 0x8c, X, 0, w_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } }, -{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg2, 0 } }, -{ "mov", 2, 0x8e, X, 0, w_Suf|Modrm|IgnoreSize, { WordMem, SReg2, 0 } }, -{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg3, 0 } }, -{ "mov", 2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize, { WordMem, SReg3, 0 } }, -/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit - mode they are 64bit.*/ -{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, -{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, -{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, - -/* Move with sign extend. */ -/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid - conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, -{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, -{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, -/* Intel Syntax next 3 insns */ -{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, -{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, - -/* Move with zero extend. We can't remove "movzb" since existing - assembly codes may use it. */ -{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -/* "movzbl" & "movzbw" should not be unified into "movzb" for - consistency with the sign extending moves above. */ -{"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, -{"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, -{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* These instructions are not particulary useful, since the zero extend - 32->64 is implicit, but we can encode them. */ -{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, -/* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful, - since the zero extend 32->64 is implicit, but we can encode them). */ -{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, - -/* Push instructions. */ -{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -/* In 64bit mode, the operand size is implicitly 64bit. */ -{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, -{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, -{"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, - -{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, - -/* Pop instructions. */ -{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, -#define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -/* In 64bit mode, the operand size is implicitly 64bit. */ -{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, -{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, - -{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, - -/* Exchange instructions. - xchg commutes: we allow both operand orders. - - In the 64bit code, xchg eax, eax is reused for new nop instruction. */ -#if 0 /* While the two entries that are disabled generate shorter code - for xchg eax, reg (on x86_64), the special case xchg eax, eax - does not get handled correctly - it degenerates into nop, but - that way the side effect of zero-extending eax to rax is lost. */ -{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, -#else -{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, -{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } }, -{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } }, -#endif -{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, - -/* In/out from ports. */ -/* XXX should reject %rax */ -{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, -{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, -{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, -{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, -{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, -{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, -{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, -{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, - -/* Load effective address. */ -{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, - -/* Load segment registers from memory. */ -{"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, - -/* Flags register instructions. */ -{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, -{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, -{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, -{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, -{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, -{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, -{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, -{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, -{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, - -/* Arithmetic. */ -{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, -{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -/* clr with 1 operand is really xor with 2 operands. */ -{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, - -{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, -{"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, - -/* Conversion insns. */ -/* Intel naming */ -{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -/* AT&T naming */ -{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, - -/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are - expanding 64-bit multiplies, and *cannot* be selected to accomplish - 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) - These multiplies can only be selected with single operand forms. */ -{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, -/* imul with 2 operands mimics imul with 3 by putting the register in - both i.rm.reg & i.rm.regmem fields. regKludge enables this - transformation. */ -{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, -{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, - -{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, -{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, - -{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -/* Control transfer instructions. */ -{"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax */ -{"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax */ -{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, -{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, - -#define JUMP_PC_RELATIVE 0xeb -{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} }, -{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax. */ -{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax. */ -{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, -{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, - -{"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} }, -{"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, -{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, -{"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} }, -{"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} }, - -/* Conditional jumps. */ -{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, - -/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ -{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, -{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, -{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, -{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, - -/* The loop instructions also use the address size prefix to select - %cx rather than %ecx for the loop count, so the `w' form of these - instructions emit an address size prefix rather than a data size - prefix. */ -{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, - -/* Set byte on flag instructions. */ -{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, - -/* String manipulation. */ -{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, -{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, -{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, -{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, -{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, -{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, -{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, -{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, - -/* Bit manipulation. */ -{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, - -/* Interrupts & op. sys insns. */ -/* See gas/config/tc-i386.c for conversion of 'int $3' into the special - int 3 insn. */ -#define INT_OPCODE 0xcd -#define INT3_OPCODE 0xcc -{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, -{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, -{"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, -/* i386sl, i486sl, later 486, and Pentium. */ -{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, - -{"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} }, - -{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, -/* nop is actually 'xchgl %eax, %eax'. */ -{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, - -/* Protection control. */ -{"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, - -{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -/* Floating point instructions. */ - -/* load */ -{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -/* Intel Syntax */ -{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} }, -{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, - -/* store (no pop) */ -{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -{"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -/* store (with pop) */ -{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -/* Intel Syntax */ -{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} }, -{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, - -/* exchange %st<n> with %st0 */ -{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fxch %st(1) */ -{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, - -/* comparison (without pop) */ -{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fcom %st(1) */ -{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, -{"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -{"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -/* comparison (with pop) */ -{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fcomp %st(1) */ -{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, -{"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -{"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, - -/* unordered comparison (with pop) */ -{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fucom %st(1) */ -{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, -{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fucomp %st(1) */ -{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, -{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, - -{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, -{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, - -/* load constants into %st0 */ -{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, -{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, -{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, -{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, -{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, -{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, -{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, - -/* Arithmetic. */ - -/* add */ -{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -/* alias for fadd %st(i), %st */ -{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for faddp */ -{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for faddp %st, %st(1) */ -{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, -{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, - -/* subtract */ -{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fsubp */ -{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, -#endif - -/* subtract reverse */ -{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fsubrp */ -{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, -#endif - -/* multiply */ -{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fmulp */ -{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, -{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, - -/* divide */ -{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fdivp */ -{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, -#endif - -/* divide reverse */ -{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fdivrp */ -{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, -#endif - -{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, -{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, -{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, -{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, -{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, -{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, -{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, -{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, -{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, -{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, -{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, -{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, -{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, -{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, -{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, -{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, -{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, -{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, - -/* processor control */ -{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, -{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, -{"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, -{"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, -{"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, -/* XXX should reject %al, %eax, and %rax */ -{"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} }, -{"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, -/* XXX should reject %al, %eax, and %rax */ -{"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} }, -{"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, -{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, -{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, -{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, -/* Short forms of fldenv, fstenv use data size prefix. */ -{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, - -{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* P6:free st(i), pop st */ -{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, -#define FWAIT_OPCODE 0x9b -{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, - -/* Opcode prefixes; we allow them as separate insns too. */ - -#define ADDR_PREFIX_OPCODE 0x67 -{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -#define DATA_PREFIX_OPCODE 0x66 -{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -#define LOCK_PREFIX_OPCODE 0xf0 -{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -#define CS_PREFIX_OPCODE 0x2e -{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -#define DS_PREFIX_OPCODE 0x3e -{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -#define ES_PREFIX_OPCODE 0x26 -{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, -#define FS_PREFIX_OPCODE 0x64 -{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, -#define GS_PREFIX_OPCODE 0x65 -{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, -#define SS_PREFIX_OPCODE 0x36 -{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, -#define REPNE_PREFIX_OPCODE 0xf2 -#define REPE_PREFIX_OPCODE 0xf3 -{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"ht", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"hnt", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, - -/* 486 extensions. */ - -{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, -{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} }, - -/* 586 and late 486 extensions. */ -{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, - -/* Pentium extensions. */ -{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} }, - -/* Pentium II/Pentium Pro extensions. */ -{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, -{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* official undefined instr. */ -{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* alias for ud2 */ -{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* 2nd. official undefined instr. */ -{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, - -{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, - -/* Pentium4 extensions. */ - -{"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } }, -{"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } }, -{"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, -{"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, -{"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } }, - -/* MMX/SSE2 instructions. */ - -{"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } }, -/* These really shouldn't allow for Reg64 (movq is the right mnemonic for - copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's - spec). AMD's spec, having been in existence for much longer, failed to - recognize that and specified movd for 32- and 64-bit operations. */ -{"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit displacement value. */ -{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } }, -{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movq", 2, 0x0f6e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, -{"movq", 2, 0x660f6e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660f7e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, -/* We put the 64bit displacement first and we only mark constants - larger than 32bit as Disp64. */ -{"movq", 2, 0xa0, X, Cpu64, NoSuf|D|W|Size64, { Disp64, Acc, 0 } }, -{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, -{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, -{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, -/* The segment register moves accept Reg64 so that a segment register - can be copied to a 64 bit register, and vice versa. */ -{"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|InvMem, 0 } }, -{"movq", 2, 0x8e, X, Cpu64, NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } }, -/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit - mode they are 64bit.*/ -{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, -{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, -/* Real MMX instructions. */ -{"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* PIII Katmai New Instructions / SIMD instructions. */ - -{"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, -{"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, -{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, -{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } }, -{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, -{"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, -{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, -{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, -{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, -{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, -{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, -{"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } }, -{"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, -{"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* SSE-2 instructions. */ - -{"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -/* Intel mode string compare. */ -{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, -{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, -{"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -/* Intel mode string move. */ -{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, -{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, -{"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, -{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, -{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, -{"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* Prescott New Instructions. */ - -{"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, -{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} }, -{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"haddpd", 2, 0x660f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"haddps", 2, 0xf20f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubpd", 2, 0x660f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubps", 2, 0xf20f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"lddqu", 2, 0xf20ff0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"monitor", 0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, -/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ -{"monitor", 3, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, Reg32} }, -{"movddup", 2, 0xf20f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movshdup", 2, 0xf30f16, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movsldup", 2, 0xf30f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mwait", 0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, -/* Need to ensure only "mwait %eax,%ecx" is accepted. */ -{"mwait", 2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, 0} }, - -/* VMX instructions. */ -{"vmcall", 0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmclear", 1, 0x660fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"vmlaunch", 0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmresume", 0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmptrld", 1, 0x0fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"vmptrst", 1, 0x0fc7, 7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"vmread", 2, 0x0f78, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} }, -{"vmread", 2, 0x0f78, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} }, -{"vmwrite", 2, 0x0f79, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} }, -{"vmwrite", 2, 0x0f79, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} }, -{"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, - -/* AMD 3DNow! instructions. */ - -{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, - -/* AMD extensions. */ -{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, -{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, -{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, -{"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, - -/* AMD Pacifica additions. */ -{"clgi", 0, 0x0f01, 0xdd, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"invlpga", 0, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -/* Need to ensure only "invlpga ...,%ecx" is accepted. */ -{"invlpga", 2, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { AnyMem, Reg32, 0 } }, -{"skinit", 0, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"skinit", 1, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, -{"stgi", 0, 0x0f01, 0xdc, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmload", 0, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmload", 1, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, -{"vmmcall", 0, 0x0f01, 0xd9, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmrun", 0, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmrun", 1, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, -{"vmsave", 0, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmsave", 1, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, - -/* VIA PadLock extensions. */ -{"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -/* Aliases without hyphens. */ -{"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -/* Alias for xstore-rng. */ -{"xstore", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, - -/* sentinel */ -{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } -}; -#undef X -#undef NoSuf -#undef b_Suf -#undef w_Suf -#undef l_Suf -#undef q_Suf -#undef x_Suf -#undef bw_Suf -#undef bl_Suf -#undef wl_Suf -#undef wlq_Suf -#undef sl_Suf -#undef bwl_Suf -#undef bwlq_Suf -#undef FP -#undef l_FP -#undef q_FP -#undef x_FP -#undef sl_FP - -#define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */ - -/* 386 register table. */ - -static const reg_entry i386_regtab[] = -{ - /* Make %st first as we test for it. */ - {"st", FloatReg|FloatAcc, 0, 0}, - /* 8 bit regs */ -#define REGNAM_AL 1 /* Entry in i386_regtab. */ - {"al", Reg8|Acc, 0, 0}, - {"cl", Reg8|ShiftCount, 0, 1}, - {"dl", Reg8, 0, 2}, - {"bl", Reg8, 0, 3}, - {"ah", Reg8, 0, 4}, - {"ch", Reg8, 0, 5}, - {"dh", Reg8, 0, 6}, - {"bh", Reg8, 0, 7}, - {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ - {"cxl", Reg8, RegRex64, 1}, - {"dxl", Reg8, RegRex64, 2}, - {"bxl", Reg8, RegRex64, 3}, - {"spl", Reg8, RegRex64, 4}, - {"bpl", Reg8, RegRex64, 5}, - {"sil", Reg8, RegRex64, 6}, - {"dil", Reg8, RegRex64, 7}, - {"r8b", Reg8, RegRex64|RegRex, 0}, - {"r9b", Reg8, RegRex64|RegRex, 1}, - {"r10b", Reg8, RegRex64|RegRex, 2}, - {"r11b", Reg8, RegRex64|RegRex, 3}, - {"r12b", Reg8, RegRex64|RegRex, 4}, - {"r13b", Reg8, RegRex64|RegRex, 5}, - {"r14b", Reg8, RegRex64|RegRex, 6}, - {"r15b", Reg8, RegRex64|RegRex, 7}, - /* 16 bit regs */ -#define REGNAM_AX 25 - {"ax", Reg16|Acc, 0, 0}, - {"cx", Reg16, 0, 1}, - {"dx", Reg16|InOutPortReg, 0, 2}, - {"bx", Reg16|BaseIndex, 0, 3}, - {"sp", Reg16, 0, 4}, - {"bp", Reg16|BaseIndex, 0, 5}, - {"si", Reg16|BaseIndex, 0, 6}, - {"di", Reg16|BaseIndex, 0, 7}, - {"r8w", Reg16, RegRex, 0}, - {"r9w", Reg16, RegRex, 1}, - {"r10w", Reg16, RegRex, 2}, - {"r11w", Reg16, RegRex, 3}, - {"r12w", Reg16, RegRex, 4}, - {"r13w", Reg16, RegRex, 5}, - {"r14w", Reg16, RegRex, 6}, - {"r15w", Reg16, RegRex, 7}, - /* 32 bit regs */ -#define REGNAM_EAX 41 - {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */ - {"ecx", Reg32|BaseIndex, 0, 1}, - {"edx", Reg32|BaseIndex, 0, 2}, - {"ebx", Reg32|BaseIndex, 0, 3}, - {"esp", Reg32, 0, 4}, - {"ebp", Reg32|BaseIndex, 0, 5}, - {"esi", Reg32|BaseIndex, 0, 6}, - {"edi", Reg32|BaseIndex, 0, 7}, - {"r8d", Reg32|BaseIndex, RegRex, 0}, - {"r9d", Reg32|BaseIndex, RegRex, 1}, - {"r10d", Reg32|BaseIndex, RegRex, 2}, - {"r11d", Reg32|BaseIndex, RegRex, 3}, - {"r12d", Reg32|BaseIndex, RegRex, 4}, - {"r13d", Reg32|BaseIndex, RegRex, 5}, - {"r14d", Reg32|BaseIndex, RegRex, 6}, - {"r15d", Reg32|BaseIndex, RegRex, 7}, - {"rax", Reg64|BaseIndex|Acc, 0, 0}, - {"rcx", Reg64|BaseIndex, 0, 1}, - {"rdx", Reg64|BaseIndex, 0, 2}, - {"rbx", Reg64|BaseIndex, 0, 3}, - {"rsp", Reg64, 0, 4}, - {"rbp", Reg64|BaseIndex, 0, 5}, - {"rsi", Reg64|BaseIndex, 0, 6}, - {"rdi", Reg64|BaseIndex, 0, 7}, - {"r8", Reg64|BaseIndex, RegRex, 0}, - {"r9", Reg64|BaseIndex, RegRex, 1}, - {"r10", Reg64|BaseIndex, RegRex, 2}, - {"r11", Reg64|BaseIndex, RegRex, 3}, - {"r12", Reg64|BaseIndex, RegRex, 4}, - {"r13", Reg64|BaseIndex, RegRex, 5}, - {"r14", Reg64|BaseIndex, RegRex, 6}, - {"r15", Reg64|BaseIndex, RegRex, 7}, - /* Segment registers. */ - {"es", SReg2, 0, 0}, - {"cs", SReg2, 0, 1}, - {"ss", SReg2, 0, 2}, - {"ds", SReg2, 0, 3}, - {"fs", SReg3, 0, 4}, - {"gs", SReg3, 0, 5}, - /* Control registers. */ - {"cr0", Control, 0, 0}, - {"cr1", Control, 0, 1}, - {"cr2", Control, 0, 2}, - {"cr3", Control, 0, 3}, - {"cr4", Control, 0, 4}, - {"cr5", Control, 0, 5}, - {"cr6", Control, 0, 6}, - {"cr7", Control, 0, 7}, - {"cr8", Control, RegRex, 0}, - {"cr9", Control, RegRex, 1}, - {"cr10", Control, RegRex, 2}, - {"cr11", Control, RegRex, 3}, - {"cr12", Control, RegRex, 4}, - {"cr13", Control, RegRex, 5}, - {"cr14", Control, RegRex, 6}, - {"cr15", Control, RegRex, 7}, - /* Debug registers. */ - {"db0", Debug, 0, 0}, - {"db1", Debug, 0, 1}, - {"db2", Debug, 0, 2}, - {"db3", Debug, 0, 3}, - {"db4", Debug, 0, 4}, - {"db5", Debug, 0, 5}, - {"db6", Debug, 0, 6}, - {"db7", Debug, 0, 7}, - {"db8", Debug, RegRex, 0}, - {"db9", Debug, RegRex, 1}, - {"db10", Debug, RegRex, 2}, - {"db11", Debug, RegRex, 3}, - {"db12", Debug, RegRex, 4}, - {"db13", Debug, RegRex, 5}, - {"db14", Debug, RegRex, 6}, - {"db15", Debug, RegRex, 7}, - {"dr0", Debug, 0, 0}, - {"dr1", Debug, 0, 1}, - {"dr2", Debug, 0, 2}, - {"dr3", Debug, 0, 3}, - {"dr4", Debug, 0, 4}, - {"dr5", Debug, 0, 5}, - {"dr6", Debug, 0, 6}, - {"dr7", Debug, 0, 7}, - {"dr8", Debug, RegRex, 0}, - {"dr9", Debug, RegRex, 1}, - {"dr10", Debug, RegRex, 2}, - {"dr11", Debug, RegRex, 3}, - {"dr12", Debug, RegRex, 4}, - {"dr13", Debug, RegRex, 5}, - {"dr14", Debug, RegRex, 6}, - {"dr15", Debug, RegRex, 7}, - /* Test registers. */ - {"tr0", Test, 0, 0}, - {"tr1", Test, 0, 1}, - {"tr2", Test, 0, 2}, - {"tr3", Test, 0, 3}, - {"tr4", Test, 0, 4}, - {"tr5", Test, 0, 5}, - {"tr6", Test, 0, 6}, - {"tr7", Test, 0, 7}, - /* MMX and simd registers. */ - {"mm0", RegMMX, 0, 0}, - {"mm1", RegMMX, 0, 1}, - {"mm2", RegMMX, 0, 2}, - {"mm3", RegMMX, 0, 3}, - {"mm4", RegMMX, 0, 4}, - {"mm5", RegMMX, 0, 5}, - {"mm6", RegMMX, 0, 6}, - {"mm7", RegMMX, 0, 7}, - {"xmm0", RegXMM, 0, 0}, - {"xmm1", RegXMM, 0, 1}, - {"xmm2", RegXMM, 0, 2}, - {"xmm3", RegXMM, 0, 3}, - {"xmm4", RegXMM, 0, 4}, - {"xmm5", RegXMM, 0, 5}, - {"xmm6", RegXMM, 0, 6}, - {"xmm7", RegXMM, 0, 7}, - {"xmm8", RegXMM, RegRex, 0}, - {"xmm9", RegXMM, RegRex, 1}, - {"xmm10", RegXMM, RegRex, 2}, - {"xmm11", RegXMM, RegRex, 3}, - {"xmm12", RegXMM, RegRex, 4}, - {"xmm13", RegXMM, RegRex, 5}, - {"xmm14", RegXMM, RegRex, 6}, - {"xmm15", RegXMM, RegRex, 7}, - /* No type will make this register rejected for all purposes except - for addressing. This saves creating one extra type for RIP. */ - {"rip", BaseIndex, 0, 0} -}; - -static const reg_entry i386_float_regtab[] = -{ - {"st(0)", FloatReg|FloatAcc, 0, 0}, - {"st(1)", FloatReg, 0, 1}, - {"st(2)", FloatReg, 0, 2}, - {"st(3)", FloatReg, 0, 3}, - {"st(4)", FloatReg, 0, 4}, - {"st(5)", FloatReg, 0, 5}, - {"st(6)", FloatReg, 0, 6}, - {"st(7)", FloatReg, 0, 7} -}; - -#define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */ - -/* Segment stuff. */ -static const seg_entry cs = { "cs", 0x2e }; -static const seg_entry ds = { "ds", 0x3e }; -static const seg_entry ss = { "ss", 0x36 }; -static const seg_entry es = { "es", 0x26 }; -static const seg_entry fs = { "fs", 0x64 }; -static const seg_entry gs = { "gs", 0x65 }; - diff --git a/include/opcode/i860.h b/include/opcode/i860.h deleted file mode 100644 index 7836bff05..000000000 --- a/include/opcode/i860.h +++ /dev/null @@ -1,507 +0,0 @@ -/* Table of opcodes for the i860. - Copyright 1989, 1991, 2000, 2002, 2003 Free Software Foundation, Inc. - -This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. - -GAS/GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GAS/GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GAS or GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ - - -/* Structure of an opcode table entry. */ -struct i860_opcode -{ - /* The opcode name. */ - const char *name; - - /* Bits that must be set. */ - unsigned long match; - - /* Bits that must not be set. */ - unsigned long lose; - - const char *args; - - /* Nonzero if this is a possible expand-instruction. */ - char expand; -}; - - -enum expand_type -{ - E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY -}; - - -/* All i860 opcodes are 32 bits, except for the pseudo-instructions - and the operations utilizing a 32-bit address expression, an - unsigned 32-bit constant, or a signed 32-bit constant. - These opcodes are expanded into a two-instruction sequence for - any situation where the immediate operand does not fit in 32 bits. - In the case of the add and subtract operations the expansion is - to a three-instruction sequence (ex: orh, or, adds). In cases - where the address is to be relocated, the instruction is - expanded to handle the worse case, this could be optimized at - the final link if the actual address were known. - - The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. - These instructions are implemented as a one or two instruction - sequence of other operations. - - The match component is a mask saying which bits must match a - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing one character - for each operand of the instruction. - -Kinds of operands: - # Number used by optimizer. It is ignored. - 1 src1 integer register. - 2 src2 integer register. - d dest register. - c ctrlreg control register. - i 16 bit immediate. - I 16 bit immediate, aligned 2^0. (ld.b) - J 16 bit immediate, aligned 2^1. (ld.s) - K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) - L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) - M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) - 5 5 bit immediate. - l lbroff 26 bit PC relative immediate. - r sbroff 16 bit PC relative immediate. - s split 16 bit immediate. - S split 16 bit immediate, aligned 2^0. (st.b) - T split 16 bit immediate, aligned 2^1. (st.s) - U split 16 bit immediate, aligned 2^2. (st.l) - e src1 floating point register. - f src2 floating point register. - g dest floating point register. */ - - -/* The order of the opcodes in this table is significant. The assembler - requires that all instances of the same mnemonic must be consecutive. - If they aren't, the assembler will not function properly. - - The order of opcodes does not affect the disassembler. */ - -static const struct i860_opcode i860_opcodes[] = -{ -/* REG-Format Instructions. */ -{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ -{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ -{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ -{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ -{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ -{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ -{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ - -{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ -{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ -{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ -{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ - -{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ - -{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ -{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ -{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ -{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ -{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ -{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ -{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ -{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ -{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ -{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ -{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ -{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ - -{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ -{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ -{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ -{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ -{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ -{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ -{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ -{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ -{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ -{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ -{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ -{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ - -{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ -{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ -{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ -{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ -{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ -{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ -{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ -{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ -{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ -{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ -{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ -{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ - -{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ -{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ - -{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ -{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ -{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ -{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ -{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ -{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ -{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ -{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ - -{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ -{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ -{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ -{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ -{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ -{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ -{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ - -{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ -{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ -{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ -{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ - -{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ - -{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ -{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ - -{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ -{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ -{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ -{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ -{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ -{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ -{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ -{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ -{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ -{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ -{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ -{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ - -{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ -{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ -{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ -{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ -{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ -{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ - -/* Core Escape Instruction Format */ -{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ -{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ -{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ -{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ -{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ -{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ -{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ -{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ -{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ -{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ -{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ -{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ -{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ -{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ - -/* CTRL-Format Instructions */ -{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ -{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ -{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ -{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ -{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ -{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ - -/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ -{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, -{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, -{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, -{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, -{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, -{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, -{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, -{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, -{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, -{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, -{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, -{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, -{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, -{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, -{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, -{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, -{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, -{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, -{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, -{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, -{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, -{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, -{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, -{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, -{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, -{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, -{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, -{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, -{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, -{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, -{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, -{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, -{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, -{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, -{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, -{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, -{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, -{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, -{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, -{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, -{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, -{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, -{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, -{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, -{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, -{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, -{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, -{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ -{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, -{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, -{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, -{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, -{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, -{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, -{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, -{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, -{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, -{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, -{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, -{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, -{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, -{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, -{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, -{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, -{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, -{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, -{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, -{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, -{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, -{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, -{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, -{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, -{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, -{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, -{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, -{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, -{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, -{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, -{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, -{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, -{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, -{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, -{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, -{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, -{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, -{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, -{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, -{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, -{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, -{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, -{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, -{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, -{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, -{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, -{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, -{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ -{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, -{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, -{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, -{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, -{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, -{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, -{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, -{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, -{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, -{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, -{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, -{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, -{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, -{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, -{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, -{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, -{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, -{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, -{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, -{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, -{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, -{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, -{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, -{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, -{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, -{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, -{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, -{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, -{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, -{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, -{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, -{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, -{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, -{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, -{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, -{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, -{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, -{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, -{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, -{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, -{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, -{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, -{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, -{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, -{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, - -/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ -{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, -{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, -{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, -{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, -{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, -{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, -{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, -{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, -{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, -{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, -{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, -{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, -{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, -{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, -{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, -{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, -{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, -{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, -{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, -{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, -{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, -{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, -{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, -{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, -{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, -{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, -{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, -{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, -{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, -{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, -{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, -{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, -{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, -{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, -{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, -{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, -{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, -{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, -{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, -{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, -{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, -{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, -{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, -{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, -{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, - -{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ -{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ -{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ -{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ -{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ -{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ -{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ -{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ -{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ -{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ -{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ -{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ -{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ -/* Opcode pfgt has R bit cleared; pfle has R bit set. */ -{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ -{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ -/* Opcode pfgt has R bit cleared; pfle has R bit set. */ -{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ -{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ -{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ -{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ -{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ -{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ -{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ -{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ -{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ -{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ -{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ -{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ -{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ -{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ -{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ -{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ -{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ -{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ -{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ -{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ -{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ -{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ -{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ -{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ -{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ -{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ -{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ - -/* Floating point pseudo-instructions. */ -{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ -{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ -{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ -{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ -{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ -{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ -{ 0, 0, 0, 0, 0 }, - -}; - -#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) - - diff --git a/include/opcode/i960.h b/include/opcode/i960.h deleted file mode 100644 index 0999aa15d..000000000 --- a/include/opcode/i960.h +++ /dev/null @@ -1,525 +0,0 @@ -/* Basic 80960 instruction formats. - - Copyright 2001 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. - - The 'COJ' instructions are actually COBR instructions with the 'b' in - the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary: - if the displacement will not fit in 13 bits, the assembler will replace them - with the corresponding compare and branch instructions. - - All of the 'MEMn' instructions are the same format; the 'n' in the name - indicates the default index scale factor (the size of the datum operated on). - - The FBRA formats are not actually an instruction format. They are the - "convenience directives" for branching on floating-point comparisons, - each of which generates 2 instructions (a 'bno' and one other branch). - - The CALLJ format is not actually an instruction format. It indicates that - the instruction generated (a CTRL-format 'call') should have its relocation - specially flagged for link-time replacement with a 'bal' or 'calls' if - appropriate. */ - -#define CTRL 0 -#define COBR 1 -#define COJ 2 -#define REG 3 -#define MEM1 4 -#define MEM2 5 -#define MEM4 6 -#define MEM8 7 -#define MEM12 8 -#define MEM16 9 -#define FBRA 10 -#define CALLJ 11 - -/* Masks for the mode bits in REG format instructions */ -#define M1 0x0800 -#define M2 0x1000 -#define M3 0x2000 - -/* Generate the 12-bit opcode for a REG format instruction by placing the - * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits - * 7-10. - */ - -#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7) - -/* Generate a template for a REG format instruction: place the opcode bits - * in the appropriate fields and OR in mode bits for the operands that will not - * be used. I.e., - * set m1=1, if src1 will not be used - * set m2=1, if src2 will not be used - * set m3=1, if dst will not be used - * - * Setting the "unused" mode bits to 1 speeds up instruction execution(!). - * The information is also useful to us because some 1-operand REG instructions - * use the src1 field, others the dst field; and some 2-operand REG instructions - * use src1/src2, others src1/dst. The set mode bits enable us to distinguish. - */ -#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ -#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ -#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ -#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */ -#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */ -#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */ - -/* DESCRIPTOR BYTES FOR REGISTER OPERANDS - * - * Interpret names as follows: - * R: global or local register only - * RS: global, local, or (if target allows) special-function register only - * RL: global or local register, or integer literal - * RSL: global, local, or (if target allows) special-function register; - * or integer literal - * F: global, local, or floating-point register - * FL: global, local, or floating-point register; or literal (including - * floating point) - * - * A number appended to a name indicates that registers must be aligned, - * as follows: - * 2: register number must be multiple of 2 - * 4: register number must be multiple of 4 - */ - -#define SFR 0x10 /* Mask for the "sfr-OK" bit */ -#define LIT 0x08 /* Mask for the "literal-OK" bit */ -#define FP 0x04 /* Mask for "floating-point-OK" bit */ - -/* This macro ors the bits together. Note that 'align' is a mask - * for the low 0, 1, or 2 bits of the register number, as appropriate. - */ -#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr ) - -#define R OP( 0, 0, 0, 0 ) -#define RS OP( 0, 0, 0, SFR ) -#define RL OP( 0, LIT, 0, 0 ) -#define RSL OP( 0, LIT, 0, SFR ) -#define F OP( 0, 0, FP, 0 ) -#define FL OP( 0, LIT, FP, 0 ) -#define R2 OP( 1, 0, 0, 0 ) -#define RL2 OP( 1, LIT, 0, 0 ) -#define F2 OP( 1, 0, FP, 0 ) -#define FL2 OP( 1, LIT, FP, 0 ) -#define R4 OP( 3, 0, 0, 0 ) -#define RL4 OP( 3, LIT, 0, 0 ) -#define F4 OP( 3, 0, FP, 0 ) -#define FL4 OP( 3, LIT, FP, 0 ) - -#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ - -/* Macros to extract info from the register operand descriptor byte 'od'. - */ -#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */ -#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */ -#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */ -#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0) - /* TRUE if reg #n is properly aligned */ -#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/ - -/* Description of a single i80960 instruction */ -struct i960_opcode { - long opcode; /* 32 bits, constant fields filled in, rest zeroed */ - char *name; /* Assembler mnemonic */ - short iclass; /* Class: see #defines below */ - char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ - char num_ops; /* Number of operands */ - char operand[3];/* Operand descriptors; same order as assembler instr */ -}; - -/* Classes of 960 intructions: - * - each instruction falls into one class. - * - each target architecture supports one or more classes. - * - * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass(). - */ -#define I_BASE 0x01 /* 80960 base instruction set */ -#define I_CX 0x02 /* 80960Cx instruction */ -#define I_DEC 0x04 /* Decimal instruction */ -#define I_FP 0x08 /* Floating point instruction */ -#define I_KX 0x10 /* 80960Kx instruction */ -#define I_MIL 0x20 /* Military instruction */ -#define I_CASIM 0x40 /* CA simulator instruction */ -#define I_CX2 0x80 /* Cx/Jx/Hx instructions */ -#define I_JX 0x100 /* Jx/Hx instruction */ -#define I_HX 0x200 /* Hx instructions */ - -/****************************************************************************** - * - * TABLE OF i960 INSTRUCTION DESCRIPTIONS - * - ******************************************************************************/ - -const struct i960_opcode i960_opcodes[] = { - - /* if a CTRL instruction has an operand, it's always a displacement */ - - /* callj default=='call' */ - { 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } }, - { 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bf same as bno */ - { 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bru same as bno */ - { 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brg same as bg */ - { 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bre same as be */ - { 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brge same as bge */ - { 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brl same as bl */ - { 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brlg same as bne */ - { 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* brle same as ble */ - { 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bt same as bo */ - { 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } }, - /* bro same as bo */ - { 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } }, - { 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } }, - /* faultf same as faultno */ - { 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } }, - { 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } }, - /* faultt syn for faulto */ - { 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } }, - - { 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } }, - - /* If a COBR (or COJ) has 3 operands, the last one is always a - * displacement and does not appear explicitly in the table. - */ - - { 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } }, - { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } }, - { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } }, - { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } }, - - { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } }, - { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } }, - { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } }, - { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } }, - { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } }, - { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } }, - { 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } }, - { 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } }, - { 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } }, - { 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } }, - { 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } }, - { 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } }, - { 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } }, - { 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } }, - { 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } }, - { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } }, - { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } }, - - { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } }, - { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } }, - { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } }, - { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } }, - { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } }, - { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } }, - { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, - { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } }, - { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } }, - { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } }, - { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } }, - { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } }, - { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } }, - { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } }, - { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } }, - - /* Floating-point instructions */ - - { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } }, - { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } }, - { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } }, - { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } }, - { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } }, - { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } }, - { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } }, - { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } }, - { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } }, - { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } }, - { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } }, - { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } }, - { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } }, - { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } }, - { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } }, - { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } }, - { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } }, - { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } }, - { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } }, - { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } }, - { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } }, - { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } }, - { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } }, - - /* These are the floating point branch instructions. Each actually - * generates 2 branch instructions: the first a CTRL instruction with - * the indicated opcode, and the second a 'bno'. - */ - - { 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } }, - { 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } }, - - - /* Decimal instructions */ - - { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } }, - { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } }, - - - /* KX extensions */ - - { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } }, - { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } }, - { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } }, - { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } }, - - - /* MC extensions */ - - { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } }, - { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } }, - { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } }, - { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } }, - { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } }, - { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } }, - { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } }, - { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } }, - { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } }, - { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } }, - { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } }, - { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } }, - { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } }, - - - /* CX extensions */ - - { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } }, - { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } }, - { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } }, - { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } }, - - - /* Jx extensions. */ - { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } }, - - { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } }, - { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } }, - - { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } }, - - { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } }, - { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } }, - { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } }, - { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } }, - { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } }, - { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } }, - - /* Hx extensions. */ - { 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } }, - - /* END OF TABLE */ - - { 0, NULL, 0, 0, 0, { 0, 0, 0 } } -}; - - /* end of i960-opcode.h */ diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h deleted file mode 100644 index 58553b3ad..000000000 --- a/include/opcode/ia64.h +++ /dev/null @@ -1,392 +0,0 @@ -/* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ - -#ifndef opcode_ia64_h -#define opcode_ia64_h - -#include <sys/types.h> - -#include "bfd.h" - - -typedef BFD_HOST_U_64_BIT ia64_insn; - -enum ia64_insn_type - { - IA64_TYPE_NIL = 0, /* illegal type */ - IA64_TYPE_A, /* integer alu (I- or M-unit) */ - IA64_TYPE_I, /* non-alu integer (I-unit) */ - IA64_TYPE_M, /* memory (M-unit) */ - IA64_TYPE_B, /* branch (B-unit) */ - IA64_TYPE_F, /* floating-point (F-unit) */ - IA64_TYPE_X, /* long encoding (X-unit) */ - IA64_TYPE_DYN, /* Dynamic opcode */ - IA64_NUM_TYPES - }; - -enum ia64_unit - { - IA64_UNIT_NIL = 0, /* illegal unit */ - IA64_UNIT_I, /* integer unit */ - IA64_UNIT_M, /* memory unit */ - IA64_UNIT_B, /* branching unit */ - IA64_UNIT_F, /* floating-point unit */ - IA64_UNIT_L, /* long "unit" */ - IA64_UNIT_X, /* may be integer or branch unit */ - IA64_NUM_UNITS - }; - -/* Changes to this enumeration must be propagated to the operand table in - bfd/cpu-ia64-opc.c - */ -enum ia64_opnd - { - IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ - - /* constants */ - IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ - IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ - IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ - IA64_OPND_C1, /* the constant 1 */ - IA64_OPND_C8, /* the constant 8 */ - IA64_OPND_C16, /* the constant 16 */ - IA64_OPND_GR0, /* gr0 */ - IA64_OPND_IP, /* instruction pointer (ip) */ - IA64_OPND_PR, /* predicate register (pr) */ - IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ - IA64_OPND_PSR, /* processor status register (psr) */ - IA64_OPND_PSR_L, /* processor status register L (psr.l) */ - IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ - - /* register operands: */ - IA64_OPND_AR3, /* third application register # (bits 20-26) */ - IA64_OPND_B1, /* branch register # (bits 6-8) */ - IA64_OPND_B2, /* branch register # (bits 13-15) */ - IA64_OPND_CR3, /* third control register # (bits 20-26) */ - IA64_OPND_F1, /* first floating-point register # */ - IA64_OPND_F2, /* second floating-point register # */ - IA64_OPND_F3, /* third floating-point register # */ - IA64_OPND_F4, /* fourth floating-point register # */ - IA64_OPND_P1, /* first predicate # */ - IA64_OPND_P2, /* second predicate # */ - IA64_OPND_R1, /* first register # */ - IA64_OPND_R2, /* second register # */ - IA64_OPND_R3, /* third register # */ - IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ - - /* indirect operands: */ - IA64_OPND_CPUID_R3, /* cpuid[reg] */ - IA64_OPND_DBR_R3, /* dbr[reg] */ - IA64_OPND_DTR_R3, /* dtr[reg] */ - IA64_OPND_ITR_R3, /* itr[reg] */ - IA64_OPND_IBR_R3, /* ibr[reg] */ - IA64_OPND_MR3, /* memory at addr of third register # */ - IA64_OPND_MSR_R3, /* msr[reg] */ - IA64_OPND_PKR_R3, /* pkr[reg] */ - IA64_OPND_PMC_R3, /* pmc[reg] */ - IA64_OPND_PMD_R3, /* pmd[reg] */ - IA64_OPND_RR_R3, /* rr[reg] */ - - /* immediate operands: */ - IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ - IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ - IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ - IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ - IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ - IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ - IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ - IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ - IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ - IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ - IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ - IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ - IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ - IA64_OPND_SOF, /* 8-bit stack frame size */ - IA64_OPND_SOL, /* 8-bit size of locals */ - IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ - IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ - IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ - IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ - IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ - IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ - IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ - IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ - IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ - IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ - IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ - IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ - IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ - IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ - IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ - IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ - IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ - IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ - IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ - IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ - IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ - IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ - IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ - IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ - IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ - IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ - - IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ - }; - -enum ia64_dependency_mode -{ - IA64_DV_RAW, - IA64_DV_WAW, - IA64_DV_WAR, -}; - -enum ia64_dependency_semantics -{ - IA64_DVS_NONE, - IA64_DVS_IMPLIED, - IA64_DVS_IMPLIEDF, - IA64_DVS_DATA, - IA64_DVS_INSTR, - IA64_DVS_SPECIFIC, - IA64_DVS_STOP, - IA64_DVS_OTHER, -}; - -enum ia64_resource_specifier -{ - IA64_RS_ANY, - IA64_RS_AR_K, - IA64_RS_AR_UNAT, - IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ - IA64_RS_ARb, /* 48-63, 112-127 */ - IA64_RS_BR, - IA64_RS_CFM, - IA64_RS_CPUID, - IA64_RS_CR_IRR, - IA64_RS_CR_LRR, - IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */ - IA64_RS_DBR, - IA64_RS_FR, - IA64_RS_FRb, - IA64_RS_GR0, - IA64_RS_GR, - IA64_RS_IBR, - IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ - IA64_RS_MSR, - IA64_RS_PKR, - IA64_RS_PMC, - IA64_RS_PMD, - IA64_RS_PR, /* non-rotating, 1-15 */ - IA64_RS_PRr, /* rotating, 16-62 */ - IA64_RS_PR63, - IA64_RS_RR, - - IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ - IA64_RS_CRX, /* CRs not in RS_CR */ - IA64_RS_PSR, /* PSR bits */ - IA64_RS_RSE, /* implementation-specific RSE resources */ - IA64_RS_AR_FPSR, -}; - -enum ia64_rse_resource -{ - IA64_RSE_N_STACKED_PHYS, - IA64_RSE_BOF, - IA64_RSE_STORE_REG, - IA64_RSE_LOAD_REG, - IA64_RSE_BSPLOAD, - IA64_RSE_RNATBITINDEX, - IA64_RSE_CFLE, - IA64_RSE_NDIRTY, -}; - -/* Information about a given resource dependency */ -struct ia64_dependency -{ - /* Name of the resource */ - const char *name; - /* Does this dependency need further specification? */ - enum ia64_resource_specifier specifier; - /* Mode of dependency */ - enum ia64_dependency_mode mode; - /* Dependency semantics */ - enum ia64_dependency_semantics semantics; - /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ -#define REG_NONE (-1) - int regindex; - /* Special info on semantics */ - const char *info; -}; - -/* Two arrays of indexes into the ia64_dependency table. - chks are dependencies to check for conflicts when an opcode is - encountered; regs are dependencies to register (mark as used) when an - opcode is used. chks correspond to readers (RAW) or writers (WAW or - WAR) of a resource, while regs correspond to writers (RAW or WAW) and - readers (WAR) of a resource. */ -struct ia64_opcode_dependency -{ - int nchks; - const unsigned short *chks; - int nregs; - const unsigned short *regs; -}; - -/* encode/extract the note/index for a dependency */ -#define RDEP(N,X) (((N)<<11)|(X)) -#define NOTE(X) (((X)>>11)&0x1F) -#define DEP(X) ((X)&0x7FF) - -/* A template descriptor describes the execution units that are active - for each of the three slots. It also specifies the location of - instruction group boundaries that may be present between two slots. */ -struct ia64_templ_desc - { - int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ - enum ia64_unit exec_unit[3]; - const char *name; - }; - -/* The opcode table is an array of struct ia64_opcode. */ - -struct ia64_opcode - { - /* The opcode name. */ - const char *name; - - /* The type of the instruction: */ - enum ia64_insn_type type; - - /* Number of output operands: */ - int num_outputs; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - ia64_insn opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - ia64_insn mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - enum ia64_opnd operands[5]; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned int flags; - - /* Used by ia64_find_next_opcode (). */ - short ent_index; - - /* Opcode dependencies. */ - const struct ia64_opcode_dependency *dependencies; - }; - -/* Values defined for the flags field of a struct ia64_opcode. */ - -#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ -#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ -#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ -#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ -#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ -#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ -#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ -#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ -#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ -#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ -#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ - -/* A macro to extract the major opcode from an instruction. */ -#define IA64_OP(i) (((i) >> 37) & 0xf) - -enum ia64_operand_class - { - IA64_OPND_CLASS_CST, /* constant */ - IA64_OPND_CLASS_REG, /* register */ - IA64_OPND_CLASS_IND, /* indirect register */ - IA64_OPND_CLASS_ABS, /* absolute value */ - IA64_OPND_CLASS_REL, /* IP-relative value */ - }; - -/* The operands table is an array of struct ia64_operand. */ - -struct ia64_operand -{ - enum ia64_operand_class class; - - /* Set VALUE as the operand bits for the operand of type SELF in the - instruction pointed to by CODE. If an error occurs, *CODE is not - modified and the returned string describes the cause of the - error. If no error occurs, NULL is returned. */ - const char *(*insert) (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code); - - /* Extract the operand bits for an operand of type SELF from - instruction CODE store them in *VALUE. If an error occurs, the - cause of the error is described by the string returned. If no - error occurs, NULL is returned. */ - const char *(*extract) (const struct ia64_operand *self, ia64_insn code, - ia64_insn *value); - - /* A string whose meaning depends on the operand class. */ - - const char *str; - - struct bit_field - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - } - field[4]; /* no operand has more than this many bit-fields */ - - unsigned int flags; - - const char *desc; /* brief description */ -}; - -/* Values defined for the flags field of a struct ia64_operand. */ - -/* Disassemble as signed decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) -/* Disassemble as unsigned decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) - -extern const struct ia64_templ_desc ia64_templ_desc[16]; - -/* The tables are sorted by major opcode number and are otherwise in - the order in which the disassembler should consider instructions. */ -extern struct ia64_opcode ia64_opcodes_a[]; -extern struct ia64_opcode ia64_opcodes_i[]; -extern struct ia64_opcode ia64_opcodes_m[]; -extern struct ia64_opcode ia64_opcodes_b[]; -extern struct ia64_opcode ia64_opcodes_f[]; -extern struct ia64_opcode ia64_opcodes_d[]; - - -extern struct ia64_opcode *ia64_find_opcode (const char *name); -extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent); - -extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn, - enum ia64_insn_type type); - -extern void ia64_free_opcode (struct ia64_opcode *ent); -extern const struct ia64_dependency *ia64_find_dependency (int index); - -/* To avoid circular library dependencies, this array is implemented - in bfd/cpu-ia64-opc.c: */ -extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; - -#endif /* opcode_ia64_h */ diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h deleted file mode 100644 index cddc59ad0..000000000 --- a/include/opcode/m68hc11.h +++ /dev/null @@ -1,427 +0,0 @@ -/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table - Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@nerim.fr) - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _OPCODE_M68HC11_H -#define _OPCODE_M68HC11_H - -/* Flags for the definition of the 68HC11 & 68HC12 CCR. */ -#define M6811_S_BIT 0x80 /* Stop disable */ -#define M6811_X_BIT 0x40 /* X-interrupt mask */ -#define M6811_H_BIT 0x20 /* Half carry flag */ -#define M6811_I_BIT 0x10 /* I-interrupt mask */ -#define M6811_N_BIT 0x08 /* Negative */ -#define M6811_Z_BIT 0x04 /* Zero */ -#define M6811_V_BIT 0x02 /* Overflow */ -#define M6811_C_BIT 0x01 /* Carry */ - -/* 68HC11 register address offsets (range 0..0x3F or 0..64). - The absolute address of the I/O register depends on the setting - of the M6811_INIT register. At init time, the I/O registers are - mapped at 0x1000. Address of registers is then: - - 0x1000 + M6811_xxx -*/ -#define M6811_PORTA 0x00 /* Port A register */ -#define M6811__RES1 0x01 /* Unused/Reserved */ -#define M6811_PIOC 0x02 /* Parallel I/O Control register */ -#define M6811_PORTC 0x03 /* Port C register */ -#define M6811_PORTB 0x04 /* Port B register */ -#define M6811_PORTCL 0x05 /* Alternate latched port C */ -#define M6811__RES6 0x06 /* Unused/Reserved */ -#define M6811_DDRC 0x07 /* Data direction register for port C */ -#define M6811_PORTD 0x08 /* Port D register */ -#define M6811_DDRD 0x09 /* Data direction register for port D */ -#define M6811_PORTE 0x0A /* Port E input register */ -#define M6811_CFORC 0x0B /* Compare Force Register */ -#define M6811_OC1M 0x0C /* OC1 Action Mask register */ -#define M6811_OC1D 0x0D /* OC1 Action Data register */ -#define M6811_TCTN 0x0E /* Timer Counter Register */ -#define M6811_TCTN_H 0x0E /* " " " High part */ -#define M6811_TCTN_L 0x0F /* " " " Low part */ -#define M6811_TIC1 0x10 /* Input capture 1 register */ -#define M6811_TIC1_H 0x10 /* " " " High part */ -#define M6811_TIC1_L 0x11 /* " " " Low part */ -#define M6811_TIC2 0x12 /* Input capture 2 register */ -#define M6811_TIC2_H 0x12 /* " " " High part */ -#define M6811_TIC2_L 0x13 /* " " " Low part */ -#define M6811_TIC3 0x14 /* Input capture 3 register */ -#define M6811_TIC3_H 0x14 /* " " " High part */ -#define M6811_TIC3_L 0x15 /* " " " Low part */ -#define M6811_TOC1 0x16 /* Output Compare 1 register */ -#define M6811_TOC1_H 0x16 /* " " " High part */ -#define M6811_TOC1_L 0x17 /* " " " Low part */ -#define M6811_TOC2 0x18 /* Output Compare 2 register */ -#define M6811_TOC2_H 0x18 /* " " " High part */ -#define M6811_TOC2_L 0x19 /* " " " Low part */ -#define M6811_TOC3 0x1A /* Output Compare 3 register */ -#define M6811_TOC3_H 0x1A /* " " " High part */ -#define M6811_TOC3_L 0x1B /* " " " Low part */ -#define M6811_TOC4 0x1C /* Output Compare 4 register */ -#define M6811_TOC4_H 0x1C /* " " " High part */ -#define M6811_TOC4_L 0x1D /* " " " Low part */ -#define M6811_TOC5 0x1E /* Output Compare 5 register */ -#define M6811_TOC5_H 0x1E /* " " " High part */ -#define M6811_TOC5_L 0x1F /* " " " Low part */ -#define M6811_TCTL1 0x20 /* Timer Control register 1 */ -#define M6811_TCTL2 0x21 /* Timer Control register 2 */ -#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ -#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ -#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ -#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ -#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ -#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ -#define M6811_SPCR 0x28 /* SPI Control register */ -#define M6811_SPSR 0x29 /* SPI Status register */ -#define M6811_SPDR 0x2A /* SPI Data register */ -#define M6811_BAUD 0x2B /* SCI Baud register */ -#define M6811_SCCR1 0x2C /* SCI Control register 1 */ -#define M6811_SCCR2 0x2D /* SCI Control register 2 */ -#define M6811_SCSR 0x2E /* SCI Status register */ -#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ -#define M6811_ADCTL 0x30 /* A/D Control register */ -#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ -#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ -#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ -#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ -#define M6811__RES35 0x35 -#define M6811__RES36 0x36 -#define M6811__RES37 0x37 -#define M6811__RES38 0x38 -#define M6811_OPTION 0x39 /* System Configuration Options */ -#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ -#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ -#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ -#define M6811_INIT 0x3D /* Ram and I/O mapping register */ -#define M6811_TEST1 0x3E /* Factory test control register */ -#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ - - -/* Flags of the CONFIG register (in EEPROM). */ -#define M6811_NOSEC 0x08 /* Security mode disable */ -#define M6811_NOCOP 0x04 /* COP system disable */ -#define M6811_ROMON 0x02 /* Enable on-chip rom */ -#define M6811_EEON 0x01 /* Enable on-chip eeprom */ - -/* Flags of the PPROG register. */ -#define M6811_BYTE 0x10 /* Byte mode */ -#define M6811_ROW 0x08 /* Row mode */ -#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ -#define M6811_EELAT 0x02 /* EEPROM Latch Control */ -#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ - -/* Flags of the PIOC register. */ -#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ -#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ -#define M6811_CWOM 0x20 /* Port C Wire OR mode */ -#define M6811_HNDS 0x10 /* Handshake mode */ -#define M6811_OIN 0x08 /* Output or Input handshaking */ -#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ -#define M6811_EGA 0x02 /* Active Edge for Strobe A */ -#define M6811_INVB 0x01 /* Invert Strobe B */ - -/* Flags of the SCCR1 register. */ -#define M6811_R8 0x80 /* Receive Data bit 8 */ -#define M6811_T8 0x40 /* Transmit data bit 8 */ -#define M6811__SCCR1_5 0x20 /* Unused */ -#define M6811_M 0x10 /* SCI Character length */ -#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ - -/* Flags of the SCCR2 register. */ -#define M6811_TIE 0x80 /* Transmit Interrupt enable */ -#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ -#define M6811_RIE 0x20 /* Receive Interrupt Enable */ -#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ -#define M6811_TE 0x08 /* Transmit Enable */ -#define M6811_RE 0x04 /* Receive Enable */ -#define M6811_RWU 0x02 /* Receiver Wake Up */ -#define M6811_SBK 0x01 /* Send Break */ - -/* Flags of the SCSR register. */ -#define M6811_TDRE 0x80 /* Transmit Data Register Empty */ -#define M6811_TC 0x40 /* Transmit Complete */ -#define M6811_RDRF 0x20 /* Receive Data Register Full */ -#define M6811_IDLE 0x10 /* Idle Line Detect */ -#define M6811_OR 0x08 /* Overrun Error */ -#define M6811_NF 0x04 /* Noise Flag */ -#define M6811_FE 0x02 /* Framing Error */ -#define M6811__SCSR_0 0x01 /* Unused */ - -/* Flags of the BAUD register. */ -#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ -#define M6811__BAUD_6 0x40 /* Not used */ -#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ -#define M6811_SCP0 0x10 -#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ -#define M6811_SCR2 0x04 /* SCI Baud rate select */ -#define M6811_SCR1 0x02 -#define M6811_SCR0 0x01 - -#define M6811_BAUD_DIV_1 (0) -#define M6811_BAUD_DIV_3 (M6811_SCP0) -#define M6811_BAUD_DIV_4 (M6811_SCP1) -#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) - -/* Flags of the SPCR register. */ -#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ -#define M6811_SPE 0x40 /* Serial Peripheral System Enable */ -#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ -#define M6811_MSTR 0x10 /* Master Mode Select */ -#define M6811_CPOL 0x08 /* Clock Polarity */ -#define M6811_CPHA 0x04 /* Clock Phase */ -#define M6811_SPR1 0x02 /* SPI Clock Rate Select */ -#define M6811_SPR0 0x01 - -/* Flags of the SPSR register. */ -#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ -#define M6811_WCOL 0x40 /* Write Collision */ -#define M6811_MODF 0x10 /* Mode Fault */ - -/* Flags of the ADCTL register. */ -#define M6811_CCF 0x80 /* Conversions Complete Flag */ -#define M6811_SCAN 0x20 /* Continuous Scan Control */ -#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ -#define M6811_CD 0x08 /* Channel Select D */ -#define M6811_CC 0x04 /* C */ -#define M6811_CB 0x02 /* B */ -#define M6811_CA 0x01 /* A */ - -/* Flags of the CFORC register. */ -#define M6811_FOC1 0x80 /* Force Output Compare 1 */ -#define M6811_FOC2 0x40 /* 2 */ -#define M6811_FOC3 0x20 /* 3 */ -#define M6811_FOC4 0x10 /* 4 */ -#define M6811_FOC5 0x08 /* 5 */ - -/* Flags of the OC1M register. */ -#define M6811_OC1M7 0x80 /* Output Compare 7 */ -#define M6811_OC1M6 0x40 /* 6 */ -#define M6811_OC1M5 0x20 /* 5 */ -#define M6811_OC1M4 0x10 /* 4 */ -#define M6811_OC1M3 0x08 /* 3 */ - -/* Flags of the OC1D register. */ -#define M6811_OC1D7 0x80 -#define M6811_OC1D6 0x40 -#define M6811_OC1D5 0x20 -#define M6811_OC1D4 0x10 -#define M6811_OC1D3 0x08 - -/* Flags of the TCTL1 register. */ -#define M6811_OM2 0x80 /* Output Mode 2 */ -#define M6811_OL2 0x40 /* Output Level 2 */ -#define M6811_OM3 0x20 -#define M6811_OL3 0x10 -#define M6811_OM4 0x08 -#define M6811_OL4 0x04 -#define M6811_OM5 0x02 -#define M6811_OL5 0x01 - -/* Flags of the TCTL2 register. */ -#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ -#define M6811_EDG1A 0x10 -#define M6811_EDG2B 0x08 /* Input 2 */ -#define M6811_EDG2A 0x04 -#define M6811_EDG3B 0x02 /* Input 3 */ -#define M6811_EDG3A 0x01 - -/* Flags of the TMSK1 register. */ -#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ -#define M6811_OC2I 0x40 /* 2 */ -#define M6811_OC3I 0x20 /* 3 */ -#define M6811_OC4I 0x10 /* 4 */ -#define M6811_OC5I 0x08 /* 5 */ -#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ -#define M6811_IC2I 0x02 /* 2 */ -#define M6811_IC3I 0x01 /* 3 */ - -/* Flags of the TFLG1 register. */ -#define M6811_OC1F 0x80 /* Output Compare 1 Flag */ -#define M6811_OC2F 0x40 /* 2 */ -#define M6811_OC3F 0x20 /* 3 */ -#define M6811_OC4F 0x10 /* 4 */ -#define M6811_OC5F 0x08 /* 5 */ -#define M6811_IC1F 0x04 /* Input Capture 1 Flag */ -#define M6811_IC2F 0x02 /* 2 */ -#define M6811_IC3F 0x01 /* 3 */ - -/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ -#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ -#define M6811_RTII 0x40 /* RTI Interrupt Enable */ -#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ -#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ -#define M6811_PR1 0x02 /* Timer prescaler */ -#define M6811_PR0 0x01 /* Timer prescaler */ -#define M6811_TPR_1 0x00 /* " " prescale div 1 */ -#define M6811_TPR_4 0x01 /* " " prescale div 4 */ -#define M6811_TPR_8 0x02 /* " " prescale div 8 */ -#define M6811_TPR_16 0x03 /* " " prescale div 16 */ - -/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ -#define M6811_TOF 0x80 /* Timer overflow bit */ -#define M6811_RTIF 0x40 /* Read time interrupt flag */ -#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ -#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ - -/* Flags of Pulse Accumulator Control Register (PACTL). */ -#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ -#define M6811_PAEN 0x40 /* Pulse accumulator system enable */ -#define M6811_PAMOD 0x20 /* Pulse accumulator mode */ -#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ -#define M6811_RTR1 0x02 /* RTI Interrupt rates select */ -#define M6811_RTR0 0x01 /* " " " " */ - -/* Flags of the Options register. */ -#define M6811_ADPU 0x80 /* A/D Powerup */ -#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ -#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ -#define M6811_DLY 0x10 /* Stop exit turn on delay */ -#define M6811_CME 0x08 /* Clock Monitor enable */ -#define M6811_CR1 0x02 /* COP timer rate select */ -#define M6811_CR0 0x01 /* COP timer rate select */ - -/* Flags of the HPRIO register. */ -#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ -#define M6811_SMOD 0x40 /* Special Mode */ -#define M6811_MDA 0x20 /* Mode Select A */ -#define M6811_IRV 0x10 /* Internal Read Visibility */ -#define M6811_PSEL3 0x08 /* Priority Select */ -#define M6811_PSEL2 0x04 -#define M6811_PSEL1 0x02 -#define M6811_PSEL0 0x01 - -/* Some insns used by gas to turn relative branches into absolute ones. */ -#define M6811_BRA 0x20 -#define M6811_JMP 0x7e -#define M6811_BSR 0x8d -#define M6811_JSR 0xbd -#define M6812_JMP 0x06 -#define M6812_BSR 0x07 -#define M6812_JSR 0x16 - -/* Instruction code pages. Code page 1 is the default. */ -/*#define M6811_OPCODE_PAGE1 0x00*/ -#define M6811_OPCODE_PAGE2 0x18 -#define M6811_OPCODE_PAGE3 0x1A -#define M6811_OPCODE_PAGE4 0xCD - - -/* 68HC11 operands formats as stored in the m6811_opcode table. These - flags do not correspond to anything in the 68HC11 or 68HC12. - They are only used by GAS to recognize operands. */ -#define M6811_OP_NONE 0 /* No operand */ -#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */ -#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */ -#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */ -#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */ -#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ -#define M6812_OP_REG 0x0020 /* Register operand 1 */ -#define M6812_OP_REG_2 0x0040 /* Register operand 2 */ - -#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */ -#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */ -#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ -#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ -#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ -#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ -#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ -#define M6812_OP_PAGE 0x4000 /* Page number */ -#define M6811_OP_MASK 0x07FFF -#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ -#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */ -#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */ -#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */ -#define M6811_OP_PAGE1 0x0000 -#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ -#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ -#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ -#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */ - -#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ -#define M6812_ACC_IND 0x00800000 /* [D,r] */ -#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ -#define M6812_PRE_DEC 0x02000000 /* n,-r */ -#define M6812_POST_INC 0x04000000 /* n,r+ */ -#define M6812_POST_DEC 0x08000000 /* n,r- */ -#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ -#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ -#define M6812_OP_IDX_P2 0x40000000 - -/* Markers to identify some instructions. */ -#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ -#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ -#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ - -#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ -#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ -#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ -#define M6812_OP_TBCC_MARKER 0x01000000 - -#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ - -#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ -#define M6811_OP_LOW_ADDR 0x02000000 - -#define M68HC12_BANK_VIRT 0x010000 -#define M68HC12_BANK_MASK 0x00003fff -#define M68HC12_BANK_BASE 0x00008000 -#define M68HC12_BANK_SHIFT 14 -#define M68HC12_BANK_PAGE_MASK 0x0ff - - -/* CPU identification. */ -#define cpu6811 0x01 -#define cpu6812 0x02 -#define cpu6812s 0x04 - -/* The opcode table is an array of struct m68hc11_opcode. */ -struct m68hc11_opcode { - const char* name; /* Op-code name */ - long format; - unsigned char size; - unsigned char opcode; - unsigned char cycles_low; - unsigned char cycles_high; - unsigned char set_flags_mask; - unsigned char clr_flags_mask; - unsigned char chg_flags_mask; - unsigned char arch; -}; - -/* Alias definition for 68HC12. */ -struct m68hc12_opcode_alias -{ - const char* name; - const char* translation; - unsigned char size; - unsigned char code1; - unsigned char code2; -}; - -/* The opcode table. The table contains all the opcodes (all pages). - You can't rely on the order. */ -extern const struct m68hc11_opcode m68hc11_opcodes[]; -extern const int m68hc11_num_opcodes; - -/* Alias table for 68HC12. It translates some 68HC11 insn which are not - implemented in 68HC12 but have equivalent translations. */ -extern const struct m68hc12_opcode_alias m68hc12_alias[]; -extern const int m68hc12_num_alias; - -#endif /* _OPCODE_M68HC11_H */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h deleted file mode 100644 index 84bef9895..000000000 --- a/include/opcode/m68k.h +++ /dev/null @@ -1,381 +0,0 @@ -/* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, - 2003, 2004 Free Software Foundation, Inc. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 1, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* These are used as bit flags for the arch field in the m68k_opcode - structure. */ -#define _m68k_undef 0 -#define m68000 0x001 -#define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ -#define m68010 0x002 -#define m68020 0x004 -#define m68030 0x008 -#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; - gas will deal with the few differences. */ -#define m68040 0x010 -/* There is no 68050. */ -#define m68060 0x020 -#define m68881 0x040 -#define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ -#define m68851 0x080 -#define cpu32 0x100 /* e.g., 68332 */ - -#define mcfmac 0x200 /* ColdFire MAC. */ -#define mcfemac 0x400 /* ColdFire EMAC. */ -#define cfloat 0x800 /* ColdFire FPU. */ -#define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ - -#define mcfisa_a 0x2000 /* ColdFire ISA_A. */ -#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ -#define mcfisa_b 0x8000 /* ColdFire ISA_B. */ -#define mcfusp 0x10000 /* ColdFire USP instructions. */ - -#define mcf5200 0x20000 -#define mcf5206e 0x40000 -#define mcf521x 0x80000 -#define mcf5249 0x100000 -#define mcf528x 0x200000 -#define mcf5307 0x400000 -#define mcf5407 0x800000 -#define mcf5470 0x1000000 -#define mcf5480 0x2000000 - - /* Handy aliases. */ -#define m68040up (m68040 | m68060) -#define m68030up (m68030 | m68040up) -#define m68020up (m68020 | m68030up) -#define m68010up (m68010 | cpu32 | m68020up) -#define m68000up (m68000 | m68010up) - -#define mfloat (m68881 | m68882 | m68040 | m68060) -#define mmmu (m68851 | m68030 | m68040 | m68060) - -/* The structure used to hold information for an opcode. */ - -struct m68k_opcode -{ - /* The opcode name. */ - const char *name; - /* The pseudo-size of the instruction(in bytes). Used to determine - number of bytes necessary to disassemble the instruction. */ - unsigned int size; - /* The opcode itself. */ - unsigned long opcode; - /* The mask used by the disassembler. */ - unsigned long match; - /* The arguments. */ - const char *args; - /* The architectures which support this opcode. */ - unsigned int arch; -}; - -/* The structure used to hold information for an opcode alias. */ - -struct m68k_opcode_alias -{ - /* The alias name. */ - const char *alias; - /* The instruction for which this is an alias. */ - const char *primary; -}; - -/* We store four bytes of opcode for all opcodes because that is the - most any of them need. The actual length of an instruction is - always at least 2 bytes, and is as much longer as necessary to hold - the operands it has. - - The match field is a mask saying which bits must match particular - opcode in order for an instruction to be an instance of that - opcode. - - The args field is a string containing two characters for each - operand of the instruction. The first specifies the kind of - operand; the second, the place it is stored. */ - -/* Kinds of operands: - Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+- - - D data register only. Stored as 3 bits. - A address register only. Stored as 3 bits. - a address register indirect only. Stored as 3 bits. - R either kind of register. Stored as 4 bits. - r either kind of register indirect only. Stored as 4 bits. - At the moment, used only for cas2 instruction. - F floating point coprocessor register only. Stored as 3 bits. - O an offset (or width): immediate data 0-31 or data register. - Stored as 6 bits in special format for BF... insns. - + autoincrement only. Stored as 3 bits (number of the address register). - - autodecrement only. Stored as 3 bits (number of the address register). - Q quick immediate data. Stored as 3 bits. - This matches an immediate operand only when value is in range 1 .. 8. - M moveq immediate data. Stored as 8 bits. - This matches an immediate operand only when value is in range -128..127 - T trap vector immediate data. Stored as 4 bits. - - k K-factor for fmove.p instruction. Stored as a 7-bit constant or - a three bit register offset, depending on the field type. - - # immediate data. Stored in special places (b, w or l) - which say how many bits to store. - ^ immediate data for floating point instructions. Special places - are offset by 2 bytes from '#'... - B pc-relative address, converted to an offset - that is treated as immediate data. - d displacement and register. Stores the register as 3 bits - and stores the displacement in the entire second word. - - C the CCR. No need to store it; this is just for filtering validity. - S the SR. No need to store, just as with CCR. - U the USP. No need to store, just as with CCR. - E the MAC ACC. No need to store, just as with CCR. - e the EMAC ACC[0123]. - G the MAC/EMAC MACSR. No need to store, just as with CCR. - g the EMAC ACCEXT{01,23}. - H the MASK. No need to store, just as with CCR. - i the MAC/EMAC scale factor. - - I Coprocessor ID. Not printed if 1. The Coprocessor ID is always - extracted from the 'd' field of word one, which means that an extended - coprocessor opcode can be skipped using the 'i' place, if needed. - - s System Control register for the floating point coprocessor. - - J Misc register for movec instruction, stored in 'j' format. - Possible values: - 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] - 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] - 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] - 0x003 TC MMU Translation Control [60, 40] - 0x004 ITT0 Instruction Transparent - Translation reg 0 [60, 40] - 0x005 ITT1 Instruction Transparent - Translation reg 1 [60, 40] - 0x006 DTT0 Data Transparent - Translation reg 0 [60, 40] - 0x007 DTT1 Data Transparent - Translation reg 1 [60, 40] - 0x008 BUSCR Bus Control Register [60] - 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] - 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] - 0x802 CAAR Cache Address Register [ 30, 20] - 0x803 MSP Master Stack Pointer [ 40, 30, 20] - 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] - 0x805 MMUSR MMU Status reg [ 40] - 0x806 URP User Root Pointer [60, 40] - 0x807 SRP Supervisor Root Pointer [60, 40] - 0x808 PCR Processor Configuration reg [60] - 0xC00 ROMBAR ROM Base Address Register [520X] - 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] - 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] - 0xC0F MBAR0 RAM Base Address Register 0 [520X] - 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] - 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] - - L Register list of the type d0-d7/a0-a7 etc. - (New! Improved! Can also hold fp0-fp7, as well!) - The assembler tries to see if the registers match the insn by - looking at where the insn wants them stored. - - l Register list like L, but with all the bits reversed. - Used for going the other way. . . - - c cache identifier which may be "nc" for no cache, "ic" - for instruction cache, "dc" for data cache, or "bc" - for both caches. Used in cinv and cpush. Always - stored in position "d". - - u Any register, with ``upper'' or ``lower'' specification. Used - in the mac instructions with size word. - - The remainder are all stored as 6 bits using an address mode and a - register number; they differ in which addressing modes they match. - - * all (modes 0-6,7.0-4) - ~ alterable memory (modes 2-6,7.0,7.1) - (not 0,1,7.2-4) - % alterable (modes 0-6,7.0,7.1) - (not 7.2-4) - ; data (modes 0,2-6,7.0-4) - (not 1) - @ data, but not immediate (modes 0,2-6,7.0-3) - (not 1,7.4) - ! control (modes 2,5,6,7.0-3) - (not 0,1,3,4,7.4) - & alterable control (modes 2,5,6,7.0,7.1) - (not 0,1,3,4,7.2-4) - $ alterable data (modes 0,2-6,7.0,7.1) - (not 1,7.2-4) - ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) - (not 1,3,4,7.2-4) - / control, or data register (modes 0,2,5,6,7.0-3) - (not 1,3,4,7.4) - > *save operands (modes 2,4,5,6,7.0,7.1) - (not 0,1,3,7.2-4) - < *restore operands (modes 2,3,5,6,7.0-3) - (not 0,1,4,7.4) - - coldfire move operands: - m (modes 0-4) - n (modes 5,7.2) - o (modes 6,7.0,7.1,7.3,7.4) - p (modes 0-5) - - coldfire bset/bclr/btst/mulsl/mulul operands: - q (modes 0,2-5) - v (modes 0,2-5,7.0,7.1) - b (modes 0,2-5,7.2) - w (modes 2-5,7.2) - y (modes 2,5) - z (modes 2,5,7.2) - x mov3q immediate operand. - 4 (modes 2,3,4,5) - */ - -/* For the 68851: */ -/* I didn't use much imagination in choosing the - following codes, so many of them aren't very - mnemonic. -rab - - 0 32 bit pmmu register - Possible values: - 000 TC Translation Control Register (68030, 68851) - - 1 16 bit pmmu register - 111 AC Access Control (68851) - - 2 8 bit pmmu register - 100 CAL Current Access Level (68851) - 101 VAL Validate Access Level (68851) - 110 SCC Stack Change Control (68851) - - 3 68030-only pmmu registers (32 bit) - 010 TT0 Transparent Translation reg 0 - (aka Access Control reg 0 -- AC0 -- on 68ec030) - 011 TT1 Transparent Translation reg 1 - (aka Access Control reg 1 -- AC1 -- on 68ec030) - - W wide pmmu registers - Possible values: - 001 DRP Dma Root Pointer (68851) - 010 SRP Supervisor Root Pointer (68030, 68851) - 011 CRP Cpu Root Pointer (68030, 68851) - - f function code register (68030, 68851) - 0 SFC - 1 DFC - - V VAL register only (68851) - - X BADx, BACx (16 bit) - 100 BAD Breakpoint Acknowledge Data (68851) - 101 BAC Breakpoint Acknowledge Control (68851) - - Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) - Z PCSR (68851) - - | memory (modes 2-6, 7.*) - - t address test level (68030 only) - Stored as 3 bits, range 0-7. - Also used for breakpoint instruction now. - -*/ - -/* Places to put an operand, for non-general operands: - Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ - - s source, low bits of first word. - d dest, shifted 9 in first word - 1 second word, shifted 12 - 2 second word, shifted 6 - 3 second word, shifted 0 - 4 third word, shifted 12 - 5 third word, shifted 6 - 6 third word, shifted 0 - 7 second word, shifted 7 - 8 second word, shifted 10 - 9 second word, shifted 5 - D store in both place 1 and place 3; for divul and divsl. - B first word, low byte, for branch displacements - W second word (entire), for branch displacements - L second and third words (entire), for branch displacements - (also overloaded for move16) - b second word, low byte - w second word (entire) [variable word/long branch offset for dbra] - W second word (entire) (must be signed 16 bit value) - l second and third word (entire) - g variable branch offset for bra and similar instructions. - The place to store depends on the magnitude of offset. - t store in both place 7 and place 8; for floating point operations - c branch offset for cpBcc operations. - The place to store is word two if bit six of word one is zero, - and words two and three if bit six of word one is one. - i Increment by two, to skip over coprocessor extended operands. Only - works with the 'I' format. - k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. - Also used for dynamic fmovem instruction. - C floating point coprocessor constant - 7 bits. Also used for static - K-factors... - j Movec register #, stored in 12 low bits of second word. - m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word - and remaining 3 bits of register shifted 9 bits in first word. - Indicate upper/lower in 1 bit shifted 7 bits in second word. - Use with `R' or `u' format. - n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split - with MSB shifted 6 bits in first word and remaining 3 bits of - register shifted 9 bits in first word. No upper/lower - indication is done.) Use with `R' or `u' format. - o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). - Indicate upper/lower in 1 bit shifted 7 bits in second word. - Use with `R' or `u' format. - M For M[S]ACw; 4 bits in low bits of first word. Indicate - upper/lower in 1 bit shifted 6 bits in second word. Use with - `R' or `u' format. - N For M[S]ACw; 4 bits in low bits of second word. Indicate - upper/lower in 1 bit shifted 6 bits in second word. Use with - `R' or `u' format. - h shift indicator (scale factor), 1 bit shifted 10 in second word - - Places to put operand, for general operands: - d destination, shifted 6 bits in first word - b source, at low bit of first word, and immediate uses one byte - w source, at low bit of first word, and immediate uses two bytes - l source, at low bit of first word, and immediate uses four bytes - s source, at low bit of first word. - Used sometimes in contexts where immediate is not allowed anyway. - f single precision float, low bit of 1st word, immediate uses 4 bytes - F double precision float, low bit of 1st word, immediate uses 8 bytes - x extended precision float, low bit of 1st word, immediate uses 12 bytes - p packed float, low bit of 1st word, immediate uses 12 bytes - G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) - H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) - F EMAC ACCx - f EMAC ACCy - I MAC/EMAC scale factor - / Like 's', but set 2nd word, bit 5 if trailing_ampersand set - ] first word, bit 10 -*/ - -extern const struct m68k_opcode m68k_opcodes[]; -extern const struct m68k_opcode_alias m68k_opcode_aliases[]; - -extern const int m68k_numopcodes, m68k_numaliases; - -/* end of m68k-opcode.h */ diff --git a/include/opcode/m88k.h b/include/opcode/m88k.h deleted file mode 100644 index 258968606..000000000 --- a/include/opcode/m88k.h +++ /dev/null @@ -1,454 +0,0 @@ -/* Table of opcodes for the Motorola M88k family. - Copyright 1989, 1990, 1991, 1993, 2001, 2002 - Free Software Foundation, Inc. - -This file is part of GDB and GAS. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* - * Disassembler Instruction Table - * - * The first field of the table is the opcode field. If an opcode - * is specified which has any non-opcode bits on, a system error - * will occur when the system attempts the install it into the - * instruction table. The second parameter is a pointer to the - * instruction mnemonic. Each operand is specified by offset, width, - * and type. The offset is the bit number of the least significant - * bit of the operand with bit 0 being the least significant bit of - * the instruction. The width is the number of bits used to specify - * the operand. The type specifies the output format to be used for - * the operand. The valid formats are: register, register indirect, - * hex constant, and bit field specification. The last field is a - * pointer to the next instruction in the linked list. These pointers - * are initialized by init_disasm(). - * - * Revision History - * - * Revision 1.0 11/08/85 Creation date - * 1.1 02/05/86 Updated instruction mnemonic table MD - * 1.2 06/16/86 Updated SIM_FLAGS for floating point - * 1.3 09/20/86 Updated for new encoding - * 05/11/89 R. Trawick adapted from Motorola disassembler - */ - -#include <stdio.h> - -/* Define the number of bits in the primary opcode field of the instruction, - the destination field, the source 1 and source 2 fields. */ - -/* Size of opcode field. */ -#define OP 8 - -/* Size of destination. */ -#define DEST 6 - -/* Size of source1. */ -#define SOURCE1 6 - -/* Size of source2. */ -#define SOURCE2 6 - -/* Number of registers. */ -#define REGs 32 - -/* Type definitions. */ - -typedef unsigned int UINT; -#define WORD long -#define FLAG unsigned -#define STATE short - -/* The next four equates define the priorities that the various classes - * of instructions have regarding writing results back into registers and - * signalling exceptions. */ - -/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ -#undef PMEM - -/* Integer priority. */ -#define PINT 0 - -/* Floating point priority. */ -#define PFLT 1 - -/* Memory priority. */ -#define PMEM 2 - -/* Not applicable, instruction doesn't write to regs. */ -#define NA 3 - -/* Highest of these priorities. */ -#define HIPRI 3 - -/* The instruction registers are an artificial mechanism to speed up - * simulator execution. In the real processor, an instruction register - * is 32 bits wide. In the simulator, the 32 bit instruction is kept in - * a structure field called rawop, and the instruction is partially decoded, - * and split into various fields and flags which make up the other fields - * of the structure. - * The partial decode is done when the instructions are initially loaded - * into simulator memory. The simulator code memory is not an array of - * 32 bit words, but is an array of instruction register structures. - * Yes this wastes memory, but it executes much quicker. - */ - -struct IR_FIELDS -{ - unsigned op:OP, - dest: DEST, - src1: SOURCE1, - src2: SOURCE2; - int ltncy, - extime, - /* Writeback priority. */ - wb_pri; - /* Immediate size. */ - unsigned imm_flags:2, - /* Register source 1 used. */ - rs1_used:1, - /* Register source 2 used. */ - rs2_used:1, - /* Register source/dest. used. */ - rsd_used:1, - /* Complement. */ - c_flag:1, - /* Upper half word. */ - u_flag:1, - /* Execute next. */ - n_flag:1, - /* Uses writeback slot. */ - wb_flag:1, - /* Dest size. */ - dest_64:1, - /* Source 1 size. */ - s1_64:1, - /* Source 2 size. */ - s2_64:1, - scale_flag:1, - /* Scaled register. */ - brk_flg:1; -}; - -struct mem_segs -{ - /* Pointer (returned by calloc) to segment. */ - struct mem_wrd *seg; - - /* Base load address from file headers. */ - unsigned long baseaddr; - - /* Ending address of segment. */ - unsigned long endaddr; - - /* Segment control flags (none defined). */ - int flags; -}; - -#define MAXSEGS (10) /* max number of segment allowed */ -#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ - -#if 0 -#define BRK_RD (0x01) /* break on memory read */ -#define BRK_WR (0x02) /* break on memory write */ -#define BRK_EXEC (0x04) /* break on execution */ -#define BRK_CNT (0x08) /* break on terminal count */ -#endif - -struct mem_wrd -{ - /* Simulator instruction break down. */ - struct IR_FIELDS opcode; - union { - /* Memory element break down. */ - unsigned long l; - unsigned short s[2]; - unsigned char c[4]; - } mem; -}; - -/* Size of each 32 bit memory model. */ -#define MEMWRDSIZE (sizeof (struct mem_wrd)) - -extern struct mem_segs memory[]; -extern struct PROCESSOR m78000; - -struct PROCESSOR -{ - unsigned WORD - /* Execute instruction pointer. */ - ip, - /* Vector base register. */ - vbr, - /* Processor status register. */ - psr; - - /* Source 1. */ - WORD S1bus, - /* Source 2. */ - S2bus, - /* Destination. */ - Dbus, - /* Data address bus. */ - DAbus, - ALU, - /* Data registers. */ - Regs[REGs], - /* Max clocks before reg is available. */ - time_left[REGs], - /* Writeback priority of reg. */ - wb_pri[REGs], - /* Integer unit control regs. */ - SFU0_regs[REGs], - /* Floating point control regs. */ - SFU1_regs[REGs], - Scoreboard[REGs], - Vbr; - unsigned WORD scoreboard, - Psw, - Tpsw; - /* Waiting for a jump instruction. */ - FLAG jump_pending:1; -}; - -/* Size of immediate field. */ - -#define i26bit 1 -#define i16bit 2 -#define i10bit 3 - -/* Definitions for fields in psr. */ - -#define psr_mode 31 -#define psr_rbo 30 -#define psr_ser 29 -#define psr_carry 28 -#define psr_sf7m 11 -#define psr_sf6m 10 -#define psr_sf5m 9 -#define psr_sf4m 8 -#define psr_sf3m 7 -#define psr_sf2m 6 -#define psr_sf1m 5 -#define psr_mam 4 -#define psr_inm 3 -#define psr_exm 2 -#define psr_trm 1 -#define psr_ovfm 0 - -/* The 1 clock operations. */ - -#define ADDU 1 -#define ADDC 2 -#define ADDUC 3 -#define ADD 4 - -#define SUBU ADD+1 -#define SUBB ADD+2 -#define SUBUB ADD+3 -#define SUB ADD+4 - -#define AND_ ADD+5 -#define OR ADD+6 -#define XOR ADD+7 -#define CMP ADD+8 - -/* Loads. */ - -#define LDAB CMP+1 -#define LDAH CMP+2 -#define LDA CMP+3 -#define LDAD CMP+4 - -#define LDB LDAD+1 -#define LDH LDAD+2 -#define LD LDAD+3 -#define LDD LDAD+4 -#define LDBU LDAD+5 -#define LDHU LDAD+6 - -/* Stores. */ - -#define STB LDHU+1 -#define STH LDHU+2 -#define ST LDHU+3 -#define STD LDHU+4 - -/* Exchange. */ - -#define XMEMBU LDHU+5 -#define XMEM LDHU+6 - -/* Branches. */ - -#define JSR STD+1 -#define BSR STD+2 -#define BR STD+3 -#define JMP STD+4 -#define BB1 STD+5 -#define BB0 STD+6 -#define RTN STD+7 -#define BCND STD+8 - -/* Traps. */ - -#define TB1 BCND+1 -#define TB0 BCND+2 -#define TCND BCND+3 -#define RTE BCND+4 -#define TBND BCND+5 - -/* Misc. */ - -#define MUL TBND + 1 -#define DIV MUL +2 -#define DIVU MUL +3 -#define MASK MUL +4 -#define FF0 MUL +5 -#define FF1 MUL +6 -#define CLR MUL +7 -#define SET MUL +8 -#define EXT MUL +9 -#define EXTU MUL +10 -#define MAK MUL +11 -#define ROT MUL +12 - -/* Control register manipulations. */ - -#define LDCR ROT +1 -#define STCR ROT +2 -#define XCR ROT +3 - -#define FLDCR ROT +4 -#define FSTCR ROT +5 -#define FXCR ROT +6 - -#define NOP XCR +1 - -/* Floating point instructions. */ - -#define FADD NOP +1 -#define FSUB NOP +2 -#define FMUL NOP +3 -#define FDIV NOP +4 -#define FSQRT NOP +5 -#define FCMP NOP +6 -#define FIP NOP +7 -#define FLT NOP +8 -#define INT NOP +9 -#define NINT NOP +10 -#define TRNC NOP +11 -#define FLDC NOP +12 -#define FSTC NOP +13 -#define FXC NOP +14 - -#define UEXT(src,off,wid) \ - ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) - -#define SEXT(src,off,wid) \ - (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) - -#define MAKE(src,off,wid) \ - ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) - -#define opword(n) (unsigned long) (memaddr->mem.l) - -/* Constants and masks. */ - -#define SFU0 0x80000000 -#define SFU1 0x84000000 -#define SFU7 0x9c000000 -#define RRI10 0xf0000000 -#define RRR 0xf4000000 -#define SFUMASK 0xfc00ffe0 -#define RRRMASK 0xfc00ffe0 -#define RRI10MASK 0xfc00fc00 -#define DEFMASK 0xfc000000 -#define CTRL 0x0000f000 -#define CTRLMASK 0xfc00f800 - -/* Operands types. */ - -enum operand_type -{ - HEX = 1, - REG = 2, - CONT = 3, - IND = 3, - BF = 4, - /* Scaled register. */ - REGSC = 5, - /* Control register. */ - CRREG = 6, - /* Floating point control register. */ - FCRREG = 7, - PCREL = 8, - CONDMASK = 9, - /* Extended register. */ - XREG = 10, - /* Decimal. */ - DEC = 11 -}; - -/* Hashing specification. */ - -#define HASHVAL 79 - -/* Structure templates. */ - -typedef struct -{ - unsigned int offset; - unsigned int width; - enum operand_type type; -} OPSPEC; - -struct SIM_FLAGS -{ - int ltncy, /* latency (max number of clocks needed to execute). */ - extime, /* execution time (min number of clocks needed to execute). */ - wb_pri; /* writeback slot priority. */ - unsigned op:OP, /* simulator version of opcode. */ - imm_flags:2, /* 10,16 or 26 bit immediate flags. */ - rs1_used:1, /* register source 1 used. */ - rs2_used:1, /* register source 2 used. */ - rsd_used:1, /* register source/dest used. */ - c_flag:1, /* complement. */ - u_flag:1, /* upper half word. */ - n_flag:1, /* execute next. */ - wb_flag:1, /* uses writeback slot. */ - dest_64:1, /* double precision dest. */ - s1_64:1, /* double precision source 1. */ - s2_64:1, /* double precision source 2. */ - scale_flag:1; /* register is scaled. */ -}; - -typedef struct INSTRUCTAB { - unsigned int opcode; - char *mnemonic; - OPSPEC op1,op2,op3; - struct SIM_FLAGS flgs; -} INSTAB; - - -#define NO_OPERAND {0,0,0} - -extern const INSTAB instructions[]; - -/* - * Local Variables: - * fill-column: 131 - * End: - */ diff --git a/include/opcode/maxq.h b/include/opcode/maxq.h deleted file mode 100644 index f621ac156..000000000 --- a/include/opcode/maxq.h +++ /dev/null @@ -1,1132 +0,0 @@ -/* maxq.h -- Header file for MAXQ opcode table. - - Copyright (C) 2004 Free Software Foundation, Inc. - - This file is part of GDB, GAS, and the GNU binutils. - - Written by Vineet Sharma(vineets@noida.hcltech.com) - Inderpreet Singh (inderpreetb@noida.hcltech.com) - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public License - as published by the Free Software Foundation; either version 2, or (at - your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they will - be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General - Public License for more details. - - You should have received a copy of the GNU General Public License along - with this file; see the file COPYING. If not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _MAXQ20_H_ -#define _MAXQ20_H_ - -/* This file contains the opcode table for the MAXQ10/20 processor. The table - has been designed on the lines of the SH processor with the following - fields: - (1) Instruction Name - (2) Instruction arguments description - (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4 - |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8) - (4) Architecture supported - - The Register table is also defined. It contains the following fields - (1) Register name - (2) Module Number - (3) Module Index - (4) Opcode - (5) Regtype - - The Memory access table is defined containing the various opcodes for - memory access containing the following fields - (1) Memory access Operand Name - (2) Memory access Operand opcode. */ - -# define MAXQ10 0x0001 -# define MAXQ20 0x0002 -# define MAX (MAXQ10 | MAXQ20) - -/* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte: - NOP_DST 2nd byte: NOP_SRC. */ -# define NOP_FMT 1 -# define NOP_SRC 0x3A -# define NOP_DST 0x5A - -typedef enum -{ - ZEROBIT = 0x1, /* A zero followed by 3 bits. */ - ONEBIT = 0x2, /* A one followed by 3 bits. */ - REG = 0x4, /* Register. */ - MEM = 0x8, /* Memory access. */ - IMM = 0x10, /* Immediate value. */ - DISP = 0x20, /* Displacement value. */ - BIT = 0x40, /* Bit value. */ - FMT = 0x80, /* The format bit. */ - IMMBIT = 0x100, /* An immediate bit. */ - FLAG = 0x200, /* A Flag. */ - DATA = 0x400, /* Symbol in the data section. */ - BIT_BUCKET = 0x800, /* FOr BIT BUCKET. */ -} -UNKNOWN_OP; - -typedef enum -{ - NO_ARG = 0, - A_IMM = 0x01, /* An 8 bit immediate value. */ - A_REG = 0x2, /* An 8 bit source register. */ - A_MEM = 0x4, /* A 7 bit destination register. */ - FLAG_C = 0x8, /* Carry Flag. */ - FLAG_NC = 0x10, /* No Carry (~C) flag. */ - FLAG_Z = 0x20, /* Zero Flag. */ - FLAG_NZ = 0x40, /* Not Zero Flag. */ - FLAG_S = 0x80, /* Sign Flag. */ - FLAG_E = 0x100, /* Equals Flag. */ - FLAG_NE = 0x200, /* Not Equal Flag. */ - ACC_BIT = 0x400, /* One of the 16 accumulator bits of the form Acc.<b>. */ - DST_BIT = 0x800, /* One of the 8 bits of the specified SRC. */ - SRC_BIT = 0x1000, /* One of the 8 bits of the specified source register. */ - A_BIT_0 = 0x2000, /* #0. */ - A_BIT_1 = 0x4000, /* #1. */ - A_DISP = 0x8000, /* Displacement Operand. */ - A_DATA = 0x10000, /* Data in the data section. */ - A_BIT_BUCKET = 0x200000, -} -MAX_ARG_TYPE; - -typedef struct -{ - char * name; /* Name of the instruction. */ - unsigned int op_number; /* Operand Number or the number of operands. */ - MAX_ARG_TYPE arg[2]; /* Types of operands. */ - int format; /* Format bit. */ - int dst[2]; /* Destination in the move instruction. */ - int src[2]; /* Source in the move instruction. */ - int arch; /* The Machine architecture. */ - unsigned int instr_id; /* Added for decode and dissassembly. */ -} -MAXQ20_OPCODE_INFO; - -/* Structure for holding opcodes of the same name. */ -typedef struct -{ - const MAXQ20_OPCODE_INFO *start; /* The first opcode. */ - const MAXQ20_OPCODE_INFO *end; /* The last opcode. */ -} -MAXQ20_OPCODES; - -/* The entry into the hash table will be of the type MAXX_OPCODES. */ - -/* The definition of the table. */ -const MAXQ20_OPCODE_INFO op_table[] = -{ - /* LOGICAL OPERATIONS */ - /* AND src : f001 1010 ssss ssss */ - {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0}, - {REG | MEM | IMM | DISP, 0}, MAX, 0x11}, - /* AND Acc.<b> : 1111 1010 bbbb 1010 */ - {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39}, - /* OR src : f010 1010 ssss ssss */ - {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0}, - {REG | MEM | IMM | DISP, 0}, MAX, 0x12}, - /* OR Acc.<b> : 1010 1010 bbbb 1010 */ - {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A}, - /* XOR src : f011 1010 ssss ssss */ - {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0}, - {REG | MEM | IMM | DISP, 0}, MAX, 0x13}, - /* XOR Acc.<b> : 1011 1010 bbbb 1010 */ - {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B}, - /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */ - /* CPL : 1000 1010 0001 1010 */ - {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21}, - /* CPL C : 1101 1010 0010 1010 */ - {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D}, - /* NEG : 1000 1010 1001 1010 */ - {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29}, - /* SLA : 1000 1010 0010 1010 */ - {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22}, - /* SLA2: 1000 1010 0011 1010 */ - {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23}, - /* SLA4: 1000 1010 0110 1010 */ - {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26}, - /* RL : 1000 1010 0100 1010 */ - {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24}, - /* RLC : 1000 1010 0101 1010 */ - {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25}, - /* SRA : 1000 1010 1111 1010 */ - {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F}, - /* SRA2: 1000 1010 1110 1010 */ - {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E}, - /* SRA4: 1000 1010 1011 1010 */ - {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B}, - /* SR : 1000 1010 1010 1010 */ - {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A}, - /* RR : 1000 1010 1100 1010 */ - {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C}, - /* RRC : 1000 1010 1101 1010 */ - {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D}, - /* MATH OPERATIONS */ - /* ADD src : f100 1010 ssss ssss */ - {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x14}, - /* ADDC src : f110 1010 ssss ssss */ - {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x16}, - /* SUB src : f101 1010 ssss ssss */ - {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x15}, - /* SUBB src : f111 1010 ssss ssss */ - {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x17}, - /* BRANCHING OPERATIONS */ - - /* DJNZ LC[0] src: f100 1101 ssss ssss */ - {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0xA4}, - /* DJNZ LC[1] src: f101 1101 ssss ssss */ - {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0xA5}, - /* CALL src : f011 1101 ssss ssss */ - {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0xA3}, - /* JUMP src : f000 1100 ssss ssss */ - {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x50}, - /* JUMP C,src : f010 1100 ssss ssss */ - {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x52}, - /* JUMP NC,src: f110 1100 ssss ssss */ - {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x56}, - /* JUMP Z,src : f001 1100 ssss ssss */ - {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x51}, - /* JUMP NZ,src: f101 1100 ssss ssss */ - {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x55}, - /* JUMP E,src : 0011 1100 ssss ssss */ - {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53}, - /* JUMP NE,src: 0111 1100 ssss ssss */ - {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57}, - /* JUMP S,src : f100 1100 ssss ssss */ - {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0x54}, - /* RET : 1000 1100 0000 1101 */ - {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68}, - /* RET C : 1010 1100 0000 1101 */ - {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A}, - /* RET NC : 1110 1100 0000 1101 */ - {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E}, - /* RET Z : 1001 1100 0000 1101 */ - {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69}, - /* RET NZ : 1101 1100 0000 1101 */ - {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D}, - /* RET S : 1100 1100 0000 1101 */ - {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C}, - /* RETI : 1000 1100 1000 1101 */ - {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78}, - /* ADDED ACCORDING TO NEW SPECIFICATION */ - - /* RETI C : 1010 1100 1000 1101 */ - {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A}, - /* RETI NC : 1110 1100 1000 1101 */ - {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E}, - /* RETI Z : 1001 1100 1000 1101 */ - {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79}, - /* RETI NZ : 1101 1100 1000 1101 */ - {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D}, - /* RETI S : 1100 1100 1000 1101 */ - {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C}, - /* MISCELLANEOUS INSTRUCTIONS */ - /* CMP src : f111 1000 ssss ssss */ - {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0}, - {REG | MEM | IMM | DISP, 0}, MAX, 0xD7}, - /* DATA TRANSFER OPERATIONS */ - /* XCH : 1000 1010 1000 1010 */ - {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28}, - /* XCHN : 1000 1010 0111 1010 */ - {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27}, - /* PUSH src : f000 1101 ssss ssss */ - {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0}, - {IMM | REG | MEM | DISP, 0}, MAX, 0xA0}, - /* POP dst : 1ddd dddd 0000 1101 */ - {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0}, - /* Added according to new spec */ - /* POPI dst : 1ddd dddd 1000 1101 */ - {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0}, - /* MOVE dst,src: fddd dddd ssss ssss */ - {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT, - {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80}, - /* BIT OPERATIONS */ - /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */ - {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E}, - /* MOVE C,#0 : 1101 1010 0000 1010 */ - {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D}, - /* MOVE C,#1 : 1101 1010 0001 1010 */ - {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D}, - /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */ - {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F}, - /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */ - {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40}, - /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */ - {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41}, - /* MOVE C,src.<b> : fbbb 0111 ssss ssss */ - {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97}, - /* NOP : 1101 1010 0011 1010 */ - {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D}, - {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00} -}; - -/* All the modules. */ - -#define MOD0 0x0 -#define MOD1 0x1 -#define MOD2 0x2 -#define MOD3 0x3 -#define MOD4 0x4 -#define MOD5 0x5 -#define MOD6 0x6 -#define MOD7 0x7 -#define MOD8 0x8 -#define MOD9 0x9 -#define MODA 0xa -#define MODB 0xb -#define MODC 0xc -#define MODD 0xd -#define MODE 0xe -#define MODF 0xf - -/* Added according to new specification. */ -#define MOD10 0x10 -#define MOD11 0x11 -#define MOD12 0x12 -#define MOD13 0x13 -#define MOD14 0x14 -#define MOD15 0x15 -#define MOD16 0x16 -#define MOD17 0x17 -#define MOD18 0x18 -#define MOD19 0x19 -#define MOD1A 0x1a -#define MOD1B 0x1b -#define MOD1C 0x1c -#define MOD1D 0x1d -#define MOD1E 0x1e -#define MOD1F 0x1f - -/* - Peripheral Register Modules - */ -/* Serial Register Modules. */ -#define CTRL MOD8 /* For the module containing the control registers. */ -#define ACC MOD9 /* For the module containing the 16 accumulators. */ -#define Act_ACC MODA /* For the module containing the active accumulator. */ -#define PFX MODB /* For the module containing the prefix registers. */ -#define IP MODC /* For the module containing the instruction pointer register. */ -#define SPIV MODD /* For the module containing the stack pointer and the interrupt vector. */ -#define LC MODD /* For the module containing the loop counters and HILO registers. */ -#define DP MODF /* For the module containig the data pointer registers. */ - -/* Register Types. */ -typedef enum _Reg_type -{ Reg_8R, /* 8 bit register. read only. */ - Reg_16R, /* 16 bit register, read only. */ - Reg_8W, /* 8 bit register, both read and write. */ - Reg_16W /* 16 bit register, both read and write. */ -} -Reg_type; - -/* Register Structure. */ -typedef struct reg -{ - char *reg_name; /* Register name. */ - short int Mod_name; /* The module name. */ - short int Mod_index; /* The module index. */ - int opcode; /* The opcode of the register. */ - Reg_type rtype; /* 8 bit/16 bit and read only/read write. */ - int arch; /* The Machine architecture. */ -} -reg_entry; - -reg_entry *new_reg_table = NULL; -int num_of_reg = 0; - -typedef struct -{ - char *rname; - int rindex; -} -reg_index; - -/* Register Table description. */ -reg_entry system_reg_table[] = -{ - /* Serial Registers */ - /* MODULE 8 Registers : I call them the control registers. */ - /* Accumulator Pointer CTRL[0h] */ - { - "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX}, - /* Accumulator Pointer Control Register : CTRL[1h] */ - - { - "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX}, - /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */ - { - "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX}, - /* Interrupt and Control Register : CTRL[5h] */ - { - "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX}, - /* Interrupt Mask Register : CTRL[6h] */ - { - "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX}, - /* Interrupt System Control : CTRL[8h] */ - { - "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX}, - /* Interrupt Identification Register : CTRL[Bh] */ - { - "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX}, - /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */ - { - "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX}, - /* Watchdog Control Register : CTRL[Fh] */ - { - "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX}, - /* The 16 accumulator registers : ACC[0h-Fh] */ - { - "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20}, - { - "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20}, - { - "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20}, - { - "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20}, - { - "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20}, - { - "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20}, - { - "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20}, - { - "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20}, - { - "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20}, - { - "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20}, - { - "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20}, - { - "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20}, - { - "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20}, - { - "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20}, - { - "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20}, - { - "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20}, - /* The Active Accumulators : Act_Acc[0h-1h] */ - { - "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20}, - { - "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20}, - /* The 16 accumulator registers : ACC[0h-Fh] */ - { - "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10}, - { - "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10}, - { - "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10}, - { - "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10}, - { - "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10}, - { - "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10}, - { - "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10}, - { - "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10}, - { - "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10}, - { - "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10}, - { - "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10}, - { - "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10}, - { - "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10}, - { - "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10}, - { - "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10}, - { - "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10}, - /* The Active Accumulators : Act_Acc[0h-1h] */ - { - "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10}, - /* The Active Accumulators : Act_Acc[0h-1h] */ - { - "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10}, - /* The Prefix Registers : PFX[0h,2h] */ - { - "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX}, - { - "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX}, - { - "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX}, - { - "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX}, - { - "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX}, - { - "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX}, - { - "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX}, - { - "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX}, - /* The Instruction Pointer Registers : IP[0h,8h] */ - { - "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX}, - /* The Stack Pointer Registers : SPIV[1h,9h] */ - { - "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX}, - /* The Interrupt Vector Registers : SPIV[2h,Ah] */ - { - "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX}, - /* ADDED for New Specification */ - - /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */ - { - "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX}, - { - "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX}, - /* MODULE Eh Whole Column has changed */ - - { - "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX}, - { - "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX}, - { - "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX}, - { - "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX}, - { - "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX}, - { - "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX}, - { - "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX}, - { - "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX}, - { - "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX}, - /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */ - { - "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX}, - { - "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX}, -}; -typedef struct -{ - char *name; - int type; -} -match_table; - -#define GPIO0 0x00 /* Gerneral Purpose I/O Module 0. */ -#define GPIO1 0x01 /* Gerneral Purpose I/O Module 1. */ -#define RTC 0x00 /* Real Time Clock Module. */ -#define MAC 0x02 /* Hardware Multiplier Module. */ -#define SER0 0x02 /* Contains the UART Registers. */ -#define SPI 0x03 /* Serial Pheripheral Interface Module. */ -#define OWBM 0x03 /* One Wire Bus Module. */ -#define SER1 0x03 /* Contains the UART Registers. */ -#define TIMER20 0x03 /* Timer Counter Module 2. */ -#define TIMER21 0x04 /* Timer Counter Module 2. */ -#define JTAGD 0x03 /* In-Circuit Debugging Support. */ -#define LCD 0x03 /* LCD register Modules. */ - -/* Plugable modules register table f. */ - -reg_entry peripheral_reg_table[] = -{ - /* -------- The GPIO Module Registers -------- */ - /* Port n Output Registers : GPIO[0h-4h] */ - { - "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX}, - { - "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX}, - { - "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX}, - { - "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX}, - /* External Interrupt Flag Register : GPIO[6h] */ - { - "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX}, - /* External Interrupt Enable Register : GPIO[7h] */ - { - "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX}, - /* Port n Input Registers : GPIO[8h-Bh] */ - { - "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX}, - { - "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX}, - { - "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX}, - { - "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX}, - { - "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX}, - /* Port n Direction Registers : GPIO[Ch-Fh] */ - { - "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX}, - { - "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX}, - { - "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX}, - { - "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX}, - /* -------- Real Time Counter Module RTC -------- */ - /* RTC Control Register : [01h] */ - { - "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX}, - /* RTC Seconds High [02h] */ - { - "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX}, - /* RTC Seconds Low [03h] */ - { - "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX}, - /* RTC Subsecond Register [04h] */ - { - "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX}, - /* RTC Alarm seconds high [05h] */ - { - "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX}, - /* RTC Alarm seconds high [06h] */ - { - "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX}, - /* RTC Subsecond Alarm Register [07h] */ - { - "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX}, - /* -------- The GPIO Module Registers -------- */ - /* Port n Output Registers : GPIO[0h-4h] */ - { - "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX}, - { - "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX}, - { - "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX}, - { - "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX}, - /* External Interrupt Flag Register : GPIO[6h] */ - { - "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX}, - /* External Interrupt Enable Register : GPIO[7h] */ - { - "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX}, - /* Port n Input Registers : GPIO[8h-Bh] */ - { - "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX}, - { - "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX}, - { - "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX}, - { - "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX}, - { - "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX}, - /* Port n Direction Registers : GPIO[Ch-Fh] */ - { - "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX}, - { - "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX}, - { - "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX}, - { - "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX}, -#if 0 - /* Supply Boltage Check Register */ - { - "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX}, - /* Wake up output register */ - { - "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX}, -#endif /* */ - - /* -------- MAC Hardware multiplier module -------- */ - /* MAC Hardware Multiplier control register: [01h] */ - { - "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX}, - /* MAC Multiplier Operand A Register [02h] */ - { - "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX}, - /* MAC Multiplier Operand B Register [03h] */ - { - "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX}, - /* MAC Multiplier Accumulator 2 Register [04h] */ - { - "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX}, - /* MAC Multiplier Accumulator 1 Register [05h] */ - { - "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX}, - /* MAC Multiplier Accumulator 0 Register [06h] */ - { - "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX}, - /* -------- The Serial I/O module SER -------- */ - /* UART registers */ - /* Serial Port Control Register : SER[6h] */ - { - "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX}, - /* Serial Data Buffer Register : SER[7h] */ - { - "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX}, - /* Serial Port Mode Register : SER[4h] */ - { - "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX}, - /* Serial Port Phase Register : SER[4h] */ - { - "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX}, - /* ------ LCD Display Module ---------- */ - { - "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX}, - { - "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX}, - { - "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX}, - { - "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX}, - { - "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX}, - { - "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX}, - { - "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX}, - { - "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX}, - { - "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX}, - { - "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX}, - { - "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX}, - { - "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX}, - { - "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX}, - { - "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX}, - { - "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX}, - { - "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX}, - { - "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX}, - { - "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX}, - { - "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX}, - /* -------- SPI registers -------- */ - /* SPI data buffer Register : SER[7h] */ - { - "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX}, - /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */ - { - "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX}, - /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read - only. */ - { - "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX}, - /* SPI Clock Register : SER[Ah] */ - { - "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX}, - /* -------- One Wire Bus Master OWBM -------- */ - /* OWBM One Wire address Register register: [01h] */ - { - "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX}, - /* OWBM One Wire Data register: [02h] */ - { - "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX}, - /* -------- The Serial I/O module SER -------- */ - /* UART registers */ - /* Serial Port Control Register : SER[6h] */ - { - "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX}, - /* Serial Data Buffer Register : SER[7h] */ - { - "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX}, - /* Serial Port Mode Register : SER[4h] */ - { - "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX}, - /* Serial Port Phase Register : SER[4h] */ - { - "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX}, - /* -------- Timer/Counter 2 Module -------- */ - /* Timer 2 configuration Register : TC[3h] */ - { - "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX}, - { - "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX}, - { - "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX}, - { - "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX}, - { - "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX}, - { - "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX}, - { - "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX}, - { - "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX}, - { - "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX}, - /* Timer 2-1 configuration Register : TC[4h] */ - - { - "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX}, - { - "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX}, - { - "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX}, - { - "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX}, - { - "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX}, - { - "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX}, - { - "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX}, - { - "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX}, - { - "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX}, - { - "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX}, - { - "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX}, - { - "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX}, - { - "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX}, - { - "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX}, - { - "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX}, - { - "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX}, - { - "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX}, - { - "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX}, - { - NULL, 0, 0, 0, 0, 0} -}; - -/* Memory access argument. */ -struct mem_access -{ - char *name; /* Name of the Memory access operand. */ - int opcode; /* Its corresponding opcode. */ -}; -typedef struct mem_access mem_access; - -/* The Memory table for accessing the data memory through particular registers. */ -struct mem_access mem_table[] = -{ - /* The Pop Operation on the stack. */ - {"@SP--", 0x0d}, - /* Data Pointer 0 */ - {"@DP[0]", 0x0f}, - /* Data Ponter 1 */ - {"@DP[1]", 0x4f}, - /* Data Pointer 0 post increment */ - {"@DP[0]++", 0x1f}, - /* Data Pointer 1 post increment */ - {"@DP[1]++", 0x5f}, - /* Data Pointer 0 post decrement */ - {"@DP[0]--", 0x2f}, - /* Data Pointer 1 post decrement */ - {"@DP[1]--", 0x6f}, - /* ADDED According to New Specification. */ - - {"@BP[OFFS]", 0x0E}, - {"@BP[OFFS++]", 0x1E}, - {"@BP[OFFS--]", 0x2E}, - {"NUL", 0x76}, - {"@++SP", 0x0D}, - {"@BP[++OFFS]", 0x1E}, - {"@BP[--OFFS]", 0x2E}, - {"@++DP[0]", 0x1F}, - {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F} -}; - -/* Register bit argument. */ -struct reg_bit -{ - reg_entry *reg; - int bit; -}; -typedef struct reg_bit reg_bit; - -/* There are certain names given to particular bits of some registers. - These will be taken care of here. */ -struct bit_name -{ - char *name; - char *reg_bit; -}; -typedef struct bit_name bit_name; - -bit_name bit_table[] = -{ - { - "RI", "SCON.0"}, - /* FOr APC */ - { - "MOD0", "APC.0"}, - { - "MOD1", "APC.1"}, - { - "MOD2", "APC.2"}, - { - "IDS", "APC.6"}, - { - "CLR", "APC.6"}, - /* For PSF */ - { - "E", "PSF.0"}, - { - "C", "PSF.1"}, - { - "OV", "PSF.2"}, - { - "S", "PSF.6"}, - { - "Z", "PSF.7"}, - /* For IC */ - - { - "IGE", "IC.0"}, - { - "INS", "IC.1"}, - { - "CGDS", "IC.5"}, - /* For IMR */ - - { - "IM0", "IMR.0"}, - { - "IM1", "IMR.1"}, - { - "IM2", "IMR.2"}, - { - "IM3", "IMR.3"}, - { - "IM4", "IMR.4"}, - { - "IM5", "IMR.5"}, - { - "IMS", "IMR.7"}, - /* For SC */ - { - "PWL", "SC.1"}, - { - "ROD", "SC.2"}, - { - "UPA", "SC.3"}, - { - "CDA0", "SC.4"}, - { - "CDA1", "SC.5"}, - /* For IIR */ - - { - "II0", "IIR.0"}, - { - "II1", "IIR.1"}, - { - "II2", "IIR.2"}, - { - "II3", "IIR.3"}, - { - "II4", "IIR.4"}, - { - "II5", "IIR.5"}, - { - "IIS", "IIR.7"}, - /* For CKCN */ - - { - "CD0", "CKCN.0"}, - { - "CD1", "CKCN.1"}, - { - "PMME", "CKCN.2"}, - { - "SWB", "CKCN.3"}, - { - "STOP", "CKCN.4"}, - { - "RGMD", "CKCN.5"}, - { - "RGSL", "CKCN.6"}, - /* For WDCN */ - - { - "RWT", "WDCN.0"}, - { - "EWT", "WDCN.1"}, - { - "WTRF", "WDCN.2"}, - { - "WDIF", "WDCN.3"}, - { - "WD0", "WDCN.4"}, - { - "WD1", "WDCN.5"}, - { - "EWDI", "WDCN.6"}, - { - "POR", "WDCN.7"}, - /* For DPC */ - - { - "DPS0", "DPC.0"}, - { - "DPS1", "DPC.1"}, - { - "WBS0", "DPC.2"}, - { - "WBS1", "DPC.3"}, - { - "WBS2", "DPC.4"}, - - /* For SCON */ - { - "TI", "SCON.1"}, - { - "RB8", "SCON.2"}, - { - "TB8", "SCON.3"}, - { - "REN", "SCON.4"}, - { - "SM2", "SCON.5"}, - { - "SM1", "SCON.6"}, - { - "SM0", "SCON.7"}, - { - "FE", "SCON.7"} -}; - -const char *LSInstr[] = -{ - "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP", - "DJNZ", "CALL", NULL -}; - -typedef enum -{ - DST, - SRC, - BOTH, -} -type1; - -struct mem_access_syntax -{ - char name[12]; /* Name of the Memory access operand. */ - type1 type; - char *invalid_op[5]; -}; -typedef struct mem_access_syntax mem_access_syntax; - -/* The Memory Access table for accessing the data memory through particular - registers. */ -const mem_access_syntax mem_access_syntax_table[] = -{ - { - "@SP--", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - /* Data Pointer 0 */ - { - "@DP[0]", BOTH, - { - "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}}, - /* Data Ponter 1 */ - { - "@DP[1]", BOTH, - { - "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}}, - /* Data Pointer 0 post increment */ - { - "@DP[0]++", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - /* Data Pointer 1 post increment */ - { - "@DP[1]++", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - /* Data Pointer 0 post decrement */ - { - "@DP[0]--", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - /* Data Pointer 1 post decrement */ - { - "@DP[1]--", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - /* ADDED According to New Specification */ - - { - "@BP[OFFS]", BOTH, - { - "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}}, - { - "@BP[OFFS++]", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - { - "@BP[OFFS--]", SRC, - { - NULL, NULL, NULL, NULL, NULL}}, - { - "NUL", DST, - { - NULL, NULL, NULL, NULL, NULL}}, - { - "@++SP", DST, - { - NULL, NULL, NULL, NULL, NULL}}, - { - "@BP[++OFFS]", DST, - { - "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}}, - { - "@BP[--OFFS]", DST, - { - "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}}, - { - "@++DP[0]", DST, - { - "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}}, - { - "@++DP[1]", DST, - { - "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}}, - { - "@--DP[0]", DST, - { - "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}}, - { - "@--DP[1]", DST, - { - "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}} -}; - -#endif diff --git a/include/opcode/mips.h b/include/opcode/mips.h deleted file mode 100644 index e46ba2c09..000000000 --- a/include/opcode/mips.h +++ /dev/null @@ -1,985 +0,0 @@ -/* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005 - Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _MIPS_H_ -#define _MIPS_H_ - -/* These are bit masks and shift counts to use to access the various - fields of an instruction. To retrieve the X field of an - instruction, use the expression - (i >> OP_SH_X) & OP_MASK_X - To set the same field (to j), use - i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) - - Make sure you use fields that are appropriate for the instruction, - of course. - - The 'i' format uses OP, RS, RT and IMMEDIATE. - - The 'j' format uses OP and TARGET. - - The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. - - The 'b' format uses OP, RS, RT and DELTA. - - The floating point 'i' format uses OP, RS, RT and IMMEDIATE. - - The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. - - A breakpoint instruction uses OP, CODE and SPEC (10 bits of the - breakpoint instruction are not defined; Kane says the breakpoint - code field in BREAK is 20 bits; yet MIPS assemblers and debuggers - only use ten bits). An optional two-operand form of break/sdbbp - allows the lower ten bits to be set too, and MIPS32 and later - architectures allow 20 bits to be set with a signal operand - (using CODE20). - - The syscall instruction uses CODE20. - - The general coprocessor instructions use COPZ. */ - -#define OP_MASK_OP 0x3f -#define OP_SH_OP 26 -#define OP_MASK_RS 0x1f -#define OP_SH_RS 21 -#define OP_MASK_FR 0x1f -#define OP_SH_FR 21 -#define OP_MASK_FMT 0x1f -#define OP_SH_FMT 21 -#define OP_MASK_BCC 0x7 -#define OP_SH_BCC 18 -#define OP_MASK_CODE 0x3ff -#define OP_SH_CODE 16 -#define OP_MASK_CODE2 0x3ff -#define OP_SH_CODE2 6 -#define OP_MASK_RT 0x1f -#define OP_SH_RT 16 -#define OP_MASK_FT 0x1f -#define OP_SH_FT 16 -#define OP_MASK_CACHE 0x1f -#define OP_SH_CACHE 16 -#define OP_MASK_RD 0x1f -#define OP_SH_RD 11 -#define OP_MASK_FS 0x1f -#define OP_SH_FS 11 -#define OP_MASK_PREFX 0x1f -#define OP_SH_PREFX 11 -#define OP_MASK_CCC 0x7 -#define OP_SH_CCC 8 -#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ -#define OP_SH_CODE20 6 -#define OP_MASK_SHAMT 0x1f -#define OP_SH_SHAMT 6 -#define OP_MASK_FD 0x1f -#define OP_SH_FD 6 -#define OP_MASK_TARGET 0x3ffffff -#define OP_SH_TARGET 0 -#define OP_MASK_COPZ 0x1ffffff -#define OP_SH_COPZ 0 -#define OP_MASK_IMMEDIATE 0xffff -#define OP_SH_IMMEDIATE 0 -#define OP_MASK_DELTA 0xffff -#define OP_SH_DELTA 0 -#define OP_MASK_FUNCT 0x3f -#define OP_SH_FUNCT 0 -#define OP_MASK_SPEC 0x3f -#define OP_SH_SPEC 0 -#define OP_SH_LOCC 8 /* FP condition code. */ -#define OP_SH_HICC 18 /* FP condition code. */ -#define OP_MASK_CC 0x7 -#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ -#define OP_MASK_COP1NORM 0x1 /* a single bit. */ -#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ -#define OP_MASK_COP1SPEC 0xf -#define OP_MASK_COP1SCLR 0x4 -#define OP_MASK_COP1CMP 0x3 -#define OP_SH_COP1CMP 4 -#define OP_SH_FORMAT 21 /* FP short format field. */ -#define OP_MASK_FORMAT 0x7 -#define OP_SH_TRUE 16 -#define OP_MASK_TRUE 0x1 -#define OP_SH_GE 17 -#define OP_MASK_GE 0x01 -#define OP_SH_UNSIGNED 16 -#define OP_MASK_UNSIGNED 0x1 -#define OP_SH_HINT 16 -#define OP_MASK_HINT 0x1f -#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ -#define OP_MASK_MMI 0x3f -#define OP_SH_MMISUB 6 -#define OP_MASK_MMISUB 0x1f -#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ -#define OP_SH_PERFREG 1 -#define OP_SH_SEL 0 /* Coprocessor select field. */ -#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ -#define OP_SH_CODE19 6 /* 19 bit wait code. */ -#define OP_MASK_CODE19 0x7ffff -#define OP_SH_ALN 21 -#define OP_MASK_ALN 0x7 -#define OP_SH_VSEL 21 -#define OP_MASK_VSEL 0x1f -#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, - but 0x8-0xf don't select bytes. */ -#define OP_SH_VECBYTE 22 -#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ -#define OP_SH_VECALIGN 21 -#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ -#define OP_SH_INSMSB 11 -#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ -#define OP_SH_EXTMSBD 11 - -/* MIPS DSP ASE */ -#define OP_SH_DSPACC 11 -#define OP_MASK_DSPACC 0x3 -#define OP_SH_DSPACC_S 21 -#define OP_MASK_DSPACC_S 0x3 -#define OP_SH_DSPSFT 20 -#define OP_MASK_DSPSFT 0x3f -#define OP_SH_DSPSFT_7 19 -#define OP_MASK_DSPSFT_7 0x7f -#define OP_SH_SA3 21 -#define OP_MASK_SA3 0x7 -#define OP_SH_SA4 21 -#define OP_MASK_SA4 0xf -#define OP_SH_IMM8 16 -#define OP_MASK_IMM8 0xff -#define OP_SH_IMM10 16 -#define OP_MASK_IMM10 0x3ff -#define OP_SH_WRDSP 11 -#define OP_MASK_WRDSP 0x3f -#define OP_SH_RDDSP 16 -#define OP_MASK_RDDSP 0x3f - -/* MIPS MT ASE */ -#define OP_SH_MT_U 5 -#define OP_MASK_MT_U 0x1 -#define OP_SH_MT_H 4 -#define OP_MASK_MT_H 0x1 -#define OP_SH_MTACC_T 18 -#define OP_MASK_MTACC_T 0x3 -#define OP_SH_MTACC_D 13 -#define OP_MASK_MTACC_D 0x3 - -#define OP_OP_COP0 0x10 -#define OP_OP_COP1 0x11 -#define OP_OP_COP2 0x12 -#define OP_OP_COP3 0x13 -#define OP_OP_LWC1 0x31 -#define OP_OP_LWC2 0x32 -#define OP_OP_LWC3 0x33 /* a.k.a. pref */ -#define OP_OP_LDC1 0x35 -#define OP_OP_LDC2 0x36 -#define OP_OP_LDC3 0x37 /* a.k.a. ld */ -#define OP_OP_SWC1 0x39 -#define OP_OP_SWC2 0x3a -#define OP_OP_SWC3 0x3b -#define OP_OP_SDC1 0x3d -#define OP_OP_SDC2 0x3e -#define OP_OP_SDC3 0x3f /* a.k.a. sd */ - -/* Values in the 'VSEL' field. */ -#define MDMX_FMTSEL_IMM_QH 0x1d -#define MDMX_FMTSEL_IMM_OB 0x1e -#define MDMX_FMTSEL_VEC_QH 0x15 -#define MDMX_FMTSEL_VEC_OB 0x16 - -/* This structure holds information for a particular instruction. */ - -struct mips_opcode -{ - /* The name of the instruction. */ - const char *name; - /* A string describing the arguments for this instruction. */ - const char *args; - /* The basic opcode for the instruction. When assembling, this - opcode is modified by the arguments to produce the actual opcode - that is used. If pinfo is INSN_MACRO, then this is 0. */ - unsigned long match; - /* If pinfo is not INSN_MACRO, then this is a bit mask for the - relevant portions of the opcode when disassembling. If the - actual opcode anded with the match field equals the opcode field, - then we have found the correct instruction. If pinfo is - INSN_MACRO, then this field is the macro identifier. */ - unsigned long mask; - /* For a macro, this is INSN_MACRO. Otherwise, it is a collection - of bits describing the instruction, notably any relevant hazard - information. */ - unsigned long pinfo; - /* A collection of additional bits describing the instruction. */ - unsigned long pinfo2; - /* A collection of bits describing the instruction sets of which this - instruction or macro is a member. */ - unsigned long membership; -}; - -/* These are the characters which may appear in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - Each of these characters corresponds to a mask field defined above. - - "<" 5 bit shift amount (OP_*_SHAMT) - ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) - "a" 26 bit target address (OP_*_TARGET) - "b" 5 bit base register (OP_*_RS) - "c" 10 bit breakpoint code (OP_*_CODE) - "d" 5 bit destination register specifier (OP_*_RD) - "h" 5 bit prefx hint (OP_*_PREFX) - "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) - "j" 16 bit signed immediate (OP_*_DELTA) - "k" 5 bit cache opcode in target register position (OP_*_CACHE) - Also used for immediate operands in vr5400 vector insns. - "o" 16 bit signed offset (OP_*_DELTA) - "p" 16 bit PC relative branch target address (OP_*_DELTA) - "q" 10 bit extra breakpoint code (OP_*_CODE2) - "r" 5 bit same register used as both source and target (OP_*_RS) - "s" 5 bit source register specifier (OP_*_RS) - "t" 5 bit target register (OP_*_RT) - "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) - "v" 5 bit same register used as both source and destination (OP_*_RS) - "w" 5 bit same register used as both target and destination (OP_*_RT) - "U" 5 bit same destination register in both OP_*_RD and OP_*_RT - (used by clo and clz) - "C" 25 bit coprocessor function code (OP_*_COPZ) - "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) - "J" 19 bit wait function code (OP_*_CODE19) - "x" accept and ignore register name - "z" must be zero register - "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) - "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). - Enforces: 0 <= pos < 32. - "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - (Also used by "dext" w/ different limits, but limits for - that are checked by the M_DEXT macro.) - "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). - Enforces: 32 <= pos < 64. - "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - - Floating point instructions: - "D" 5 bit destination register (OP_*_FD) - "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) - "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) - "S" 5 bit fs source 1 register (OP_*_FS) - "T" 5 bit ft source 2 register (OP_*_FT) - "R" 5 bit fr source 3 register (OP_*_FR) - "V" 5 bit same register used as floating source and destination (OP_*_FS) - "W" 5 bit same register used as floating target and destination (OP_*_FT) - - Coprocessor instructions: - "E" 5 bit target register (OP_*_RT) - "G" 5 bit destination register (OP_*_RD) - "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) - "P" 5 bit performance-monitor register (OP_*_PERFREG) - "e" 5 bit vector register byte specifier (OP_*_VECBYTE) - "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) - see also "k" above - "+D" Combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only. - - Macro instructions: - "A" General 32 bit expression - "I" 32 bit immediate (value placed in imm_expr). - "+I" 32 bit immediate (value placed in imm2_expr). - "F" 64 bit floating point constant in .rdata - "L" 64 bit floating point constant in .lit8 - "f" 32 bit floating point constant - "l" 32 bit floating point constant in .lit4 - - MDMX instruction operands (note that while these use the FP register - fields, they accept both $fN and $vN names for the registers): - "O" MDMX alignment offset (OP_*_ALN) - "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) - "X" MDMX destination register (OP_*_FD) - "Y" MDMX source register (OP_*_FS) - "Z" MDMX source register (OP_*_FT) - - DSP ASE usage: - "3" 3 bit unsigned immediate (OP_*_SA3) - "4" 4 bit unsigned immediate (OP_*_SA4) - "5" 8 bit unsigned immediate (OP_*_IMM8) - "6" 5 bit unsigned immediate (OP_*_RS) - "7" 2 bit dsp accumulator register (OP_*_DSPACC) - "8" 6 bit unsigned immediate (OP_*_WRDSP) - "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) - "0" 6 bit signed immediate (OP_*_DSPSFT) - ":" 7 bit signed immediate (OP_*_DSPSFT_7) - "'" 6 bit unsigned immediate (OP_*_RDDSP) - "@" 10 bit signed immediate (OP_*_IMM10) - - MT ASE usage: - "!" 1 bit immediate at bit 5 - "$" 1 bit immediate at bit 4 - "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) - "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) - "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) - "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only - - Other: - "()" parens surrounding optional value - "," separates operands - "[]" brackets around index for vector-op scalar operand specifier (vr5400) - "+" Start of extension sequence. - - Characters used so far, for quick reference when adding more: - "34567890" - "%[]<>(),+:'@!$*&" - "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdefghijklopqrstuvwxz" - - Extension character sequences used so far ("+" followed by the - following), for quick reference when adding more: - "ABCDEFGHIT" - "t" -*/ - -/* These are the bits which may be set in the pinfo field of an - instructions, if it is not equal to INSN_MACRO. */ - -/* Modifies the general purpose register in OP_*_RD. */ -#define INSN_WRITE_GPR_D 0x00000001 -/* Modifies the general purpose register in OP_*_RT. */ -#define INSN_WRITE_GPR_T 0x00000002 -/* Modifies general purpose register 31. */ -#define INSN_WRITE_GPR_31 0x00000004 -/* Modifies the floating point register in OP_*_FD. */ -#define INSN_WRITE_FPR_D 0x00000008 -/* Modifies the floating point register in OP_*_FS. */ -#define INSN_WRITE_FPR_S 0x00000010 -/* Modifies the floating point register in OP_*_FT. */ -#define INSN_WRITE_FPR_T 0x00000020 -/* Reads the general purpose register in OP_*_RS. */ -#define INSN_READ_GPR_S 0x00000040 -/* Reads the general purpose register in OP_*_RT. */ -#define INSN_READ_GPR_T 0x00000080 -/* Reads the floating point register in OP_*_FS. */ -#define INSN_READ_FPR_S 0x00000100 -/* Reads the floating point register in OP_*_FT. */ -#define INSN_READ_FPR_T 0x00000200 -/* Reads the floating point register in OP_*_FR. */ -#define INSN_READ_FPR_R 0x00000400 -/* Modifies coprocessor condition code. */ -#define INSN_WRITE_COND_CODE 0x00000800 -/* Reads coprocessor condition code. */ -#define INSN_READ_COND_CODE 0x00001000 -/* TLB operation. */ -#define INSN_TLB 0x00002000 -/* Reads coprocessor register other than floating point register. */ -#define INSN_COP 0x00004000 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00008000 -/* Instruction loads value from coprocessor, requiring delay. */ -#define INSN_LOAD_COPROC_DELAY 0x00010000 -/* Instruction has unconditional branch delay slot. */ -#define INSN_UNCOND_BRANCH_DELAY 0x00020000 -/* Instruction has conditional branch delay slot. */ -#define INSN_COND_BRANCH_DELAY 0x00040000 -/* Conditional branch likely: if branch not taken, insn nullified. */ -#define INSN_COND_BRANCH_LIKELY 0x00080000 -/* Moves to coprocessor register, requiring delay. */ -#define INSN_COPROC_MOVE_DELAY 0x00100000 -/* Loads coprocessor register from memory, requiring delay. */ -#define INSN_COPROC_MEMORY_DELAY 0x00200000 -/* Reads the HI register. */ -#define INSN_READ_HI 0x00400000 -/* Reads the LO register. */ -#define INSN_READ_LO 0x00800000 -/* Modifies the HI register. */ -#define INSN_WRITE_HI 0x01000000 -/* Modifies the LO register. */ -#define INSN_WRITE_LO 0x02000000 -/* Takes a trap (easier to keep out of delay slot). */ -#define INSN_TRAP 0x04000000 -/* Instruction stores value into memory. */ -#define INSN_STORE_MEMORY 0x08000000 -/* Instruction uses single precision floating point. */ -#define FP_S 0x10000000 -/* Instruction uses double precision floating point. */ -#define FP_D 0x20000000 -/* Instruction is part of the tx39's integer multiply family. */ -#define INSN_MULT 0x40000000 -/* Instruction synchronize shared memory. */ -#define INSN_SYNC 0x80000000 - -/* These are the bits which may be set in the pinfo2 field of an - instruction. */ - -/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ -#define INSN2_ALIAS 0x00000001 -/* Instruction reads MDMX accumulator. */ -#define INSN2_READ_MDMX_ACC 0x00000002 -/* Instruction writes MDMX accumulator. */ -#define INSN2_WRITE_MDMX_ACC 0x00000004 - -/* Instruction is actually a macro. It should be ignored by the - disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff - -/* Masks used to mark instructions to indicate which MIPS ISA level - they were introduced in. ISAs, as defined below, are logical - ORs of these bits, indicating that they support the instructions - defined at the given level. */ - -#define INSN_ISA_MASK 0x00000fff -#define INSN_ISA1 0x00000001 -#define INSN_ISA2 0x00000002 -#define INSN_ISA3 0x00000004 -#define INSN_ISA4 0x00000008 -#define INSN_ISA5 0x00000010 -#define INSN_ISA32 0x00000020 -#define INSN_ISA64 0x00000040 -#define INSN_ISA32R2 0x00000080 -#define INSN_ISA64R2 0x00000100 - -/* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x0400f000 - -/* DSP ASE */ -#define INSN_DSP 0x00001000 -/* MIPS 16 ASE */ -#define INSN_MIPS16 0x00002000 -/* MIPS-3D ASE */ -#define INSN_MIPS3D 0x00004000 -/* MDMX ASE */ -#define INSN_MDMX 0x00008000 - -/* Chip specific instructions. These are bitmasks. */ - -/* MIPS R4650 instruction. */ -#define INSN_4650 0x00010000 -/* LSI R4010 instruction. */ -#define INSN_4010 0x00020000 -/* NEC VR4100 instruction. */ -#define INSN_4100 0x00040000 -/* Toshiba R3900 instruction. */ -#define INSN_3900 0x00080000 -/* MIPS R10000 instruction. */ -#define INSN_10000 0x00100000 -/* Broadcom SB-1 instruction. */ -#define INSN_SB1 0x00200000 -/* NEC VR4111/VR4181 instruction. */ -#define INSN_4111 0x00400000 -/* NEC VR4120 instruction. */ -#define INSN_4120 0x00800000 -/* NEC VR5400 instruction. */ -#define INSN_5400 0x01000000 -/* NEC VR5500 instruction. */ -#define INSN_5500 0x02000000 -/* MT ASE */ -#define INSN_MT 0x04000000 - -/* MIPS ISA defines, use instead of hardcoding ISA level. */ - -#define ISA_UNKNOWN 0 /* Gas internal use. */ -#define ISA_MIPS1 (INSN_ISA1) -#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) -#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) -#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) -#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) - -#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) -#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) - -#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) -#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) - - -/* CPU defines, use instead of hardcoding processor number. Keep this - in sync with bfd/archures.c in order for machine selection to work. */ -#define CPU_UNKNOWN 0 /* Gas internal use. */ -#define CPU_R3000 3000 -#define CPU_R3900 3900 -#define CPU_R4000 4000 -#define CPU_R4010 4010 -#define CPU_VR4100 4100 -#define CPU_R4111 4111 -#define CPU_VR4120 4120 -#define CPU_R4300 4300 -#define CPU_R4400 4400 -#define CPU_R4600 4600 -#define CPU_R4650 4650 -#define CPU_R5000 5000 -#define CPU_VR5400 5400 -#define CPU_VR5500 5500 -#define CPU_R6000 6000 -#define CPU_RM7000 7000 -#define CPU_R8000 8000 -#define CPU_RM9000 9000 -#define CPU_R10000 10000 -#define CPU_R12000 12000 -#define CPU_MIPS16 16 -#define CPU_MIPS32 32 -#define CPU_MIPS32R2 33 -#define CPU_MIPS5 5 -#define CPU_MIPS64 64 -#define CPU_MIPS64R2 65 -#define CPU_SB1 12310201 /* octal 'SB', 01. */ - -/* Test for membership in an ISA including chip specific ISAs. INSN - is pointer to an element of the opcode table; ISA is the specified - ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to - test, or zero if no CPU specific ISA test is desired. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu) \ - (((insn)->membership & isa) != 0 \ - || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ - || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ - || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ - && ((insn)->membership & INSN_10000) != 0) \ - || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ - || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ - || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ - || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ - || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ - || 0) /* Please keep this term for easier source merging. */ - -/* This is a list of macro expanded instructions. - - _I appended means immediate - _A appended means address - _AB appended means address with base register - _D appended means 64 bit floating point constant - _S appended means 32 bit floating point constant. */ - -enum -{ - M_ABS, - M_ADD_I, - M_ADDU_I, - M_AND_I, - M_BEQ, - M_BEQ_I, - M_BEQL_I, - M_BGE, - M_BGEL, - M_BGE_I, - M_BGEL_I, - M_BGEU, - M_BGEUL, - M_BGEU_I, - M_BGEUL_I, - M_BGT, - M_BGTL, - M_BGT_I, - M_BGTL_I, - M_BGTU, - M_BGTUL, - M_BGTU_I, - M_BGTUL_I, - M_BLE, - M_BLEL, - M_BLE_I, - M_BLEL_I, - M_BLEU, - M_BLEUL, - M_BLEU_I, - M_BLEUL_I, - M_BLT, - M_BLTL, - M_BLT_I, - M_BLTL_I, - M_BLTU, - M_BLTUL, - M_BLTU_I, - M_BLTUL_I, - M_BNE, - M_BNE_I, - M_BNEL_I, - M_DABS, - M_DADD_I, - M_DADDU_I, - M_DDIV_3, - M_DDIV_3I, - M_DDIVU_3, - M_DDIVU_3I, - M_DEXT, - M_DINS, - M_DIV_3, - M_DIV_3I, - M_DIVU_3, - M_DIVU_3I, - M_DLA_AB, - M_DLCA_AB, - M_DLI, - M_DMUL, - M_DMUL_I, - M_DMULO, - M_DMULO_I, - M_DMULOU, - M_DMULOU_I, - M_DREM_3, - M_DREM_3I, - M_DREMU_3, - M_DREMU_3I, - M_DSUB_I, - M_DSUBU_I, - M_DSUBU_I_2, - M_J_A, - M_JAL_1, - M_JAL_2, - M_JAL_A, - M_L_DOB, - M_L_DAB, - M_LA_AB, - M_LB_A, - M_LB_AB, - M_LBU_A, - M_LBU_AB, - M_LCA_AB, - M_LD_A, - M_LD_OB, - M_LD_AB, - M_LDC1_AB, - M_LDC2_AB, - M_LDC3_AB, - M_LDL_AB, - M_LDR_AB, - M_LH_A, - M_LH_AB, - M_LHU_A, - M_LHU_AB, - M_LI, - M_LI_D, - M_LI_DD, - M_LI_S, - M_LI_SS, - M_LL_AB, - M_LLD_AB, - M_LS_A, - M_LW_A, - M_LW_AB, - M_LWC0_A, - M_LWC0_AB, - M_LWC1_A, - M_LWC1_AB, - M_LWC2_A, - M_LWC2_AB, - M_LWC3_A, - M_LWC3_AB, - M_LWL_A, - M_LWL_AB, - M_LWR_A, - M_LWR_AB, - M_LWU_AB, - M_MOVE, - M_MUL, - M_MUL_I, - M_MULO, - M_MULO_I, - M_MULOU, - M_MULOU_I, - M_NOR_I, - M_OR_I, - M_REM_3, - M_REM_3I, - M_REMU_3, - M_REMU_3I, - M_DROL, - M_ROL, - M_DROL_I, - M_ROL_I, - M_DROR, - M_ROR, - M_DROR_I, - M_ROR_I, - M_S_DA, - M_S_DOB, - M_S_DAB, - M_S_S, - M_SC_AB, - M_SCD_AB, - M_SD_A, - M_SD_OB, - M_SD_AB, - M_SDC1_AB, - M_SDC2_AB, - M_SDC3_AB, - M_SDL_AB, - M_SDR_AB, - M_SEQ, - M_SEQ_I, - M_SGE, - M_SGE_I, - M_SGEU, - M_SGEU_I, - M_SGT, - M_SGT_I, - M_SGTU, - M_SGTU_I, - M_SLE, - M_SLE_I, - M_SLEU, - M_SLEU_I, - M_SLT_I, - M_SLTU_I, - M_SNE, - M_SNE_I, - M_SB_A, - M_SB_AB, - M_SH_A, - M_SH_AB, - M_SW_A, - M_SW_AB, - M_SWC0_A, - M_SWC0_AB, - M_SWC1_A, - M_SWC1_AB, - M_SWC2_A, - M_SWC2_AB, - M_SWC3_A, - M_SWC3_AB, - M_SWL_A, - M_SWL_AB, - M_SWR_A, - M_SWR_AB, - M_SUB_I, - M_SUBU_I, - M_SUBU_I_2, - M_TEQ_I, - M_TGE_I, - M_TGEU_I, - M_TLT_I, - M_TLTU_I, - M_TNE_I, - M_TRUNCWD, - M_TRUNCWS, - M_ULD, - M_ULD_A, - M_ULH, - M_ULH_A, - M_ULHU, - M_ULHU_A, - M_ULW, - M_ULW_A, - M_USH, - M_USH_A, - M_USW, - M_USW_A, - M_USD, - M_USD_A, - M_XOR_I, - M_COP0, - M_COP1, - M_COP2, - M_COP3, - M_NUM_MACROS -}; - - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -extern const struct mips_opcode mips_builtin_opcodes[]; -extern const int bfd_mips_num_builtin_opcodes; -extern struct mips_opcode *mips_opcodes; -extern int bfd_mips_num_opcodes; -#define NUMOPCODES bfd_mips_num_opcodes - - -/* The rest of this file adds definitions for the mips16 TinyRISC - processor. */ - -/* These are the bitmasks and shift counts used for the different - fields in the instruction formats. Other than OP, no masks are - provided for the fixed portions of an instruction, since they are - not needed. - - The I format uses IMM11. - - The RI format uses RX and IMM8. - - The RR format uses RX, and RY. - - The RRI format uses RX, RY, and IMM5. - - The RRR format uses RX, RY, and RZ. - - The RRI_A format uses RX, RY, and IMM4. - - The SHIFT format uses RX, RY, and SHAMT. - - The I8 format uses IMM8. - - The I8_MOVR32 format uses RY and REGR32. - - The IR_MOV32R format uses REG32R and MOV32Z. - - The I64 format uses IMM8. - - The RI64 format uses RY and IMM5. - */ - -#define MIPS16OP_MASK_OP 0x1f -#define MIPS16OP_SH_OP 11 -#define MIPS16OP_MASK_IMM11 0x7ff -#define MIPS16OP_SH_IMM11 0 -#define MIPS16OP_MASK_RX 0x7 -#define MIPS16OP_SH_RX 8 -#define MIPS16OP_MASK_IMM8 0xff -#define MIPS16OP_SH_IMM8 0 -#define MIPS16OP_MASK_RY 0x7 -#define MIPS16OP_SH_RY 5 -#define MIPS16OP_MASK_IMM5 0x1f -#define MIPS16OP_SH_IMM5 0 -#define MIPS16OP_MASK_RZ 0x7 -#define MIPS16OP_SH_RZ 2 -#define MIPS16OP_MASK_IMM4 0xf -#define MIPS16OP_SH_IMM4 0 -#define MIPS16OP_MASK_REGR32 0x1f -#define MIPS16OP_SH_REGR32 0 -#define MIPS16OP_MASK_REG32R 0x1f -#define MIPS16OP_SH_REG32R 3 -#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) -#define MIPS16OP_MASK_MOVE32Z 0x7 -#define MIPS16OP_SH_MOVE32Z 0 -#define MIPS16OP_MASK_IMM6 0x3f -#define MIPS16OP_SH_IMM6 5 - -/* These are the characters which may appears in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - "y" 3 bit register (MIPS16OP_*_RY) - "x" 3 bit register (MIPS16OP_*_RX) - "z" 3 bit register (MIPS16OP_*_RZ) - "Z" 3 bit register (MIPS16OP_*_MOVE32Z) - "v" 3 bit same register as source and destination (MIPS16OP_*_RX) - "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) - "S" stack pointer ($sp or $29) - "P" program counter - "R" return address register ($ra or $31) - "X" 5 bit MIPS register (MIPS16OP_*_REGR32) - "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) - "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) - "a" 26 bit jump address - "e" 11 bit extension value - "l" register list for entry instruction - "L" register list for exit instruction - - The remaining codes may be extended. Except as otherwise noted, - the full extended operand is a 16 bit signed value. - "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) - ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) - "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) - "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) - "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) - "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) - "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) - "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) - "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) - "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) - "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) - "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) - "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) - "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) - "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) - "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) - "q" 11 bit branch address (MIPS16OP_*_IMM11) - "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) - "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) - "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) - */ - -/* For the mips16, we use the same opcode table format and a few of - the same flags. However, most of the flags are different. */ - -/* Modifies the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_WRITE_X 0x00000001 -/* Modifies the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_WRITE_Y 0x00000002 -/* Modifies the register in MIPS16OP_*_RZ. */ -#define MIPS16_INSN_WRITE_Z 0x00000004 -/* Modifies the T ($24) register. */ -#define MIPS16_INSN_WRITE_T 0x00000008 -/* Modifies the SP ($29) register. */ -#define MIPS16_INSN_WRITE_SP 0x00000010 -/* Modifies the RA ($31) register. */ -#define MIPS16_INSN_WRITE_31 0x00000020 -/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ -#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 -/* Reads the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_READ_X 0x00000080 -/* Reads the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_READ_Y 0x00000100 -/* Reads the register in MIPS16OP_*_MOVE32Z. */ -#define MIPS16_INSN_READ_Z 0x00000200 -/* Reads the T ($24) register. */ -#define MIPS16_INSN_READ_T 0x00000400 -/* Reads the SP ($29) register. */ -#define MIPS16_INSN_READ_SP 0x00000800 -/* Reads the RA ($31) register. */ -#define MIPS16_INSN_READ_31 0x00001000 -/* Reads the program counter. */ -#define MIPS16_INSN_READ_PC 0x00002000 -/* Reads the general purpose register in MIPS16OP_*_REGR32. */ -#define MIPS16_INSN_READ_GPR_X 0x00004000 -/* Is a branch insn. */ -#define MIPS16_INSN_BRANCH 0x00010000 - -/* The following flags have the same value for the mips16 opcode - table: - INSN_UNCOND_BRANCH_DELAY - INSN_COND_BRANCH_DELAY - INSN_COND_BRANCH_LIKELY (never used) - INSN_READ_HI - INSN_READ_LO - INSN_WRITE_HI - INSN_WRITE_LO - INSN_TRAP - INSN_ISA3 - */ - -extern const struct mips_opcode mips16_opcodes[]; -extern const int bfd_mips16_num_opcodes; - -#endif /* _MIPS_H_ */ diff --git a/include/opcode/mmix.h b/include/opcode/mmix.h deleted file mode 100644 index 7f561c639..000000000 --- a/include/opcode/mmix.h +++ /dev/null @@ -1,186 +0,0 @@ -/* mmix.h -- Header file for MMIX opcode table - Copyright (C) 2001, 2003 Free Software Foundation, Inc. - Written by Hans-Peter Nilsson (hp@bitrange.com) - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version 2, -or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* We could have just a char*[] table indexed by the register number, but - that would not allow for synonyms. The table is terminated with an - entry with a NULL name. */ -struct mmix_spec_reg -{ - const char *name; - unsigned int number; -}; - -/* General indication of the type of instruction. */ -enum mmix_insn_type - { - mmix_type_pseudo, - mmix_type_normal, - mmix_type_branch, - mmix_type_condbranch, - mmix_type_memaccess_octa, - mmix_type_memaccess_tetra, - mmix_type_memaccess_wyde, - mmix_type_memaccess_byte, - mmix_type_memaccess_block, - mmix_type_jsr - }; - -/* Type of operands an instruction takes. Use when parsing assembly code - and disassembling. */ -enum mmix_operands_type - { - mmix_operands_none = 0, - - /* All operands are registers: "$X,$Y,$Z". */ - mmix_operands_regs, - - /* "$X,YZ", like SETH. */ - mmix_operands_reg_yz, - - /* The regular "$X,$Y,$Z|Z". - The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is - assumed. */ - mmix_operands_regs_z_opt, - - /* The regular "$X,$Y,$Z|Z". */ - mmix_operands_regs_z, - - /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ - mmix_operands_jmp, - - /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an - integer. */ - mmix_operands_pushgo, - - /* Two registers or a register and a byte, like FLOT, possibly with - rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ - mmix_operands_roundregs_z, - - /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ - mmix_operands_pop, - - /* Two registers, possibly with rounding: "$X,$Z" or - "$X,ROUND_MODE,$Z". */ - mmix_operands_roundregs, - - /* "XYZ", like SYNC. */ - mmix_operands_sync, - - /* "X,$Y,$Z|Z", like SYNCD. */ - mmix_operands_x_regs_z, - - /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ - mmix_operands_neg, - - /* "$X,Address, like GETA or branches. */ - mmix_operands_regaddr, - - /* "$X|X,Address, like PUSHJ. */ - mmix_operands_pushj, - - /* "$X,spec_reg"; GET. */ - mmix_operands_get, - - /* "spec_reg,$Z|Z"; PUT. */ - mmix_operands_put, - - /* Two registers, "$X,$Y". */ - mmix_operands_set, - - /* "$X,0"; SAVE. */ - mmix_operands_save, - - /* "0,$Z"; UNSAVE. */ - mmix_operands_unsave, - - /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three - operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ - mmix_operands_xyz_opt, - - /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted - and will then be assumed zero. */ - mmix_operands_resume, - - /* These are specials to handle that pseudo-directives are specified - like ordinary insns when being mmixal-compatible. They signify the - specific pseudo-directive rather than the operands type. */ - - /* LOC. */ - mmix_operands_loc, - - /* PREFIX. */ - mmix_operands_prefix, - - /* BYTE. */ - mmix_operands_byte, - - /* WYDE. */ - mmix_operands_wyde, - - /* TETRA. */ - mmix_operands_tetra, - - /* OCTA. */ - mmix_operands_octa, - - /* LOCAL. */ - mmix_operands_local, - - /* BSPEC. */ - mmix_operands_bspec, - - /* ESPEC. */ - mmix_operands_espec, - }; - -struct mmix_opcode - { - const char *name; - unsigned long match; - unsigned long lose; - enum mmix_operands_type operands; - - /* This is used by the disassembly function. */ - enum mmix_insn_type type; - }; - -/* Declare the actual tables. */ -extern const struct mmix_opcode mmix_opcodes[]; - -/* This one is terminated with an entry with a NULL name. */ -extern const struct mmix_spec_reg mmix_spec_regs[]; - -/* Some insn values we use when padding and synthesizing address loads. */ -#define IMM_OFFSET_BIT 1 -#define COND_INV_BIT 0x8 -#define PRED_INV_BIT 0x10 - -#define PUSHGO_INSN_BYTE 0xbe -#define GO_INSN_BYTE 0x9e -#define SETL_INSN_BYTE 0xe3 -#define INCML_INSN_BYTE 0xe6 -#define INCMH_INSN_BYTE 0xe5 -#define INCH_INSN_BYTE 0xe4 -#define SWYM_INSN_BYTE 0xfd -#define JMP_INSN_BYTE 0xf0 - -/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) - global registers. */ -#define MAX_GREGS 223 diff --git a/include/opcode/mn10200.h b/include/opcode/mn10200.h deleted file mode 100644 index 51e44c629..000000000 --- a/include/opcode/mn10200.h +++ /dev/null @@ -1,110 +0,0 @@ -/* mn10200.h -- Header file for Matsushita 10200 opcode table - Copyright 1996, 1997 Free Software Foundation, Inc. - Written by Jeff Law, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef MN10200_H -#define MN10200_H - -/* The opcode table is an array of struct mn10200_opcode. */ - -struct mn10200_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* The format of this opcode. */ - unsigned char format; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct mn10200_opcode mn10200_opcodes[]; -extern const int mn10200_num_opcodes; - - -/* The operands table is an array of struct mn10200_operand. */ - -struct mn10200_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the mn10200_opcodes table. */ - -extern const struct mn10200_operand mn10200_operands[]; - -/* Values defined for the flags field of a struct mn10200_operand. */ -#define MN10200_OPERAND_DREG 0x1 - -#define MN10200_OPERAND_AREG 0x2 - -#define MN10200_OPERAND_PSW 0x4 - -#define MN10200_OPERAND_MDR 0x8 - -#define MN10200_OPERAND_SIGNED 0x10 - -#define MN10200_OPERAND_PROMOTE 0x20 - -#define MN10200_OPERAND_PAREN 0x40 - -#define MN10200_OPERAND_REPEATED 0x80 - -#define MN10200_OPERAND_EXTENDED 0x100 - -#define MN10200_OPERAND_NOCHECK 0x200 - -#define MN10200_OPERAND_PCREL 0x400 - -#define MN10200_OPERAND_MEMADDR 0x800 - -#define MN10200_OPERAND_RELAX 0x1000 - -#define FMT_1 1 -#define FMT_2 2 -#define FMT_3 3 -#define FMT_4 4 -#define FMT_5 5 -#define FMT_6 6 -#define FMT_7 7 -#endif /* MN10200_H */ diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h deleted file mode 100644 index a47ef48a3..000000000 --- a/include/opcode/mn10300.h +++ /dev/null @@ -1,169 +0,0 @@ -/* mn10300.h -- Header file for Matsushita 10300 opcode table - Copyright 1996, 1997, 1998, 1999, 2003 Free Software Foundation, Inc. - Written by Jeff Law, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef MN10300_H -#define MN10300_H - -/* The opcode table is an array of struct mn10300_opcode. */ - -#define MN10300_MAX_OPERANDS 8 -struct mn10300_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* A bitmask. For each operand, nonzero if it must not have the same - register specification as all other operands with a nonzero bit in - this flag. ie 0x81 would indicate that operands 7 and 0 must not - match. Note that we count operands from left to right as they appear - in the operands specification below. */ - unsigned int no_match_operands; - - /* The format of this opcode. */ - unsigned char format; - - /* Bitmask indicating what cpu variants this opcode is available on. - We assume mn10300 base opcodes are available everywhere, so we only - have to note opcodes which are available on other variants. */ - unsigned int machine; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[MN10300_MAX_OPERANDS]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct mn10300_opcode mn10300_opcodes[]; -extern const int mn10300_num_opcodes; - - -/* The operands table is an array of struct mn10300_operand. */ - -struct mn10300_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the mn10300_opcodes table. */ - -extern const struct mn10300_operand mn10300_operands[]; - -/* Values defined for the flags field of a struct mn10300_operand. */ -#define MN10300_OPERAND_DREG 0x1 - -#define MN10300_OPERAND_AREG 0x2 - -#define MN10300_OPERAND_SP 0x4 - -#define MN10300_OPERAND_PSW 0x8 - -#define MN10300_OPERAND_MDR 0x10 - -#define MN10300_OPERAND_SIGNED 0x20 - -#define MN10300_OPERAND_PROMOTE 0x40 - -#define MN10300_OPERAND_PAREN 0x80 - -#define MN10300_OPERAND_REPEATED 0x100 - -#define MN10300_OPERAND_EXTENDED 0x200 - -#define MN10300_OPERAND_SPLIT 0x400 - -#define MN10300_OPERAND_REG_LIST 0x800 - -#define MN10300_OPERAND_PCREL 0x1000 - -#define MN10300_OPERAND_MEMADDR 0x2000 - -#define MN10300_OPERAND_RELAX 0x4000 - -#define MN10300_OPERAND_USP 0x8000 - -#define MN10300_OPERAND_SSP 0x10000 - -#define MN10300_OPERAND_MSP 0x20000 - -#define MN10300_OPERAND_PC 0x40000 - -#define MN10300_OPERAND_EPSW 0x80000 - -#define MN10300_OPERAND_RREG 0x100000 - -#define MN10300_OPERAND_XRREG 0x200000 - -#define MN10300_OPERAND_PLUS 0x400000 - -#define MN10300_OPERAND_24BIT 0x800000 - -#define MN10300_OPERAND_FSREG 0x1000000 - -#define MN10300_OPERAND_FDREG 0x2000000 - -#define MN10300_OPERAND_FPCR 0x4000000 - -/* Opcode Formats. */ -#define FMT_S0 1 -#define FMT_S1 2 -#define FMT_S2 3 -#define FMT_S4 4 -#define FMT_S6 5 -#define FMT_D0 6 -#define FMT_D1 7 -#define FMT_D2 8 -#define FMT_D4 9 -#define FMT_D5 10 -#define FMT_D6 11 -#define FMT_D7 12 -#define FMT_D8 13 -#define FMT_D9 14 -#define FMT_D10 15 -#define FMT_D3 16 - -/* Variants of the mn10300 which have additional opcodes. */ -#define MN103 300 -#define AM30 300 - -#define AM33 330 -#define AM33_2 332 - -#endif /* MN10300_H */ diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h deleted file mode 100644 index eec2f1e45..000000000 --- a/include/opcode/msp430.h +++ /dev/null @@ -1,125 +0,0 @@ -/* Opcode table for the TI MSP430 microcontrollers - - Copyright 2002, 2004 Free Software Foundation, Inc. - Contributed by Dmitry Diky <diwil@mail.ru> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef __MSP430_H_ -#define __MSP430_H_ - -struct msp430_operand_s -{ - int ol; /* Operand length words. */ - int am; /* Addr mode. */ - int reg; /* Register. */ - int mode; /* Pperand mode. */ -#define OP_REG 0 -#define OP_EXP 1 -#ifndef DASM_SECTION - expressionS exp; -#endif -}; - -#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ - -struct msp430_opcode_s -{ - char *name; - int fmt; - int insn_opnumb; - int bin_opcode; - int bin_mask; -}; - -#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } - -static struct msp430_opcode_s msp430_opcodes[] = -{ - MSP_INSN (and, 1, 2, 0xf000, 0xf000), - MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), - MSP_INSN (xor, 1, 2, 0xe000, 0xf000), - MSP_INSN (setz, 0, 0, 0xd322, 0xffff), - MSP_INSN (setc, 0, 0, 0xd312, 0xffff), - MSP_INSN (eint, 0, 0, 0xd232, 0xffff), - MSP_INSN (setn, 0, 0, 0xd222, 0xffff), - MSP_INSN (bis, 1, 2, 0xd000, 0xf000), - MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), - MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), - MSP_INSN (dint, 0, 0, 0xc232, 0xffff), - MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), - MSP_INSN (bic, 1, 2, 0xc000, 0xf000), - MSP_INSN (bit, 1, 2, 0xb000, 0xf000), - MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), - MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), - MSP_INSN (tst, 0, 1, 0x9300, 0xff30), - MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), - MSP_INSN (decd, 0, 1, 0x8320, 0xff30), - MSP_INSN (dec, 0, 1, 0x8310, 0xff30), - MSP_INSN (sub, 1, 2, 0x8000, 0xf000), - MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), - MSP_INSN (subc, 1, 2, 0x7000, 0xf000), - MSP_INSN (adc, 0, 1, 0x6300, 0xff30), - MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), - MSP_INSN (addc, 1, 2, 0x6000, 0xf000), - MSP_INSN (incd, 0, 1, 0x5320, 0xff30), - MSP_INSN (inc, 0, 1, 0x5310, 0xff30), - MSP_INSN (rla, 0, 2, 0x5000, 0xf000), - MSP_INSN (add, 1, 2, 0x5000, 0xf000), - MSP_INSN (nop, 0, 0, 0x4303, 0xffff), - MSP_INSN (clr, 0, 1, 0x4300, 0xff30), - MSP_INSN (ret, 0, 0, 0x4130, 0xff30), - MSP_INSN (pop, 0, 1, 0x4130, 0xff30), - MSP_INSN (br, 0, 3, 0x4000, 0xf000), - MSP_INSN (mov, 1, 2, 0x4000, 0xf000), - MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), - MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), - MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), - MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), - MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), - MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), - MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), - MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), - MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), - MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), - MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), - MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), - MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), - MSP_INSN (call, 2, 1, 0x1280, 0xffc0), - MSP_INSN (push, 2, 1, 0x1200, 0xff80), - MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), - MSP_INSN (rra, 2, 1, 0x1100, 0xff80), - MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), - MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), - /* Simple polymorphs. */ - MSP_INSN (beq, 4, 0, 0, 0xffff), - MSP_INSN (bne, 4, 1, 0, 0xffff), - MSP_INSN (blt, 4, 2, 0, 0xffff), - MSP_INSN (bltu, 4, 3, 0, 0xffff), - MSP_INSN (bge, 4, 4, 0, 0xffff), - MSP_INSN (bgeu, 4, 5, 0, 0xffff), - MSP_INSN (bltn, 4, 6, 0, 0xffff), - MSP_INSN (jump, 4, 7, 0, 0xffff), - /* Long polymorphs. */ - MSP_INSN (bgt, 5, 0, 0, 0xffff), - MSP_INSN (bgtu, 5, 1, 0, 0xffff), - MSP_INSN (bleu, 5, 2, 0, 0xffff), - MSP_INSN (ble, 5, 3, 0, 0xffff), - - /* End of instruction set. */ - { NULL, 0, 0, 0, 0 } -}; - -#endif diff --git a/include/opcode/np1.h b/include/opcode/np1.h deleted file mode 100644 index ebe37f5d2..000000000 --- a/include/opcode/np1.h +++ /dev/null @@ -1,422 +0,0 @@ -/* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB. - -GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, -{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, -{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, -{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, -{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, -{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, -{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, - -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, -{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, -{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, -{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, - -{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, -{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, -{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, -{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, -{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, -{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, -{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, - -{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, -{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, -{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, -{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, -{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, -{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, -{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, -{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, -{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, -{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, -{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, -{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, -{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, -{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, -{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, -{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, -{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, -{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, -{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, -{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, -{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, -{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, -{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, - -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, -{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, - -{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, -{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, -{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, -{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, -{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, -{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, - -{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, -{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, -{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, -{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, - -{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, -{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, -{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, -{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, -{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, - -{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, -{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, -{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, -{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, -{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, -{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, - -{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, -{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, -{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, - -{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, -{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, -{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, -{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, -{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, -{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, -{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, -{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, -{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, -{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, - -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, -{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, - -{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, -{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, -{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, -{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, -{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, -{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, -{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, -{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, -{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, -{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, -{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, -{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, -{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, -{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, - -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, - -{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, -{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, -{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, - -{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, -{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, -{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, -{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, -{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, -{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, -{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, -{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, -{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, -{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, -{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, - -{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, -{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, -{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, -{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, -{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, -{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, -{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, -{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, -{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, -{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, -{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, -{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, -{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, -{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, -{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, -{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, -{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, -{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, -{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, -{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, -{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, -{ "break", 0x28090000, 0xfc0f0000, "", 2 }, -{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, -{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, -{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, -{ "block", 0x04060000, 0xfc0f0000, "", 2 }, -{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, -{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, -{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, -{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, -{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, -{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, -{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, -{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, -{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, -{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, -{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, -{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, -{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, - -{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, -{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, -{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, - -{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, -{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, -{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, -{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, -{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/include/opcode/ns32k.h b/include/opcode/ns32k.h deleted file mode 100644 index 5cb2f97cc..000000000 --- a/include/opcode/ns32k.h +++ /dev/null @@ -1,487 +0,0 @@ -/* ns32k-opcode.h -- Opcode table for National Semi 32k processor - Copyright 1987, 1991, 1994, 2002 Free Software Foundation, Inc. - -This file is part of GAS, the GNU Assembler. - -GAS is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GAS is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GAS; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - - -#ifdef SEQUENT_COMPATABILITY -#define DEF_MODEC 20 -#define DEF_MODEL 21 -#endif - -#ifndef DEF_MODEC -#define DEF_MODEC 20 -#endif - -#ifndef DEF_MODEL -#define DEF_MODEL 20 -#endif -/* - After deciding the instruction entry (via hash.c) the instruction parser - will try to match the operands after the instruction to the required set - given in the entry operandfield. Every operand will result in a change in - the opcode or the addition of data to the opcode. - The operands in the source instruction are checked for inconsistent - semantics. - - F : 32 bit float general form - L : 64 bit float " - B : byte " - W : word " - D : double-word " - A : double-word gen-address-form ie no regs, no immediate - I : integer writeable gen int except immediate (A + reg) - Z : floating writeable gen float except immediate (Z + freg) - d : displacement - b : displacement - pc relative addressing acb - p : displacement - pc relative addressing br bcond bsr cxp - q : quick - i : immediate (8 bits) - This is not a standard ns32k operandtype, it is used to build - instructions like svc arg1,arg2 - Svc is the instruction SuperVisorCall and is sometimes used to - call OS-routines from usermode. Some args might be handy! - r : register number (3 bits) - O : setcfg instruction optionslist - C : cinv instruction optionslist - S : stringinstruction optionslist - U : registerlist save,enter - u : registerlist restore,exit - M : mmu register - P : cpu register - g : 3:rd operand of inss or exts instruction - G : 4:th operand of inss or exts instruction - Those operands are encoded in the same byte. - This byte is placed last in the instruction. - f : operand of sfsr - H : sequent-hack for bsr (Warning) - -column 1 instructions - 2 number of bits in opcode. - 3 number of bits in opcode explicitly - determined by the instruction type. - 4 opcodeseed, the number we build our opcode - from. - 5 operandtypes, used by operandparser. - 6 size in bytes of immediate -*/ -struct ns32k_opcode { - const char *name; - unsigned char opcode_id_size; /* not used by the assembler */ - unsigned char opcode_size; - unsigned long opcode_seed; - const char *operands; - unsigned char im_size; /* not used by dissassembler */ - const char *default_args; /* default to those args when none given */ - char default_modec; /* default to this addr-mode when ambigous - ie when the argument of a general addr-mode - is a plain constant */ - char default_model; /* is a plain label */ -}; - -#ifdef comment -/* This section was from the gdb version of this file. */ - -#ifndef ns32k_opcodeT -#define ns32k_opcodeT int -#endif /* no ns32k_opcodeT */ - -struct not_wot /* ns32k opcode table: wot to do with this */ - /* particular opcode */ -{ - int obits; /* number of opcode bits */ - int ibits; /* number of instruction bits */ - ns32k_opcodeT code; /* op-code (may be > 8 bits!) */ - const char *args; /* how to compile said opcode */ -}; - -struct not /* ns32k opcode text */ -{ - const char *name; /* opcode name: lowercase string [key] */ - struct not_wot detail; /* rest of opcode table [datum] */ -}; - -/* Instructions look like this: - - basic instruction--1, 2, or 3 bytes - index byte for operand A, if operand A is indexed--1 byte - index byte for operand B, if operand B is indexed--1 byte - addressing extension for operand A - addressing extension for operand B - implied operands - - Operand A is the operand listed first in the following opcode table. - Operand B is the operand listed second in the following opcode table. - All instructions have at most 2 general operands, so this is enough. - The implied operands are associated with operands other than A and B. - - Each operand has a digit and a letter. - - The digit gives the position in the assembly language. The letter, - one of the following, tells us what kind of operand it is. */ - -/* F : 32 bit float - * L : 64 bit float - * B : byte - * W : word - * D : double-word - * I : integer not immediate - * Z : floating not immediate - * d : displacement - * q : quick - * i : immediate (8 bits) - * r : register number (3 bits) - * p : displacement - pc relative addressing -*/ - - -#endif /* comment */ - -static const struct ns32k_opcode ns32k_opcodes[]= -{ - { "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL }, - { "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL }, - { "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL }, - { "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, - { "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, - { "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, - { "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 }, - { "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, - { "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "beq", 8,8, 0x0a, "1p", 0, "", 21,21 }, - { "bne", 8,8, 0x1a, "1p", 0, "", 21,21 }, - { "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 }, - { "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 }, - { "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 }, - { "bls", 8,8, 0x5a, "1p", 0, "", 21,21 }, - { "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 }, - { "ble", 8,8, 0x7a, "1p", 0, "", 21,21 }, - { "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 }, - { "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 }, - { "blo", 8,8, 0xaa, "1p", 0, "", 21,21 }, - { "bhs", 8,8, 0xba, "1p", 0, "", 21,21 }, - { "blt", 8,8, 0xca, "1p", 0, "", 21,21 }, - { "bge", 8,8, 0xda, "1p", 0, "", 21,21 }, - { "but", 8,8, 0xea, "1p", 0, "", 21,21 }, - { "buf", 8,8, 0xfa, "1p", 0, "", 21,21 }, - { "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "br", 8,8, 0xea, "1p", 0, "", 21,21 }, -#ifdef SEQUENT_COMPATABILITY - { "bsr", 8,8, 0x02, "1H", 0, "", 21,21 }, -#else - { "bsr", 8,8, 0x02, "1p", 0, "", 21,21 }, -#endif - { "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, - { "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, - { "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, - { "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL }, - { "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL }, - { "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, - { "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, - { "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL }, - { "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL }, - { "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, - { "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, - { "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL }, - { "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL }, - { "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL }, - { "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, - { "cxp", 8,8, 0x22, "1p", 0, "", 21,21 }, - { "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL }, - { "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL }, - { "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL }, - { "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL }, - { "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL }, - { "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL }, - { "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL }, - { "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, - { "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, - { "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, - { "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL }, - { "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL }, - { "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL }, - { "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL }, - { "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL }, - { "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL }, - { "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, - { "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, - { "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, - { "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 }, - { "jump", 11,16, 0x27f, "1A", 4, "", 21,21 }, - { "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL }, - { "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL }, - { "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL }, - { "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL }, - { "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL }, - { "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, - { "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, - { "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, - { "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, - { "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, - { "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, - { "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, - { "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, - { "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, - { "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, - { "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL }, - { "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL }, - { "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL }, - { "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL }, - { "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL }, - { "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, - { "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, - { "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, - { "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL }, - { "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL }, - { "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL }, - { "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, - { "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL }, - { "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL }, - { "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL }, - { "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL }, - { "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, -#ifdef NS32K_SVC_IMMED_OPERANDS - { "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */ -#else - { "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL }, -#endif - { "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, - { "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, - { "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, - { "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, - { "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL }, - { "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL }, - { "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, - { "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, - { "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, - { "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, - { "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, - { "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, - { "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, - { "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, - { "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, - { "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, -}; - -#define MAX_ARGS 4 -#define ARG_LEN 50 - diff --git a/include/opcode/or32.h b/include/opcode/or32.h deleted file mode 100644 index 3412b22b6..000000000 --- a/include/opcode/or32.h +++ /dev/null @@ -1,180 +0,0 @@ -/* Table of opcodes for the OpenRISC 1000 ISA. - Copyright 2002, 2003 Free Software Foundation, Inc. - Contributed by Damjan Lampret (lampret@opencores.org). - - This file is part of or1k_gen_isa, or1ksim, GDB and GAS. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* We treat all letters the same in encode/decode routines so - we need to assign some characteristics to them like signess etc. */ - -#ifndef OR32_H_ISA -#define OR32_H_ISA - -#define NUM_UNSIGNED (0) -#define NUM_SIGNED (1) - -#define MAX_GPRS 32 -#define PAGE_SIZE 4096 -#undef __HALF_WORD_INSN__ - -#define OPERAND_DELIM (',') - -#define OR32_IF_DELAY (1) -#define OR32_W_FLAG (2) -#define OR32_R_FLAG (4) - -struct or32_letter -{ - char letter; - int sign; - /* int reloc; relocation per letter ?? */ -}; - -/* Main instruction specification array. */ -struct or32_opcode -{ - /* Name of the instruction. */ - char *name; - - /* A string of characters which describe the operands. - Valid characters are: - ,() Itself. Characters appears in the assembly code. - rA Register operand. - rB Register operand. - rD Register operand. - I An immediate operand, range -32768 to 32767. - J An immediate operand, range . (unused) - K An immediate operand, range 0 to 65535. - L An immediate operand, range 0 to 63. - M An immediate operand, range . (unused) - N An immediate operand, range -33554432 to 33554431. - O An immediate operand, range . (unused). */ - char *args; - - /* Opcode and operand encoding. */ - char *encoding; - void (*exec) (void); - unsigned int flags; -}; - -#define OPTYPE_LAST (0x80000000) -#define OPTYPE_OP (0x40000000) -#define OPTYPE_REG (0x20000000) -#define OPTYPE_SIG (0x10000000) -#define OPTYPE_DIS (0x08000000) -#define OPTYPE_DST (0x04000000) -#define OPTYPE_SBIT (0x00001F00) -#define OPTYPE_SHR (0x0000001F) -#define OPTYPE_SBIT_SHR (8) - -/* MM: Data how to decode operands. */ -extern struct insn_op_struct -{ - unsigned long type; - unsigned long data; -} **op_start; - -#ifdef HAS_EXECUTION -extern void l_invalid (void); -extern void l_sfne (void); -extern void l_bf (void); -extern void l_add (void); -extern void l_sw (void); -extern void l_sb (void); -extern void l_sh (void); -extern void l_lwz (void); -extern void l_lbs (void); -extern void l_lbz (void); -extern void l_lhs (void); -extern void l_lhz (void); -extern void l_movhi (void); -extern void l_and (void); -extern void l_or (void); -extern void l_xor (void); -extern void l_sub (void); -extern void l_mul (void); -extern void l_div (void); -extern void l_divu (void); -extern void l_sll (void); -extern void l_sra (void); -extern void l_srl (void); -extern void l_j (void); -extern void l_jal (void); -extern void l_jalr (void); -extern void l_jr (void); -extern void l_rfe (void); -extern void l_nop (void); -extern void l_bnf (void); -extern void l_sfeq (void); -extern void l_sfgts (void); -extern void l_sfges (void); -extern void l_sflts (void); -extern void l_sfles (void); -extern void l_sfgtu (void); -extern void l_sfgeu (void); -extern void l_sfltu (void); -extern void l_sfleu (void); -extern void l_mtspr (void); -extern void l_mfspr (void); -extern void l_sys (void); -extern void l_trap (void); /* CZ 21/06/01. */ -extern void l_macrc (void); -extern void l_mac (void); -extern void l_msb (void); -extern void l_invalid (void); -extern void l_cust1 (void); -extern void l_cust2 (void); -extern void l_cust3 (void); -extern void l_cust4 (void); -#endif -extern void l_none (void); - -extern const struct or32_letter or32_letters[]; - -extern const struct or32_opcode or32_opcodes[]; - -extern const unsigned int or32_num_opcodes; - -/* Calculates instruction length in bytes. Always 4 for OR32. */ -extern int insn_len (int); - -/* Is individual insn's operand signed or unsigned? */ -extern int letter_signed (char); - -/* Number of letters in the individual lettered operand. */ -extern int letter_range (char); - -/* MM: Returns index of given instruction name. */ -extern int insn_index (char *); - -/* MM: Returns instruction name from index. */ -extern const char *insn_name (int); - -/* MM: Constructs new FSM, based on or32_opcodes. */ -extern void build_automata (void); - -/* MM: Destructs FSM. */ -extern void destruct_automata (void); - -/* MM: Decodes instruction using FSM. Call build_automata first. */ -extern int insn_decode (unsigned int); - -/* Disassemble one instruction from insn to disassemble. - Return the size of the instruction. */ -int disassemble_insn (unsigned long); - -#endif diff --git a/include/opcode/pdp11.h b/include/opcode/pdp11.h deleted file mode 100644 index 0f0256ba2..000000000 --- a/include/opcode/pdp11.h +++ /dev/null @@ -1,85 +0,0 @@ -/* PDP-11 opcde list. - Copyright 2001, 2002 Free Software Foundation, Inc. - -This file is part of GDB and GAS. - -GDB and GAS are free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB and GAS are distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB or GAS; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* - * PDP-11 opcode types. - */ - -#define PDP11_OPCODE_NO_OPS 0 -#define PDP11_OPCODE_REG 1 /* register */ -#define PDP11_OPCODE_OP 2 /* generic operand */ -#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ -#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, - reversed syntax */ -#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float - operand */ -#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ -#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ -#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative - displacement */ -#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ -#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ -#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ -#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ -#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu - accumulator */ -#define PDP11_OPCODE_FOP 14 /* generic float operand */ -#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int - operand */ -#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu - accumulator */ - -/* - * PDP-11 instruction set extensions. - * - * Please keep the numbers low, as they are used as indices into - * an array. - */ - -#define PDP11_NONE 0 /* not in instruction set */ -#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ -#define PDP11_CSM 2 /* commercial instruction set */ -#define PDP11_CIS 3 /* commercial instruction set */ -#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ -#define PDP11_FIS 5 /* KEV11 floating-point instructions */ -#define PDP11_FPP 6 /* FP-11 floating-point instructions */ -#define PDP11_LEIS 7 /* limited extended instruction set - (11/40 etc) */ -#define PDP11_MFPT 8 /* move from processor type */ -#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, - wrtlck */ -#define PDP11_MXPS 10 /* move from/to processor status */ -#define PDP11_SPL 11 /* set priority level */ -#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ -#define PDP11_EXT_NUM 13 /* total number of extension types */ - -struct pdp11_opcode -{ - const char *name; - int opcode; - int mask; - int type; - int extension; -}; - -extern const struct pdp11_opcode pdp11_opcodes[]; -extern const struct pdp11_opcode pdp11_aliases[]; -extern const int pdp11_num_opcodes, pdp11_num_aliases; - -/* end of pdp11.h */ diff --git a/include/opcode/pj.h b/include/opcode/pj.h deleted file mode 100644 index 30201d685..000000000 --- a/include/opcode/pj.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Definitions for decoding the picoJava opcode table. - Copyright 1999, 2002, 2003 Free Software Foundation, Inc. - Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - - -/* Names used to describe the type of instruction arguments, used by - the assembler and disassembler. Attributes are encoded in various fields. */ - -/* reloc size pcrel uns */ -#define O_N 0 -#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) -#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) -#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) -#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) -#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) -#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) -#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) -#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) - -#define ASIZE(x) ((x) & 0x7) -#define PCREL(x) (!!((x) & (1<<6))) -#define UNS(x) (!!((x) & (1<<3))) - - -typedef struct pj_opc_info_t -{ - short opcode; - short opcode_next; - char len; - unsigned char arg[2]; - union { - const char *name; - void (*func) (struct pj_opc_info_t *, char *); - } u; -} pj_opc_info_t; diff --git a/include/opcode/pn.h b/include/opcode/pn.h deleted file mode 100644 index f8d474f60..000000000 --- a/include/opcode/pn.h +++ /dev/null @@ -1,282 +0,0 @@ -/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB. - -GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, -{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, -{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, -{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, -{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bei", 0x00060000, 0xffff0000, "", 2 }, -{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, -{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, -{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, -{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, -{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, -{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, -{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, -{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, -{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, -{ "call", 0x28080000, 0xfc0f0000, "", 2 }, -{ "callm", 0x5c080000, 0xff880000, "", 4 }, -{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, -{ "cea", 0x000f0000, 0xffff0000, "", 2 }, -{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, -{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, -{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, -{ "dae", 0x000e0000, 0xffff0000, "", 2 }, -{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, -{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, -{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, -{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, -{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "eae", 0x00080000, 0xffff0000, "", 2 }, -{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, -{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, -{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, -{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, -{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, -{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, -{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, -{ "halt", 0x00000000, 0xffff0000, "", 2 }, -{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, -{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, -{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, -{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, -{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, -{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, -{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, -{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, -{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "nop", 0x00020000, 0xffff0000, "", 2 }, -{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, -{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, -{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, -{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, -{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, -{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, -{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, -{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, -{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, -{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, -{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, -{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, -{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, -{ "sea", 0x000d0000, 0xffff0000, "", 2 }, -{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, -{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, -{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "smc", 0x04070000, 0xfc070000, "", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, -{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, -{ "svc", 0xc8060000, 0xffff0000, "", 4 }, -{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, -{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, -{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, -{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, -{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, -{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, -{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, -{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "uei", 0x00070000, 0xffff0000, "", 2 }, -{ "wait", 0x00010000, 0xffff0000, "", 2 }, -{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, -{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, -{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, -{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, -{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h deleted file mode 100644 index f66263086..000000000 --- a/include/opcode/ppc.h +++ /dev/null @@ -1,316 +0,0 @@ -/* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005 - Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef PPC_H -#define PPC_H - -/* The opcode table is an array of struct powerpc_opcode. */ - -struct powerpc_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct powerpc_opcode powerpc_opcodes[]; -extern const int powerpc_num_opcodes; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* Opcode is defined for the PowerPC architecture. */ -#define PPC_OPCODE_PPC 1 - -/* Opcode is defined for the POWER (RS/6000) architecture. */ -#define PPC_OPCODE_POWER 2 - -/* Opcode is defined for the POWER2 (Rios 2) architecture. */ -#define PPC_OPCODE_POWER2 4 - -/* Opcode is only defined on 32 bit architectures. */ -#define PPC_OPCODE_32 8 - -/* Opcode is only defined on 64 bit architectures. */ -#define PPC_OPCODE_64 0x10 - -/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 - is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, - but it also supports many additional POWER instructions. */ -#define PPC_OPCODE_601 0x20 - -/* Opcode is supported in both the Power and PowerPC architectures - (ie, compiler's -mcpu=common or assembler's -mcom). */ -#define PPC_OPCODE_COMMON 0x40 - -/* Opcode is supported for any Power or PowerPC platform (this is - for the assembler's -many option, and it eliminates duplicates). */ -#define PPC_OPCODE_ANY 0x80 - -/* Opcode is supported as part of the 64-bit bridge. */ -#define PPC_OPCODE_64_BRIDGE 0x100 - -/* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC 0x200 - -/* Opcode is supported by PowerPC 403 processor. */ -#define PPC_OPCODE_403 0x400 - -/* Opcode is supported by PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE 0x800 - -/* Opcode is only supported by 64-bit PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE64 0x1000 - -/* Opcode is supported by PowerPC 440 processor. */ -#define PPC_OPCODE_440 0x2000 - -/* Opcode is only supported by Power4 architecture. */ -#define PPC_OPCODE_POWER4 0x4000 - -/* Opcode isn't supported by Power4 architecture. */ -#define PPC_OPCODE_NOPOWER4 0x8000 - -/* Opcode is only supported by POWERPC Classic architecture. */ -#define PPC_OPCODE_CLASSIC 0x10000 - -/* Opcode is only supported by e500x2 Core. */ -#define PPC_OPCODE_SPE 0x20000 - -/* Opcode is supported by e500x2 Integer select APU. */ -#define PPC_OPCODE_ISEL 0x40000 - -/* Opcode is an e500 SPE floating point instruction. */ -#define PPC_OPCODE_EFS 0x80000 - -/* Opcode is supported by branch locking APU. */ -#define PPC_OPCODE_BRLOCK 0x100000 - -/* Opcode is supported by performance monitor APU. */ -#define PPC_OPCODE_PMR 0x200000 - -/* Opcode is supported by cache locking APU. */ -#define PPC_OPCODE_CACHELCK 0x400000 - -/* Opcode is supported by machine check APU. */ -#define PPC_OPCODE_RFMCI 0x800000 - -/* Opcode is only supported by Power5 architecture. */ -#define PPC_OPCODE_POWER5 0x1000000 - -/* Opcode is supported by PowerPC e300 family. */ -#define PPC_OPCODE_E300 0x2000000 - -/* A macro to extract the major opcode from an instruction. */ -#define PPC_OP(i) (((i) >> 26) & 0x3f) - -/* The operands table is an array of struct powerpc_operand. */ - -struct powerpc_operand -{ - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (*insert) - (unsigned long instruction, long op, int dialect, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & PPC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (unsigned long instruction, int dialect, int *invalid); - - /* One bit syntax flags. */ - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct powerpc_operand powerpc_operands[]; - -/* Values defined for the flags field of a struct powerpc_operand. */ - -/* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (01) - -/* This operand takes signed values, but also accepts a full positive - range of values when running in 32 bit mode. That is, if bits is - 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, - this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (02) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics such as mr, for which two - operands fields are identical. The assembler should call the - insert function with any op value. The disassembler should call - the extract function, ignore the return value, and check the value - placed in the valid argument. */ -#define PPC_OPERAND_FAKE (04) - -/* The next operand should be wrapped in parentheses rather than - separated from this one by a comma. This is used for the load and - store instructions which want their operands to look like - reg,displacement(reg) - */ -#define PPC_OPERAND_PARENS (010) - -/* This operand may use the symbolic names for the CR fields, which - are - lt 0 gt 1 eq 2 so 3 un 3 - cr0 0 cr1 1 cr2 2 cr3 3 - cr4 4 cr5 5 cr6 6 cr7 7 - These may be combined arithmetically, as in cr2*4+gt. These are - only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR (020) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (040) - -/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ -#define PPC_OPERAND_GPR_0 (0100) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0200) - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0400) - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (01000) - -/* This operand is optional, and is zero if omitted. This is used for - example, in the optional BF field in the comparison instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (02000) - -/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand - is omitted, then for the next operand use this operand value plus - 1, ignoring the next operand field for the opcode. This wretched - hack is needed because the Power rotate instructions can take - either 4 or 5 operands. The disassembler should print this operand - out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (04000) - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define PPC_OPERAND_NEGATIVE (010000) - -/* This operand names a vector unit register. The disassembler - prints these with a leading 'v'. */ -#define PPC_OPERAND_VR (020000) - -/* This operand is for the DS field in a DS form instruction. */ -#define PPC_OPERAND_DS (040000) - -/* This operand is for the DQ field in a DQ form instruction. */ -#define PPC_OPERAND_DQ (0100000) - -/* The POWER and PowerPC assemblers use a few macros. We keep them - with the operands table for simplicity. The macro table is an - array of struct powerpc_macro. */ - -struct powerpc_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct powerpc_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct powerpc_macro powerpc_macros[]; -extern const int powerpc_num_macros; - -#endif /* PPC_H */ diff --git a/include/opcode/pyr.h b/include/opcode/pyr.h deleted file mode 100644 index a523dfd72..000000000 --- a/include/opcode/pyr.h +++ /dev/null @@ -1,305 +0,0 @@ -/* pyramid.opcode.h -- gdb initial attempt. - - Copyright 2001 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* pyramid opcode table: wot to do with this - particular opcode */ - -struct pyr_datum -{ - char nargs; - char * args; /* how to compile said opcode */ - unsigned long mask; /* Bit vector: which operand modes are valid - for this opcode */ - unsigned char code; /* op-code (always 6(?) bits */ -}; - -typedef struct pyr_insn_format -{ - unsigned int mode :4; - unsigned int operator :8; - unsigned int index_scale :2; - unsigned int index_reg :6; - unsigned int operand_1 :6; - unsigned int operand_2:6; -} pyr_insn_format; - - -/* We store four bytes of opcode for all opcodes. - Pyramid is sufficiently RISCy that: - - insns are always an integral number of words; - - the length of any insn can be told from the first word of - the insn. (ie, if there are zero, one, or two words of - immediate operand/offset). - - - The args component is a string containing two characters for each - operand of the instruction. The first specifies the kind of operand; - the second, the place it is stored. */ - -/* Kinds of operands: - mask assembler syntax description - 0x0001: movw Rn,Rn register to register - 0x0002: movw K,Rn quick immediate to register - 0x0004: movw I,Rn long immediate to register - 0x0008: movw (Rn),Rn register indirect to register - movw (Rn)[x],Rn register indirect to register - 0x0010: movw I(Rn),Rn offset register indirect to register - movw I(Rn)[x],Rn offset register indirect, indexed, to register - - 0x0020: movw Rn,(Rn) register to register indirect - 0x0040: movw K,(Rn) quick immediate to register indirect - 0x0080: movw I,(Rn) long immediate to register indirect - 0x0100: movw (Rn),(Rn) register indirect to-register indirect - 0x0100: movw (Rn),(Rn) register indirect to-register indirect - 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect - 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect - - 0x0400: movw Rn,I(Rn) register to register indirect+offset - 0x0800: movw K,I(Rn) quick immediate to register indirect+offset - 0x1000: movw I,I(Rn) long immediate to register indirect+offset - 0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset - 0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect - +offset - 0x0000: (irregular) ??? - - - Each insn has a four-bit field encoding the type(s) of its operands. -*/ - -/* Some common combinations - */ - -/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/ -#define GEN_TO_REG (31) - -#define UNKNOWN ((unsigned long)-1) -#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15)) - -#define CONVERT (1|8|0x10|0x20|0x200) - -#define K_TO_REG (2) -#define I_TO_REG (4) -#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG) -#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG) - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ - -struct pyr_opcode /* pyr opcode text */ -{ - char * name; /* opcode name: lowercase string [key] */ - struct pyr_datum datum; /* rest of opcode table [datum] */ -}; - -#define pyr_how args -#define pyr_nargs nargs -#define pyr_mask mask -#define pyr_name name - -struct pyr_opcode pyr_opcodes[] = -{ - {"movb", { 2, "", UNKNOWN, 0x11}, }, - {"movh", { 2, "", UNKNOWN, 0x12} }, - {"movw", { 2, "", ANY, 0x10} }, - {"movl", { 2, "", ANY, 0x13} }, - {"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} }, - {"mnegf", { 2, "", 0x1, 0x15} }, - {"mnegd", { 2, "", 0x1, 0x16} }, - {"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} }, - {"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} }, - {"mabsf", { 2, "", 0x1, 0x19} }, - {"mabsd", { 2, "", 0x1, 0x1a} }, - {"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} }, - {"mtstf", { 2, "", 0x1, 0x1d} }, - {"mtstd", { 2, "", 0x1, 0x1e} }, - {"mova", { 2, "", 0x8|0x10, 0x1f} }, - {"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} }, - {"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} }, - /* 2 insns out of order here */ - {"movbl", { 2, "", 1, 0x4f} }, - {"filbl", { 2, "", 1, 0x4e} }, - - {"cvtbw", { 2, "", CONVERT, 0x22} }, - {"cvthw", { 2, "", CONVERT, 0x23} }, - {"cvtwb", { 2, "", CONVERT, 0x24} }, - {"cvtwh", { 2, "", CONVERT, 0x25} }, - {"cvtwf", { 2, "", CONVERT, 0x26} }, - {"cvtwd", { 2, "", CONVERT, 0x27} }, - {"cvtfw", { 2, "", CONVERT, 0x28} }, - {"cvtfd", { 2, "", CONVERT, 0x29} }, - {"cvtdw", { 2, "", CONVERT, 0x2a} }, - {"cvtdf", { 2, "", CONVERT, 0x2b} }, - - {"addw", { 2, "", GEN_TO_REG, 0x40} }, - {"addwc", { 2, "", GEN_TO_REG, 0x41} }, - {"subw", { 2, "", GEN_TO_REG, 0x42} }, - {"subwb", { 2, "", GEN_TO_REG, 0x43} }, - {"rsubw", { 2, "", GEN_TO_REG, 0x44} }, - {"mulw", { 2, "", GEN_TO_REG, 0x45} }, - {"emul", { 2, "", GEN_TO_REG, 0x47} }, - {"umulw", { 2, "", GEN_TO_REG, 0x46} }, - {"divw", { 2, "", GEN_TO_REG, 0x48} }, - {"ediv", { 2, "", GEN_TO_REG, 0x4a} }, - {"rdivw", { 2, "", GEN_TO_REG, 0x4b} }, - {"udivw", { 2, "", GEN_TO_REG, 0x49} }, - {"modw", { 2, "", GEN_TO_REG, 0x4c} }, - {"umodw", { 2, "", GEN_TO_REG, 0x4d} }, - - - {"addf", { 2, "", 1, 0x50} }, - {"addd", { 2, "", 1, 0x51} }, - {"subf", { 2, "", 1, 0x52} }, - {"subd", { 2, "", 1, 0x53} }, - {"mulf", { 2, "", 1, 0x56} }, - {"muld", { 2, "", 1, 0x57} }, - {"divf", { 2, "", 1, 0x58} }, - {"divd", { 2, "", 1, 0x59} }, - - - {"cmpb", { 2, "", UNKNOWN, 0x61} }, - {"cmph", { 2, "", UNKNOWN, 0x62} }, - {"cmpw", { 2, "", UNKNOWN, 0x60} }, - {"ucmpb", { 2, "", UNKNOWN, 0x66} }, - /* WHY no "ucmph"??? */ - {"ucmpw", { 2, "", UNKNOWN, 0x65} }, - {"xchw", { 2, "", UNKNOWN, 0x0f} }, - - - {"andw", { 2, "", GEN_TO_REG, 0x30} }, - {"orw", { 2, "", GEN_TO_REG, 0x31} }, - {"xorw", { 2, "", GEN_TO_REG, 0x32} }, - {"bicw", { 2, "", GEN_TO_REG, 0x33} }, - {"lshlw", { 2, "", GEN_TO_REG, 0x38} }, - {"ashlw", { 2, "", GEN_TO_REG, 0x3a} }, - {"ashll", { 2, "", GEN_TO_REG, 0x3c} }, - {"ashrw", { 2, "", GEN_TO_REG, 0x3b} }, - {"ashrl", { 2, "", GEN_TO_REG, 0x3d} }, - {"rotlw", { 2, "", GEN_TO_REG, 0x3e} }, - {"rotrw", { 2, "", GEN_TO_REG, 0x3f} }, - - /* push and pop insns are "going away next release". */ - {"pushw", { 2, "", GEN_TO_REG, 0x0c} }, - {"popw", { 2, "", (0x1|0x8|0x10), 0x0d} }, - {"pusha", { 2, "", (0x8|0x10), 0x0e} }, - - {"bitsw", { 2, "", UNKNOWN, 0x35} }, - {"bitcw", { 2, "", UNKNOWN, 0x36} }, - /* some kind of ibra/dbra insns??*/ - {"icmpw", { 2, "", UNKNOWN, 0x67} }, - {"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/ - {"acmpw", { 2, "", 1, 0x6b} }, - - /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op - insn with a 2nd op of tr14. The assembler will have to grok this. */ - {"call", { 2, "", GEN_TO_REG, 0x04} }, - {"call", { 1, "", GEN_TO_REG, 0x04} }, - - {"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/ - /* Ret is usually written as a 0-op insn, but gets disassembled as a - 1-op insn. The operand is always tr15. */ - {"ret", { 0, "", UNKNOWN, 0x09} }, - {"ret", { 1, "", UNKNOWN, 0x09} }, - {"adsf", { 2, "", (1|2|4), 0x08} }, - {"retd", { 2, "", UNKNOWN, 0x0a} }, - {"btc", { 2, "", UNKNOWN, 0x01} }, - {"bfc", { 2, "", UNKNOWN, 0x02} }, - /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */ - {"jump", { 1, "", UNKNOWN, 0x00} }, - {"btp", { 2, "", UNKNOWN, 0xf00} }, - /* read control-stack pointer is another 1-or-2 operand insn. */ - {"rcsp", { 2, "", UNKNOWN, 0x01f} }, - {"rcsp", { 1, "", UNKNOWN, 0x01f} } -}; - -/* end: pyramid.opcode.h */ -/* One day I will have to take the time to find out what operands - are valid for these insns, and guess at what they mean. - - I can't imagine what the "I???" insns (iglob, etc) do. - - the arithmetic-sounding insns ending in "p" sound awfully like BCD - arithmetic insns: - dshlp -> Decimal SHift Left Packed - dshrp -> Decimal SHift Right Packed - and cvtlp would be convert long to packed. - I have no idea how the operands are interpreted; but having them be - a long register with (address, length) of an in-memory packed BCD operand - would not be surprising. - They are unlikely to be a packed bcd string: 64 bits of long give - is only 15 digits+sign, which isn't enough for COBOL. - */ -#if 0 - {"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/ - /* The OSx Operating System Porting Guide claims SSL does things - with tr12 (a register reserved to it) to do with static block-structure - references. SSL=Set Static Link? It's "Going away next release". */ - {"ssl", { 2, "", UNKNOWN, 0x00} }, - {"ccmps", { 2, "", UNKNOWN, 0x00} }, - {"lcd", { 2, "", UNKNOWN, 0x00} }, - {"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/ - {"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/ - {"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/ - {"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/ - {"ldti", { 2, "", UNKNOWN, 0x00} }, - {"ldb", { 2, "", UNKNOWN, 0x00} }, - {"stp", { 2, "", UNKNOWN, 0x00} }, - {"stti", { 2, "", UNKNOWN, 0x00} }, - {"stb", { 2, "", UNKNOWN, 0x00} }, - {"stu", { 2, "", UNKNOWN, 0x00} }, - {"addp", { 2, "", UNKNOWN, 0x00} }, - {"subp", { 2, "", UNKNOWN, 0x00} }, - {"mulp", { 2, "", UNKNOWN, 0x00} }, - {"divp", { 2, "", UNKNOWN, 0x00} }, - {"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */ - {"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */ - {"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/ - {"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/ - {"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/ - {"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/ - {"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/ - {"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/ - {"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/ - {"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/ - {"cmovs", { 2, "", UNKNOWN, 0x00} }, - {"rsubw", { 2, "", UNKNOWN, 0x00} }, - {"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */ - {"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */ - {"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */ - {"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/ - {"callr", { 2, "", UNKNOWN, 0x00} }, - {"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/ - {"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/ - {"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/ - {"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/ - {"ssi", { 2, "", UNKNOWN, 0x00} }, - {"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/ - {"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */ - {"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/ - {"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/ - {"flic", { 2, "", UNKNOWN, 0x00} }, - {"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */ - {"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */ - {"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */ - {"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */ - {"lamst", { 2, "", UNKNOWN, 0x00} }, - {"tio", { 2, "", UNKNOWN, 0x00} }, -#endif diff --git a/include/opcode/s390.h b/include/opcode/s390.h deleted file mode 100644 index 7bb30de28..000000000 --- a/include/opcode/s390.h +++ /dev/null @@ -1,146 +0,0 @@ -/* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001, 2003 Free Software Foundation, Inc. - Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef S390_H -#define S390_H - -/* List of instruction sets variations. */ - -enum s390_opcode_mode_val - { - S390_OPCODE_ESA = 0, - S390_OPCODE_ZARCH - }; - -enum s390_opcode_cpu_val - { - S390_OPCODE_G5 = 0, - S390_OPCODE_G6, - S390_OPCODE_Z900, - S390_OPCODE_Z990, - S390_OPCODE_Z9_109 - }; - -/* The opcode table is an array of struct s390_opcode. */ - -struct s390_opcode - { - /* The opcode name. */ - const char * name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned char opcode[6]; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned char mask[6]; - - /* The opcode length in bytes. */ - int oplen; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[6]; - - /* Bitmask of execution modes this opcode is available for. */ - unsigned int modes; - - /* First cpu this opcode is available for. */ - enum s390_opcode_cpu_val min_cpu; - }; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct s390_opcode s390_opcodes[]; -extern const int s390_num_opcodes; - -/* A opcode format table for the .insn pseudo mnemonic. */ -extern const struct s390_opcode s390_opformats[]; -extern const int s390_num_opformats; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* The operands table is an array of struct s390_operand. */ - -struct s390_operand - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - unsigned long flags; - }; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct s390_operand s390_operands[]; - -/* Values defined for the flags field of a struct s390_operand. */ - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define S390_OPERAND_GPR 0x1 - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define S390_OPERAND_FPR 0x2 - -/* This operand names an access register. The disassembler - prints these with a leading 'a'. */ -#define S390_OPERAND_AR 0x4 - -/* This operand names a control register. The disassembler - prints these with a leading 'c'. */ -#define S390_OPERAND_CR 0x8 - -/* This operand is a displacement. */ -#define S390_OPERAND_DISP 0x10 - -/* This operand names a base register. */ -#define S390_OPERAND_BASE 0x20 - -/* This operand names an index register, it can be skipped. */ -#define S390_OPERAND_INDEX 0x40 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define S390_OPERAND_PCREL 0x80 - -/* This operand takes signed values. */ -#define S390_OPERAND_SIGNED 0x100 - -/* This operand is a length. */ -#define S390_OPERAND_LENGTH 0x200 - -/* This operand is optional. Only a single operand at the end of - the instruction may be optional. */ -#define S390_OPERAND_OPTIONAL 0x400 - - #endif /* S390_H */ diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h deleted file mode 100644 index 9e238be93..000000000 --- a/include/opcode/sparc.h +++ /dev/null @@ -1,237 +0,0 @@ -/* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003, 2005 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#include "ansidecl.h" - -/* The SPARC opcode table (and other related data) is defined in - the opcodes library in sparc-opc.c. If you change anything here, make - sure you fix up that file, and vice versa. */ - - /* FIXME-someday: perhaps the ,a's and such should be embedded in the - instruction's name rather than the args. This would make gas faster, pinsn - slower, but would mess up some macros a bit. xoxorich. */ - -/* List of instruction sets variations. - These values are such that each element is either a superset of a - preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P - returns non-zero. - The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. - Don't change this without updating sparc-opc.c. */ - -enum sparc_opcode_arch_val -{ - SPARC_OPCODE_ARCH_V6 = 0, - SPARC_OPCODE_ARCH_V7, - SPARC_OPCODE_ARCH_V8, - SPARC_OPCODE_ARCH_SPARCLET, - SPARC_OPCODE_ARCH_SPARCLITE, - /* V9 variants must appear last. */ - SPARC_OPCODE_ARCH_V9, - SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ - SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ - SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ -}; - -/* The highest architecture in the table. */ -#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) - -/* Given an enum sparc_opcode_arch_val, return the bitmask to use in - insn encoding/decoding. */ -#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) - -/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ -#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) - -/* Table of cpu variants. */ - -typedef struct sparc_opcode_arch -{ - const char *name; - /* Mask of sparc_opcode_arch_val's supported. - EG: For v7 this would be - (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). - These are short's because sparc_opcode.architecture is. */ - short supported; -} sparc_opcode_arch; - -extern const struct sparc_opcode_arch sparc_opcode_archs[]; - -/* Given architecture name, look up it's sparc_opcode_arch_val value. */ -extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); - -/* Return the bitmask of supported architectures for ARCH. */ -#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) - -/* Non-zero if ARCH1 conflicts with ARCH2. - IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ -#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ - (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH1)) \ - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH2))) - -/* Structure of an opcode table entry. */ - -typedef struct sparc_opcode -{ - const char *name; - unsigned long match; /* Bits that must be set. */ - unsigned long lose; /* Bits that must not be set. */ - const char *args; - /* This was called "delayed" in versions before the flags. */ - char flags; - short architecture; /* Bitmask of sparc_opcode_arch_val's. */ -} sparc_opcode; - -#define F_DELAYED 1 /* Delayed branch. */ -#define F_ALIAS 2 /* Alias for a "real" instruction. */ -#define F_UNBR 4 /* Unconditional branch. */ -#define F_CONDBR 8 /* Conditional branch. */ -#define F_JSR 16 /* Subroutine call. */ -#define F_FLOAT 32 /* Floating point instruction (not a branch). */ -#define F_FBR 64 /* Floating point branch. */ -/* FIXME: Add F_ANACHRONISTIC flag for v9. */ - -/* All sparc opcodes are 32 bits, except for the `set' instruction (really a - macro), which is 64 bits. It is handled as a special case. - - The match component is a mask saying which bits must match a particular - opcode in order for an instruction to be an instance of that opcode. - - The args component is a string containing one character for each operand of the - instruction. - - Kinds of operands: - # Number used by optimizer. It is ignored. - 1 rs1 register. - 2 rs2 register. - d rd register. - e frs1 floating point register. - v frs1 floating point register (double/even). - V frs1 floating point register (quad/multiple of 4). - f frs2 floating point register. - B frs2 floating point register (double/even). - R frs2 floating point register (quad/multiple of 4). - g frsd floating point register. - H frsd floating point register (double/even). - J frsd floating point register (quad/multiple of 4). - b crs1 coprocessor register - c crs2 coprocessor register - D crsd coprocessor register - m alternate space register (asr) in rd - M alternate space register (asr) in rs1 - h 22 high bits. - X 5 bit unsigned immediate - Y 6 bit unsigned immediate - 3 SIAM mode (3 bits). (v9b) - K MEMBAR mask (7 bits). (v9) - j 10 bit Immediate. (v9) - I 11 bit Immediate. (v9) - i 13 bit Immediate. - n 22 bit immediate. - k 2+14 bit PC relative immediate. (v9) - G 19 bit PC relative immediate. (v9) - l 22 bit PC relative immediate. - L 30 bit PC relative immediate. - a Annul. The annul bit is set. - A Alternate address space. Stored as 8 bits. - C Coprocessor state register. - F floating point state register. - p Processor state register. - N Branch predict clear ",pn" (v9) - T Branch predict set ",pt" (v9) - z %icc. (v9) - Z %xcc. (v9) - q Floating point queue. - r Single register that is both rs1 and rd. - O Single register that is both rs2 and rd. - Q Coprocessor queue. - S Special case. - t Trap base register. - w Window invalid mask register. - y Y register. - u sparclet coprocessor registers in rd position - U sparclet coprocessor registers in rs1 position - E %ccr. (v9) - s %fprs. (v9) - P %pc. (v9) - W %tick. (v9) - o %asi. (v9) - 6 %fcc0. (v9) - 7 %fcc1. (v9) - 8 %fcc2. (v9) - 9 %fcc3. (v9) - ! Privileged Register in rd (v9) - ? Privileged Register in rs1 (v9) - * Prefetch function constant. (v9) - x OPF field (v9 impdep). - 0 32/64 bit immediate for set or setx (v9) insns - _ Ancillary state register in rd (v9a) - / Ancillary state register in rs1 (v9a) - - The following chars are unused: (note: ,[] are used as punctuation) - [45]. */ - -#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ -#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ -#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ -#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ -#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ -#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ -#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ -#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ -#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ -#define F1(x) (OP (x)) -#define DISP30(x) ((x) & 0x3fffffff) -#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ -#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ -#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ -#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ -#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ -#define ASI_RS2(x) (SIMM13 (x)) -#define MEMBAR(x) ((x) & 0x7f) -#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ - -#define ANNUL (1 << 29) -#define BPRED (1 << 19) /* V9. */ -#define IMMED F3I (1) -#define RD_G0 RD (~0) -#define RS1_G0 RS1 (~0) -#define RS2_G0 RS2 (~0) - -extern const struct sparc_opcode sparc_opcodes[]; -extern const int sparc_num_opcodes; - -extern int sparc_encode_asi (const char *); -extern const char *sparc_decode_asi (int); -extern int sparc_encode_membar (const char *); -extern const char *sparc_decode_membar (int); -extern int sparc_encode_prefetch (const char *); -extern const char *sparc_decode_prefetch (int); -extern int sparc_encode_sparclet_cpreg (const char *); -extern const char *sparc_decode_sparclet_cpreg (int); - -/* Local Variables: - fill-column: 131 - comment-column: 0 - End: */ - diff --git a/include/opcode/tahoe.h b/include/opcode/tahoe.h deleted file mode 100644 index b5cee249e..000000000 --- a/include/opcode/tahoe.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Ported by the State University of New York at Buffalo by the Distributed - * Computer Systems Lab, Department of Computer Science, 1991. - */ - -#ifndef tahoe_opcodeT -#define tahoe_opcodeT int -#endif /* no tahoe_opcodeT */ - -struct vot_wot /* tahoe opcode table: wot to do with this */ - /* particular opcode */ -{ - char * args; /* how to compile said opcode */ - tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ -}; - -struct vot /* tahoe opcode text */ -{ - char * name; /* opcode name: lowercase string [key] */ - struct vot_wot detail; /* rest of opcode table [datum] */ -}; - -#define vot_how args -#define vot_code code -#define vot_detail detail -#define vot_name name - -static struct vot -votstrs[] = -{ -{ "halt", {"", 0x00 } }, -{ "sinf", {"", 0x05 } }, -{ "ldf", {"rl", 0x06 } }, -{ "ldd", {"rq", 0x07 } }, -{ "addb2", {"rbmb", 0x08 } }, -{ "movb", {"rbwb", 0x09 } }, -{ "addw2", {"rwmw", 0x0a } }, -{ "movw", {"rwww", 0x0b } }, -{ "addl2", {"rlml", 0x0c } }, -{ "movl", {"rlwl", 0x0d } }, -{ "bbs", {"rlvlbw", 0x0e } }, -{ "nop", {"", 0x10 } }, -{ "brb", {"bb", 0x11 } }, -{ "brw", {"bw", 0x13 } }, -{ "cosf", {"", 0x15 } }, -{ "lnf", {"rl", 0x16 } }, -{ "lnd", {"rq", 0x17 } }, -{ "addb3", {"rbrbwb", 0x18 } }, -{ "cmpb", {"rbwb", 0x19 } }, -{ "addw3", {"rwrwww", 0x1a } }, -{ "cmpw", {"rwww", 0x1b } }, -{ "addl3", {"rlrlwl", 0x1c } }, -{ "cmpl", {"rlwl", 0x1d } }, -{ "bbc", {"rlvlbw", 0x1e } }, -{ "rei", {"", 0x20 } }, -{ "bneq", {"bb", 0x21 } }, -{ "bnequ", {"bb", 0x21 } }, -{ "cvtwl", {"rwwl", 0x23 } }, -{ "stf", {"wl", 0x26 } }, -{ "std", {"wq", 0x27 } }, -{ "subb2", {"rbmb", 0x28 } }, -{ "mcomb", {"rbwb", 0x29 } }, -{ "subw2", {"rwmw", 0x2a } }, -{ "mcomw", {"rwww", 0x2b } }, -{ "subl2", {"rlml", 0x2c } }, -{ "mcoml", {"rlwl", 0x2d } }, -{ "emul", {"rlrlrlwq", 0x2e } }, -{ "aoblss", {"rlmlbw", 0x2f } }, -{ "bpt", {"", 0x30 } }, -{ "beql", {"bb", 0x31 } }, -{ "beqlu", {"bb", 0x31 } }, -{ "cvtwb", {"rwwb", 0x33 } }, -{ "logf", {"", 0x35 } }, -{ "cmpf", {"rl", 0x36 } }, -{ "cmpd", {"rq", 0x37 } }, -{ "subb3", {"rbrbwb", 0x38 } }, -{ "bitb", {"rbrb", 0x39 } }, -{ "subw3", {"rwrwww", 0x3a } }, -{ "bitw", {"rwrw", 0x3b } }, -{ "subl3", {"rlrlwl", 0x3c } }, -{ "bitl", {"rlrl", 0x3d } }, -{ "ediv", {"rlrqwlwl", 0x3e } }, -{ "aobleq", {"rlmlbw", 0x3f } }, -{ "ret", {"", 0x40 } }, -{ "bgtr", {"bb", 0x41 } }, -{ "sqrtf", {"", 0x45 } }, -{ "cmpf2", {"rl", 0x46 } }, -{ "cmpd2", {"rqrq", 0x47 } }, -{ "shll", {"rbrlwl", 0x48 } }, -{ "clrb", {"wb", 0x49 } }, -{ "shlq", {"rbrqwq", 0x4a } }, -{ "clrw", {"ww", 0x4b } }, -{ "mull2", {"rlml", 0x4c } }, -{ "clrl", {"wl", 0x4d } }, -{ "shal", {"rbrlwl", 0x4e } }, -{ "bleq", {"bb", 0x51 } }, -{ "expf", {"", 0x55 } }, -{ "tstf", {"", 0x56 } }, -{ "tstd", {"", 0x57 } }, -{ "shrl", {"rbrlwl", 0x58 } }, -{ "tstb", {"rb", 0x59 } }, -{ "shrq", {"rbrqwq", 0x5a } }, -{ "tstw", {"rw", 0x5b } }, -{ "mull3", {"rlrlwl", 0x5c } }, -{ "tstl", {"rl", 0x5d } }, -{ "shar", {"rbrlwl", 0x5e } }, -{ "bbssi", {"rlmlbw", 0x5f } }, -{ "ldpctx", {"", 0x60 } }, -{ "pushd", {"", 0x67 } }, -{ "incb", {"mb", 0x69 } }, -{ "incw", {"mw", 0x6b } }, -{ "divl2", {"rlml", 0x6c } }, -{ "incl", {"ml", 0x6d } }, -{ "cvtlb", {"rlwb", 0x6f } }, -{ "svpctx", {"", 0x70 } }, -{ "jmp", {"ab", 0x71 } }, -{ "cvlf", {"rl", 0x76 } }, -{ "cvld", {"rl", 0x77 } }, -{ "decb", {"mb", 0x79 } }, -{ "decw", {"mw", 0x7b } }, -{ "divl3", {"rlrlwl", 0x7c } }, -{ "decl", {"ml", 0x7d } }, -{ "cvtlw", {"rlww", 0x7f } }, -{ "bgeq", {"bb", 0x81 } }, -{ "movs2", {"abab", 0x82 } }, -{ "cvfl", {"wl", 0x86 } }, -{ "cvdl", {"wl", 0x87 } }, -{ "orb2", {"rbmb", 0x88 } }, -{ "cvtbl", {"rbwl", 0x89 } }, -{ "orw2", {"rwmw", 0x8a } }, -{ "bispsw", {"rw", 0x8b } }, -{ "orl2", {"rlml", 0x8c } }, -{ "adwc", {"rlml", 0x8d } }, -{ "adda", {"rlml", 0x8e } }, -{ "blss", {"bb", 0x91 } }, -{ "cmps2", {"abab", 0x92 } }, -{ "ldfd", {"rl", 0x97 } }, -{ "orb3", {"rbrbwb", 0x98 } }, -{ "cvtbw", {"rbww", 0x99 } }, -{ "orw3", {"rwrwww", 0x9a } }, -{ "bicpsw", {"rw", 0x9b } }, -{ "orl3", {"rlrlwl", 0x9c } }, -{ "sbwc", {"rlml", 0x9d } }, -{ "suba", {"rlml", 0x9e } }, -{ "bgtru", {"bb", 0xa1 } }, -{ "cvdf", {"", 0xa6 } }, -{ "andb2", {"rbmb", 0xa8 } }, -{ "movzbl", {"rbwl", 0xa9 } }, -{ "andw2", {"rwmw", 0xaa } }, -{ "loadr", {"rwal", 0xab } }, -{ "andl2", {"rlml", 0xac } }, -{ "mtpr", {"rlrl", 0xad } }, -{ "ffs", {"rlwl", 0xae } }, -{ "blequ", {"bb", 0xb1 } }, -{ "negf", {"", 0xb6 } }, -{ "negd", {"", 0xb7 } }, -{ "andb3", {"rbrbwb", 0xb8 } }, -{ "movzbw", {"rbww", 0xb9 } }, -{ "andw3", {"rwrwww", 0xba } }, -{ "storer", {"rwal", 0xbb } }, -{ "andl3", {"rlrlwl", 0xbc } }, -{ "mfpr", {"rlwl", 0xbd } }, -{ "ffc", {"rlwl", 0xbe } }, -{ "calls", {"rbab", 0xbf } }, -{ "prober", {"rbabrl", 0xc0 } }, -{ "bvc", {"bb", 0xc1 } }, -{ "movs3", {"ababrw", 0xc2 } }, -{ "movzwl", {"rwwl", 0xc3 } }, -{ "addf", {"rl", 0xc6 } }, -{ "addd", {"rq", 0xc7 } }, -{ "xorb2", {"rbmb", 0xc8 } }, -{ "movob", {"rbwb", 0xc9 } }, -{ "xorw2", {"rwmw", 0xca } }, -{ "movow", {"rwww", 0xcb } }, -{ "xorl2", {"rlml", 0xcc } }, -{ "movpsl", {"wl", 0xcd } }, -{ "kcall", {"rw", 0xcf } }, -{ "probew", {"rbabrl", 0xd0 } }, -{ "bvs", {"bb", 0xd1 } }, -{ "cmps3", {"ababrw", 0xd2 } }, -{ "subf", {"rq", 0xd6 } }, -{ "subd", {"rq", 0xd7 } }, -{ "xorb3", {"rbrbwb", 0xd8 } }, -{ "pushb", {"rb", 0xd9 } }, -{ "xorw3", {"rwrwww", 0xda } }, -{ "pushw", {"rw", 0xdb } }, -{ "xorl3", {"rlrlwl", 0xdc } }, -{ "pushl", {"rl", 0xdd } }, -{ "insque", {"abab", 0xe0 } }, -{ "bcs", {"bb", 0xe1 } }, -{ "bgequ", {"bb", 0xe1 } }, -{ "mulf", {"rq", 0xe6 } }, -{ "muld", {"rq", 0xe7 } }, -{ "mnegb", {"rbwb", 0xe8 } }, -{ "movab", {"abwl", 0xe9 } }, -{ "mnegw", {"rwww", 0xea } }, -{ "movaw", {"awwl", 0xeb } }, -{ "mnegl", {"rlwl", 0xec } }, -{ "moval", {"alwl", 0xed } }, -{ "remque", {"ab", 0xf0 } }, -{ "bcc", {"bb", 0xf1 } }, -{ "blssu", {"bb", 0xf1 } }, -{ "divf", {"rq", 0xf6 } }, -{ "divd", {"rq", 0xf7 } }, -{ "movblk", {"alalrw", 0xf8 } }, -{ "pushab", {"ab", 0xf9 } }, -{ "pushaw", {"aw", 0xfb } }, -{ "casel", {"rlrlrl", 0xfc } }, -{ "pushal", {"al", 0xfd } }, -{ "callf", {"rbab", 0xfe } }, -{ "" , "" } /* empty is end sentinel */ - -}; diff --git a/include/opcode/tic30.h b/include/opcode/tic30.h deleted file mode 100644 index 198e04e17..000000000 --- a/include/opcode/tic30.h +++ /dev/null @@ -1,691 +0,0 @@ -/* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright 1998 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -02110-1301, USA. */ - -/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a - header file. */ - -#ifndef _TMS320_H_ -#define _TMS320_H_ - -struct _register -{ - char *name; - unsigned char opcode; - unsigned char regtype; -}; - -typedef struct _register reg; - -#define REG_Rn 0x01 -#define REG_ARn 0x02 -#define REG_DP 0x03 -#define REG_OTHER 0x04 - -static const reg tic30_regtab[] = { - { "r0", 0x00, REG_Rn }, - { "r1", 0x01, REG_Rn }, - { "r2", 0x02, REG_Rn }, - { "r3", 0x03, REG_Rn }, - { "r4", 0x04, REG_Rn }, - { "r5", 0x05, REG_Rn }, - { "r6", 0x06, REG_Rn }, - { "r7", 0x07, REG_Rn }, - { "ar0",0x08, REG_ARn }, - { "ar1",0x09, REG_ARn }, - { "ar2",0x0A, REG_ARn }, - { "ar3",0x0B, REG_ARn }, - { "ar4",0x0C, REG_ARn }, - { "ar5",0x0D, REG_ARn }, - { "ar6",0x0E, REG_ARn }, - { "ar7",0x0F, REG_ARn }, - { "dp", 0x10, REG_DP }, - { "ir0",0x11, REG_OTHER }, - { "ir1",0x12, REG_OTHER }, - { "bk", 0x13, REG_OTHER }, - { "sp", 0x14, REG_OTHER }, - { "st", 0x15, REG_OTHER }, - { "ie", 0x16, REG_OTHER }, - { "if", 0x17, REG_OTHER }, - { "iof",0x18, REG_OTHER }, - { "rs", 0x19, REG_OTHER }, - { "re", 0x1A, REG_OTHER }, - { "rc", 0x1B, REG_OTHER }, - { "R0", 0x00, REG_Rn }, - { "R1", 0x01, REG_Rn }, - { "R2", 0x02, REG_Rn }, - { "R3", 0x03, REG_Rn }, - { "R4", 0x04, REG_Rn }, - { "R5", 0x05, REG_Rn }, - { "R6", 0x06, REG_Rn }, - { "R7", 0x07, REG_Rn }, - { "AR0",0x08, REG_ARn }, - { "AR1",0x09, REG_ARn }, - { "AR2",0x0A, REG_ARn }, - { "AR3",0x0B, REG_ARn }, - { "AR4",0x0C, REG_ARn }, - { "AR5",0x0D, REG_ARn }, - { "AR6",0x0E, REG_ARn }, - { "AR7",0x0F, REG_ARn }, - { "DP", 0x10, REG_DP }, - { "IR0",0x11, REG_OTHER }, - { "IR1",0x12, REG_OTHER }, - { "BK", 0x13, REG_OTHER }, - { "SP", 0x14, REG_OTHER }, - { "ST", 0x15, REG_OTHER }, - { "IE", 0x16, REG_OTHER }, - { "IF", 0x17, REG_OTHER }, - { "IOF",0x18, REG_OTHER }, - { "RS", 0x19, REG_OTHER }, - { "RE", 0x1A, REG_OTHER }, - { "RC", 0x1B, REG_OTHER }, - { "", 0, 0 } -}; - -static const reg *const tic30_regtab_end - = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); - -/* Indirect Addressing Modes Modification Fields */ -/* Indirect Addressing with Displacement */ -#define PreDisp_Add 0x00 -#define PreDisp_Sub 0x01 -#define PreDisp_Add_Mod 0x02 -#define PreDisp_Sub_Mod 0x03 -#define PostDisp_Add_Mod 0x04 -#define PostDisp_Sub_Mod 0x05 -#define PostDisp_Add_Circ 0x06 -#define PostDisp_Sub_Circ 0x07 -/* Indirect Addressing with Index Register IR0 */ -#define PreIR0_Add 0x08 -#define PreIR0_Sub 0x09 -#define PreIR0_Add_Mod 0x0A -#define PreIR0_Sub_Mod 0x0B -#define PostIR0_Add_Mod 0x0C -#define PostIR0_Sub_Mod 0x0D -#define PostIR0_Add_Circ 0x0E -#define PostIR0_Sub_Circ 0x0F -/* Indirect Addressing with Index Register IR1 */ -#define PreIR1_Add 0x10 -#define PreIR1_Sub 0x11 -#define PreIR1_Add_Mod 0x12 -#define PreIR1_Sub_Mod 0x13 -#define PostIR1_Add_Mod 0x14 -#define PostIR1_Sub_Mod 0x15 -#define PostIR1_Add_Circ 0x16 -#define PostIR1_Sub_Circ 0x17 -/* Indirect Addressing (Special Cases) */ -#define IndirectOnly 0x18 -#define PostIR0_Add_BitRev 0x19 - -typedef struct { - char *syntax; - unsigned char modfield; - unsigned char displacement; -} ind_addr_type; - -#define IMPLIED_DISP 0x01 -#define DISP_REQUIRED 0x02 -#define NO_DISP 0x03 - -static const ind_addr_type tic30_indaddr_tab[] = { - { "*+ar", PreDisp_Add, IMPLIED_DISP }, - { "*-ar", PreDisp_Sub, IMPLIED_DISP }, - { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, - { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, - { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, - { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, - { "*+ar()", PreDisp_Add, DISP_REQUIRED }, - { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, - { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, - { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, - { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, - { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, - { "*+ar(ir0)", PreIR0_Add, NO_DISP }, - { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, - { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, - { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, - { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, - { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, - { "*+ar(ir1)", PreIR1_Add, NO_DISP }, - { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, - { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, - { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, - { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, - { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, - { "*ar", IndirectOnly, NO_DISP }, - { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, - { "", 0,0 } -}; - -static const ind_addr_type *const tic30_indaddrtab_end - = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); - -/* Possible operand types */ -/* Register types */ -#define Rn 0x0001 -#define ARn 0x0002 -#define DPReg 0x0004 -#define OtherReg 0x0008 -/* Addressing mode types */ -#define Direct 0x0010 -#define Indirect 0x0020 -#define Imm16 0x0040 -#define Disp 0x0080 -#define Imm24 0x0100 -#define Abs24 0x0200 -/* 3 operand addressing mode types */ -#define op3T1 0x0400 -#define op3T2 0x0800 -/* Interrupt vector */ -#define IVector 0x1000 -/* Not required */ -#define NotReq 0x2000 - -#define GAddr1 Rn | Direct | Indirect | Imm16 -#define GAddr2 GAddr1 | AllReg -#define TAddr1 op3T1 | Rn | Indirect -#define TAddr2 op3T2 | Rn | Indirect -#define Reg Rn | ARn -#define AllReg Reg | DPReg | OtherReg - -typedef struct _template -{ - char *name; - unsigned int operands; /* how many operands */ - unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ - /* the bits in opcode_modifier are used to generate the final opcode from - the base_opcode. These bits also are used to detect alternate forms of - the same instruction */ - unsigned int opcode_modifier; - - /* opcode_modifier bits: */ -#define AddressMode 0x00600000 -#define PCRel 0x02000000 -#define StackOp 0x001F0000 -#define Rotate StackOp - - /* operand_types[i] describes the type of operand i. This is made - by OR'ing together all of the possible type masks. (e.g. - 'operand_types[i] = Reg|Imm' specifies that operand i can be - either a register or an immediate operand */ - unsigned int operand_types[3]; - /* This defines the number type of an immediate argument to an instruction. */ - int imm_arg_type; -#define Imm_None 0 -#define Imm_Float 1 -#define Imm_SInt 2 -#define Imm_UInt 3 -} -template; - -static const template tic30_optab[] = { - { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, - { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, - { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, - { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, - { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, - { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, - { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, - { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, - { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, - { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ - { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, - { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, - { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, - { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, - { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, - { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, - { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, - { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, - { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, - { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, - { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, - { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, - { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, - { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, - { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, - { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, - { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, - { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, - { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, - { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, - { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, - { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, - { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, - { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, - { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, - { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, - { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, - { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, - { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, - { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, - { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, - { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, - { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } -}; - -static const template *const tic30_optab_end = - tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); - -typedef struct { - char *name; - unsigned int operands_1; - unsigned int operands_2; - unsigned int base_opcode; - unsigned int operand_types[2][3]; - /* Which operand fits into which part of the final opcode word. */ - int oporder; -} partemplate; - -/* oporder defines - not very descriptive. */ -#define OO_4op1 0 -#define OO_4op2 1 -#define OO_4op3 2 -#define OO_5op1 3 -#define OO_5op2 4 -#define OO_PField 5 - -static const partemplate tic30_paroptab[] = { - { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } -}; - -static const partemplate *const tic30_paroptab_end = - tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); - -#endif diff --git a/include/opcode/tic4x.h b/include/opcode/tic4x.h deleted file mode 100644 index 8830a7df1..000000000 --- a/include/opcode/tic4x.h +++ /dev/null @@ -1,1079 +0,0 @@ -/* Table of opcodes for the Texas Instruments TMS320C[34]X family. - - Copyright (C) 2002, 2003 Free Software Foundation. - - Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33) -#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44) - -/* Define some bitfield extraction/insertion macros. */ -#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) -#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l)) -#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l)) -#define INSERTU(inst, val, m, l) (inst |= ((val) << (l))) -#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l) - -/* Define register numbers. */ -typedef enum - { - REG_R0, REG_R1, REG_R2, REG_R3, - REG_R4, REG_R5, REG_R6, REG_R7, - REG_AR0, REG_AR1, REG_AR2, REG_AR3, - REG_AR4, REG_AR5, REG_AR6, REG_AR7, - REG_DP, REG_IR0, REG_IR1, REG_BK, - REG_SP, REG_ST, REG_DIE, REG_IIE, - REG_IIF, REG_RS, REG_RE, REG_RC, - REG_R8, REG_R9, REG_R10, REG_R11, - REG_IVTP, REG_TVTP - } -c4x_reg_t; - -/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */ - -#define REG_IE REG_DIE /* C3x only */ -#define REG_IF REG_IIE /* C3x only */ -#define REG_IOF REG_IIF /* C3x only */ - -#define TIC3X_REG_MAX REG_RC -#define TIC4X_REG_MAX REG_TVTP - -/* Register table size including C4x expansion regs. */ -#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1) - -struct tic4x_register -{ - char * name; - unsigned long regno; -}; - -typedef struct tic4x_register tic4x_register_t; - -/* We could store register synonyms here. */ -static const tic4x_register_t tic3x_registers[] = -{ - {"f0", REG_R0}, - {"r0", REG_R0}, - {"f1", REG_R1}, - {"r1", REG_R1}, - {"f2", REG_R2}, - {"r2", REG_R2}, - {"f3", REG_R3}, - {"r3", REG_R3}, - {"f4", REG_R4}, - {"r4", REG_R4}, - {"f5", REG_R5}, - {"r5", REG_R5}, - {"f6", REG_R6}, - {"r6", REG_R6}, - {"f7", REG_R7}, - {"r7", REG_R7}, - {"ar0", REG_AR0}, - {"ar1", REG_AR1}, - {"ar2", REG_AR2}, - {"ar3", REG_AR3}, - {"ar4", REG_AR4}, - {"ar5", REG_AR5}, - {"ar6", REG_AR6}, - {"ar7", REG_AR7}, - {"dp", REG_DP}, - {"ir0", REG_IR0}, - {"ir1", REG_IR1}, - {"bk", REG_BK}, - {"sp", REG_SP}, - {"st", REG_ST}, - {"ie", REG_IE}, - {"if", REG_IF}, - {"iof", REG_IOF}, - {"rs", REG_RS}, - {"re", REG_RE}, - {"rc", REG_RC}, - {"", 0} -}; - -const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1); - -/* Define C4x registers in addition to C3x registers. */ -static const tic4x_register_t tic4x_registers[] = -{ - {"die", REG_DIE}, /* Clobbers C3x REG_IE */ - {"iie", REG_IIE}, /* Clobbers C3x REG_IF */ - {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */ - {"f8", REG_R8}, - {"r8", REG_R8}, - {"f9", REG_R9}, - {"r9", REG_R9}, - {"f10", REG_R10}, - {"r10", REG_R10}, - {"f11", REG_R11}, - {"r11", REG_R11}, - {"ivtp", REG_IVTP}, - {"tvtp", REG_TVTP}, - {"", 0} -}; - -const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1); - -struct tic4x_cond -{ - char * name; - unsigned long cond; -}; - -typedef struct tic4x_cond tic4x_cond_t; - -/* Define conditional branch/load suffixes. Put desired form for - disassembler last. */ -static const tic4x_cond_t tic4x_conds[] = -{ - { "u", 0x00 }, - { "c", 0x01 }, { "lo", 0x01 }, - { "ls", 0x02 }, - { "hi", 0x03 }, - { "nc", 0x04 }, { "hs", 0x04 }, - { "z", 0x05 }, { "eq", 0x05 }, - { "nz", 0x06 }, { "ne", 0x06 }, - { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 }, - { "le", 0x08 }, - { "p", 0x09 }, { "gt", 0x09 }, - { "nn", 0x0a }, { "ge", 0x0a }, - { "nv", 0x0c }, - { "v", 0x0d }, - { "nuf", 0x0e }, - { "uf", 0x0f }, - { "nlv", 0x10 }, - { "lv", 0x11 }, - { "nluf", 0x12 }, - { "luf", 0x13 }, - { "zuf", 0x14 }, - /* Dummy entry, not included in num_conds. This - lets code examine entry i+1 without checking - if we've run off the end of the table. */ - { "", 0x0} -}; - -const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1); - -struct tic4x_indirect -{ - char * name; - unsigned long modn; -}; - -typedef struct tic4x_indirect tic4x_indirect_t; - -/* Define indirect addressing modes where: - d displacement (signed) - y ir0 - z ir1 */ - -static const tic4x_indirect_t tic4x_indirects[] = -{ - { "*+a(d)", 0x00 }, - { "*-a(d)", 0x01 }, - { "*++a(d)", 0x02 }, - { "*--a(d)", 0x03 }, - { "*a++(d)", 0x04 }, - { "*a--(d)", 0x05 }, - { "*a++(d)%", 0x06 }, - { "*a--(d)%", 0x07 }, - { "*+a(y)", 0x08 }, - { "*-a(y)", 0x09 }, - { "*++a(y)", 0x0a }, - { "*--a(y)", 0x0b }, - { "*a++(y)", 0x0c }, - { "*a--(y)", 0x0d }, - { "*a++(y)%", 0x0e }, - { "*a--(y)%", 0x0f }, - { "*+a(z)", 0x10 }, - { "*-a(z)", 0x11 }, - { "*++a(z)", 0x12 }, - { "*--a(z)", 0x13 }, - { "*a++(z)", 0x14 }, - { "*a--(z)", 0x15 }, - { "*a++(z)%", 0x16 }, - { "*a--(z)%", 0x17 }, - { "*a", 0x18 }, - { "*a++(y)b", 0x19 }, - /* Dummy entry, not included in num_indirects. This - lets code examine entry i+1 without checking - if we've run off the end of the table. */ - { "", 0x0} -}; - -#define TIC3X_MODN_MAX 0x19 - -const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1); - -/* Instruction template. */ -struct tic4x_inst -{ - char * name; - unsigned long opcode; - unsigned long opmask; - char * args; - unsigned long oplevel; -}; - -typedef struct tic4x_inst tic4x_inst_t; - -/* Opcode infix - B condition 16--20 U,C,Z,LO,HI, etc. - C condition 23--27 U,C,Z,LO,HI, etc. - - Arguments - , required arg follows - ; optional arg follows - - Argument types bits [classes] - example - ----------------------------------------------------------- - * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0) - # direct (for LDP) 0--15 [Z] - @start, start - @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start - A address register 22--24 [D] - AR0, AR7 - B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x) - C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5) - E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP - e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 - F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1 - G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP - g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 - H register (0-7) 18--16 [LS,M,P,Q] - R0, R7 - I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) - i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5 - J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) - j indirect (enhanced) 8--15 [M] - *+AR0(1), R5 - K register 19--21 [LL,M,Q,QC] - R0, R7 - L register 22--24 [LL,LS,P,Q,QC] - R0, R7 - M register (R2,R3) 22--22 [M] R2, R3 - N register (R0,R1) 23--23 [M] R0, R1 - O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5) - P displacement (PC Rel) 0--15 [D,J,JS] - @start, start - Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP - q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11 - R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP - r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11 - S short int immediate 0--15 [A,AB,AY,BI] - -5, 5 - T integer (C4x) 16--20 [Z] - -5, 12 - U unsigned integer 0--15 [AU,A3] - 0, 65535 - V vector (C4x: 0--8) 0--4 [Z] - 25, 7 - W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5 - X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP - Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0 - Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP -*/ - -#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ -#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */ - -/* Define the instruction level */ -#define OP_C3X 0x1 /* C30 support - supported by all */ -#define OP_C4X 0x2 /* C40 support - C40, C44 */ -#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type - I and J is enhanced in these classes - C31>=6.0, - C32>=2.0, C33 */ -#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0, - LC31, C31>=5.0, C32 */ -#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0, - C32, C33, C40>=5.0, C44 */ - -/* The following class definition is a classification scheme for - putting instructions with similar type of arguments together. It - simplifies the op-code definitions significantly, as we then only - need to use the class macroes for 95% of the DSP's opcodes. -*/ - -/* A: General 2-operand integer operations - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Register (R) - Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI, - SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn, - MBn, MHn, MPYSHI, MPYUHI -*/ -#define A_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ - { name, opcode|0x00600000, 0xffe00000, "S,R", level } - -/* AB: General 2-operand integer operation with condition - Syntax: <i>c src, dst - c = Condition - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Register (R) - Instr: 1/0 - LDIc -*/ -#define AB_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \ - { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \ - { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \ - { name, opcode|0x40600000, 0xf0600000, "S,R", level } - -/* AU: General 2-operand unsigned integer operation - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) - dst = Register (R) - Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn -*/ -#define AU_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ - { name, opcode|0x00600000, 0xffe00000, "U,R", level } - -/* AF: General 2-operand float to integer operation - Syntax: <i> src, dst - src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) - dst = Register (R) - Instr: 1/0 - FIX -*/ -#define AF_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ - { name, opcode|0x00600000, 0xffe00000, "F,R", level } - -/* A2: Limited 1-operand (integer) operation - Syntax: <i> src - src = Register (Q), Indirect (*), None - Instr: 1/0 - NOP -*/ -#define A2_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*", level }, \ - { name, opcode|0x00000000, 0xffe00000, "" , level } - -/* A3: General 1-operand unsigned integer operation - Syntax: <i> src - src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) - Instr: 1/0 - RPTS -*/ -#define A3_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffff0000, "Q", level }, \ - { name, opcode|0x00200000, 0xffff0000, "@", level }, \ - { name, opcode|0x00400000, 0xffff0000, "*", level }, \ - { name, opcode|0x00600000, 0xffff0000, "U", level } - -/* A6: Limited 2-operand integer operation - Syntax: <i> src, dst - src = Direct (@), Indirect (*) - dst = Register (R) - Instr: 1/1 - LDII, C4x: SIGI -*/ -#define A6_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,R", level } - -/* A7: Limited 2-operand integer store operation - Syntax: <i> src, dst - src = Register (R) - dst = Direct (@), Indirect (*) - Instr: 2/0 - STI, STII -*/ -#define A7_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \ - { name, opcode|0x00400000, 0xffe00000, "R,*", level } - -/* AY: General 2-operand signed address load operation - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Address register - ARx, IRx, DP, BK, SP (Y) - Instr: 0/1 - C4x: LDA - Note: Q and Y should *never* be the same register -*/ -#define AY_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \ - { name, opcode|0x00600000, 0xffe00000, "S,Y", level } - -/* B: General 2-operand float operation - Syntax: <i> src, dst - src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) - dst = Register 0-11 (r) - Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND, - SUBF, SUBRF, C4x: RSQRF, TOIEEE -*/ -#define B_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ - { name, opcode|0x00600000, 0xffe00000, "F,r", level } - -/* BA: General 2-operand integer to float operation - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Float immediate (F) - dst = Register 0-11 (r) - Instr: 0/1 - C4x: CRCPF -*/ -#define BA_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ - { name, opcode|0x00600000, 0xffe00000, "F,r", level } - -/* BB: General 2-operand conditional float operation - Syntax: <i>c src, dst - c = Condition - src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) - dst = Register 0-11 (r) - Instr: 1/0 - LDFc -*/ -#define BB_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \ - { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \ - { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \ - { name, opcode|0x40600000, 0xf0600000, "F,r", level } - -/* BI: General 2-operand integer to float operation (yet different to BA) - Syntax: <i> src, dst - src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) - dst = Register 0-11 (r) - Instr: 1/0 - FLOAT -*/ -#define BI_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ - { name, opcode|0x00600000, 0xffe00000, "S,r", level } - -/* B6: Limited 2-operand float operation - Syntax: <i> src, dst - src = Direct (@), Indirect (*) - dst = Register 0-11 (r) - Instr: 1/1 - LDFI, C4x: FRIEEE -*/ -#define B6_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ - { name, opcode|0x00400000, 0xffe00000, "*,r", level } - -/* B7: Limited 2-operand float store operation - Syntax: <i> src, dst - src = Register 0-11 (r) - dst = Direct (@), Indirect (*) - Instr: 2/0 - STF, STFI -*/ -#define B7_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \ - { name, opcode|0x00400000, 0xffe00000, "r,*", level } - -/* D: Decrement and brach operations - Syntax: <i>c ARn, dst - c = condition - ARn = AR register 0-7 (A) - dst = Register (Q), PC-relative (P) - Instr: 2/0 - DBc, DBcD - Alias: <name1> <name2> -*/ -#define D_CLASS_INSN(name1, name2, opcode, level) \ - { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ - { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \ - { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ - { name2, opcode|0x02000000, 0xfe200000, "A,P", level } - -/* I: General branch operations - Syntax: <i> dst - dst = Address (B) - Instr: 3/1 - BR, BRD, CALL, C4x: LAJ -*/ - -/* I2: General branch operations (C4x addition) - Syntax: <i> dst - dst = Address (B), C4x: Register (Q) - Instr: 2/0 - RPTB, RPTBD -*/ - -/* J: General conditional branch operations - Syntax: <i>c dst - c = Condition - dst = Register (Q), PC-relative (P) - Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc - Alias: <name1> <name2> -*/ -#define J_CLASS_INSN(name1, name2, opcode, level) \ - { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \ - { name1, opcode|0x02000000, 0xffe00000, "P", level }, \ - { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \ - { name2, opcode|0x02000000, 0xffe00000, "P", level } - -/* JS: General conditional branch operations - Syntax: <i>c dst - c = Condition - dst = Register (Q), PC-relative (P) - Instr: 1/1 - CALLc, C4X: LAJc -*/ - -/* LL: Load-load parallell operation - Syntax: <i> src2, dst2 || <i> src1, dst1 - src1 = Indirect 0,1,IR0,IR1 (J) - dst1 = Register 0-7 (K) - src2 = Indirect 0,1,IR0,IR1, ENH: Register (i) - dst2 = Register 0-7 (L) - Instr: 2/0 - LDF||LDF, LDI||LDI - Alias: i||i, i1||i2, i2||i1 -*/ -#define LL_CLASS_INSN(name, opcode, level) \ - { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \ - { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \ - { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level } - -/* LS: Store-store parallell operation - Syntax: <i> src2, dst2 || <i> src1, dst1 - src1 = Register 0-7 (H) - dst1 = Indirect 0,1,IR0,IR1 (J) - src2 = Register 0-7 (L) - dst2 = Indirect 0,1,IR0,IR1, ENH: register (i) - Instr: 2/0 - STF||STF, STI||STI - Alias: i||i, i1||i2, i2||i1. -*/ -#define LS_CLASS_INSN(name, opcode, level) \ - { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \ - { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \ - { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level } - -/* M: General multiply and add/sub operations - Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual - <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual - <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01] - <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual - <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual - <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03] - src1 = Register 0-7 (K) - src2 = Register 0-7 (H) - src3 = Indirect 0,1,IR0,IR1, ENH: register (j) - src4 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-1 (N) - dst2 = Register 2-3 (M) - Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3 - Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3 -*/ -#define M_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ - { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ - { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ - { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ - { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ - { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ - { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ - { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ - { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ - { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ - { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ - { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ - { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ - { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ - { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level } - -/* P: General 2-operand operation with parallell store - Syntax: <ia> src2, dst1 || <ib> src3, dst2 - src2 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-7 (L) - src3 = Register 0-7 (H) - dst2 = Indirect 0,1,IR0,IR1 (J) - Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF, - LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF, - TOIEEE||STF - Alias: a||b, b||a -*/ -#define P_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \ - { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level } - -/* Q: General 3-operand operation with parallell store - Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2 - src1 = Register 0-7 (K) - src2 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-7 (L) - src3 = Register 0-7 (H) - dst2 = Indirect 0,1,IR0,IR1 (J) - Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI - Alias: a||b, b||a, a3||b, b||a3 -*/ -#define Q_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ - { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \ - { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ - { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level } - -/* QC: General commutative 3-operand operation with parallell store - Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2 - <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual - src1 = Register 0-7 (K) - src2 = Indirect 0,1,IR0,IR1, ENH: register (i) - dst1 = Register 0-7 (L) - src3 = Register 0-7 (H) - dst2 = Indirect 0,1,IR0,IR1 (J) - Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI, - OR3||STI, XOR3||STI - Alias: a||b, b||a, a3||b, b||a3 -*/ -#define QC_CLASS_INSN(namea, nameb, opcode, level) \ - { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ - { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ - { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \ - { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \ - { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ - { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ - { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \ - { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level } - -/* R: General register integer operation - Syntax: <i> dst - dst = Register (R) - Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC -*/ -#define R_CLASS_INSN(name, opcode, level) \ - { name, opcode, 0xffe0ffff, "R", level } - -/* RF: General register float operation - Syntax: <i> dst - dst = Register 0-11 (r) - Instr: 2/0 - POPF, PUSHF -*/ -#define RF_CLASS_INSN(name, opcode, level) \ - { name, opcode, 0xffe0ffff, "r", level } - -/* S: General 3-operand float operation - Syntax: <i> src2, src1, dst - src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) - src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register 0-11 (r) - Instr: 1/0 - SUBF3 - Alias: i, i3 -*/ -#define S_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } - -/* SC: General commutative 3-operand float operation - Syntax: <i> src2, src1, dst - Manual - <i> src1, src2, dst - src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) - src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register 0-11 (r) - Instr: 2/0 - ADDF3, MPYF3 - Alias: i, i3 -*/ -#define SC_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ - { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } - -/* S2: General 3-operand float operation with 2 args - Syntax: <i> src2, src1 - src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) - src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - Instr: 1/0 - CMPF3 - Alias: i, i3 -*/ -#define S2_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \ - { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } - -/* T: General 3-operand integer operand - Syntax: <i> src2, src1, dst - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register (R) - Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3 - Alias: i, i3 -*/ -#define T_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } - -/* TC: General commutative 3-operand integer operation - Syntax: <i> src2, src1, dst - <i> src1, src2, dst - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - dst = Register (R) - Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI - Alias: i, i3 -*/ -#define TC_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ - { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } - -/* T2: General 3-operand integer operation with 2 args - Syntax: <i> src2, src1 - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) - Instr: 1/0 - CMPI3 - Alias: i, i3 -*/ -#define T2_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } - -/* T2C: General commutative 3-operand integer operation with 2 args - Syntax: <i> src2, src1 - Manual - <i> src1, src2 - src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) - src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0) - Instr: 1/0 - TSTB3 - Alias: i, i3 -*/ -#define T2C_CLASS_INSN(name, opcode, level) \ - { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ - { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ - { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ - { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ - { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ - { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ - { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ - { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ - { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ - { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ - { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } - -/* Z: Misc operations with or without arguments - Syntax: <i> <arg1>,... - Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, - TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK -*/ - - -/* Define tic4x opcodes for assembler and disassembler. */ -static const tic4x_inst_t tic4x_insts[] = -{ - /* Put synonyms after the desired forms in table so that they get - overwritten in the lookup table. The disassembler will thus - print the `proper' mnemonics. Note that the disassembler - only decodes the 11 MSBs, so instructions like ldp @0x500 will - be printed as ldiu 5, dp. Note that with parallel instructions, - the second part is executed before the first part, unless - the sti1||sti2 form is used. We also allow sti2||sti1 - which is equivalent to the default sti||sti form. - */ - B_CLASS_INSN( "absf", 0x00000000, OP_C3X ), - P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ), - A_CLASS_INSN( "absi", 0x00800000, OP_C3X ), - P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ), - A_CLASS_INSN( "addc", 0x01000000, OP_C3X ), - TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ), - B_CLASS_INSN( "addf", 0x01800000, OP_C3X ), - SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ), - QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ), - A_CLASS_INSN( "addi", 0x02000000, OP_C3X ), - TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ), - QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ), - AU_CLASS_INSN( "and", 0x02800000, OP_C3X ), - TC_CLASS_INSN( "and", 0x01800000, OP_C3X ), - QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ), - AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ), - T_CLASS_INSN( "andn", 0x02000000, OP_C3X ), - A_CLASS_INSN( "ash", 0x03800000, OP_C3X ), - T_CLASS_INSN( "ash", 0x02800000, OP_C3X ), - Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ), - J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ), - J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ), - J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ), - J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ), - { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ - { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ - { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ - { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */ - { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */ - B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ), - S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ), - A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ), - T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ), - D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ), - D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ), - AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ), - P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ), - BI_CLASS_INSN( "float", 0x05800000, OP_C3X ), - P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ), - B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ), - P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ), - { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */ - { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */ - { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ - { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ - { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */ - { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */ - { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */ - { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */ - { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ), - A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ), - A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ), - A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ), - AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ), - AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ), - AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ), - AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ), - AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ), - B_CLASS_INSN( "lde", 0x06800000, OP_C3X ), - { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */ - B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ), - LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ), - P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ), - BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ), - B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ), - { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */ - { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ), - LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ), - P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ), - AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ), - A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ), - { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */ - B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ), - { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */ - { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ), - A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ), - AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ), - AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ), - { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ - A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ), - T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ), - Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ), - A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ), - A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ), - A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ), - A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ), - A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ), - A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ), - A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ), - A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ), - { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ - A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ), - A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ), - A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ), - A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ), - A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ), - A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ), - A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ), - A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ), - B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ), - SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ), - M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ), - QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ), - M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ), - A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ), - TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ), - M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ), - QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ), - M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ), - A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ), - TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ), - A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ), - TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ), - A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ), - B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ), - P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ), - A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ), - P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ), - A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ), - B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ), - AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ), - P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ), - AU_CLASS_INSN( "or", 0x10000000, OP_C3X ), - TC_CLASS_INSN( "or", 0x05800000, OP_C3X ), - QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ), - R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ), - RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ), - R_CLASS_INSN( "push", 0x0f200000, OP_C3X ), - RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ), - BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ), - { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ - { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */ - { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */ - { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */ - { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ - { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */ - B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ), - R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ), - R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ), - R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ), - R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ), - { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */ - { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ - { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */ - { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ - A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ), - B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ), - { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ - A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ), - B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ), - LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ), - B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ), - A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ), - { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */ - { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */ - LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ), - A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ), - { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */ - { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */ - A_CLASS_INSN( "subb", 0x16800000, OP_C3X ), - T_CLASS_INSN( "subb", 0x06000000, OP_C3X ), - A_CLASS_INSN( "subc", 0x17000000, OP_C3X ), - B_CLASS_INSN( "subf", 0x17800000, OP_C3X ), - S_CLASS_INSN( "subf", 0x06800000, OP_C3X ), - Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ), - A_CLASS_INSN( "subi", 0x18000000, OP_C3X ), - T_CLASS_INSN( "subi", 0x07000000, OP_C3X ), - Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ), - A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ), - B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ), - A_CLASS_INSN( "subri", 0x19800000, OP_C3X ), - { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ - B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ), - P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ), - { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */ - { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */ - AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ), - T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ), - AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ), - TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ), - QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ), - - /* Dummy entry, not included in tic4x_num_insts. This - lets code examine entry i + 1 without checking - if we've run off the end of the table. */ - { "", 0x0, 0x00, "", 0 } -}; - -const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1); diff --git a/include/opcode/tic54x.h b/include/opcode/tic54x.h deleted file mode 100644 index a37ae33a8..000000000 --- a/include/opcode/tic54x.h +++ /dev/null @@ -1,163 +0,0 @@ -/* tic54x.h -- Header file for TI TMS320C54X opcode table - Copyright 1999, 2000, 2001 Free Software Foundation, Inc. - Written by Timothy Wall (twall@cygnus.com) - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -02110-1301, USA. */ - -#ifndef _opcode_tic54x_h_ -#define _opcode_tic54x_h_ - -typedef struct _symbol -{ - const char *name; - unsigned short value; -} symbol; - -enum optype { - OPT = 0x8000, - OP_None = 0x0, - - OP_Xmem, /* AR3 or AR4, indirect */ - OP_Ymem, /* AR3 or AR4, indirect */ - OP_pmad, /* PROG mem, direct */ - OP_dmad, /* DATA mem, direct */ - OP_Smem, - OP_Lmem, /* 32-bit single-addressed (direct/indirect) */ - OP_MMR, - OP_PA, - OP_Sind, - OP_xpmad, - OP_xpmad_ms7, - OP_MMRX, - OP_MMRY, - - OP_SRC1, /* src accumulator in bit 8 */ - OP_SRC, /* src accumulator in bit 9 */ - OP_RND, /* rounded result dst accumulator, opposite of bit 8 */ - OP_DST, /* dst accumulator in bit 8 */ - OP_ARX, /* arX in bits 0-3 */ - OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */ - OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */ - OP_B, /* ACC B only */ - OP_A, /* ACC A only */ - - OP_lk, /* 16-bit immediate, '#' optional */ - OP_TS, - OP_k8, /* -128 <= k <= 128 */ - OP_16, /* literal "16" */ - OP_BITC, /* 0 to 16 */ - OP_CC, /* condition code */ - OP_CC2, /* 4-bit condition code */ - OP_CC3, /* 2-bit condition code */ - OP_123, /* 1, 2, or 3 */ - OP_031, /* 0-31, numeric */ - OP_k5, /* 0 to 31 */ - OP_k8u, /* 0 to 255 */ - OP_ASM, /* "ASM" */ - OP_T, /* "T" */ - OP_DP, /* "DP" */ - OP_ARP, /* "ARP" */ - OP_k3, /* 0-7 */ - OP_lku, /* 0 to 65535 */ - OP_N, /* 0/1 or ST0/ST1 */ - OP_SBIT, /* status bit or 0-15 */ - OP_12, /* one or two */ - OP_k9, /* 9 bits of data page (DP) address */ - OP_TRN, /* "TRN" */ - -}; - -typedef struct _template -{ - /* The opcode mnemonic */ - const char *name; - unsigned int words; /* insn size in words */ - int minops, maxops; /* min/max operand count */ - /* The significant bits in the opcode. Other bits are zero. - Instructions with more than 16 bits of opcode store the rest in the upper - 16 bits. - */ - unsigned short opcode; -#define INDIRECT(OP) ((OP)&0x80) -#define MOD(OP) (((OP)>>3)&0xF) -#define ARF(OP) ((OP)&0x7) -#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12) -#define SRC(OP) ((OP)&0x200) -#define DST(OP) ((OP)&0x100) -#define SRC1(OP) ((OP)&0x100) -#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F)) -#define SHFT(OP) ((OP)&0xF) -#define ARX(OP) ((OP)&0x7) -#define XMEM(OP) (((OP)&0x00F0)>>4) -#define YMEM(OP) ((OP)&0x000F) -#define XMOD(C) (((C)&0xC)>>2) -#define XARX(C) (((C)&0x3)+2) -#define CC3(OP) (((OP)>>8)&0x3) -#define SBIT(OP) ((OP)&0xF) -#define MMR(OP) ((OP)&0x7F) -#define MMRX(OP) ((((OP)>>4)&0xF)+16) -#define MMRY(OP) (((OP)&0xF)+16) - -#define OPTYPE(X) ((X)&~OPT) - - /* Ones in this mask indicate which bits must match the opcode field. - Zeroes indicate don't care bits (operands and/or opcode options) */ - unsigned short mask; - - /* An array of operand codes (at most 4 operands) */ -#define MAX_OPERANDS 4 - enum optype operand_types[MAX_OPERANDS]; - - /* Special purpose flags (e.g. branch type, parallel, delay, etc) - */ - unsigned short flags; -#define B_NEXT 0 /* normal execution, next insn is next address */ -#define B_BRANCH 1 /* next insn is in opcode */ -#define B_RET 2 /* next insn is on stack */ -#define B_BACC 3 /* next insn is in acc */ -#define B_REPEAT 4 /* next insn repeats */ -#define FL_BMASK 0x07 - -#define FL_DELAY 0x10 /* instruction uses delay slots */ -#define FL_EXT 0x20 /* instruction takes two words */ -#define FL_FAR 0x40 /* far mode addressing */ -#define FL_LP 0x80 /* LP-only instruction */ -#define FL_NR 0x100 /* no repeat allowed */ -#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ - -#define FL_PAR 0x400 /* Parallel instruction. */ - - unsigned short opcode2, mask2; /* some insns have an extended opcode */ - - const char* parname; - enum optype paroperand_types[MAX_OPERANDS]; - -} template; - -extern const template tic54x_unknown_opcode; -extern const template tic54x_optab[]; -extern const template tic54x_paroptab[]; -extern const symbol mmregs[], regs[]; -extern const symbol condition_codes[], cc2_codes[], status_bits[]; -extern const symbol cc3_codes[]; -extern const char *misc_symbols[]; -struct disassemble_info; -extern const template* tic54x_get_insn (struct disassemble_info *, - bfd_vma, unsigned short, int *); - -#endif /* _opcode_tic54x_h_ */ diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h deleted file mode 100644 index c89b81c6d..000000000 --- a/include/opcode/tic80.h +++ /dev/null @@ -1,282 +0,0 @@ -/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table - Copyright 1996, 1997, 2003 Free Software Foundation, Inc. - Written by Fred Fish (fnf@cygnus.com), Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef TIC80_H -#define TIC80_H - -/* The opcode table is an array of struct tic80_opcode. */ - -struct tic80_opcode -{ - /* The opcode name. */ - - const char *name; - - /* The opcode itself. Those bits which will be filled in with operands - are zeroes. */ - - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a mask - containing ones indicating those bits which must match the opcode - field, and zeroes indicating those bits which need not match (and are - presumably filled in by operands). */ - - unsigned long mask; - - /* Special purpose flags for this opcode. */ - - unsigned char flags; - - /* An array of operand codes. Each code is an index into the operand - table. They appear in the order which the operands must appear in - assembly code, and are terminated by a zero. FIXME: Adjust size to - match actual requirements when TIc80 support is complete */ - - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise in - the order in which the disassembler should consider instructions. - FIXME: This isn't currently true. */ - -extern const struct tic80_opcode tic80_opcodes[]; -extern const int tic80_num_opcodes; - - -/* The operands table is an array of struct tic80_operand. */ - -struct tic80_operand -{ - /* The number of bits in the operand. */ - - int bits; - - /* How far the operand is left shifted in the instruction. */ - - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - - unsigned long (*insert) - (unsigned long instruction, long op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & TIC80_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - - long (*extract) (unsigned long instruction, int *invalid); - - /* One bit syntax flags. */ - - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the tic80_opcodes table. */ - -extern const struct tic80_operand tic80_operands[]; - - -/* Values defined for the flags field of a struct tic80_operand. - - Note that flags for all predefined symbols, such as the general purpose - registers (ex: r10), control registers (ex: FPST), condition codes (ex: - eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be - or'd into an int where the lower bits contain the actual numeric value - that correponds to this predefined symbol. This way a single int can - contain both the value of the symbol and it's type. - */ - -/* This operand must be an even register number. Floating point numbers - for example are stored in even/odd register pairs. */ - -#define TIC80_OPERAND_EVEN (1 << 0) - -/* This operand must be an odd register number and must be one greater than - the register number of the previous operand. I.E. the second register in - an even/odd register pair. */ - -#define TIC80_OPERAND_ODD (1 << 1) - -/* This operand takes signed values. */ - -#define TIC80_OPERAND_SIGNED (1 << 2) - -/* This operand may be either a predefined constant name or a numeric value. - An example would be a condition code like "eq0.b" which has the numeric - value 0x2. */ - -#define TIC80_OPERAND_NUM (1 << 3) - -/* This operand should be wrapped in parentheses rather than separated - from the previous one by a comma. This is used for various - instructions, like the load and store instructions, which want - their operands to look like "displacement(reg)" */ - -#define TIC80_OPERAND_PARENS (1 << 4) - -/* This operand is a PC relative branch offset. The disassembler prints - these symbolically if possible. Note that the offsets are taken as word - offsets. */ - -#define TIC80_OPERAND_PCREL (1 << 5) - -/* This flag is a hint to the disassembler for using hex as the prefered - printing format, even for small positive or negative immediate values. - Normally values in the range -999 to 999 are printed as signed decimal - values and other values are printed in hex. */ - -#define TIC80_OPERAND_BITFIELD (1 << 6) - -/* This operand may have a ":m" modifier specified by bit 17 in a short - immediate form instruction. */ - -#define TIC80_OPERAND_M_SI (1 << 7) - -/* This operand may have a ":m" modifier specified by bit 15 in a long - immediate or register form instruction. */ - -#define TIC80_OPERAND_M_LI (1 << 8) - -/* This operand may have a ":s" modifier specified in bit 11 in a long - immediate or register form instruction. */ - -#define TIC80_OPERAND_SCALED (1 << 9) - -/* This operand is a floating point value */ - -#define TIC80_OPERAND_FLOAT (1 << 10) - -/* This operand is an byte offset from a base relocation. The lower - two bits of the final relocated address are ignored when the value is - written to the program counter. */ - -#define TIC80_OPERAND_BASEREL (1 << 11) - -/* This operand is an "endmask" field for a shift instruction. - It is treated special in that it can have values of 0-32, - where 0 and 32 result in the same instruction. The assembler - must be able to accept both endmask values. This disassembler - has no way of knowing from the instruction which value was - given at assembly time, so it just uses '0'. */ - -#define TIC80_OPERAND_ENDMASK (1 << 12) - -/* This operand is one of the 32 general purpose registers. - The disassembler prints these with a leading 'r'. */ - -#define TIC80_OPERAND_GPR (1 << 27) - -/* This operand is a floating point accumulator register. - The disassembler prints these with a leading 'a'. */ - -#define TIC80_OPERAND_FPA ( 1 << 28) - -/* This operand is a control register number, either numeric or - symbolic (like "EIF", "EPC", etc). - The disassembler prints these symbolically. */ - -#define TIC80_OPERAND_CR (1 << 29) - -/* This operand is a condition code, either numeric or - symbolic (like "eq0.b", "ne0.w", etc). - The disassembler prints these symbolically. */ - -#define TIC80_OPERAND_CC (1 << 30) - -/* This operand is a bit number, either numeric or - symbolic (like "eq.b", "or.f", etc). - The disassembler prints these symbolically. - Note that they appear in the instruction in 1's complement relative - to the values given in the manual. */ - -#define TIC80_OPERAND_BITNUM (1 << 31) - -/* This mask is used to strip operand bits from an int that contains - both operand bits and a numeric value in the lsbs. */ - -#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) - - -/* Flag bits for the struct tic80_opcode flags field. */ - -#define TIC80_VECTOR 01 /* Is a vector instruction */ -#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ - - -/* The opcodes library contains a table that allows translation from predefined - symbol names to numeric values, and vice versa. */ - -/* Structure to hold information about predefined symbols. */ - -struct predefined_symbol -{ - char *name; /* name to recognize */ - int value; -}; - -#define PDS_NAME(pdsp) ((pdsp) -> name) -#define PDS_VALUE(pdsp) ((pdsp) -> value) - -/* Translation array. */ -extern const struct predefined_symbol tic80_predefined_symbols[]; -/* How many members in the array. */ -extern const int tic80_num_predefined_symbols; - -/* Translate value to symbolic name. */ -const char *tic80_value_to_symbol (int val, int class); - -/* Translate symbolic name to value. */ -int tic80_symbol_to_value (char *name, int class); - -const struct predefined_symbol *tic80_next_predefined_symbol - (const struct predefined_symbol *); - -#endif /* TIC80_H */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h deleted file mode 100644 index 436ff3996..000000000 --- a/include/opcode/v850.h +++ /dev/null @@ -1,166 +0,0 @@ -/* v850.h -- Header file for NEC V850 opcode table - Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc. - Written by J.T. Conklin, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef V850_H -#define V850_H - -/* The opcode table is an array of struct v850_opcode. */ - -struct v850_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; - - /* Which (if any) operand is a memory operand. */ - unsigned int memop; - - /* Target processor(s). A bit field of processors which support - this instruction. Note a bit field is used as some instructions - are available on multiple, different processor types, whereas - other instructions are only available on one specific type. */ - unsigned int processors; -}; - -/* Values for the processors field in the v850_opcode structure. */ -#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ -#define PROCESSOR_ALL -1 /* Any processor. */ -#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ -#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ -#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ -#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */ - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct v850_opcode v850_opcodes[]; -extern const int v850_num_opcodes; - - -/* The operands table is an array of struct v850_operand. */ - -struct v850_operand -{ - /* The number of bits in the operand. */ - /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ - int bits; - - /* (bits >= 0): How far the operand is left shifted in the instruction. */ - /* (bits == -1): Bit mask of the bits in the operand. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (* insert) - (unsigned long instruction, long op, const char ** errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); - if (o->flags & V850_OPERAND_SIGNED) - op = (op << (32 - o->bits)) >> (32 - o->bits); - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - unsigned long (* extract) (unsigned long instruction, int * invalid); - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the v850_opcodes table. */ - -extern const struct v850_operand v850_operands[]; - -/* Values defined for the flags field of a struct v850_operand. */ - -/* This operand names a general purpose register */ -#define V850_OPERAND_REG 0x01 - -/* This operand names a system register */ -#define V850_OPERAND_SRG 0x02 - -/* This operand names a condition code used in the setf instruction */ -#define V850_OPERAND_CC 0x04 - -/* This operand takes signed values */ -#define V850_OPERAND_SIGNED 0x08 - -/* This operand is the ep register. */ -#define V850_OPERAND_EP 0x10 - -/* This operand is a PC displacement */ -#define V850_OPERAND_DISP 0x20 - -/* This is a relaxable operand. Only used for D9->D22 branch relaxing - right now. We may need others in the future (or maybe handle them like - promoted operands on the mn10300?) */ -#define V850_OPERAND_RELAX 0x40 - -/* The register specified must not be r0 */ -#define V850_NOT_R0 0x80 - -/* push/pop type instruction, V850E specific. */ -#define V850E_PUSH_POP 0x100 - -/* 16 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE16 0x200 - -/* 32 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE32 0x400 - -#endif /* V850_H */ diff --git a/include/opcode/vax.h b/include/opcode/vax.h deleted file mode 100644 index a52130396..000000000 --- a/include/opcode/vax.h +++ /dev/null @@ -1,382 +0,0 @@ -/* Vax opcde list. - Copyright 1989, 1991, 1992, 1995 Free Software Foundation, Inc. - -This file is part of GDB and GAS. - -GDB and GAS are free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB and GAS are distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB or GAS; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef vax_opcodeT -#define vax_opcodeT int -#endif /* no vax_opcodeT */ - -struct vot_wot /* vax opcode table: wot to do with this */ - /* particular opcode */ -{ - const char *args; /* how to compile said opcode */ - vax_opcodeT code; /* op-code (may be > 8 bits!) */ -}; - -struct vot /* vax opcode text */ -{ - const char *name; /* opcode name: lowercase string [key] */ - struct vot_wot detail; /* rest of opcode table [datum] */ -}; - -#define vot_how args -#define vot_code code -#define vot_detail detail -#define vot_name name - -static const struct vot -votstrs[] = -{ -{ "halt", {"", 0x00 } }, -{ "nop", {"", 0x01 } }, -{ "rei", {"", 0x02 } }, -{ "bpt", {"", 0x03 } }, -{ "ret", {"", 0x04 } }, -{ "rsb", {"", 0x05 } }, -{ "ldpctx", {"", 0x06 } }, -{ "svpctx", {"", 0x07 } }, -{ "cvtps", {"rwabrwab", 0x08 } }, -{ "cvtsp", {"rwabrwab", 0x09 } }, -{ "index", {"rlrlrlrlrlwl", 0x0a } }, -{ "crc", {"abrlrwab", 0x0b } }, -{ "prober", {"rbrwab", 0x0c } }, -{ "probew", {"rbrwab", 0x0d } }, -{ "insque", {"abab", 0x0e } }, -{ "remque", {"abwl", 0x0f } }, -{ "bsbb", {"bb", 0x10 } }, -{ "brb", {"bb", 0x11 } }, -{ "bneq", {"bb", 0x12 } }, -{ "bnequ", {"bb", 0x12 } }, -{ "beql", {"bb", 0x13 } }, -{ "beqlu", {"bb", 0x13 } }, -{ "bgtr", {"bb", 0x14 } }, -{ "bleq", {"bb", 0x15 } }, -{ "jsb", {"ab", 0x16 } }, -{ "jmp", {"ab", 0x17 } }, -{ "bgeq", {"bb", 0x18 } }, -{ "blss", {"bb", 0x19 } }, -{ "bgtru", {"bb", 0x1a } }, -{ "blequ", {"bb", 0x1b } }, -{ "bvc", {"bb", 0x1c } }, -{ "bvs", {"bb", 0x1d } }, -{ "bcc", {"bb", 0x1e } }, -{ "bgequ", {"bb", 0x1e } }, -{ "blssu", {"bb", 0x1f } }, -{ "bcs", {"bb", 0x1f } }, -{ "addp4", {"rwabrwab", 0x20 } }, -{ "addp6", {"rwabrwabrwab", 0x21 } }, -{ "subp4", {"rwabrwab", 0x22 } }, -{ "subp6", {"rwabrwabrwab", 0x23 } }, -{ "cvtpt", {"rwababrwab", 0x24 } }, -{ "mulp", {"rwabrwabrwab", 0x25 } }, -{ "cvttp", {"rwababrwab", 0x26 } }, -{ "divp", {"rwabrwabrwab", 0x27 } }, -{ "movc3", {"rwabab", 0x28 } }, -{ "cmpc3", {"rwabab", 0x29 } }, -{ "scanc", {"rwababrb", 0x2a } }, -{ "spanc", {"rwababrb", 0x2b } }, -{ "movc5", {"rwabrbrwab", 0x2c } }, -{ "cmpc5", {"rwabrbrwab", 0x2d } }, -{ "movtc", {"rwabrbabrwab", 0x2e } }, -{ "movtuc", {"rwabrbabrwab", 0x2f } }, -{ "bsbw", {"bw", 0x30 } }, -{ "brw", {"bw", 0x31 } }, -{ "cvtwl", {"rwwl", 0x32 } }, -{ "cvtwb", {"rwwb", 0x33 } }, -{ "movp", {"rwabab", 0x34 } }, -{ "cmpp3", {"rwabab", 0x35 } }, -{ "cvtpl", {"rwabwl", 0x36 } }, -{ "cmpp4", {"rwabrwab", 0x37 } }, -{ "editpc", {"rwababab", 0x38 } }, -{ "matchc", {"rwabrwab", 0x39 } }, -{ "locc", {"rbrwab", 0x3a } }, -{ "skpc", {"rbrwab", 0x3b } }, -{ "movzwl", {"rwwl", 0x3c } }, -{ "acbw", {"rwrwmwbw", 0x3d } }, -{ "movaw", {"awwl", 0x3e } }, -{ "pushaw", {"aw", 0x3f } }, -{ "addf2", {"rfmf", 0x40 } }, -{ "addf3", {"rfrfwf", 0x41 } }, -{ "subf2", {"rfmf", 0x42 } }, -{ "subf3", {"rfrfwf", 0x43 } }, -{ "mulf2", {"rfmf", 0x44 } }, -{ "mulf3", {"rfrfwf", 0x45 } }, -{ "divf2", {"rfmf", 0x46 } }, -{ "divf3", {"rfrfwf", 0x47 } }, -{ "cvtfb", {"rfwb", 0x48 } }, -{ "cvtfw", {"rfww", 0x49 } }, -{ "cvtfl", {"rfwl", 0x4a } }, -{ "cvtrfl", {"rfwl", 0x4b } }, -{ "cvtbf", {"rbwf", 0x4c } }, -{ "cvtwf", {"rwwf", 0x4d } }, -{ "cvtlf", {"rlwf", 0x4e } }, -{ "acbf", {"rfrfmfbw", 0x4f } }, -{ "movf", {"rfwf", 0x50 } }, -{ "cmpf", {"rfrf", 0x51 } }, -{ "mnegf", {"rfwf", 0x52 } }, -{ "tstf", {"rf", 0x53 } }, -{ "emodf", {"rfrbrfwlwf", 0x54 } }, -{ "polyf", {"rfrwab", 0x55 } }, -{ "cvtfd", {"rfwd", 0x56 } }, - /* opcode 57 is not defined yet */ -{ "adawi", {"rwmw", 0x58 } }, - /* opcode 59 is not defined yet */ - /* opcode 5a is not defined yet */ - /* opcode 5b is not defined yet */ -{ "insqhi", {"abaq", 0x5c } }, -{ "insqti", {"abaq", 0x5d } }, -{ "remqhi", {"aqwl", 0x5e } }, -{ "remqti", {"aqwl", 0x5f } }, -{ "addd2", {"rdmd", 0x60 } }, -{ "addd3", {"rdrdwd", 0x61 } }, -{ "subd2", {"rdmd", 0x62 } }, -{ "subd3", {"rdrdwd", 0x63 } }, -{ "muld2", {"rdmd", 0x64 } }, -{ "muld3", {"rdrdwd", 0x65 } }, -{ "divd2", {"rdmd", 0x66 } }, -{ "divd3", {"rdrdwd", 0x67 } }, -{ "cvtdb", {"rdwb", 0x68 } }, -{ "cvtdw", {"rdww", 0x69 } }, -{ "cvtdl", {"rdwl", 0x6a } }, -{ "cvtrdl", {"rdwl", 0x6b } }, -{ "cvtbd", {"rbwd", 0x6c } }, -{ "cvtwd", {"rwwd", 0x6d } }, -{ "cvtld", {"rlwd", 0x6e } }, -{ "acbd", {"rdrdmdbw", 0x6f } }, -{ "movd", {"rdwd", 0x70 } }, -{ "cmpd", {"rdrd", 0x71 } }, -{ "mnegd", {"rdwd", 0x72 } }, -{ "tstd", {"rd", 0x73 } }, -{ "emodd", {"rdrbrdwlwd", 0x74 } }, -{ "polyd", {"rdrwab", 0x75 } }, -{ "cvtdf", {"rdwf", 0x76 } }, - /* opcode 77 is not defined yet */ -{ "ashl", {"rbrlwl", 0x78 } }, -{ "ashq", {"rbrqwq", 0x79 } }, -{ "emul", {"rlrlrlwq", 0x7a } }, -{ "ediv", {"rlrqwlwl", 0x7b } }, -{ "clrd", {"wd", 0x7c } }, -{ "clrg", {"wg", 0x7c } }, -{ "clrq", {"wd", 0x7c } }, -{ "movq", {"rqwq", 0x7d } }, -{ "movaq", {"aqwl", 0x7e } }, -{ "movad", {"adwl", 0x7e } }, -{ "pushaq", {"aq", 0x7f } }, -{ "pushad", {"ad", 0x7f } }, -{ "addb2", {"rbmb", 0x80 } }, -{ "addb3", {"rbrbwb", 0x81 } }, -{ "subb2", {"rbmb", 0x82 } }, -{ "subb3", {"rbrbwb", 0x83 } }, -{ "mulb2", {"rbmb", 0x84 } }, -{ "mulb3", {"rbrbwb", 0x85 } }, -{ "divb2", {"rbmb", 0x86 } }, -{ "divb3", {"rbrbwb", 0x87 } }, -{ "bisb2", {"rbmb", 0x88 } }, -{ "bisb3", {"rbrbwb", 0x89 } }, -{ "bicb2", {"rbmb", 0x8a } }, -{ "bicb3", {"rbrbwb", 0x8b } }, -{ "xorb2", {"rbmb", 0x8c } }, -{ "xorb3", {"rbrbwb", 0x8d } }, -{ "mnegb", {"rbwb", 0x8e } }, -{ "caseb", {"rbrbrb", 0x8f } }, -{ "movb", {"rbwb", 0x90 } }, -{ "cmpb", {"rbrb", 0x91 } }, -{ "mcomb", {"rbwb", 0x92 } }, -{ "bitb", {"rbrb", 0x93 } }, -{ "clrb", {"wb", 0x94 } }, -{ "tstb", {"rb", 0x95 } }, -{ "incb", {"mb", 0x96 } }, -{ "decb", {"mb", 0x97 } }, -{ "cvtbl", {"rbwl", 0x98 } }, -{ "cvtbw", {"rbww", 0x99 } }, -{ "movzbl", {"rbwl", 0x9a } }, -{ "movzbw", {"rbww", 0x9b } }, -{ "rotl", {"rbrlwl", 0x9c } }, -{ "acbb", {"rbrbmbbw", 0x9d } }, -{ "movab", {"abwl", 0x9e } }, -{ "pushab", {"ab", 0x9f } }, -{ "addw2", {"rwmw", 0xa0 } }, -{ "addw3", {"rwrwww", 0xa1 } }, -{ "subw2", {"rwmw", 0xa2 } }, -{ "subw3", {"rwrwww", 0xa3 } }, -{ "mulw2", {"rwmw", 0xa4 } }, -{ "mulw3", {"rwrwww", 0xa5 } }, -{ "divw2", {"rwmw", 0xa6 } }, -{ "divw3", {"rwrwww", 0xa7 } }, -{ "bisw2", {"rwmw", 0xa8 } }, -{ "bisw3", {"rwrwww", 0xa9 } }, -{ "bicw2", {"rwmw", 0xaa } }, -{ "bicw3", {"rwrwww", 0xab } }, -{ "xorw2", {"rwmw", 0xac } }, -{ "xorw3", {"rwrwww", 0xad } }, -{ "mnegw", {"rwww", 0xae } }, -{ "casew", {"rwrwrw", 0xaf } }, -{ "movw", {"rwww", 0xb0 } }, -{ "cmpw", {"rwrw", 0xb1 } }, -{ "mcomw", {"rwww", 0xb2 } }, -{ "bitw", {"rwrw", 0xb3 } }, -{ "clrw", {"ww", 0xb4 } }, -{ "tstw", {"rw", 0xb5 } }, -{ "incw", {"mw", 0xb6 } }, -{ "decw", {"mw", 0xb7 } }, -{ "bispsw", {"rw", 0xb8 } }, -{ "bicpsw", {"rw", 0xb9 } }, -{ "popr", {"rw", 0xba } }, -{ "pushr", {"rw", 0xbb } }, -{ "chmk", {"rw", 0xbc } }, -{ "chme", {"rw", 0xbd } }, -{ "chms", {"rw", 0xbe } }, -{ "chmu", {"rw", 0xbf } }, -{ "addl2", {"rlml", 0xc0 } }, -{ "addl3", {"rlrlwl", 0xc1 } }, -{ "subl2", {"rlml", 0xc2 } }, -{ "subl3", {"rlrlwl", 0xc3 } }, -{ "mull2", {"rlml", 0xc4 } }, -{ "mull3", {"rlrlwl", 0xc5 } }, -{ "divl2", {"rlml", 0xc6 } }, -{ "divl3", {"rlrlwl", 0xc7 } }, -{ "bisl2", {"rlml", 0xc8 } }, -{ "bisl3", {"rlrlwl", 0xc9 } }, -{ "bicl2", {"rlml", 0xca } }, -{ "bicl3", {"rlrlwl", 0xcb } }, -{ "xorl2", {"rlml", 0xcc } }, -{ "xorl3", {"rlrlwl", 0xcd } }, -{ "mnegl", {"rlwl", 0xce } }, -{ "casel", {"rlrlrl", 0xcf } }, -{ "movl", {"rlwl", 0xd0 } }, -{ "cmpl", {"rlrl", 0xd1 } }, -{ "mcoml", {"rlwl", 0xd2 } }, -{ "bitl", {"rlrl", 0xd3 } }, -{ "clrf", {"wf", 0xd4 } }, -{ "clrl", {"wl", 0xd4 } }, -{ "tstl", {"rl", 0xd5 } }, -{ "incl", {"ml", 0xd6 } }, -{ "decl", {"ml", 0xd7 } }, -{ "adwc", {"rlml", 0xd8 } }, -{ "sbwc", {"rlml", 0xd9 } }, -{ "mtpr", {"rlrl", 0xda } }, -{ "mfpr", {"rlwl", 0xdb } }, -{ "movpsl", {"wl", 0xdc } }, -{ "pushl", {"rl", 0xdd } }, -{ "moval", {"alwl", 0xde } }, -{ "movaf", {"afwl", 0xde } }, -{ "pushal", {"al", 0xdf } }, -{ "pushaf", {"af", 0xdf } }, -{ "bbs", {"rlvbbb", 0xe0 } }, -{ "bbc", {"rlvbbb", 0xe1 } }, -{ "bbss", {"rlvbbb", 0xe2 } }, -{ "bbcs", {"rlvbbb", 0xe3 } }, -{ "bbsc", {"rlvbbb", 0xe4 } }, -{ "bbcc", {"rlvbbb", 0xe5 } }, -{ "bbssi", {"rlvbbb", 0xe6 } }, -{ "bbcci", {"rlvbbb", 0xe7 } }, -{ "blbs", {"rlbb", 0xe8 } }, -{ "blbc", {"rlbb", 0xe9 } }, -{ "ffs", {"rlrbvbwl", 0xea } }, -{ "ffc", {"rlrbvbwl", 0xeb } }, -{ "cmpv", {"rlrbvbrl", 0xec } }, -{ "cmpzv", {"rlrbvbrl", 0xed } }, -{ "extv", {"rlrbvbwl", 0xee } }, -{ "extzv", {"rlrbvbwl", 0xef } }, -{ "insv", {"rlrlrbvb", 0xf0 } }, -{ "acbl", {"rlrlmlbw", 0xf1 } }, -{ "aoblss", {"rlmlbb", 0xf2 } }, -{ "aobleq", {"rlmlbb", 0xf3 } }, -{ "sobgeq", {"mlbb", 0xf4 } }, -{ "sobgtr", {"mlbb", 0xf5 } }, -{ "cvtlb", {"rlwb", 0xf6 } }, -{ "cvtlw", {"rlww", 0xf7 } }, -{ "ashp", {"rbrwabrbrwab", 0xf8 } }, -{ "cvtlp", {"rlrwab", 0xf9 } }, -{ "callg", {"abab", 0xfa } }, -{ "calls", {"rlab", 0xfb } }, -{ "xfc", {"", 0xfc } }, - /* undefined opcodes here */ -{ "cvtdh", {"rdwh", 0x32fd } }, -{ "cvtgf", {"rgwh", 0x33fd } }, -{ "addg2", {"rgmg", 0x40fd } }, -{ "addg3", {"rgrgwg", 0x41fd } }, -{ "subg2", {"rgmg", 0x42fd } }, -{ "subg3", {"rgrgwg", 0x43fd } }, -{ "mulg2", {"rgmg", 0x44fd } }, -{ "mulg3", {"rgrgwg", 0x45fd } }, -{ "divg2", {"rgmg", 0x46fd } }, -{ "divg3", {"rgrgwg", 0x47fd } }, -{ "cvtgb", {"rgwb", 0x48fd } }, -{ "cvtgw", {"rgww", 0x49fd } }, -{ "cvtgl", {"rgwl", 0x4afd } }, -{ "cvtrgl", {"rgwl", 0x4bfd } }, -{ "cvtbg", {"rbwg", 0x4cfd } }, -{ "cvtwg", {"rwwg", 0x4dfd } }, -{ "cvtlg", {"rlwg", 0x4efd } }, -{ "acbg", {"rgrgmgbw", 0x4ffd } }, -{ "movg", {"rgwg", 0x50fd } }, -{ "cmpg", {"rgrg", 0x51fd } }, -{ "mnegg", {"rgwg", 0x52fd } }, -{ "tstg", {"rg", 0x53fd } }, -{ "emodg", {"rgrwrgwlwg", 0x54fd } }, -{ "polyg", {"rgrwab", 0x55fd } }, -{ "cvtgh", {"rgwh", 0x56fd } }, - /* undefined opcodes here */ -{ "addh2", {"rhmh", 0x60fd } }, -{ "addh3", {"rhrhwh", 0x61fd } }, -{ "subh2", {"rhmh", 0x62fd } }, -{ "subh3", {"rhrhwh", 0x63fd } }, -{ "mulh2", {"rhmh", 0x64fd } }, -{ "mulh3", {"rhrhwh", 0x65fd } }, -{ "divh2", {"rhmh", 0x66fd } }, -{ "divh3", {"rhrhwh", 0x67fd } }, -{ "cvthb", {"rhwb", 0x68fd } }, -{ "cvthw", {"rhww", 0x69fd } }, -{ "cvthl", {"rhwl", 0x6afd } }, -{ "cvtrhl", {"rhwl", 0x6bfd } }, -{ "cvtbh", {"rbwh", 0x6cfd } }, -{ "cvtwh", {"rwwh", 0x6dfd } }, -{ "cvtlh", {"rlwh", 0x6efd } }, -{ "acbh", {"rhrhmhbw", 0x6ffd } }, -{ "movh", {"rhwh", 0x70fd } }, -{ "cmph", {"rhrh", 0x71fd } }, -{ "mnegh", {"rhwh", 0x72fd } }, -{ "tsth", {"rh", 0x73fd } }, -{ "emodh", {"rhrwrhwlwh", 0x74fd } }, -{ "polyh", {"rhrwab", 0x75fd } }, -{ "cvthg", {"rhwg", 0x76fd } }, - /* undefined opcodes here */ -{ "clrh", {"wh", 0x7cfd } }, -{ "clro", {"wo", 0x7cfd } }, -{ "movo", {"rowo", 0x7dfd } }, -{ "movah", {"ahwl", 0x7efd } }, -{ "movao", {"aowl", 0x7efd } }, -{ "pushah", {"ah", 0x7ffd } }, -{ "pushao", {"ao", 0x7ffd } }, - /* undefined opcodes here */ -{ "cvtfh", {"rfwh", 0x98fd } }, -{ "cvtfg", {"rfwg", 0x99fd } }, - /* undefined opcodes here */ -{ "cvthf", {"rhwf", 0xf6fd } }, -{ "cvthd", {"rhwd", 0xf7fd } }, - /* undefined opcodes here */ -{ "bugl", {"rl", 0xfdff } }, -{ "bugw", {"rw", 0xfeff } }, - /* undefined opcodes here */ - -{ "", {"", 0} } /* empty is end sentinel */ - -}; /* votstrs */ - -/* end: vax.opcode.h */ |