diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 71 | ||||
| -rw-r--r-- | include/demangle.h | 3 | ||||
| -rw-r--r-- | include/dis-asm.h | 3 | ||||
| -rw-r--r-- | include/dwarf2.def | 2 | ||||
| -rw-r--r-- | include/elf/ChangeLog | 32 | ||||
| -rw-r--r-- | include/elf/aarch64.h | 215 | ||||
| -rw-r--r-- | include/elf/arm.h | 3 | ||||
| -rw-r--r-- | include/elf/common.h | 4 | ||||
| -rw-r--r-- | include/elf/tilegx.h | 20 | ||||
| -rw-r--r-- | include/mach-o/ChangeLog | 51 | ||||
| -rw-r--r-- | include/mach-o/codesign.h | 85 | ||||
| -rw-r--r-- | include/mach-o/external.h | 326 | ||||
| -rw-r--r-- | include/mach-o/loader.h | 360 | ||||
| -rw-r--r-- | include/mach-o/reloc.h | 33 | ||||
| -rw-r--r-- | include/mach-o/x86-64.h | 37 | ||||
| -rw-r--r-- | include/objalloc.h | 4 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 62 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 928 | ||||
| -rw-r--r-- | include/opcode/arm.h | 26 | ||||
| -rw-r--r-- | include/opcode/hppa.h | 8 | ||||
| -rw-r--r-- | include/opcode/ia64.h | 9 | ||||
| -rw-r--r-- | include/opcode/mips.h | 135 | ||||
| -rw-r--r-- | include/opcode/moxie.h | 4 | ||||
| -rw-r--r-- | include/opcode/s390.h | 1 | ||||
| -rw-r--r-- | include/opcode/sparc.h | 1 | ||||
| -rw-r--r-- | include/plugin-api.h | 33 |
26 files changed, 2392 insertions, 64 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 4ad0de858..e702ebe61 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,74 @@ +2012-10-08 Jason Merrill <jason@redhat.com> + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_TLS_INIT and DEMANGLE_COMPONENT_TLS_WRAPPER. + +2012-09-18 Florian Weimer <fweimer@redhat.com> + + PR other/54411 + * objalloc.h (objalloc_alloc): Do not use fast path on wraparound. + +2012-09-27 Anthony Green <green@moxielogic.com> + + * opcode/moxie.h (MOXIE_BAD): New define. + +2012-09-12 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com> + + * elf/aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc. + +2012-09-06 Cary Coutant <ccoutant@google.com> + + * dwarf2.def: Edit comment. + +2012-08-24 Sriraman Tallam <tmsriram@google.com> + + * plugin-api.h (ld_plugin_allow_unique_segment_for_sections): + New interface. + (ld_plugin_unique_segment_for_sections): New interface. + (LDPT_ALLOW_UNIQUE_SEGMENT_FOR_SECTIONS): New enum val. + (LDPT_UNIQUE_SEGMENT_FOR_SECTIONS): New enum val. + (tv_allow_unique_segment_for_sections): New member. + (tv_unique_segment_for_sections): New member. + +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * opcode/arm.h (ARM_CPU_IS_ANY): New define. + +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * elf/arm.h (TAG_CPU_ARCH_V8): New define. + (MAX_TAG_CPU_ARCH): Update. + * opcode/arm.h (ARM_EXT_V8): New define. + (FPU_VFP_EXT_ARMV8): Likewise. + (FPU_NEON_EXT_ARMV8): Likewise. + (FPU_CRYPTO_EXT_ARMV8): Likewise. + (ARM_AEXT_V8A): Likewise. + (FPU_VFP_ARMV8): Likwise. + (FPU_NEON_ARMV8): Likewise. + (FPU_CRYPTO_ARMV8): Likewise. + (FPU_ARCH_VFP_ARMV8): Likewise. + (FPU_ARCH_NEON_VFP_ARMV8): Likewise. + (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise. + (ARM_ARCH_V8A): Likwise. + (ARM_ARCH_V8A_FP): Likewise. + (ARM_ARCH_V8A_SIMD): Likewise. + (ARM_ARCH_V8A_CRYPTO): Likewise. + +2012-08-13 Ian Bolton <ian.bolton@arm.com> + Laurent Desnogues <laurent.desnogues@arm.com> + Jim MacArthur <jim.macarthur@arm.com> + Marcus Shawcroft <marcus.shawcroft@arm.com> + Nigel Stephens <nigel.stephens@arm.com> + Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + Richard Earnshaw <rearnsha@arm.com> + Sofiane Naci <sofiane.naci@arm.com> + Tejas Belagod <tejas.belagod@arm.com> + Yufeng Zhang <yufeng.zhang@arm.com> + + * dis-asm.h (print_insn_aarch64): New declaration. + (print_aarch64_disassembler_options): New declaration. + (aarch64_symbol_is_valid): New declaration. + 2012-08-02 Sean Keys <skeys@ipdatasys.com> * elf/m68hc11.h: #define E_M68HC11_NO_BANK_WARNING diff --git a/include/demangle.h b/include/demangle.h index 34b3ed3cd..5da79d852 100644 --- a/include/demangle.h +++ b/include/demangle.h @@ -272,6 +272,9 @@ enum demangle_component_type /* A guard variable. This has one subtree, the name for which this is a guard variable. */ DEMANGLE_COMPONENT_GUARD, + /* The init and wrapper functions for C++11 thread_local variables. */ + DEMANGLE_COMPONENT_TLS_INIT, + DEMANGLE_COMPONENT_TLS_WRAPPER, /* A reference temporary. This has one subtree, the name for which this is a temporary. */ DEMANGLE_COMPONENT_REFTEMP, diff --git a/include/dis-asm.h b/include/dis-asm.h index 661e7cf58..25d44fcc3 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -220,6 +220,7 @@ typedef struct disassemble_info target address. Return number of octets processed. */ typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); +extern int print_insn_aarch64 (bfd_vma, disassemble_info *); extern int print_insn_alpha (bfd_vma, disassemble_info *); extern int print_insn_avr (bfd_vma, disassemble_info *); extern int print_insn_bfin (bfd_vma, disassemble_info *); @@ -307,6 +308,7 @@ extern int print_insn_rl78 (bfd_vma, disassemble_info *); extern disassembler_ftype arc_get_disassembler (void *); extern disassembler_ftype cris_get_disassembler (bfd *); +extern void print_aarch64_disassembler_options (FILE *); extern void print_i386_disassembler_options (FILE *); extern void print_mips_disassembler_options (FILE *); extern void print_ppc_disassembler_options (FILE *); @@ -316,6 +318,7 @@ extern void print_s390_disassembler_options (FILE *); extern int get_arm_regname_num_options (void); extern int set_arm_regname_option (int); extern int get_arm_regnames (int, const char **, const char **, const char *const **); +extern bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *); extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); extern void disassemble_init_powerpc (struct disassemble_info *); diff --git a/include/dwarf2.def b/include/dwarf2.def index 3c3dfccf3..7fe2df126 100644 --- a/include/dwarf2.def +++ b/include/dwarf2.def @@ -586,7 +586,7 @@ DW_OP (DW_OP_GNU_convert, 0xf7) DW_OP (DW_OP_GNU_reinterpret, 0xf9) /* The GNU parameter ref extension. */ DW_OP (DW_OP_GNU_parameter_ref, 0xfa) -/* Extension for Fission. See http://gcc.gnu.org/wiki/DebugFission. */ +/* Extensions for Fission. See http://gcc.gnu.org/wiki/DebugFission. */ DW_OP (DW_OP_GNU_addr_index, 0xfb) DW_OP (DW_OP_GNU_const_index, 0xfc) /* HP extensions. */ diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index ef84aa36a..ece126a62 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,35 @@ +2012-08-27 Walter Lee <walt@tilera.com> + + * tilegx.h (R_TILEGX_IMM16_X0_HW0_PLT_PCREL): New relocation. + (R_TILEGX_IMM16_X1_HW0_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X0_HW1_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X1_HW1_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X0_HW2_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X1_HW2_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X0_HW3_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X1_HW3_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL): Ditto. + (R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL ): Ditto. + (R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL): Ditto. + +2012-08-13 Ian Bolton <ian.bolton@arm.com> + Laurent Desnogues <laurent.desnogues@arm.com> + Jim MacArthur <jim.macarthur@arm.com> + Marcus Shawcroft <marcus.shawcroft@arm.com> + Nigel Stephens <nigel.stephens@arm.com> + Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + Richard Earnshaw <rearnsha@arm.com> + Sofiane Naci <sofiane.naci@arm.com> + Tejas Belagod <tejas.belagod@arm.com> + Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h: New file. + * common.h (EM_res183): Rename to EM_AARCH64. + (EM_res184): Rename to EM_ARM184. + 2012-06-28 Iain Sandoe <iain@codesourcery.com> * common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE, diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h new file mode 100644 index 000000000..e3af4442a --- /dev/null +++ b/include/elf/aarch64.h @@ -0,0 +1,215 @@ +/* AArch64 ELF support for BFD. + + Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + +#ifndef _ELF_AARCH64_H +#define _ELF_AARCH64_H + +#include "elf/reloc-macros.h" + +/* Processor specific program header types. */ +#define PT_AARCH64_ARCHEXT (PT_LOPROC + 0) + +/* Additional section types. */ +#define SHT_AARCH64_ATTRIBUTES 0x70000003 /* Section holds attributes. */ + +/* AArch64-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an + entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined + in the input to a link step. */ + +/* Relocation types. */ + +START_RELOC_NUMBERS (elf_aarch64_reloc_type) + +/* Null relocations. */ +RELOC_NUMBER (R_AARCH64_NONE, 0) /* No reloc */ + +FAKE_RELOC (R_AARCH64_static_min, 256) + +RELOC_NUMBER (R_AARCH64_NULL, 256) /* No reloc */ + +/* Basic data relocations. */ + +/* .xword: (S+A) */ +RELOC_NUMBER (R_AARCH64_ABS64, 257) + +/* .word: (S+A) */ +RELOC_NUMBER (R_AARCH64_ABS32, 258) + +/* .half: (S+A) */ +RELOC_NUMBER (R_AARCH64_ABS16, 259) + +/* .xword: (S+A-P) */ +RELOC_NUMBER (R_AARCH64_PREL64, 260) + +/* .word: (S+A-P) */ +RELOC_NUMBER (R_AARCH64_PREL32, 261) + +/* .half: (S+A-P) */ +RELOC_NUMBER (R_AARCH64_PREL16, 262) + +/* Group relocations to create a 16, 32, 48 or 64 bit + unsigned data or abs address inline. */ + +/* MOV[ZK]: ((S+A) >> 0) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0, 263) + +/* MOV[ZK]: ((S+A) >> 0) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0_NC, 264) + +/* MOV[ZK]: ((S+A) >> 16) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1, 265) + +/* MOV[ZK]: ((S+A) >> 16) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1_NC, 266) + +/* MOV[ZK]: ((S+A) >> 32) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2, 267) + +/* MOV[ZK]: ((S+A) >> 32) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2_NC, 268) + +/* MOV[ZK]: ((S+A) >> 48) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_UABS_G3, 269) + +/* Group relocations to create high part of a 16, 32, 48 or 64 bit + signed data or abs address inline. Will change instruction + to MOVN or MOVZ depending on sign of calculated value. */ + +/* MOV[ZN]: ((S+A) >> 0) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_SABS_G0, 270) + +/* MOV[ZN]: ((S+A) >> 16) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_SABS_G1, 271) + +/* MOV[ZN]: ((S+A) >> 32) & 0xffff */ +RELOC_NUMBER (R_AARCH64_MOVW_SABS_G2, 272) + +/* Relocations to generate 19, 21 and 33 bit PC-relative load/store + addresses: PG(x) is (x & ~0xfff). */ + +/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */ +RELOC_NUMBER (R_AARCH64_LD_PREL_LO19, 273) + +/* ADR: (S+A-P) & 0x1fffff */ +RELOC_NUMBER (R_AARCH64_ADR_PREL_LO21, 274) + +/* ADRH: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */ +RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21, 275) + +/* ADRH: ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */ +RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21_NC, 276) + +/* ADD: (S+A) & 0xfff */ +RELOC_NUMBER (R_AARCH64_ADD_ABS_LO12_NC, 277) + +/* LD/ST8: (S+A) & 0xfff */ +RELOC_NUMBER (R_AARCH64_LDST8_ABS_LO12_NC, 278) + +/* Relocations for control-flow instructions. */ + +/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff. */ +RELOC_NUMBER (R_AARCH64_TSTBR14, 279) + +/* B.cond: ((S+A-P) >> 2) & 0x7ffff. */ +RELOC_NUMBER (R_AARCH64_CONDBR19, 280) + +/* 281 unused */ + +/* B: ((S+A-P) >> 2) & 0x3ffffff. */ +RELOC_NUMBER (R_AARCH64_JUMP26, 282) + +/* BL: ((S+A-P) >> 2) & 0x3ffffff. */ +RELOC_NUMBER (R_AARCH64_CALL26, 283) + +/* LD/ST16: (S+A) & 0xffe */ +RELOC_NUMBER (R_AARCH64_LDST16_ABS_LO12_NC, 284) + +/* LD/ST32: (S+A) & 0xffc */ +RELOC_NUMBER (R_AARCH64_LDST32_ABS_LO12_NC, 285) + +/* LD/ST64: (S+A) & 0xff8 */ +RELOC_NUMBER (R_AARCH64_LDST64_ABS_LO12_NC, 286) + +/* LD/ST128: (S+A) & 0xff0 */ +RELOC_NUMBER (R_AARCH64_LDST128_ABS_LO12_NC, 299) + +RELOC_NUMBER (R_AARCH64_GOT_LD_PREL19, 309) +RELOC_NUMBER (R_AARCH64_ADR_GOT_PAGE, 311) +RELOC_NUMBER (R_AARCH64_LD64_GOT_LO12_NC, 312) + +FAKE_RELOC (R_AARCH64_static_max, 313) + +FAKE_RELOC (R_AARCH64_tls_min, 512) +RELOC_NUMBER (R_AARCH64_TLSGD_ADR_PAGE21, 513) +RELOC_NUMBER (R_AARCH64_TLSGD_ADD_LO12_NC, 514) +RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, 539) +RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, 540) +RELOC_NUMBER (R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, 541) +RELOC_NUMBER (R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, 542) +RELOC_NUMBER (R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, 543) +RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G2, 544) +RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1, 545) +RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, 546) +RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0, 547) +RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, 548) +RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_HI12, 549) +RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12, 550) +RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 551) +FAKE_RELOC (R_AARCH64_tls_max, 552) + +FAKE_RELOC (R_AARCH64_tlsdesc_min, 560) +RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_PREL19, 560) +RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PREL21, 561) +RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PAGE, 562) +RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_LO12_NC, 563) +RELOC_NUMBER (R_AARCH64_TLSDESC_ADD_LO12_NC, 564) +RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G1, 565) +RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G0_NC, 566) +RELOC_NUMBER (R_AARCH64_TLSDESC_LDR, 567) +RELOC_NUMBER (R_AARCH64_TLSDESC_ADD, 568) +RELOC_NUMBER (R_AARCH64_TLSDESC_CALL, 569) +FAKE_RELOC (R_AARCH64_tlsdesc_max, 570) + +/* Dynamic relocations */ +FAKE_RELOC (R_AARCH64_dyn_min, 1024) + +/* Copy symbol at runtime. */ +RELOC_NUMBER (R_AARCH64_COPY, 1024) + +/* Create GOT entry. */ +RELOC_NUMBER (R_AARCH64_GLOB_DAT, 1025) + + /* Create PLT entry. */ +RELOC_NUMBER (R_AARCH64_JUMP_SLOT, 1026) + +/* Adjust by program base. */ +RELOC_NUMBER (R_AARCH64_RELATIVE, 1027) +RELOC_NUMBER (R_AARCH64_TLS_DTPMOD64, 1028) +RELOC_NUMBER (R_AARCH64_TLS_DTPREL64, 1029) +RELOC_NUMBER (R_AARCH64_TLS_TPREL64, 1030) +RELOC_NUMBER (R_AARCH64_TLSDESC, 1031) +FAKE_RELOC (R_AARCH64_dyn_max, 1032) + +END_RELOC_NUMBERS (R_AARCH64_end) + +#endif /* _ELF_AARCH64_H */ diff --git a/include/elf/arm.h b/include/elf/arm.h index 860fdf77a..8ea3fe881 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -101,7 +101,8 @@ #define TAG_CPU_ARCH_V6_M 11 #define TAG_CPU_ARCH_V6S_M 12 #define TAG_CPU_ARCH_V7E_M 13 -#define MAX_TAG_CPU_ARCH 13 +#define TAG_CPU_ARCH_V8 14 +#define MAX_TAG_CPU_ARCH 14 /* Pseudo-architecture to allow objects to be compatible with the subset of armv4t and armv6-m. This value should never be stored in object files. */ #define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1) diff --git a/include/elf/common.h b/include/elf/common.h index 58e489afe..1c681d562 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -287,8 +287,8 @@ #define EM_L1OM 180 /* Intel L1OM */ #define EM_K1OM 181 /* Intel K1OM */ #define EM_INTEL182 182 /* Reserved by Intel */ -#define EM_res183 183 /* Reserved by ARM */ -#define EM_res184 184 /* Reserved by ARM */ +#define EM_AARCH64 183 /* ARM 64-bit architecture */ +#define EM_ARM184 184 /* Reserved by ARM */ #define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */ #define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */ #define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */ diff --git a/include/elf/tilegx.h b/include/elf/tilegx.h index 004ce28ca..e838b8097 100644 --- a/include/elf/tilegx.h +++ b/include/elf/tilegx.h @@ -104,13 +104,21 @@ START_RELOC_NUMBERS (elf_tilegx_reloc_type) RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_GOT, 64) RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_GOT, 65) - /* Relocs 66-71 are currently not defined. */ + + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_PLT_PCREL, 66) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_PLT_PCREL, 67) + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_PLT_PCREL, 68) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_PLT_PCREL, 69) + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_PLT_PCREL, 70) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_PLT_PCREL, 71) RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_GOT, 72) RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_GOT, 73) RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_GOT, 74) RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_GOT, 75) - /* Relocs 76-77 are currently not defined. */ + + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW3_PLT_PCREL, 76) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW3_PLT_PCREL, 77) RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_TLS_GD, 78) RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_TLS_GD, 79) @@ -128,7 +136,13 @@ START_RELOC_NUMBERS (elf_tilegx_reloc_type) RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_TLS_IE, 92) RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_TLS_IE, 93) - /* Relocs 94-99 are currently not defined. */ + + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL, 94) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL, 95) + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL, 96) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL, 97) + RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL, 98) + RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL, 99) RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE, 100) RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE, 101) diff --git a/include/mach-o/ChangeLog b/include/mach-o/ChangeLog new file mode 100644 index 000000000..19eacd0c5 --- /dev/null +++ b/include/mach-o/ChangeLog @@ -0,0 +1,51 @@ +2012-02-23 Iain Sandoe <idsandoe@googlemail.com> + + * external.h: Add comments about relocations fields. Add macros + for non-scattered relocations. Move scattered relocation macros to + here. + * reloc.h: Remove macros related to external representation of reloc + fields. + +2012-01-12 Iain Sandoe <idsandoe@googlemail.com> + + * loader.h (BFD_MACH_O_INDIRECT_SYM_LOCAL): New. + (BFD_MACH_O_INDIRECT_SYM_ABS): New + +2012-01-04 Tristan Gingold <gingold@adacore.com> + + * external.h (mach_o_fvmlib_command_external): New structure. + +2012-01-04 Tristan Gingold <gingold@adacore.com> + + * loader.h: Update copyright year. + (bfd_mach_o_cpu_subtype): Add ARM subtypes. + +2012-01-04 Tristan Gingold <gingold@adacore.com> + + * external.h: Update copyright year. + (mach_o_symtab_command_external): Add comments. + (mach_o_encryption_info_command_external): New structure. + +2011-12-16 Tristan Gingold <gingold@adacore.com> + + * codesign.h: New file. + +2011-08-08 Tristan Gingold <gingold@adacore.com> + + * loader.h (bfd_mach_o_load_command_type): Add + BFD_MACH_O_LC_LOAD_UPWARD_DYLIB, BFD_MACH_O_LC_VERSION_MIN_MACOSX, + BFD_MACH_O_LC_VERSION_MIN_IPHONEOS, BFD_MACH_O_LC_FUNCTION_STARTS, + and BFD_MACH_O_LC_DYLD_ENVIRONMENT. + * external.h (mach_o_version_min_command_external): New structure. + +2011-08-08 Tristan Gingold <gingold@adacore.com> + + * loader.h: Reorder declarations. + * x86-64.h: New file. + * external.h: New file. + * reloc.h: New file. + +2011-07-06 Tristan Gingold <gingold@adacore.com> + + * loader.h: New file. + diff --git a/include/mach-o/codesign.h b/include/mach-o/codesign.h new file mode 100644 index 000000000..ee2f792ac --- /dev/null +++ b/include/mach-o/codesign.h @@ -0,0 +1,85 @@ +/* Mach-O support for BFD. + Copyright 2011 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _MACH_O_CODESIGN_H +#define _MACH_O_CODESIGN_H + +/* Codesign blob magics. */ + +/* Superblob containing all the components. */ +#define BFD_MACH_O_CS_MAGIC_EMBEDDED_SIGNATURE 0xfade0cc0 + +/* Individual code requirement. */ +#define BFD_MACH_O_CS_MAGIC_REQUIREMENT 0xfade0c00 + +/* Collection of code requirements, indexed by type. */ +#define BFD_MACH_O_CS_MAGIC_REQUIREMENTS 0xfade0c01 + +/* Directory. */ +#define BFD_MACH_O_CS_MAGIC_CODEDIRECTORY 0xfade0c02 + +/* Entitlements blob. */ +#define BFD_MACH_O_CS_MAGIC_EMBEDDED_ENTITLEMENTS 0xfade7171 + +/* Blob container. */ +#define BFD_MACH_O_CS_MAGIC_BLOB_WRAPPER 0xfade0b01 + +struct mach_o_codesign_codedirectory_external_v1 +{ + /* All the fields are in network byte order (big endian). */ + unsigned char version[4]; + unsigned char flags[4]; + unsigned char hash_offset[4]; + unsigned char ident_offset[4]; + unsigned char nbr_special_slots[4]; + unsigned char nbr_code_slots[4]; + unsigned char code_limit[4]; + unsigned char hash_size[1]; + unsigned char hash_type[1]; + unsigned char spare1[1]; + unsigned char page_size[1]; + unsigned char spare2[4]; +}; + +struct mach_o_codesign_codedirectory_v1 +{ + unsigned int version; + unsigned int flags; + unsigned int hash_offset; + unsigned int ident_offset; + unsigned int nbr_special_slots; + unsigned int nbr_code_slots; + unsigned int code_limit; + unsigned char hash_size; + unsigned char hash_type; + unsigned char spare1; + unsigned char page_size; + unsigned int spare2; +}; + +/* Value for hash_type. */ +#define BFD_MACH_O_CS_NO_HASH 0 +#define BFD_MACH_O_CS_HASH_SHA1 1 +#define BFD_MACH_O_CS_HASH_SHA256 2 +#define BFD_MACH_O_CS_HASH_PRESTANDARD_SKEIN_160x256 32 /* Skein, 160 bits */ +#define BFD_MACH_O_CS_HASH_PRESTANDARD_SKEIN_256x512 33 /* Skein, 256 bits */ + +#endif /* _MACH_O_CODESIGN_H */ diff --git a/include/mach-o/external.h b/include/mach-o/external.h new file mode 100644 index 000000000..41a293250 --- /dev/null +++ b/include/mach-o/external.h @@ -0,0 +1,326 @@ +/* Mach-O support for BFD. + Copyright 2011, 2012 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _MACH_O_EXTERNAL_H +#define _MACH_O_EXTERNAL_H + +struct mach_o_header_external +{ + unsigned char magic[4]; /* Magic number. */ + unsigned char cputype[4]; /* CPU that this object is for. */ + unsigned char cpusubtype[4]; /* CPU subtype. */ + unsigned char filetype[4]; /* Type of file. */ + unsigned char ncmds[4]; /* Number of load commands. */ + unsigned char sizeofcmds[4]; /* Total size of load commands. */ + unsigned char flags[4]; /* Flags. */ + unsigned char reserved[4]; /* Reserved (on 64-bit version only). */ +}; + +#define BFD_MACH_O_HEADER_SIZE 28 +#define BFD_MACH_O_HEADER_64_SIZE 32 + +/* 32-bit section header. */ + +struct mach_o_section_32_external +{ + unsigned char sectname[16]; /* Section name. */ + unsigned char segname[16]; /* Segment that the section belongs to. */ + unsigned char addr[4]; /* Address of this section in memory. */ + unsigned char size[4]; /* Size in bytes of this section. */ + unsigned char offset[4]; /* File offset of this section. */ + unsigned char align[4]; /* log2 of this section's alignment. */ + unsigned char reloff[4]; /* File offset of this section's relocs. */ + unsigned char nreloc[4]; /* Number of relocs for this section. */ + unsigned char flags[4]; /* Section flags/attributes. */ + unsigned char reserved1[4]; + unsigned char reserved2[4]; +}; +#define BFD_MACH_O_SECTION_SIZE 68 + +/* 64-bit section header. */ + +struct mach_o_section_64_external +{ + unsigned char sectname[16]; /* Section name. */ + unsigned char segname[16]; /* Segment that the section belongs to. */ + unsigned char addr[8]; /* Address of this section in memory. */ + unsigned char size[8]; /* Size in bytes of this section. */ + unsigned char offset[4]; /* File offset of this section. */ + unsigned char align[4]; /* log2 of this section's alignment. */ + unsigned char reloff[4]; /* File offset of this section's relocs. */ + unsigned char nreloc[4]; /* Number of relocs for this section. */ + unsigned char flags[4]; /* Section flags/attributes. */ + unsigned char reserved1[4]; + unsigned char reserved2[4]; + unsigned char reserved3[4]; +}; +#define BFD_MACH_O_SECTION_64_SIZE 80 + +struct mach_o_load_command_external +{ + unsigned char cmd[4]; /* The type of load command. */ + unsigned char cmdsize[4]; /* Size in bytes of entire command. */ +}; +#define BFD_MACH_O_LC_SIZE 8 + +struct mach_o_segment_command_32_external +{ + unsigned char segname[16]; /* Name of this segment. */ + unsigned char vmaddr[4]; /* Virtual memory address of this segment. */ + unsigned char vmsize[4]; /* Size there, in bytes. */ + unsigned char fileoff[4]; /* Offset in bytes of the data to be mapped. */ + unsigned char filesize[4]; /* Size in bytes on disk. */ + unsigned char maxprot[4]; /* Maximum permitted vm protection. */ + unsigned char initprot[4]; /* Initial vm protection. */ + unsigned char nsects[4]; /* Number of sections in this segment. */ + unsigned char flags[4]; /* Flags that affect the loading. */ +}; +#define BFD_MACH_O_LC_SEGMENT_SIZE 56 /* Include the header. */ + +struct mach_o_segment_command_64_external +{ + unsigned char segname[16]; /* Name of this segment. */ + unsigned char vmaddr[8]; /* Virtual memory address of this segment. */ + unsigned char vmsize[8]; /* Size there, in bytes. */ + unsigned char fileoff[8]; /* Offset in bytes of the data to be mapped. */ + unsigned char filesize[8]; /* Size in bytes on disk. */ + unsigned char maxprot[4]; /* Maximum permitted vm protection. */ + unsigned char initprot[4]; /* Initial vm protection. */ + unsigned char nsects[4]; /* Number of sections in this segment. */ + unsigned char flags[4]; /* Flags that affect the loading. */ +}; +#define BFD_MACH_O_LC_SEGMENT_64_SIZE 72 /* Include the header. */ + +struct mach_o_reloc_info_external +{ + unsigned char r_address[4]; + unsigned char r_symbolnum[4]; +}; +#define BFD_MACH_O_RELENT_SIZE 8 + +/* Relocations are based on 'address' being a section offset and an assumption + that sections are never more than 2^24-1 bytes in size. Relocation data + also carry information on type/size/PC-relative/extern and whether scattered + or not [stored in the MSB of the r_address]. */ + +#define BFD_MACH_O_SR_SCATTERED 0x80000000 + +/* For a non-scattered reloc, the relocation info is found in r_symbolnum. + Bytes 1 to 3 contain the symbol number (0xffffff, in a non-scattered PAIR). + Byte 4 contains the relocation info - but with differing bit-positions + dependent on target endian-ness - as below. */ + +#define BFD_MACH_O_LE_PCREL 0x01 +#define BFD_MACH_O_LE_LENGTH_SHIFT 1 +#define BFD_MACH_O_LE_EXTERN 0x08 +#define BFD_MACH_O_LE_TYPE_SHIFT 4 + +#define BFD_MACH_O_BE_PCREL 0x80 +#define BFD_MACH_O_BE_LENGTH_SHIFT 5 +#define BFD_MACH_O_BE_EXTERN 0x10 +#define BFD_MACH_O_BE_TYPE_SHIFT 0 + +/* The field sizes are the same for both BE and LE. */ +#define BFD_MACH_O_LENGTH_MASK 0x03 +#define BFD_MACH_O_TYPE_MASK 0x0f + +/* For a scattered reloc entry the info is contained in r_address. There + is no need to discriminate on target endian-ness, since the design was + arranged to produce the same layout on both. Scattered relocations are + only used for local items, therefore there is no 'extern' field. */ + +#define BFD_MACH_O_SR_PCREL 0x40000000 +#define BFD_MACH_O_GET_SR_LENGTH(s) (((s) >> 28) & 0x3) +#define BFD_MACH_O_GET_SR_TYPE(s) (((s) >> 24) & 0x0f) +#define BFD_MACH_O_GET_SR_ADDRESS(s) ((s) & 0x00ffffff) +#define BFD_MACH_O_SET_SR_LENGTH(l) (((l) & 0x3) << 28) +#define BFD_MACH_O_SET_SR_TYPE(t) (((t) & 0xf) << 24) +#define BFD_MACH_O_SET_SR_ADDRESS(s) ((s) & 0x00ffffff) + +struct mach_o_symtab_command_external +{ + unsigned char symoff[4]; /* File offset of the symbol table. */ + unsigned char nsyms[4]; /* Number of symbols. */ + unsigned char stroff[4]; /* File offset of the string table. */ + unsigned char strsize[4]; /* String table size. */ +}; + +struct mach_o_nlist_external +{ + unsigned char n_strx[4]; + unsigned char n_type[1]; + unsigned char n_sect[1]; + unsigned char n_desc[2]; + unsigned char n_value[4]; +}; +#define BFD_MACH_O_NLIST_SIZE 12 + +struct mach_o_nlist_64_external +{ + unsigned char n_strx[4]; + unsigned char n_type[1]; + unsigned char n_sect[1]; + unsigned char n_desc[2]; + unsigned char n_value[8]; +}; +#define BFD_MACH_O_NLIST_64_SIZE 16 + +struct mach_o_thread_command_external +{ + unsigned char flavour[4]; + unsigned char count[4]; +}; + +/* For commands that just have a string or a path. */ +struct mach_o_str_command_external +{ + unsigned char str[4]; +}; + +struct mach_o_dylib_command_external +{ + unsigned char name[4]; + unsigned char timestamp[4]; + unsigned char current_version[4]; + unsigned char compatibility_version[4]; +}; + +struct mach_o_dysymtab_command_external +{ + unsigned char ilocalsym[4]; /* Index of. */ + unsigned char nlocalsym[4]; /* Number of. */ + unsigned char iextdefsym[4]; + unsigned char nextdefsym[4]; + unsigned char iundefsym[4]; + unsigned char nundefsym[4]; + unsigned char tocoff[4]; + unsigned char ntoc[4]; + unsigned char modtaboff[4]; + unsigned char nmodtab[4]; + unsigned char extrefsymoff[4]; + unsigned char nextrefsyms[4]; + unsigned char indirectsymoff[4]; + unsigned char nindirectsyms[4]; + unsigned char extreloff[4]; + unsigned char nextrel[4]; + unsigned char locreloff[4]; + unsigned char nlocrel[4]; +}; + +struct mach_o_dylib_module_external +{ + unsigned char module_name[4]; + unsigned char iextdefsym[4]; + unsigned char nextdefsym[4]; + unsigned char irefsym[4]; + unsigned char nrefsym[4]; + unsigned char ilocalsym[4]; + unsigned char nlocalsym[4]; + unsigned char iextrel[4]; + unsigned char nextrel[4]; + unsigned char iinit_iterm[4]; + unsigned char ninit_nterm[4]; + unsigned char objc_module_info_addr[4]; + unsigned char objc_module_info_size[4]; +}; +#define BFD_MACH_O_DYLIB_MODULE_SIZE 52 + +struct mach_o_dylib_module_64_external +{ + unsigned char module_name[4]; + unsigned char iextdefsym[4]; + unsigned char nextdefsym[4]; + unsigned char irefsym[4]; + unsigned char nrefsym[4]; + unsigned char ilocalsym[4]; + unsigned char nlocalsym[4]; + unsigned char iextrel[4]; + unsigned char nextrel[4]; + unsigned char iinit_iterm[4]; + unsigned char ninit_nterm[4]; + unsigned char objc_module_info_size[4]; + unsigned char objc_module_info_addr[8]; +}; +#define BFD_MACH_O_DYLIB_MODULE_64_SIZE 56 + +struct mach_o_dylib_table_of_contents_external +{ + unsigned char symbol_index[4]; + unsigned char module_index[4]; +}; +#define BFD_MACH_O_TABLE_OF_CONTENT_SIZE 8 + +struct mach_o_linkedit_data_command_external +{ + unsigned char dataoff[4]; + unsigned char datasize[4]; +}; + +struct mach_o_dyld_info_command_external +{ + unsigned char rebase_off[4]; + unsigned char rebase_size[4]; + unsigned char bind_off[4]; + unsigned char bind_size[4]; + unsigned char weak_bind_off[4]; + unsigned char weak_bind_size[4]; + unsigned char lazy_bind_off[4]; + unsigned char lazy_bind_size[4]; + unsigned char export_off[4]; + unsigned char export_size[4]; +}; + +struct mach_o_version_min_command_external +{ + unsigned char version[4]; + unsigned char reserved[4]; +}; + +struct mach_o_encryption_info_command_external +{ + unsigned char cryptoff[4]; /* File offset of the encrypted area. */ + unsigned char cryptsize[4]; /* Size of the encrypted area. */ + unsigned char cryptid[4]; /* Encryption method. */ +}; + +struct mach_o_fvmlib_command_external +{ + unsigned char name[4]; /* Offset of the name. */ + unsigned char minor_version[4]; + unsigned char header_addr[4]; +}; + +struct mach_o_fat_header_external +{ + unsigned char magic[4]; + unsigned char nfat_arch[4]; /* Number of components. */ +}; + +struct mach_o_fat_arch_external +{ + unsigned char cputype[4]; + unsigned char cpusubtype[4]; + unsigned char offset[4]; /* File offset of the member. */ + unsigned char size[4]; /* Size of the member. */ + unsigned char align[4]; /* Power of 2. */ +}; + +#endif /* _MACH_O_EXTERNAL_H */ diff --git a/include/mach-o/loader.h b/include/mach-o/loader.h new file mode 100644 index 000000000..1b9b15efe --- /dev/null +++ b/include/mach-o/loader.h @@ -0,0 +1,360 @@ +/* Mach-O support for BFD. + Copyright 2011, 2012 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _MACH_O_LOADER_H +#define _MACH_O_LOADER_H + +/* Constants for header. */ + +typedef enum bfd_mach_o_mach_header_magic +{ + BFD_MACH_O_MH_MAGIC = 0xfeedface, + BFD_MACH_O_MH_CIGAM = 0xcefaedfe, + BFD_MACH_O_MH_MAGIC_64 = 0xfeedfacf, + BFD_MACH_O_MH_CIGAM_64 = 0xcffaedfe +} +bfd_mach_o_mach_header_magic; + +#define BFD_MACH_O_CPU_IS64BIT 0x1000000 + +typedef enum bfd_mach_o_cpu_type +{ + BFD_MACH_O_CPU_TYPE_VAX = 1, + BFD_MACH_O_CPU_TYPE_MC680x0 = 6, + BFD_MACH_O_CPU_TYPE_I386 = 7, + BFD_MACH_O_CPU_TYPE_MIPS = 8, + BFD_MACH_O_CPU_TYPE_MC98000 = 10, + BFD_MACH_O_CPU_TYPE_HPPA = 11, + BFD_MACH_O_CPU_TYPE_ARM = 12, + BFD_MACH_O_CPU_TYPE_MC88000 = 13, + BFD_MACH_O_CPU_TYPE_SPARC = 14, + BFD_MACH_O_CPU_TYPE_I860 = 15, + BFD_MACH_O_CPU_TYPE_ALPHA = 16, + BFD_MACH_O_CPU_TYPE_POWERPC = 18, + BFD_MACH_O_CPU_TYPE_POWERPC_64 = (BFD_MACH_O_CPU_TYPE_POWERPC | BFD_MACH_O_CPU_IS64BIT), + BFD_MACH_O_CPU_TYPE_X86_64 = (BFD_MACH_O_CPU_TYPE_I386 | BFD_MACH_O_CPU_IS64BIT) +} +bfd_mach_o_cpu_type; + +typedef enum bfd_mach_o_cpu_subtype +{ + /* i386. */ + BFD_MACH_O_CPU_SUBTYPE_X86_ALL = 3, + + /* arm. */ + BFD_MACH_O_CPU_SUBTYPE_ARM_ALL = 0, + BFD_MACH_O_CPU_SUBTYPE_ARM_V4T = 5, + BFD_MACH_O_CPU_SUBTYPE_ARM_V6 = 6, + BFD_MACH_O_CPU_SUBTYPE_ARM_V5TEJ = 7, + BFD_MACH_O_CPU_SUBTYPE_ARM_XSCALE = 8, + BFD_MACH_O_CPU_SUBTYPE_ARM_V7 = 9 +} +bfd_mach_o_cpu_subtype; + +typedef enum bfd_mach_o_filetype +{ + BFD_MACH_O_MH_OBJECT = 0x01, + BFD_MACH_O_MH_EXECUTE = 0x02, + BFD_MACH_O_MH_FVMLIB = 0x03, + BFD_MACH_O_MH_CORE = 0x04, + BFD_MACH_O_MH_PRELOAD = 0x05, + BFD_MACH_O_MH_DYLIB = 0x06, + BFD_MACH_O_MH_DYLINKER = 0x07, + BFD_MACH_O_MH_BUNDLE = 0x08, + BFD_MACH_O_MH_DYLIB_STUB = 0x09, + BFD_MACH_O_MH_DSYM = 0x0a, + BFD_MACH_O_MH_KEXT_BUNDLE = 0x0b +} +bfd_mach_o_filetype; + +typedef enum bfd_mach_o_header_flags +{ + BFD_MACH_O_MH_NOUNDEFS = 0x0000001, + BFD_MACH_O_MH_INCRLINK = 0x0000002, + BFD_MACH_O_MH_DYLDLINK = 0x0000004, + BFD_MACH_O_MH_BINDATLOAD = 0x0000008, + BFD_MACH_O_MH_PREBOUND = 0x0000010, + BFD_MACH_O_MH_SPLIT_SEGS = 0x0000020, + BFD_MACH_O_MH_LAZY_INIT = 0x0000040, + BFD_MACH_O_MH_TWOLEVEL = 0x0000080, + BFD_MACH_O_MH_FORCE_FLAT = 0x0000100, + BFD_MACH_O_MH_NOMULTIDEFS = 0x0000200, + BFD_MACH_O_MH_NOFIXPREBINDING = 0x0000400, + BFD_MACH_O_MH_PREBINDABLE = 0x0000800, + BFD_MACH_O_MH_ALLMODSBOUND = 0x0001000, + BFD_MACH_O_MH_SUBSECTIONS_VIA_SYMBOLS = 0x0002000, + BFD_MACH_O_MH_CANONICAL = 0x0004000, + BFD_MACH_O_MH_WEAK_DEFINES = 0x0008000, + BFD_MACH_O_MH_BINDS_TO_WEAK = 0x0010000, + BFD_MACH_O_MH_ALLOW_STACK_EXECUTION = 0x0020000, + BFD_MACH_O_MH_ROOT_SAFE = 0x0040000, + BFD_MACH_O_MH_SETUID_SAFE = 0x0080000, + BFD_MACH_O_MH_NO_REEXPORTED_DYLIBS = 0x0100000, + BFD_MACH_O_MH_PIE = 0x0200000, + BFD_MACH_O_MH_DEAD_STRIPPABLE_DYLIB = 0x0400000, + BFD_MACH_O_MH_HAS_TLV_DESCRIPTORS = 0x0800000, + BFD_MACH_O_MH_NO_HEAP_EXECUTION = 0x1000000 +} +bfd_mach_o_header_flags; + +/* Load command constants. */ +#define BFD_MACH_O_LC_REQ_DYLD 0x80000000 + +typedef enum bfd_mach_o_load_command_type +{ + BFD_MACH_O_LC_SEGMENT = 0x1, /* File segment to be mapped. */ + BFD_MACH_O_LC_SYMTAB = 0x2, /* Link-edit stab symbol table info (obsolete). */ + BFD_MACH_O_LC_SYMSEG = 0x3, /* Link-edit gdb symbol table info. */ + BFD_MACH_O_LC_THREAD = 0x4, /* Thread. */ + BFD_MACH_O_LC_UNIXTHREAD = 0x5, /* UNIX thread (includes a stack). */ + BFD_MACH_O_LC_LOADFVMLIB = 0x6, /* Load a fixed VM shared library. */ + BFD_MACH_O_LC_IDFVMLIB = 0x7, /* Fixed VM shared library id. */ + BFD_MACH_O_LC_IDENT = 0x8, /* Object identification information (obsolete). */ + BFD_MACH_O_LC_FVMFILE = 0x9, /* Fixed VM file inclusion. */ + BFD_MACH_O_LC_PREPAGE = 0xa, /* Prepage command (internal use). */ + BFD_MACH_O_LC_DYSYMTAB = 0xb, /* Dynamic link-edit symbol table info. */ + BFD_MACH_O_LC_LOAD_DYLIB = 0xc, /* Load a dynamically linked shared library. */ + BFD_MACH_O_LC_ID_DYLIB = 0xd, /* Dynamically linked shared lib identification. */ + BFD_MACH_O_LC_LOAD_DYLINKER = 0xe, /* Load a dynamic linker. */ + BFD_MACH_O_LC_ID_DYLINKER = 0xf, /* Dynamic linker identification. */ + BFD_MACH_O_LC_PREBOUND_DYLIB = 0x10, /* Modules prebound for a dynamically. */ + BFD_MACH_O_LC_ROUTINES = 0x11, /* Image routines. */ + BFD_MACH_O_LC_SUB_FRAMEWORK = 0x12, /* Sub framework. */ + BFD_MACH_O_LC_SUB_UMBRELLA = 0x13, /* Sub umbrella. */ + BFD_MACH_O_LC_SUB_CLIENT = 0x14, /* Sub client. */ + BFD_MACH_O_LC_SUB_LIBRARY = 0x15, /* Sub library. */ + BFD_MACH_O_LC_TWOLEVEL_HINTS = 0x16, /* Two-level namespace lookup hints. */ + BFD_MACH_O_LC_PREBIND_CKSUM = 0x17, /* Prebind checksum. */ + /* Load a dynamically linked shared library that is allowed to be + missing (weak). */ + BFD_MACH_O_LC_LOAD_WEAK_DYLIB = 0x18, + BFD_MACH_O_LC_SEGMENT_64 = 0x19, /* 64-bit segment of this file to be + mapped. */ + BFD_MACH_O_LC_ROUTINES_64 = 0x1a, /* Address of the dyld init routine + in a dylib. */ + BFD_MACH_O_LC_UUID = 0x1b, /* 128-bit UUID of the executable. */ + BFD_MACH_O_LC_RPATH = 0x1c, /* Run path addiions. */ + BFD_MACH_O_LC_CODE_SIGNATURE = 0x1d, /* Local of code signature. */ + BFD_MACH_O_LC_SEGMENT_SPLIT_INFO = 0x1e, /* Local of info to split seg. */ + BFD_MACH_O_LC_REEXPORT_DYLIB = 0x1f, /* Load and re-export lib. */ + BFD_MACH_O_LC_LAZY_LOAD_DYLIB = 0x20, /* Delay load of lib until use. */ + BFD_MACH_O_LC_ENCRYPTION_INFO = 0x21, /* Encrypted segment info. */ + BFD_MACH_O_LC_DYLD_INFO = 0x22, /* Compressed dyld information. */ + BFD_MACH_O_LC_LOAD_UPWARD_DYLIB = 0x23, /* Load upward dylib. */ + BFD_MACH_O_LC_VERSION_MIN_MACOSX = 0x24, /* Minimal MacOSX version. */ + BFD_MACH_O_LC_VERSION_MIN_IPHONEOS = 0x25, /* Minimal IOS version. */ + BFD_MACH_O_LC_FUNCTION_STARTS = 0x26, /* Compressed table of func start. */ + BFD_MACH_O_LC_DYLD_ENVIRONMENT = 0x27 /* Env variable string for dyld. */ +} +bfd_mach_o_load_command_type; + +/* Section constants. */ +/* Constants for the type of a section. */ + +typedef enum bfd_mach_o_section_type +{ + /* Regular section. */ + BFD_MACH_O_S_REGULAR = 0x0, + + /* Zero fill on demand section. */ + BFD_MACH_O_S_ZEROFILL = 0x1, + + /* Section with only literal C strings. */ + BFD_MACH_O_S_CSTRING_LITERALS = 0x2, + + /* Section with only 4 byte literals. */ + BFD_MACH_O_S_4BYTE_LITERALS = 0x3, + + /* Section with only 8 byte literals. */ + BFD_MACH_O_S_8BYTE_LITERALS = 0x4, + + /* Section with only pointers to literals. */ + BFD_MACH_O_S_LITERAL_POINTERS = 0x5, + + /* For the two types of symbol pointers sections and the symbol stubs + section they have indirect symbol table entries. For each of the + entries in the section the indirect symbol table entries, in + corresponding order in the indirect symbol table, start at the index + stored in the reserved1 field of the section structure. Since the + indirect symbol table entries correspond to the entries in the + section the number of indirect symbol table entries is inferred from + the size of the section divided by the size of the entries in the + section. For symbol pointers sections the size of the entries in + the section is 4 bytes and for symbol stubs sections the byte size + of the stubs is stored in the reserved2 field of the section + structure. */ + + /* Section with only non-lazy symbol pointers. */ + BFD_MACH_O_S_NON_LAZY_SYMBOL_POINTERS = 0x6, + + /* Section with only lazy symbol pointers. */ + BFD_MACH_O_S_LAZY_SYMBOL_POINTERS = 0x7, + + /* Section with only symbol stubs, byte size of stub in the reserved2 + field. */ + BFD_MACH_O_S_SYMBOL_STUBS = 0x8, + + /* Section with only function pointers for initialization. */ + BFD_MACH_O_S_MOD_INIT_FUNC_POINTERS = 0x9, + + /* Section with only function pointers for termination. */ + BFD_MACH_O_S_MOD_FINI_FUNC_POINTERS = 0xa, + + /* Section contains symbols that are coalesced by the linkers. */ + BFD_MACH_O_S_COALESCED = 0xb, + + /* Zero fill on demand section (possibly larger than 4 GB). */ + BFD_MACH_O_S_GB_ZEROFILL = 0xc, + + /* Section with only pairs of function pointers for interposing. */ + BFD_MACH_O_S_INTERPOSING = 0xd, + + /* Section with only 16 byte literals. */ + BFD_MACH_O_S_16BYTE_LITERALS = 0xe, + + /* Section contains DTrace Object Format. */ + BFD_MACH_O_S_DTRACE_DOF = 0xf, + + /* Section with only lazy symbol pointers to lazy loaded dylibs. */ + BFD_MACH_O_S_LAZY_DYLIB_SYMBOL_POINTERS = 0x10 +} +bfd_mach_o_section_type; + +/* The flags field of a section structure is separated into two parts a section + type and section attributes. The section types are mutually exclusive (it + can only have one type) but the section attributes are not (it may have more + than one attribute). */ + +#define BFD_MACH_O_SECTION_TYPE_MASK 0x000000ff + +/* Constants for the section attributes part of the flags field of a section + structure. */ +#define BFD_MACH_O_SECTION_ATTRIBUTES_MASK 0xffffff00 +/* System setable attributes. */ +#define BFD_MACH_O_SECTION_ATTRIBUTES_SYS 0x00ffff00 +/* User attributes. */ +#define BFD_MACH_O_SECTION_ATTRIBUTES_USR 0xff000000 + +typedef enum bfd_mach_o_section_attribute +{ + /* Section has no specified attibutes. */ + BFD_MACH_O_S_ATTR_NONE = 0, + + /* Section has local relocation entries. */ + BFD_MACH_O_S_ATTR_LOC_RELOC = 0x00000100, + + /* Section has external relocation entries. */ + BFD_MACH_O_S_ATTR_EXT_RELOC = 0x00000200, + + /* Section contains some machine instructions. */ + BFD_MACH_O_S_ATTR_SOME_INSTRUCTIONS = 0x00000400, + + /* A debug section. */ + BFD_MACH_O_S_ATTR_DEBUG = 0x02000000, + + /* Used with i386 stubs. */ + BFD_MACH_O_S_SELF_MODIFYING_CODE = 0x04000000, + + /* Blocks are live if they reference live blocks. */ + BFD_MACH_O_S_ATTR_LIVE_SUPPORT = 0x08000000, + + /* No dead stripping. */ + BFD_MACH_O_S_ATTR_NO_DEAD_STRIP = 0x10000000, + + /* Section symbols can be stripped in files with MH_DYLDLINK flag. */ + BFD_MACH_O_S_ATTR_STRIP_STATIC_SYMS = 0x20000000, + + /* Section contains coalesced symbols that are not to be in the TOC of an + archive. */ + BFD_MACH_O_S_ATTR_NO_TOC = 0x40000000, + + /* Section contains only true machine instructions. */ + BFD_MACH_O_S_ATTR_PURE_INSTRUCTIONS = 0x80000000 +} +bfd_mach_o_section_attribute; + +/* Symbol constants. */ + +/* Symbol n_type values. */ +#define BFD_MACH_O_N_STAB 0xe0 /* If any of these bits set, a symbolic debugging entry. */ +#define BFD_MACH_O_N_PEXT 0x10 /* Private external symbol bit. */ +#define BFD_MACH_O_N_TYPE 0x0e /* Mask for the type bits. */ +#define BFD_MACH_O_N_EXT 0x01 /* External symbol bit, set for external symbols. */ +#define BFD_MACH_O_N_UNDF 0x00 /* Undefined, n_sect == NO_SECT. */ +#define BFD_MACH_O_N_ABS 0x02 /* Absolute, n_sect == NO_SECT. */ +#define BFD_MACH_O_N_INDR 0x0a /* Indirect. */ +#define BFD_MACH_O_N_PBUD 0x0c /* Prebound undefined (defined in a dylib). */ +#define BFD_MACH_O_N_SECT 0x0e /* Defined in section number n_sect. */ + +#define BFD_MACH_O_NO_SECT 0 /* Symbol not in any section of the image. */ + +/* Symbol n_desc reference flags. */ +#define BFD_MACH_O_REFERENCE_MASK 0x0f +#define BFD_MACH_O_REFERENCE_FLAG_UNDEFINED_NON_LAZY 0x00 +#define BFD_MACH_O_REFERENCE_FLAG_UNDEFINED_LAZY 0x01 +#define BFD_MACH_O_REFERENCE_FLAG_DEFINED 0x02 +#define BFD_MACH_O_REFERENCE_FLAG_PRIVATE_DEFINED 0x03 +#define BFD_MACH_O_REFERENCE_FLAG_PRIVATE_UNDEFINED_NON_LAZY 0x04 +#define BFD_MACH_O_REFERENCE_FLAG_PRIVATE_UNDEFINED_LAZY 0x05 + +#define BFD_MACH_O_REFERENCED_DYNAMICALLY 0x10 +#define BFD_MACH_O_N_DESC_DISCARDED 0x20 +#define BFD_MACH_O_N_NO_DEAD_STRIP 0x20 +#define BFD_MACH_O_N_WEAK_REF 0x40 +#define BFD_MACH_O_N_WEAK_DEF 0x80 + +#define BFD_MACH_O_INDIRECT_SYM_LOCAL 0x80000000 +#define BFD_MACH_O_INDIRECT_SYM_ABS 0x40000000 + +/* Thread constants. */ + +typedef enum bfd_mach_o_ppc_thread_flavour +{ + BFD_MACH_O_PPC_THREAD_STATE = 1, + BFD_MACH_O_PPC_FLOAT_STATE = 2, + BFD_MACH_O_PPC_EXCEPTION_STATE = 3, + BFD_MACH_O_PPC_VECTOR_STATE = 4, + BFD_MACH_O_PPC_THREAD_STATE64 = 5, + BFD_MACH_O_PPC_EXCEPTION_STATE64 = 6, + BFD_MACH_O_PPC_THREAD_STATE_NONE = 7 +} +bfd_mach_o_ppc_thread_flavour; + +/* Defined in <mach/i386/thread_status.h> */ +typedef enum bfd_mach_o_i386_thread_flavour +{ + BFD_MACH_O_x86_THREAD_STATE32 = 1, + BFD_MACH_O_x86_FLOAT_STATE32 = 2, + BFD_MACH_O_x86_EXCEPTION_STATE32 = 3, + BFD_MACH_O_x86_THREAD_STATE64 = 4, + BFD_MACH_O_x86_FLOAT_STATE64 = 5, + BFD_MACH_O_x86_EXCEPTION_STATE64 = 6, + BFD_MACH_O_x86_THREAD_STATE = 7, + BFD_MACH_O_x86_FLOAT_STATE = 8, + BFD_MACH_O_x86_EXCEPTION_STATE = 9, + BFD_MACH_O_x86_DEBUG_STATE32 = 10, + BFD_MACH_O_x86_DEBUG_STATE64 = 11, + BFD_MACH_O_x86_DEBUG_STATE = 12, + BFD_MACH_O_x86_THREAD_STATE_NONE = 13 +} +bfd_mach_o_i386_thread_flavour; + +#endif /* _MACH_O_LOADER_H */ diff --git a/include/mach-o/reloc.h b/include/mach-o/reloc.h new file mode 100644 index 000000000..bab31efeb --- /dev/null +++ b/include/mach-o/reloc.h @@ -0,0 +1,33 @@ +/* Mach-O support for BFD. + Copyright 2011, 2012 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _MACH_O_RELOC_H +#define _MACH_O_RELOC_H + +/* Generic relocation types (used by i386). */ +#define BFD_MACH_O_GENERIC_RELOC_VANILLA 0 +#define BFD_MACH_O_GENERIC_RELOC_PAIR 1 +#define BFD_MACH_O_GENERIC_RELOC_SECTDIFF 2 +#define BFD_MACH_O_GENERIC_RELOC_PB_LA_PTR 3 +#define BFD_MACH_O_GENERIC_RELOC_LOCAL_SECTDIFF 4 +#define BFD_MACH_O_GENERIC_RELOC_TLV 5 + +#endif /* _MACH_O_RELOC_H */ diff --git a/include/mach-o/x86-64.h b/include/mach-o/x86-64.h new file mode 100644 index 000000000..d06bc26a7 --- /dev/null +++ b/include/mach-o/x86-64.h @@ -0,0 +1,37 @@ +/* Mach-O support for BFD. + Copyright 2011 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _MACH_O_X86_64_H +#define _MACH_O_X86_64_H + +/* X86-64 relocations. */ +#define BFD_MACH_O_X86_64_RELOC_UNSIGNED 0 /* Absolute addresses. */ +#define BFD_MACH_O_X86_64_RELOC_SIGNED 1 /* 32-bit disp. */ +#define BFD_MACH_O_X86_64_RELOC_BRANCH 2 /* 32-bit pcrel disp. */ +#define BFD_MACH_O_X86_64_RELOC_GOT_LOAD 3 /* Movq load of a GOT entry. */ +#define BFD_MACH_O_X86_64_RELOC_GOT 4 /* GOT reference. */ +#define BFD_MACH_O_X86_64_RELOC_SUBTRACTOR 5 /* Symbol difference. */ +#define BFD_MACH_O_X86_64_RELOC_SIGNED_1 6 /* 32-bit signed disp -1. */ +#define BFD_MACH_O_X86_64_RELOC_SIGNED_2 7 /* 32-bit signed disp -2. */ +#define BFD_MACH_O_X86_64_RELOC_SIGNED_4 8 /* 32-bit signed disp -4. */ +#define BFD_MACH_O_X86_64_RELOC_TLV 9 /* Thread local variables. */ + +#endif /* _MACH_O_X86_64_H */ diff --git a/include/objalloc.h b/include/objalloc.h index 36772d17b..52857663b 100644 --- a/include/objalloc.h +++ b/include/objalloc.h @@ -1,5 +1,5 @@ /* objalloc.h -- routines to allocate memory for objects - Copyright 1997, 2001 Free Software Foundation, Inc. + Copyright 1997-2012 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Solutions. This program is free software; you can redistribute it and/or modify it @@ -91,7 +91,7 @@ extern void *_objalloc_alloc (struct objalloc *, unsigned long); if (__len == 0) \ __len = 1; \ __len = (__len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); \ - (__len <= __o->current_space \ + (__len != 0 && __len <= __o->current_space \ ? (__o->current_ptr += __len, \ __o->current_space -= __len, \ (void *) (__o->current_ptr - __len)) \ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 1091973b2..5e77fbdea 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,6 +1,44 @@ +2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx + opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. + +2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. + +2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> + + * ia64.h (ia64_opnd): Add new operand types. + +2012-08-21 David S. Miller <davem@davemloft.net> + + * sparc.h (F3F4): New macro. + +2012-08-13 Ian Bolton <ian.bolton@arm.com> + Laurent Desnogues <laurent.desnogues@arm.com> + Jim MacArthur <jim.macarthur@arm.com> + Marcus Shawcroft <marcus.shawcroft@arm.com> + Nigel Stephens <nigel.stephens@arm.com> + Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + Richard Earnshaw <rearnsha@arm.com> + Sofiane Naci <sofiane.naci@arm.com> + Tejas Belagod <tejas.belagod@arm.com> + Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h: New file. + +2012-08-13 Richard Sandiford <rdsandiford@googlemail.com> + Maciej W. Rozycki <macro@codesourcery.com> + + * mips.h (mips_opcode): Add the exclusions field. + (OPCODE_IS_MEMBER): Remove macro. + (cpu_is_member): New inline function. + (opcode_is_member): Likewise. + 2012-07-31 Chao-Ying Fu <fu@mips.com> - Catherine Moore <clm@codesourcery.com> - Maciej W. Rozycki <macro@codesourcery.com> + Catherine Moore <clm@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> * mips.h: Document microMIPS DSP ASE usage. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for @@ -85,7 +123,7 @@ (XRELEASE_PREFIX_OPCODE): Likewise. 2011-12-08 Andrew Pinski <apinski@cavium.com> - Adam Nemet <anemet@caviumnetworks.com> + Adam Nemet <anemet@caviumnetworks.com> * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. @@ -116,7 +154,7 @@ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. 2011-08-09 Chao-ying Fu <fu@mips.com> - Maciej W. Rozycki <macro@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. @@ -162,7 +200,7 @@ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. 2011-07-24 Chao-ying Fu <fu@mips.com> - Maciej W. Rozycki <macro@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. @@ -725,7 +763,7 @@ 2008-11-28 Joshua Kinard <kumba@gentoo.org> * mips.h: Define CPU_R14000, CPU_R16000. - (OPCODE_IS_MEMBER): Include R14000, R16000 in test. + (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 2008-11-18 Catherine Moore <clm@codesourcery.com> @@ -964,9 +1002,9 @@ * i386.h: Replace CpuMNI with CpuSSSE3. 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> - Joseph Myers <joseph@codesourcery.com> - Ian Lance Taylor <ian@wasabisystems.com> - Ben Elliston <bje@wasabisystems.com> + Joseph Myers <joseph@codesourcery.com> + Ian Lance Taylor <ian@wasabisystems.com> + Ben Elliston <bje@wasabisystems.com> * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. @@ -1009,18 +1047,18 @@ * m68k.h (mcf_mask): Define. 2006-05-05 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> + David Ung <davidu@mips.com> * mips.h (enum): Add macro M_CACHE_AB. 2006-05-04 Thiemo Seufer <ths@mips.com> - Nigel Stephens <nigel@mips.com> + Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. 2006-04-30 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> + David Ung <davidu@mips.com> * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h new file mode 100644 index 000000000..3a26199a1 --- /dev/null +++ b/include/opcode/aarch64.h @@ -0,0 +1,928 @@ +/* AArch64 assembler/disassembler support. + + Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + +#ifndef OPCODE_AARCH64_H +#define OPCODE_AARCH64_H + +#include "bfd.h" +#include "bfd_stdint.h" +#include <assert.h> +#include <stdlib.h> + +/* The offset for pc-relative addressing is currently defined to be 0. */ +#define AARCH64_PCREL_OFFSET 0 + +typedef uint32_t aarch64_insn; + +/* The following bitmasks control CPU features. */ +#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ +#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ +#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ +#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ + +/* Architectures are the sum of the base and extensions. */ +#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ + AARCH64_FEATURE_FP \ + | AARCH64_FEATURE_SIMD) +#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) +#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ + +/* CPU-specific features. */ +typedef unsigned long aarch64_feature_set; + +#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ + (((CPU) & (FEAT)) != 0) + +#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ + do \ + { \ + (TARG) = (F1) | (F2); \ + } \ + while (0) + +#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ + do \ + { \ + (TARG) = (F1) &~ (F2); \ + } \ + while (0) + +#define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) + +#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ + (((OPC) & (FEAT)) != 0) + +enum aarch64_operand_class +{ + AARCH64_OPND_CLASS_NIL, + AARCH64_OPND_CLASS_INT_REG, + AARCH64_OPND_CLASS_MODIFIED_REG, + AARCH64_OPND_CLASS_FP_REG, + AARCH64_OPND_CLASS_SIMD_REG, + AARCH64_OPND_CLASS_SIMD_ELEMENT, + AARCH64_OPND_CLASS_SISD_REG, + AARCH64_OPND_CLASS_SIMD_REGLIST, + AARCH64_OPND_CLASS_CP_REG, + AARCH64_OPND_CLASS_ADDRESS, + AARCH64_OPND_CLASS_IMMEDIATE, + AARCH64_OPND_CLASS_SYSTEM, +}; + +/* Operand code that helps both parsing and coding. + Keep AARCH64_OPERANDS synced. */ + +enum aarch64_opnd +{ + AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ + + AARCH64_OPND_Rd, /* Integer register as destination. */ + AARCH64_OPND_Rn, /* Integer register as source. */ + AARCH64_OPND_Rm, /* Integer register as source. */ + AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ + AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ + AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ + AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ + + AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ + AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ + AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ + AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ + + AARCH64_OPND_Fd, /* Floating-point Fd. */ + AARCH64_OPND_Fn, /* Floating-point Fn. */ + AARCH64_OPND_Fm, /* Floating-point Fm. */ + AARCH64_OPND_Fa, /* Floating-point Fa. */ + AARCH64_OPND_Ft, /* Floating-point Ft. */ + AARCH64_OPND_Ft2, /* Floating-point Ft2. */ + + AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ + AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ + AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ + + AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ + AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ + AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ + AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ + AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ + AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ + AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ + AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ + AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ + AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ + AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single + structure to all lanes. */ + AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ + + AARCH64_OPND_Cn, /* Co-processor register in CRn field. */ + AARCH64_OPND_Cm, /* Co-processor register in CRm field. */ + + AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ + AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ + AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ + AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ + AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ + AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ + AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction + (no encoding). */ + AARCH64_OPND_IMM0, /* Immediate for #0. */ + AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ + AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ + AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ + AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ + AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ + AARCH64_OPND_IMM, /* Immediate. */ + AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ + AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ + AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ + AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ + AARCH64_OPND_BIT_NUM, /* Immediate. */ + AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ + AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ + AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for + each condition flag. */ + + AARCH64_OPND_LIMM, /* Logical Immediate. */ + AARCH64_OPND_AIMM, /* Arithmetic immediate. */ + AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ + AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ + AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ + + AARCH64_OPND_COND, /* Standard condition as the last operand. */ + + AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ + AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ + AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ + AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ + AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ + + AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ + AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ + AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ + AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ + AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is + negative or unaligned and there is + no writeback allowed. This operand code + is only used to support the programmer- + friendly feature of using LDR/STR as the + the mnemonic name for LDUR/STUR instructions + wherever there is no ambiguity. */ + AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ + AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ + AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ + + AARCH64_OPND_SYSREG, /* System register operand. */ + AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ + AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ + AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ + AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ + AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ + AARCH64_OPND_BARRIER, /* Barrier operand. */ + AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ + AARCH64_OPND_PRFOP, /* Prefetch operation. */ +}; + +/* Qualifier constrains an operand. It either specifies a variant of an + operand type or limits values available to an operand type. + + N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ + +enum aarch64_opnd_qualifier +{ + /* Indicating no further qualification on an operand. */ + AARCH64_OPND_QLF_NIL, + + /* Qualifying an operand which is a general purpose (integer) register; + indicating the operand data size or a specific register. */ + AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ + AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ + AARCH64_OPND_QLF_WSP, /* WSP. */ + AARCH64_OPND_QLF_SP, /* SP. */ + + /* Qualifying an operand which is a floating-point register, a SIMD + vector element or a SIMD vector element list; indicating operand data + size or the size of each SIMD vector element in the case of a SIMD + vector element list. + These qualifiers are also used to qualify an address operand to + indicate the size of data element a load/store instruction is + accessing. + They are also used for the immediate shift operand in e.g. SSHR. Such + a use is only for the ease of operand encoding/decoding and qualifier + sequence matching; such a use should not be applied widely; use the value + constraint qualifiers for immediate operands wherever possible. */ + AARCH64_OPND_QLF_S_B, + AARCH64_OPND_QLF_S_H, + AARCH64_OPND_QLF_S_S, + AARCH64_OPND_QLF_S_D, + AARCH64_OPND_QLF_S_Q, + + /* Qualifying an operand which is a SIMD vector register or a SIMD vector + register list; indicating register shape. + They are also used for the immediate shift operand in e.g. SSHR. Such + a use is only for the ease of operand encoding/decoding and qualifier + sequence matching; such a use should not be applied widely; use the value + constraint qualifiers for immediate operands wherever possible. */ + AARCH64_OPND_QLF_V_8B, + AARCH64_OPND_QLF_V_16B, + AARCH64_OPND_QLF_V_4H, + AARCH64_OPND_QLF_V_8H, + AARCH64_OPND_QLF_V_2S, + AARCH64_OPND_QLF_V_4S, + AARCH64_OPND_QLF_V_1D, + AARCH64_OPND_QLF_V_2D, + AARCH64_OPND_QLF_V_1Q, + + /* Constraint on value. */ + AARCH64_OPND_QLF_imm_0_7, + AARCH64_OPND_QLF_imm_0_15, + AARCH64_OPND_QLF_imm_0_31, + AARCH64_OPND_QLF_imm_0_63, + AARCH64_OPND_QLF_imm_1_32, + AARCH64_OPND_QLF_imm_1_64, + + /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros + or shift-ones. */ + AARCH64_OPND_QLF_LSL, + AARCH64_OPND_QLF_MSL, + + /* Special qualifier helping retrieve qualifier information during the + decoding time (currently not in use). */ + AARCH64_OPND_QLF_RETRIEVE, +}; + +/* Instruction class. */ + +enum aarch64_insn_class +{ + addsub_carry, + addsub_ext, + addsub_imm, + addsub_shift, + asimdall, + asimddiff, + asimdelem, + asimdext, + asimdimm, + asimdins, + asimdmisc, + asimdperm, + asimdsame, + asimdshf, + asimdtbl, + asisddiff, + asisdelem, + asisdlse, + asisdlsep, + asisdlso, + asisdlsop, + asisdmisc, + asisdone, + asisdpair, + asisdsame, + asisdshf, + bitfield, + branch_imm, + branch_reg, + compbranch, + condbranch, + condcmp_imm, + condcmp_reg, + condsel, + cryptoaes, + cryptosha2, + cryptosha3, + dp_1src, + dp_2src, + dp_3src, + exception, + extract, + float2fix, + float2int, + floatccmp, + floatcmp, + floatdp1, + floatdp2, + floatdp3, + floatimm, + floatsel, + ldst_immpost, + ldst_immpre, + ldst_imm9, /* immpost or immpre */ + ldst_pos, + ldst_regoff, + ldst_unpriv, + ldst_unscaled, + ldstexcl, + ldstnapair_offs, + ldstpair_off, + ldstpair_indexed, + loadlit, + log_imm, + log_shift, + movewide, + pcreladdr, + ic_system, + testbranch, +}; + +/* Opcode enumerators. */ + +enum aarch64_op +{ + OP_NIL, + OP_STRB_POS, + OP_LDRB_POS, + OP_LDRSB_POS, + OP_STRH_POS, + OP_LDRH_POS, + OP_LDRSH_POS, + OP_STR_POS, + OP_LDR_POS, + OP_STRF_POS, + OP_LDRF_POS, + OP_LDRSW_POS, + OP_PRFM_POS, + + OP_STURB, + OP_LDURB, + OP_LDURSB, + OP_STURH, + OP_LDURH, + OP_LDURSH, + OP_STUR, + OP_LDUR, + OP_STURV, + OP_LDURV, + OP_LDURSW, + OP_PRFUM, + + OP_LDR_LIT, + OP_LDRV_LIT, + OP_LDRSW_LIT, + OP_PRFM_LIT, + + OP_ADD, + OP_B, + OP_BL, + + OP_MOVN, + OP_MOVZ, + OP_MOVK, + + OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ + OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ + OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ + + OP_MOV_V, /* MOV alias for moving vector register. */ + + OP_ASR_IMM, + OP_LSR_IMM, + OP_LSL_IMM, + + OP_BIC, + + OP_UBFX, + OP_BFXIL, + OP_SBFX, + OP_SBFIZ, + OP_BFI, + OP_UBFIZ, + OP_UXTB, + OP_UXTH, + OP_UXTW, + + OP_V_MOVI_B, + + OP_CINC, + OP_CINV, + OP_CNEG, + OP_CSET, + OP_CSETM, + + OP_FCVT, + OP_FCVTN, + OP_FCVTN2, + OP_FCVTL, + OP_FCVTL2, + OP_FCVTXN_S, /* Scalar version. */ + + OP_ROR_IMM, + + OP_TOTAL_NUM, /* Pseudo. */ +}; + +/* Maximum number of operands an instruction can have. */ +#define AARCH64_MAX_OPND_NUM 6 +/* Maximum number of qualifier sequences an instruction can have. */ +#define AARCH64_MAX_QLF_SEQ_NUM 10 +/* Operand qualifier typedef; optimized for the size. */ +typedef unsigned char aarch64_opnd_qualifier_t; +/* Operand qualifier sequence typedef. */ +typedef aarch64_opnd_qualifier_t \ + aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; + +/* FIXME: improve the efficiency. */ +static inline bfd_boolean +empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) +{ + int i; + for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) + if (qualifiers[i] != AARCH64_OPND_QLF_NIL) + return FALSE; + return TRUE; +} + +/* This structure holds information for a particular opcode. */ + +struct aarch64_opcode +{ + /* The name of the mnemonic. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + aarch64_insn opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + aarch64_insn mask; + + /* Instruction class. */ + enum aarch64_insn_class iclass; + + /* Enumerator identifier. */ + enum aarch64_op op; + + /* Which architecture variant provides this instruction. */ + const aarch64_feature_set *avariant; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; + + /* A list of operand qualifier code sequence. Each operand qualifier + code qualifies the corresponding operand code. Each operand + qualifier sequence specifies a valid opcode variant and related + constraint on operands. */ + aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; + + /* Flags providing information about this instruction */ + uint32_t flags; +}; + +typedef struct aarch64_opcode aarch64_opcode; + +/* Table describing all the AArch64 opcodes. */ +extern aarch64_opcode aarch64_opcode_table[]; + +/* Opcode flags. */ +#define F_ALIAS (1 << 0) +#define F_HAS_ALIAS (1 << 1) +/* Disassembly preference priority 1-3 (the larger the higher). If nothing + is specified, it is the priority 0 by default, i.e. the lowest priority. */ +#define F_P1 (1 << 2) +#define F_P2 (2 << 2) +#define F_P3 (3 << 2) +/* Flag an instruction that is truly conditional executed, e.g. b.cond. */ +#define F_COND (1 << 4) +/* Instruction has the field of 'sf'. */ +#define F_SF (1 << 5) +/* Instruction has the field of 'size:Q'. */ +#define F_SIZEQ (1 << 6) +/* Floating-point instruction has the field of 'type'. */ +#define F_FPTYPE (1 << 7) +/* AdvSIMD scalar instruction has the field of 'size'. */ +#define F_SSIZE (1 << 8) +/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ +#define F_T (1 << 9) +/* Size of GPR operand in AdvSIMD instructions encoded in Q. */ +#define F_GPRSIZE_IN_Q (1 << 10) +/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ +#define F_LDS_SIZE (1 << 11) +/* Optional operand; assume maximum of 1 operand can be optional. */ +#define F_OPD0_OPT (1 << 12) +#define F_OPD1_OPT (2 << 12) +#define F_OPD2_OPT (3 << 12) +#define F_OPD3_OPT (4 << 12) +#define F_OPD4_OPT (5 << 12) +/* Default value for the optional operand when omitted from the assembly. */ +#define F_DEFAULT(X) (((X) & 0x1f) << 15) +/* Instruction that is an alias of another instruction needs to be + encoded/decoded by converting it to/from the real form, followed by + the encoding/decoding according to the rules of the real opcode. + This compares to the direct coding using the alias's information. + N.B. this flag requires F_ALIAS to be used together. */ +#define F_CONV (1 << 20) +/* Use together with F_ALIAS to indicate an alias opcode is a programmer + friendly pseudo instruction available only in the assembly code (thus will + not show up in the disassembly). */ +#define F_PSEUDO (1 << 21) +/* Instruction has miscellaneous encoding/decoding rules. */ +#define F_MISC (1 << 22) +/* Instruction has the field of 'N'; used in conjunction with F_SF. */ +#define F_N (1 << 23) +/* Opcode dependent field. */ +#define F_OD(X) (((X) & 0x7) << 24) +/* Next bit is 27. */ + +static inline bfd_boolean +alias_opcode_p (const aarch64_opcode *opcode) +{ + return (opcode->flags & F_ALIAS) ? TRUE : FALSE; +} + +static inline bfd_boolean +opcode_has_alias (const aarch64_opcode *opcode) +{ + return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE; +} + +/* Priority for disassembling preference. */ +static inline int +opcode_priority (const aarch64_opcode *opcode) +{ + return (opcode->flags >> 2) & 0x3; +} + +static inline bfd_boolean +pseudo_opcode_p (const aarch64_opcode *opcode) +{ + return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE; +} + +static inline bfd_boolean +optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) +{ + return (((opcode->flags >> 12) & 0x7) == idx + 1) + ? TRUE : FALSE; +} + +static inline aarch64_insn +get_optional_operand_default_value (const aarch64_opcode *opcode) +{ + return (opcode->flags >> 15) & 0x1f; +} + +static inline unsigned int +get_opcode_dependent_value (const aarch64_opcode *opcode) +{ + return (opcode->flags >> 24) & 0x7; +} + +static inline bfd_boolean +opcode_has_special_coder (const aarch64_opcode *opcode) +{ + return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T + | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE + : FALSE; +} + +struct aarch64_name_value_pair +{ + const char * name; + aarch64_insn value; +}; + +extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; +extern const struct aarch64_name_value_pair aarch64_sys_regs []; +extern const struct aarch64_name_value_pair aarch64_pstatefields []; +extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; +extern const struct aarch64_name_value_pair aarch64_prfops [32]; + +typedef struct +{ + const char *template; + uint32_t value; + int has_xt; +} aarch64_sys_ins_reg; + +extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; +extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; +extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; +extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; + +/* Shift/extending operator kinds. + N.B. order is important; keep aarch64_operand_modifiers synced. */ +enum aarch64_modifier_kind +{ + AARCH64_MOD_NONE, + AARCH64_MOD_MSL, + AARCH64_MOD_ROR, + AARCH64_MOD_ASR, + AARCH64_MOD_LSR, + AARCH64_MOD_LSL, + AARCH64_MOD_UXTB, + AARCH64_MOD_UXTH, + AARCH64_MOD_UXTW, + AARCH64_MOD_UXTX, + AARCH64_MOD_SXTB, + AARCH64_MOD_SXTH, + AARCH64_MOD_SXTW, + AARCH64_MOD_SXTX, +}; + +bfd_boolean +aarch64_extend_operator_p (enum aarch64_modifier_kind); + +enum aarch64_modifier_kind +aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); +/* Condition. */ + +typedef struct +{ + /* A list of names with the first one as the disassembly preference; + terminated by NULL if fewer than 3. */ + const char *names[3]; + aarch64_insn value; +} aarch64_cond; + +extern const aarch64_cond aarch64_conds[16]; + +const aarch64_cond* get_cond_from_value (aarch64_insn value); +const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); + +/* Structure representing an operand. */ + +struct aarch64_opnd_info +{ + enum aarch64_opnd type; + aarch64_opnd_qualifier_t qualifier; + int idx; + + union + { + struct + { + unsigned regno; + } reg; + struct + { + unsigned regno : 5; + unsigned index : 4; + } reglane; + /* e.g. LVn. */ + struct + { + unsigned first_regno : 5; + unsigned num_regs : 3; + /* 1 if it is a list of reg element. */ + unsigned has_index : 1; + /* Lane index; valid only when has_index is 1. */ + unsigned index : 4; + } reglist; + /* e.g. immediate or pc relative address offset. */ + struct + { + int64_t value; + unsigned is_fp : 1; + } imm; + /* e.g. address in STR (register offset). */ + struct + { + unsigned base_regno; + struct + { + union + { + int imm; + unsigned regno; + }; + unsigned is_reg; + } offset; + unsigned pcrel : 1; /* PC-relative. */ + unsigned writeback : 1; + unsigned preind : 1; /* Pre-indexed. */ + unsigned postind : 1; /* Post-indexed. */ + } addr; + const aarch64_cond *cond; + /* The encoding of the system register. */ + aarch64_insn sysreg; + /* The encoding of the PSTATE field. */ + aarch64_insn pstatefield; + const aarch64_sys_ins_reg *sysins_op; + const struct aarch64_name_value_pair *barrier; + const struct aarch64_name_value_pair *prfop; + }; + + /* Operand shifter; in use when the operand is a register offset address, + add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ + struct + { + enum aarch64_modifier_kind kind; + int amount; + unsigned operator_present: 1; /* Only valid during encoding. */ + /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ + unsigned amount_present: 1; + } shifter; + + unsigned skip:1; /* Operand is not completed if there is a fixup needed + to be done on it. In some (but not all) of these + cases, we need to tell libopcodes to skip the + constraint checking and the encoding for this + operand, so that the libopcodes can pick up the + right opcode before the operand is fixed-up. This + flag should only be used during the + assembling/encoding. */ + unsigned present:1; /* Whether this operand is present in the assembly + line; not used during the disassembly. */ +}; + +typedef struct aarch64_opnd_info aarch64_opnd_info; + +/* Structure representing an instruction. + + It is used during both the assembling and disassembling. The assembler + fills an aarch64_inst after a successful parsing and then passes it to the + encoding routine to do the encoding. During the disassembling, the + disassembler calls the decoding routine to decode a binary instruction; on a + successful return, such a structure will be filled with information of the + instruction; then the disassembler uses the information to print out the + instruction. */ + +struct aarch64_inst +{ + /* The value of the binary instruction. */ + aarch64_insn value; + + /* Corresponding opcode entry. */ + const aarch64_opcode *opcode; + + /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ + const aarch64_cond *cond; + + /* Operands information. */ + aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; +}; + +typedef struct aarch64_inst aarch64_inst; + +/* Diagnosis related declaration and interface. */ + +/* Operand error kind enumerators. + + AARCH64_OPDE_RECOVERABLE + Less severe error found during the parsing, very possibly because that + GAS has picked up a wrong instruction template for the parsing. + + AARCH64_OPDE_SYNTAX_ERROR + General syntax error; it can be either a user error, or simply because + that GAS is trying a wrong instruction template. + + AARCH64_OPDE_FATAL_SYNTAX_ERROR + Definitely a user syntax error. + + AARCH64_OPDE_INVALID_VARIANT + No syntax error, but the operands are not a valid combination, e.g. + FMOV D0,S0 + + AARCH64_OPDE_OUT_OF_RANGE + Error about some immediate value out of a valid range. + + AARCH64_OPDE_UNALIGNED + Error about some immediate value not properly aligned (i.e. not being a + multiple times of a certain value). + + AARCH64_OPDE_REG_LIST + Error about the register list operand having unexpected number of + registers. + + AARCH64_OPDE_OTHER_ERROR + Error of the highest severity and used for any severe issue that does not + fall into any of the above categories. + + The enumerators are only interesting to GAS. They are declared here (in + libopcodes) because that some errors are detected (and then notified to GAS) + by libopcodes (rather than by GAS solely). + + The first three errors are only deteced by GAS while the + AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as + only libopcodes has the information about the valid variants of each + instruction. + + The enumerators have an increasing severity. This is helpful when there are + multiple instruction templates available for a given mnemonic name (e.g. + FMOV); this mechanism will help choose the most suitable template from which + the generated diagnostics can most closely describe the issues, if any. */ + +enum aarch64_operand_error_kind +{ + AARCH64_OPDE_NIL, + AARCH64_OPDE_RECOVERABLE, + AARCH64_OPDE_SYNTAX_ERROR, + AARCH64_OPDE_FATAL_SYNTAX_ERROR, + AARCH64_OPDE_INVALID_VARIANT, + AARCH64_OPDE_OUT_OF_RANGE, + AARCH64_OPDE_UNALIGNED, + AARCH64_OPDE_REG_LIST, + AARCH64_OPDE_OTHER_ERROR +}; + +/* N.B. GAS assumes that this structure work well with shallow copy. */ +struct aarch64_operand_error +{ + enum aarch64_operand_error_kind kind; + int index; + const char *error; + int data[3]; /* Some data for extra information. */ +}; + +typedef struct aarch64_operand_error aarch64_operand_error; + +/* Encoding entrypoint. */ + +extern int +aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, + aarch64_insn *, aarch64_opnd_qualifier_t *, + aarch64_operand_error *); + +extern const aarch64_opcode * +aarch64_replace_opcode (struct aarch64_inst *, + const aarch64_opcode *); + +/* Given the opcode enumerator OP, return the pointer to the corresponding + opcode entry. */ + +extern const aarch64_opcode * +aarch64_get_opcode (enum aarch64_op); + +/* Generate the string representation of an operand. */ +extern void +aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, + const aarch64_opnd_info *, int, int *, bfd_vma *); + +/* Miscellaneous interface. */ + +extern int +aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); + +extern aarch64_opnd_qualifier_t +aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, + const aarch64_opnd_qualifier_t, int); + +extern int +aarch64_num_of_operands (const aarch64_opcode *); + +extern int +aarch64_stack_pointer_p (const aarch64_opnd_info *); + +extern +int aarch64_zero_register_p (const aarch64_opnd_info *); + +/* Given an operand qualifier, return the expected data element size + of a qualified operand. */ +extern unsigned char +aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); + +extern enum aarch64_operand_class +aarch64_get_operand_class (enum aarch64_opnd); + +extern const char * +aarch64_get_operand_name (enum aarch64_opnd); + +extern const char * +aarch64_get_operand_desc (enum aarch64_opnd); + +#ifdef DEBUG_AARCH64 +extern int debug_dump; + +extern void +aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); + +#define DEBUG_TRACE(M, ...) \ + { \ + if (debug_dump) \ + aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ + } + +#define DEBUG_TRACE_IF(C, M, ...) \ + { \ + if (debug_dump && (C)) \ + aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ + } +#else /* !DEBUG_AARCH64 */ +#define DEBUG_TRACE(M, ...) ; +#define DEBUG_TRACE_IF(C, M, ...) ; +#endif /* DEBUG_AARCH64 */ + +#endif /* OPCODE_AARCH64_H */ diff --git a/include/opcode/arm.h b/include/opcode/arm.h index 86e3d67db..1ac38a06f 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -34,6 +34,7 @@ #define ARM_EXT_V6 0x00001000 /* ARM V6. */ #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ /* 0x00004000 Was ARM V6Z. */ +#define ARM_EXT_V8 0x00004000 /* is now ARMv8. */ #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ #define ARM_EXT_DIV 0x00010000 /* Integer division. */ /* The 'M' in Arm V7M stands for Microcontroller. @@ -77,6 +78,9 @@ #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ +#define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ +#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ +#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, @@ -126,6 +130,9 @@ #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) #define ARM_AEXT_V7EM \ (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) +#define ARM_AEXT_V8A \ + (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ + | ARM_EXT_VIRT | ARM_EXT_V8) /* Processors with specific extensions in the co-processor space. */ #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) @@ -143,6 +150,9 @@ #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) +#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) +#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) +#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) @@ -175,6 +185,10 @@ #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) #define FPU_ARCH_NEON_VFP_V4 \ ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) +#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) +#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) +#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ + ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) @@ -211,6 +225,7 @@ #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) +#define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) /* Some useful combinations: */ #define ARM_ARCH_NONE ARM_FEATURE (0, 0) @@ -233,6 +248,14 @@ #define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) /* Features that are present in v6M and v6S-M but not other v6 cores. */ #define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) +/* v8-a+fp. */ +#define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) +/* v8-a+simd (implies fp). */ +#define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ + FPU_ARCH_NEON_VFP_ARMV8) +/* v8-a+crypto (implies simd+fp). */ +#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ + FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) /* There are too many feature bits to fit in a single word, so use a structure. For simplicity we put all core features in one word and @@ -246,6 +269,9 @@ typedef struct #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) +#define ARM_CPU_IS_ANY(CPU) \ + ((CPU).core == ((arm_feature_set)ARM_ANY).core) + #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ do { \ (TARG).core = (F1).core | (F2).core; \ diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index 907320644..489ca550d 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -895,8 +895,8 @@ static const struct pa_opcode pa_opcodes[] = { "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, { "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0}, { "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT}, { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT}, { "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, @@ -921,8 +921,8 @@ static const struct pa_opcode pa_opcodes[] = { "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, { "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0}, { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h index 4285377f7..433c5058a 100644 --- a/include/opcode/ia64.h +++ b/include/opcode/ia64.h @@ -91,6 +91,7 @@ enum ia64_opnd IA64_OPND_R2, /* second register # */ IA64_OPND_R3, /* third register # */ IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ /* memory operands: */ IA64_OPND_MR3, /* memory at addr of third register # */ @@ -105,6 +106,7 @@ enum ia64_opnd IA64_OPND_PKR_R3, /* pkr[reg] */ IA64_OPND_PMC_R3, /* pmc[reg] */ IA64_OPND_PMD_R3, /* pmd[reg] */ + IA64_OPND_DAHR_R3, /* dahr[reg] */ IA64_OPND_RR_R3, /* rr[reg] */ /* immediate operands: */ @@ -134,7 +136,9 @@ enum ia64_opnd IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ + IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ + IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ @@ -155,6 +159,9 @@ enum ia64_opnd IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ + IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ + IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ + IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ }; @@ -191,6 +198,7 @@ enum ia64_resource_specifier IA64_RS_CR_IRR, IA64_RS_CR_LRR, IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ + IA64_RS_DAHR, IA64_RS_DBR, IA64_RS_FR, IA64_RS_FRb, @@ -212,6 +220,7 @@ enum ia64_resource_specifier IA64_RS_PSR, /* PSR bits */ IA64_RS_RSE, /* implementation-specific RSE resources */ IA64_RS_AR_FPSR, + }; enum ia64_rse_resource diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 857fc7173..5691ac535 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -25,6 +25,8 @@ #ifndef _MIPS_H_ #define _MIPS_H_ +#include "bfd.h" + /* These are bit masks and shift counts to use to access the various fields of an instruction. To retrieve the X field of an instruction, use the expression @@ -353,6 +355,9 @@ struct mips_opcode /* A collection of bits describing the instruction sets of which this instruction or macro is a member. */ unsigned long membership; + /* A collection of bits describing the instruction sets of which this + instruction or macro is not a member. */ + unsigned long exclusions; }; /* These are the characters which may appear in the args field of an @@ -829,46 +834,102 @@ static const unsigned int mips_isa_table[] = #define CPU_OCTEON2 6502 #define CPU_XLR 887682 /* decimal 'XLR' */ +/* Return true if the given CPU is included in INSN_* mask MASK. */ + +static inline bfd_boolean +cpu_is_member (int cpu, unsigned int mask) +{ + switch (cpu) + { + case CPU_R4650: + case CPU_RM7000: + case CPU_RM9000: + return (mask & INSN_4650) != 0; + + case CPU_R4010: + return (mask & INSN_4010) != 0; + + case CPU_VR4100: + return (mask & INSN_4100) != 0; + + case CPU_R3900: + return (mask & INSN_3900) != 0; + + case CPU_R10000: + case CPU_R12000: + case CPU_R14000: + case CPU_R16000: + return (mask & INSN_10000) != 0; + + case CPU_SB1: + return (mask & INSN_SB1) != 0; + + case CPU_R4111: + return (mask & INSN_4111) != 0; + + case CPU_VR4120: + return (mask & INSN_4120) != 0; + + case CPU_VR5400: + return (mask & INSN_5400) != 0; + + case CPU_VR5500: + return (mask & INSN_5500) != 0; + + case CPU_LOONGSON_2E: + return (mask & INSN_LOONGSON_2E) != 0; + + case CPU_LOONGSON_2F: + return (mask & INSN_LOONGSON_2F) != 0; + + case CPU_LOONGSON_3A: + return (mask & INSN_LOONGSON_3A) != 0; + + case CPU_OCTEON: + return (mask & INSN_OCTEON) != 0; + + case CPU_OCTEONP: + return (mask & INSN_OCTEONP) != 0; + + case CPU_OCTEON2: + return (mask & INSN_OCTEON2) != 0; + + case CPU_XLR: + return (mask & INSN_XLR) != 0; + + default: + return FALSE; + } +} + /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to - test, or zero if no CPU specific ISA test is desired. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu) \ - (((isa & INSN_ISA_MASK) != 0 \ - && ((insn)->membership & INSN_ISA_MASK) != 0 \ - && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \ - (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \ - || ((isa & ~INSN_ISA_MASK) \ - & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \ - || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ - || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ - || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \ - || cpu == CPU_R16000) \ - && ((insn)->membership & INSN_10000) != 0) \ - || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ - || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ - || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ - || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ - || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ - || (cpu == CPU_LOONGSON_2E \ - && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ - || (cpu == CPU_LOONGSON_2F \ - && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ - || (cpu == CPU_LOONGSON_3A \ - && ((insn)->membership & INSN_LOONGSON_3A) != 0) \ - || (cpu == CPU_OCTEON \ - && ((insn)->membership & INSN_OCTEON) != 0) \ - || (cpu == CPU_OCTEONP \ - && ((insn)->membership & INSN_OCTEONP) != 0) \ - || (cpu == CPU_OCTEON2 \ - && ((insn)->membership & INSN_OCTEON2) != 0) \ - || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ - || 0) /* Please keep this term for easier source merging. */ + test, or zero if no CPU specific ISA test is desired. Return true + if instruction INSN is available to the given ISA and CPU. */ + +static inline bfd_boolean +opcode_is_member (const struct mips_opcode *insn, int isa, int cpu) +{ + if (!cpu_is_member (cpu, insn->exclusions)) + { + /* Test for ISA level compatibility. */ + if ((isa & INSN_ISA_MASK) != 0 + && (insn->membership & INSN_ISA_MASK) != 0 + && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] + >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) + return TRUE; + + /* Test for ASE compatibility. */ + if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0) + return TRUE; + + /* Test for processor-specific extensions. */ + if (cpu_is_member (cpu, insn->membership)) + return TRUE; + } + return FALSE; +} /* This is a list of macro expanded instructions. diff --git a/include/opcode/moxie.h b/include/opcode/moxie.h index e2bc374f0..dae40c8e8 100644 --- a/include/opcode/moxie.h +++ b/include/opcode/moxie.h @@ -60,6 +60,8 @@ #define MOXIE_F3_NARG 0x300 #define MOXIE_F3_PCREL 0x301 +#define MOXIE_BAD 0x400 + typedef struct moxie_opc_info_t { short opcode; @@ -67,6 +69,6 @@ typedef struct moxie_opc_info_t const char * name; } moxie_opc_info_t; -extern const moxie_opc_info_t moxie_form1_opc_info[64]; +extern const moxie_opc_info_t moxie_form1_opc_info[128]; extern const moxie_opc_info_t moxie_form2_opc_info[4]; extern const moxie_opc_info_t moxie_form3_opc_info[16]; diff --git a/include/opcode/s390.h b/include/opcode/s390.h index ed70830c1..531011e0f 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -40,6 +40,7 @@ enum s390_opcode_cpu_val S390_OPCODE_Z9_EC, S390_OPCODE_Z10, S390_OPCODE_Z196, + S390_OPCODE_ZEC12, S390_OPCODE_MAXCPU }; diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index b1c5e42ad..892776900 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -234,6 +234,7 @@ typedef struct sparc_opcode #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ #define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */ #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ +#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z)) #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ diff --git a/include/plugin-api.h b/include/plugin-api.h index 3220142dd..af60419a9 100644 --- a/include/plugin-api.h +++ b/include/plugin-api.h @@ -318,6 +318,33 @@ typedef enum ld_plugin_status (*ld_plugin_allow_section_ordering) (void); +/* The linker's interface for specifying that a subset of sections is + to be mapped to a unique segment. If the plugin wants to call + unique_segment_for_sections, it must call this function from a + claim_file_handler or when it is first loaded. */ + +typedef +enum ld_plugin_status +(*ld_plugin_allow_unique_segment_for_sections) (void); + +/* The linker's interface for specifying that a specific set of sections + must be mapped to a unique segment. ELF segments do not have names + and the NAME is used as the name of the newly created output section + that is then placed in the unique PT_LOAD segment. FLAGS is used to + specify if any additional segment flags need to be set. For instance, + a specific segment flag can be set to identify this segment. Unsetting + segment flags that would be set by default is not possible. The + parameter SEGMENT_ALIGNMENT when non-zero will override the default. */ + +typedef +enum ld_plugin_status +(*ld_plugin_unique_segment_for_sections) ( + const char* segment_name, + uint64_t segment_flags, + uint64_t segment_alignment, + const struct ld_plugin_section * section_list, + unsigned int num_sections); + enum ld_plugin_level { LDPL_INFO, @@ -355,7 +382,9 @@ enum ld_plugin_tag LDPT_GET_INPUT_SECTION_CONTENTS, LDPT_UPDATE_SECTION_ORDER, LDPT_ALLOW_SECTION_ORDERING, - LDPT_GET_SYMBOLS_V2 + LDPT_GET_SYMBOLS_V2, + LDPT_ALLOW_UNIQUE_SEGMENT_FOR_SECTIONS, + LDPT_UNIQUE_SEGMENT_FOR_SECTIONS }; /* The plugin transfer vector. */ @@ -385,6 +414,8 @@ struct ld_plugin_tv ld_plugin_get_input_section_contents tv_get_input_section_contents; ld_plugin_update_section_order tv_update_section_order; ld_plugin_allow_section_ordering tv_allow_section_ordering; + ld_plugin_allow_unique_segment_for_sections tv_allow_unique_segment_for_sections; + ld_plugin_unique_segment_for_sections tv_unique_segment_for_sections; } tv_u; }; |