diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/bfdlink.h | 8 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 15 | ||||
| -rw-r--r-- | include/opcode/h8300.h | 16 | ||||
| -rw-r--r-- | include/opcode/i386.h | 24 |
5 files changed, 56 insertions, 11 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 5e9ac7a10..f061efa77 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2003-06-25 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Correct spelling of "relocatable". + 2003-06-22 Zack Weinberg <zack@codesourcery.com> * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to diff --git a/include/bfdlink.h b/include/bfdlink.h index 4636025b8..10746ee98 100644 --- a/include/bfdlink.h +++ b/include/bfdlink.h @@ -1,5 +1,5 @@ /* bfdlink.h -- header file for BFD link routines - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002 + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003 Free Software Foundation, Inc. Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support. @@ -204,7 +204,7 @@ struct bfd_sym_chain struct bfd_link_info { /* TRUE if BFD should generate a relocatable object file. */ - unsigned int relocateable: 1; + unsigned int relocatable: 1; /* TRUE if BFD should generate relocation information in the final executable. */ @@ -428,7 +428,7 @@ struct bfd_link_callbacks /* A function which is called to add a symbol to a set. ENTRY is the link hash table entry for the set itself (e.g., __CTOR_LIST__). RELOC is the relocation to use for an entry in - the set when generating a relocateable file, and is also used to + the set when generating a relocatable file, and is also used to get the size of the entry when generating an executable file. ABFD, SEC and VALUE identify the value to add to the set. */ bfd_boolean (*add_to_set) @@ -439,7 +439,7 @@ struct bfd_link_callbacks destructor is found. This is only called by some object file formats. CONSTRUCTOR is TRUE for a constructor, FALSE for a destructor. This will use BFD_RELOC_CTOR when generating a - relocateable file. NAME is the name of the symbol found. ABFD, + relocatable file. NAME is the name of the symbol found. ABFD, SECTION and VALUE are the value of the symbol. */ bfd_boolean (*constructor) PARAMS ((struct bfd_link_info *, bfd_boolean constructor, diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 9785f4ec4..e100c1193 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,18 @@ +2003-06-25 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. + (IMM8U, IMM8U_NS): Define. + (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. + +2003-06-25 Richard Sandiford <rsandifo@redhat.com> + + * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and + mov.l ERs,@(dd:32,ERd) entries. + +2003-06-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Support Intel Precott New Instructions. + 2003-06-10 Gary Hade <garyhade@us.ibm.com> * ppc.h (PPC_OPERAND_DQ): Define. diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h index 4318dccbc..bfac3f8c7 100644 --- a/include/opcode/h8300.h +++ b/include/opcode/h8300.h @@ -117,6 +117,7 @@ enum h8_flags { B31 = 0x40000000, /* Bit 3 must be high. */ E = 0x80000000, /* End of nibble sequence. */ + /* Immediates smaller than 8 bits are always unsigned. */ IMM3 = IMM | L_3, IMM4 = IMM | L_4, IMM5 = IMM | L_5, @@ -124,15 +125,14 @@ enum h8_flags { IMM2 = IMM | L_2, IMM8 = IMM | SRC | L_8, + IMM8U = IMM | SRC | L_8U, IMM16 = IMM | SRC | L_16, IMM16U = IMM | SRC | L_16U, IMM32 = IMM | SRC | L_32, IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, - IMM2_NS = IMM2 | NO_SYMBOLS, IMM4_NS = IMM4 | NO_SYMBOLS, - IMM8_NS = IMM8 | NO_SYMBOLS, - IMM16_NS = IMM16 | NO_SYMBOLS, + IMM8U_NS = IMM8U | NO_SYMBOLS, IMM16U_NS = IMM16U | NO_SYMBOLS, RD8 = DST | L_8 | REG, @@ -1475,7 +1475,7 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, - MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8_NS), + MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, @@ -1501,7 +1501,7 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, - MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8_NS), + MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, @@ -1518,7 +1518,8 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, @@ -1535,7 +1536,8 @@ struct h8_opcode h8_opcodes[] = {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, - {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, diff --git a/include/opcode/i386.h b/include/opcode/i386.h index 71c204c81..cb3a99a4e 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -1302,6 +1302,30 @@ static const template i386_optab[] = { {"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +/* Prescott New Instructions. */ + +{"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +/* Intel Syntax */ +{"fisttpd", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ +{"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} }, +{"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +/* Need to ensure only "mwait %eax,%ecx" is accepted. */ +{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} }, + /* AMD 3DNow! instructions. */ {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, |