diff options
Diffstat (limited to 'libgloss/bfin/include/sys')
| -rw-r--r-- | libgloss/bfin/include/sys/_adi_platform.h | 214 | ||||
| -rw-r--r-- | libgloss/bfin/include/sys/anomaly_macros_rtl.h | 756 | ||||
| -rw-r--r-- | libgloss/bfin/include/sys/excause.h | 93 | ||||
| -rw-r--r-- | libgloss/bfin/include/sys/exception.h | 261 | ||||
| -rw-r--r-- | libgloss/bfin/include/sys/mc_typedef.h | 39 | ||||
| -rw-r--r-- | libgloss/bfin/include/sys/platform.h | 19 | ||||
| -rw-r--r-- | libgloss/bfin/include/sys/pll.h | 84 |
7 files changed, 0 insertions, 1466 deletions
diff --git a/libgloss/bfin/include/sys/_adi_platform.h b/libgloss/bfin/include/sys/_adi_platform.h deleted file mode 100644 index 95259969b..000000000 --- a/libgloss/bfin/include/sys/_adi_platform.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/* -** Include appropriate header file for platform. -** Copyright (C) 2004-2009 Analog Devices Inc. All Rights Reserved. -*/ - -#ifndef __ADI_PLATFORM_H -#define __ADI_PLATFORM_H - -#ifndef __ASSEMBLER__ - -#if defined (__ADSPBF531__) -#include <cdefBF531.h> -#elif defined (__ADSPBF532__) -#include <cdefBF532.h> -#elif defined (__ADSPBF533__) -#include <cdefBF533.h> -#elif defined (__ADSPBF534__) -#include <cdefBF534.h> -#elif defined (__ADSPBF535__) -#include <cdefBF535.h> -#elif defined (__ADSPBF536__) -#include <cdefBF536.h> -#elif defined (__ADSPBF537__) -#include <cdefBF537.h> -#elif defined (__ADSPBF538__) -#include <cdefBF538.h> -#elif defined (__ADSPBF539__) -#include <cdefBF539.h> -#elif defined (__ADSPBF561__) -#include <cdefBF561.h> -#elif defined (__AD6531__) -#include <cdefAD6531.h> -#elif defined (__AD6532__) -#include <cdefAD6532.h> -#elif defined (__AD6723__) -#include <cdefAD6723.h> -#elif defined (__AD6900__) -#include <cdefAD6900.h> -#elif defined (__AD6901__) -#include <cdefAD6901.h> -#elif defined (__AD6902__) -#include <cdefAD6902.h> -#elif defined (__AD6903__) -#include <cdefAD6903.h> -#elif defined (__AD6904__) -#include <cdefAD6904.h> -#elif defined (__AD6905__) -#include <cdefAD6905.h> -#elif defined (__MT6906__) -#include <cdefMT6906.h> -#elif defined (__ADSPBF504__) -#include <cdefBF504.h> -#elif defined (__ADSPBF504F__) -#include <cdefBF504F.h> -#elif defined (__ADSPBF506__) || defined (__ADSPBF506F__) -#include <cdefBF506F.h> -#elif defined (__ADSPBF512__) -#include <cdefBF512.h> -#elif defined (__ADSPBF514__) -#include <cdefBF514.h> -#elif defined (__ADSPBF516__) -#include <cdefBF516.h> -#elif defined (__ADSPBF518__) -#include <cdefBF518.h> -#elif defined (__ADSPBF522__) -#include <cdefBF522.h> -#elif defined (__ADSPBF523__) -#include <cdefBF523.h> -#elif defined (__ADSPBF524__) -#include <cdefBF524.h> -#elif defined (__ADSPBF525__) -#include <cdefBF525.h> -#elif defined (__ADSPBF526__) -#include <cdefBF526.h> -#elif defined (__ADSPBF527__) -#include <cdefBF527.h> -#elif defined (__ADSPBF542__) -#include <cdefBF542.h> -#elif defined (__ADSPBF542M__) -#include <cdefBF542M.h> -#elif defined (__ADSPBF544__) -#include <cdefBF544.h> -#elif defined (__ADSPBF544M__) -#include <cdefBF544M.h> -#elif defined (__ADSPBF547__) -#include <cdefBF547.h> -#elif defined (__ADSPBF547M__) -#include <cdefBF547M.h> -#elif defined (__ADSPBF548__) -#include <cdefBF548.h> -#elif defined (__ADSPBF548M__) -#include <cdefBF548M.h> -#elif defined (__ADSPBF549__) -#include <cdefBF549.h> -#elif defined (__ADSPBF549M__) -#include <cdefBF549M.h> -#elif defined (__ADSPBF592A__) -#include <cdefBF592-A.h> -#else -#error Processor Type Not Supported -#endif - - -#else - -#if defined (__ADSPBF531__) -#include <defBF531.h> -#elif defined (__ADSPBF532__) -#include <defBF532.h> -#elif defined (__ADSPBF533__) -#include <defBF533.h> -#elif defined (__ADSPBF534__) -#include <defBF534.h> -#elif defined (__ADSPBF535__) -#include <defBF535.h> -#elif defined (__ADSPBF536__) -#include <defBF536.h> -#elif defined (__ADSPBF537__) -#include <defBF537.h> -#elif defined (__ADSPBF538__) -#include <defBF538.h> -#elif defined (__ADSPBF539__) -#include <defBF539.h> -#elif defined (__ADSPBF561__) -#include <defBF561.h> -#elif defined (__AD6531__) -#include <defAD6531.h> -#elif defined (__AD6532__) -#include <defAD6532.h> -#elif defined (__AD6723__) -#include <defAD6723.h> -#elif defined (__AD6900__) -#include <defAD6900.h> -#elif defined (__AD6901__) -#include <defAD6901.h> -#elif defined (__AD6902__) -#include <defAD6902.h> -#elif defined (__AD6903__) -#include <defAD6903.h> -#elif defined (__AD6904__) -#include <defAD6904.h> -#elif defined (__AD6905__) -#include <defAD6905.h> -#elif defined (__MT6906__) -#include <defMT6906.h> -#elif defined (__ADSPBF504__) -#include <defBF504.h> -#elif defined (__ADSPBF504F__) -#include <defBF504F.h> -#elif defined (__ADSPBF506__) || defined (__ADSPBF506F__) -#include <defBF506F.h> -#elif defined (__ADSPBF512__) -#include <defBF512.h> -#elif defined (__ADSPBF514__) -#include <defBF514.h> -#elif defined (__ADSPBF516__) -#include <defBF516.h> -#elif defined (__ADSPBF518__) -#include <defBF518.h> -#elif defined (__ADSPBF522__) -#include <defBF522.h> -#elif defined (__ADSPBF523__) -#include <defBF523.h> -#elif defined (__ADSPBF524__) -#include <defBF524.h> -#elif defined (__ADSPBF525__) -#include <defBF525.h> -#elif defined (__ADSPBF526__) -#include <defBF526.h> -#elif defined (__ADSPBF527__) -#include <defBF527.h> -#elif defined (__ADSPBF542__) -#include <defBF542.h> -#elif defined (__ADSPBF542M__) -#include <defBF542M.h> -#elif defined (__ADSPBF544__) -#include <defBF544.h> -#elif defined (__ADSPBF544M__) -#include <defBF544M.h> -#elif defined (__ADSPBF547__) -#include <defBF547.h> -#elif defined (__ADSPBF547M__) -#include <defBF547M.h> -#elif defined (__ADSPBF548__) -#include <defBF548.h> -#elif defined (__ADSPBF548M__) -#include <defBF548M.h> -#elif defined (__ADSPBF549__) -#include <defBF549.h> -#elif defined (__ADSPBF549M__) -#include <defBF549M.h> -#elif defined (__ADSPBF592A__) -#include <defBF592-A.h> - -#else -#error Processor Type Not Supported -#endif - -#endif /* __ASSEMBLER__ */ - -#endif /* __INC_BLACKFIN__ */ - diff --git a/libgloss/bfin/include/sys/anomaly_macros_rtl.h b/libgloss/bfin/include/sys/anomaly_macros_rtl.h deleted file mode 100644 index f6c667afd..000000000 --- a/libgloss/bfin/include/sys/anomaly_macros_rtl.h +++ /dev/null @@ -1,756 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/************************************************************************ - * - * anomaly_macros_rtl.h : $Revision$ - * - * (c) Copyright 2005-2009 Analog Devices, Inc. All rights reserved. - * - * This file defines macros used within the run-time libraries to enable - * certain anomaly workarounds for the appropriate chips and silicon - * revisions. Certain macros are defined for silicon-revision none - this - * is to ensure behaviour is unchanged from libraries supplied with - * earlier tools versions, where a small number of anomaly workarounds - * were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__ - * is defined in this case. - * - * This file defines macros for a subset of all anomalies that may impact - * the run-time libraries. - * - ************************************************************************/ - - -#ifdef _MISRA_RULES -#pragma diag(push) -#pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour") -#pragma diag(suppress:misra_rule_19_4:"The definition of WA_05000204_CHECK_AVOID_FOR_REV cannot be parenthasised as it would fail when used in assembly library code.") -#endif /* _MISRA_RULES */ - -#if !defined(__SILICON_REVISION__) -#define __FORCE_LEGACY_WORKAROUNDS__ -#endif - - -/* 05-00-0096 - PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC -** -** ADSP-BF531/2/3 - revs 0.0-0.1, -** ADSP-BF561 - revs 0.0-0.1 (not supported in VDSP++ 4.0) -** -*/ -#define WA_05000096 \ - ((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || \ - defined(__ADSPBF561__)) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x1)) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - - -/* 05-00-0109 - Reserved bits in SYSCFG register not set at power on -** -** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3) -** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3. 0.0, 0.1 not supported in VDSP++ 4.0) -** -** Changes to start code. -*/ -#define WA_05000109 \ - ((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || \ - defined(__ADSPBF561__)) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - - -/* 05-00-0123 - DTEST_COMMAND initiated memory access may be incorrect if -** data cache or DMA is active. -** -** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3) -** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0) -*/ -#define WA_05000123 \ - ((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || \ - defined(__ADSPBF561__)) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - - -/* 05-00-0125 - Erroneous exception when enabling cache -** -** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3) -** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0) -** -*/ -#define WA_05000125 \ - ((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || \ - defined(__ADSPBF561__)) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - - -/* 05-00-0127 - Signbits instruction not functional under certain conditions -** -** ADSP-BF561 - from rev 0.0 (not yet fixed) -** -** The SIGNBITS instruction requires a NOP before it if one of its operands -** is defined in the preceding instruction. -** -*/ -#define WA_05000127 \ - (defined(__SILICON_REVISION__) && defined(__ADSPBF561__)) - - -/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset -** -** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3) -** -** Changes to start code. -** -*/ -#define WA_05000137 \ - ((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - - -/* 05-00-0158 - "Boot fails when data cache enabled: Data from a Data Cache -** fill can be corrupted after or during instruction DMA if certain core -** stalls exist" -** -** Impacted: -** BF533/3/1 : 0.0-0.4 (fixed 0.5) -** -** The workaround we have only works for si-revisions >= 0.3. No workaround for -** ealier revisions. -*/ -#define WA_05000158 \ - ((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || \ - (__SILICON_REVISION__ >= 0x3 && \ - __SILICON_REVISION__ < 0x5))) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - - -/* 05-00-0162 - DMEM_CONTROL<12> is not set on Reset -** -** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3) -** -** Changes to start code. -** -*/ -#define WA_05000162 \ - (defined(__ADSPBF561__) && \ - ((defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \ - defined(__FORCE_LEGACY_WORKAROUNDS__))) - -/* 05-00-0198 - System MMR accesses may fail when stalled by preceding memory -** read. -** -** Impacted: -** ADSP-BF531 - rev 0.1-0.4 (fixed 0.5) -** ADSP-BF532 - rev 0.1-0.4 (fixed 0.5) -** ADSP-BF533 - rev 0.1-0.4 (fixed 0.5) -** ADSP-BF534 - rev 0.0 (fixed 0.1) -** ADSP-BF536 - rev 0.0 (fixed 0.1) -** ADSP-BF537 - rev 0.0 (fixed 0.1) -** ADSP-BF561 - rev 0.2-0.3 (fixed 0.4) -** -*/ -#define WA_05000198 \ - (((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff))) || \ - ((defined(__ADSPBF534__) || \ - defined(__ADSPBF536__) || \ - defined(__ADSPBF537__) || \ - defined(__ADSPBF539__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff))) || \ - (defined(__ADSPBF561__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)))) - - -/* 05-00-0199 - Current DMA Address Shows Wrong Value During Carry Fix -** -** Impacted: -** ADSP-BF53[123] - rev 0.0-0.3 (fixed 0.4) -** ADSP-BF53[89] - rev 0.0-0.3 (fixed 0.4) -** ADSP-BF561 - rev 0.0-0.3 (fixed 0.4) -** -** Use by System Services/Device Drivers. -*/ -#define WA_05000199 \ - ((defined(__ADSPBF533_FAMILY__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \ - (defined(__ADSPBF538_FAMILY__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \ - (defined(__ADSPBF561__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)))) - - -/* 05-00-0204 - "Incorrect data read with write-through cache and -** allocate cache lines on reads only mode. -** -** This problem is cache related with high speed clocks. It apparently does -** not impact BF531 and BF532 because they cannot run at high enough clock -** to cause the anomaly. We build libs for BF532 though so that means we will -** need to do the workaround for BF532 and BF531 also. -** -** Also the 0.3 to 0.4 revision is not an inflexion for libs BF532 and BF561. -** This means a RT check may be required to avoid doing the WA for 0.4. -** -** Impacted: -** BF533 - 0.0-0.3 (fixed 0.4) -** BF534 - 0.0 (fixed 0.1) -** BF536 - 0.0 (fixed 0.1) -** BF537 - 0.0 (fixed 0.1) -** BF538 - 0.0 (fixed 0.1) -** BF539 - 0.0 (fixed 0.1) -** BF561 - 0.0-0.3 (fixed 0.4) -*/ -#if defined(__ADI_LIB_BUILD__) -# define __BUILDBF53123 1 /* building one single library for BF531/2/3 */ -#else -# define __BUILDBF53123 0 -#endif - -#define WA_05000204 \ - ((((__BUILDBF53123==1 && \ - (defined(__ADSPBF531__) || defined(__ADSPBF532__))) || \ - (defined(__ADSPBF533__) || defined(__ADSPBF561__))) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x3))) || \ - ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \ - defined(__ADSPBF537__) || defined(__ADSPBF538__) || \ - defined(__ADSPBF539__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0)))) - -#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || defined(__ADSPBF561__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x3))) -/* check at RT for 0.4 revs when doing 204 workaround */ -# define WA_05000204_CHECK_AVOID_FOR_REV <=3 -#elif ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \ - defined(__ADSPBF537__) || defined(__ADSPBF538__) || \ - defined(__ADSPBF539__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0))) -/* check at RT for 0.4 revs when doing 204 workaround */ -# define WA_05000204_CHECK_AVOID_FOR_REV <1 -#else -/* do not check at RT for 0.4 revs when doing 204 workaround */ -#endif - - -/* 05-00-0209 - Speed Path in Computational Unit Affects Certain Instructions -** -** ADSP-BF531/2/3 - revs 0.0 - 0.3 (fixed in 0.4) -** ADSP-BF534/6/7 - rev 0.0 (fixed in 0.1) -** ADSP-BF538/9 - rev 0.0 (fixed in 0.1) -** ADSP-BF561 - revs 0.0 - 0.3 (fixed in 0.4) -** -** SIGNBITS, EXTRACT, DEPOSIT, EXPADJ require a NOP before them if -** one of their operands is defined in the preceding instruction. -*/ -#define WA_05000209 \ - (defined(__SILICON_REVISION__) && \ - (((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \ - ((defined(__ADSPBF534__) || \ - defined(__ADSPBF536__) || \ - defined(__ADSPBF537__) || \ - defined(__ADSPBF538__) || \ - defined(__ADSPBF539__)) && \ - (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \ - ((defined(__ADSPBF561__)) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)))) - - -/* 05-00-0212 - PORTx_FER, PORT_MUX Registers Do Not accept "writes" correctly -** -** Impacted: -** ADSP-BF53[467] - rev 0.0 (fixed 0.1) -** -** Use by System Services/Device Drivers. -*/ -#define WA_05000212 \ - (defined(__ADSPBF537_FAMILY__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff))) - - -/* 050000244 - "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control -** Causes Failures" -** -** When instruction cache is enabled, a CSYNC/SSYNC/IDLE around a -** change of control (including asynchronous exceptions/interrupts) -** can cause unpredictable results. -** -** This macro is used by System Services/Device Drivers. -** -** Impacted: -** -** BF531/2/3 - 0.0-0.4 (fixed 0.5) -** BF534/6/7 - 0.0-0.2 (fixed 0.3) -** BF534/8/9 - 0.0-0.1 (fixed 0.2) -** BF561 - 0.0-0.3 (fixed 0.5) -*/ - -#define WA_05000244 \ - (defined(__SILICON_REVISION__) && \ - ((defined(__ADSPBF533_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF537_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x2 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF538_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF561_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)))) - - -/* 050000245 - "False Hardware Error from an Access in the Shadow of a -** Conditional Branch" -** -** If a load accesses reserved or illegal memory on the opposite control -** flow of a conditional jump to the taken path, a false hardware error -** will occur. -** -** This macro is used by System Services/Device Drivers. -** -** This is for all Blackfin LP parts. -*/ - -#define WA_05000245 \ - (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) - - -/* 050000248 - "TESTSET Operation Forces Stall on the Other Core " -** -** Use by System Services/Device Drivers. -** -** Succeed any testset to L2 with a write to L2 to avoid the other core -** stalling. This must be atomic, as an interrupt between the two would -** cause the lockout to occur until the interrupt is fully serviced. -** -** This macro is used by System Services/Device Drivers. -** -** Impacted: -** -** BF561 - 0.0-0.3 (fixed 0.5) -** -*/ - -#define WA_05000248 \ - (defined (__SILICON_REVISION__) && defined(__ADSPBF561_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) - - -/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of - * the ICPLB Data registers differ" - * - * When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may - * not update properly. For example, for a particular cache line, - * the cache tag may be valid while the contents of that cache line - * are not present in the cache. - * - * Impacted: - * - * BF531/2/3 - 0.0-0.4 (fixed 0.5) - * BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3) - * BF561 - 0.0-0.4 (fixed 0.5) - * BF566 - 0.0-0.1 (fixed 0.2) - * BF535/AD6532/AD6900 - all revs - */ -#define WA_05000258 \ - (((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x4 || \ - __SILICON_REVISION__ == 0xffff))) || \ - ((defined(__ADSPBF534__) || \ - defined(__ADSPBF536__) || \ - defined(__ADSPBF537__) || \ - defined(__ADSPBF538__) || \ - defined(__ADSPBF539__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x2 || \ - __SILICON_REVISION__ == 0xffff))) || \ - (defined(__ADSPBF561__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x4 || \ - __SILICON_REVISION__ == 0xffff))) || \ - (defined(__ADSPBF566__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x1 || \ - __SILICON_REVISION__ == 0xffff))) || \ - (!defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))) - - -/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted". - * The DCPLB_FAULT_ADDR MMR may contain the fault address of a - * aborted memory access which generated both a protection exception - * and a stall. - * - * We work around this by initially ignoring a DCPLB miss exception - * on the assumption that the faulting address might be invalid. - * We return without servicing. The exception will be raised - * again when the faulting instruction is re-executed. The fault - * address is correct this time round so the miss exception can - * be serviced as normal. The only complication is we have to - * ensure that we are about to service the same miss rather than - * a miss raised within a higher-priority interrupt handler, where - * the fault address could again be invalid. We therefore record - * the last seen RETX and only service an exception when RETX and - * the last seen RETX are equal. - * - * This problem impacts: - * BF531/2/3 - rev 0.0-0.4 (fixed 0.5) - * BF534/6/7/8/9 - rev 0.0-0.2 (fixed 0.3) - * BF561 - rev 0.0-0.4 (fixed 0.5) - * - */ - -#define WA_05000261 \ - (((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x4 || \ - __SILICON_REVISION__ == 0xffff))) || \ - ((defined(__ADSPBF534__) || \ - defined(__ADSPBF536__) || \ - defined(__ADSPBF537__) || \ - defined(__ADSPBF538__) || \ - defined(__ADSPBF539__)) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x2 || \ - __SILICON_REVISION__ == 0xffff))) || \ - (defined(__ADSPBF561__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x4 || \ - __SILICON_REVISION__ == 0xffff)))) - -/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers". - * When the SPI slave boot completes, the final DMA IRQ is cleared - * but the DMA5_CONFIG and SPI_CTL registers are not reset to their - * default states. - * - * We work around this by resetting the registers to their default - * values at the beginning of the CRT. The only issue would be when - * users boot from flash and make use of the DMA or serial port. - * In this case, users would need to modify the CRT. - * - * This problem impacts all revisions of ADSP-BF531/2/3/8/9 - */ - -#define WA_05000229 \ - (defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \ - (defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || defined(__ADSPBF538__) || \ - defined(__ADSPBF539__))) - -/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a - * particular stage". - * - * Where an interrupt occurs killing a stalled system MMR write, and the ISR - * executes an SSYNC, execution execution may stall indefinitely". - * - * The workaround is to execute a mispredicted jump over a dummy MMR read, - * thus killing the read. Also to avoid a system MMR write in two slots - * after a not predicted conditional jump. - * - * This problem impacts: - * BF531/2/3 - < 0.6 - * BF534/6/7 - < 0.3 - * BF538/9 - < 0.4 - * BF561/6 - < 0.5 - * - * Since this impacts 538/9 0.3 but not 534 0.3 (the libraries that they use) - * we have to enable this workaround for the 534 0.3 libraries (see bottom - * two lines). - */ - -#define WA_05000283 \ - (defined (__SILICON_REVISION__) && \ - (((defined(__ADSPBF531__) || \ - defined(__ADSPBF532__) || \ - defined(__ADSPBF533__)) && \ - (__SILICON_REVISION__ == 0xffff || \ - __SILICON_REVISION__ < 0x6)) || \ - ((defined(__ADSPBF534__) || \ - defined(__ADSPBF536__) || \ - defined(__ADSPBF537__)) && \ - (__SILICON_REVISION__ == 0xffff || \ - __SILICON_REVISION__ < 0x3)) || \ - ((defined(__ADSPBF538__) || \ - defined(__ADSPBF539__)) && \ - (__SILICON_REVISION__ == 0xffff || \ - __SILICON_REVISION__ < 0x4)) || \ - (defined(__ADSPBF561__)) || \ - (defined(__ADSPBF534__) && __SILICON_REVISION__ == 0x3 && \ - defined(__ADI_LIB_BUILD__)))) - - -/* 05-00-0311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences -** -** Impacted: -** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6) -** -** Use by System Services/Device Drivers. -*/ -#define WA_05000311 \ - (defined(__ADSPBF533_FAMILY__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff))) - - -/* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers - -** Are Interrupted -** -** Impacted: -** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6) -** ADSP-BF53[467] - all supported revisions -** ADSP-BF53[89] - 0.0-0.4 (fixed in 0.5) -** ADSP-BF561 - all supported revisions -** ADSP-BF54[24789] - 0.0 (fixed in 0.1) -** -** Used by VDK -*/ -#define WA_05000312 \ - (defined(__SILICON_REVISION__) && \ - (defined(__ADSPBF533_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF537_FAMILY__)) || \ - (defined(__ADSPBF538_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF548_FAMILY__) && \ - (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF561_FAMILY__))) - - -/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences -** -** Impacted: -** ADSP-BF561 - all supported revisions -** -** Use by System Services/Device Drivers. -*/ -#define WA_05000323 \ - (defined(__ADSPBF561__) && defined(__SILICON_REVISION__)) - - -/* 05-00-0365 - DMAs that Go Urgent during Tight Core Writes to External -** Memory Are Blocked -** -** Impacted: -** ADSP-BF54[24789] - all supported revisions -** ADSP-BF54[24789]M - all supported revisions -** -** Use by System Services/Device Drivers. -*/ -#define WA_05000365 \ - ((defined(__ADSPBF548_FAMILY__) || defined(__ADSPBF548M_FAMILY__)) && \ - defined(__SILICON_REVISION__)) - - -/* 05-00-0371 - Possible RETS Register Corruption when Subroutine Is under -** 5 Cycles in Duration -** -** This problem impacts: -** BF531/2/3 - 0.0-0.5 (fixed in 0.6) -** BF534/6/7 - 0.0-0.3 -** BF538/9 - 0.0-0.4 (fixed in 0.5) -** BF561 - 0.0-0.5 -** BF542/4/7/8/9 - 0.0-0.1 (fixed in 0.2) -** BF523/5/7 - 0.0-0.1 (fixed in 0.2) -** -*/ - -#define WA_05000371 \ - (defined(__SILICON_REVISION__) && \ - (defined(__ADSPBF533_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF537_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF538_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF548_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF527_FAMILY__) && \ - (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \ - (defined(__ADSPBF561__) || defined(__ADSPBF566__))) - - -/* 05-00-0380 - Data Read From L3 Memory by USB DMA May be Corrupted -** -** Impacted: -** ADSP-BF52[357] - rev 0.0-0.1 (fixed 0.2) -** -** Use by System Services/Device Drivers. -*/ -#define WA_05000380 \ - (defined(__ADSPBF527_FAMILY__) && \ - (defined(__SILICON_REVISION__) && \ - (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff))) - - -/* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data - * Cache Enabled" - * - * If you use the testset instruction to operate on L2 memory and you have data - * in external memory that is cached using WB mode, data in external memory - * and/or L2 memory can be corrupted. - * - * Workaround: Either do not use writeback cache or precede the TESTSET - * instruction with an SSYNC instruction. If preceding the TESTSET instruction - * by an SSYNC instruction, do the following: - * - * CLI R0 - * R1 = [P0] // perform a dummy read to make sure CPLB is installed - * NOP - * NOP - * SSYNC - * TESTSET (P0) - * STI R0 - * - * This problem impacts: - * BF561/6 - rev 0.0-0.5 - * - */ - -#define WA_05000412 \ - (defined (__SILICON_REVISION__) && defined(__ADSPBF561__)) - - -/* 05-00-0426 - Speculative Fetches of Indirect-Pointer Instructions Can -** Cause False Hardware Errors -** -** -** A false hardware error is generated if there is an indirect jump or -** call through a pointer which may point to reserved or illegal memory -** on the opposite control flow of a conditional jump to the taken path. -** This commonly occurs when using function pointers, which can be -** invalid (e.g., set to -1). -** -** Workaround: If instruction cache is on or the ICPLBs are enabled, -** this anomaly does not apply. If instruction cache is off and ICPLBs -** are disabled, the indirect pointer instructions must be 2 instructions -** away from the branch instruction, which can be implemented using NOPs: -** -** -** Impacted: -** All parts and revisions other than BF535 based parts. -** -** Used by System Services/Device Drivers. -*/ -#define WA_05000426 \ - (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) - - -/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read - * by Core B from L2 Memory" - * - * This issue occurs only when the accesses are performed by core B of a BF561. - * - * When a write to internal L2 memory follows a speculative read from internal - * L2 memory, the L2 write may be lost or corrupted. For this anomaly to occur, - * the speculative read must be caused by a read in the shadow of a branch. The - * accesses do not have to be consecutive accesses. In other words, the problem - * can occur even if there are multiple instructions between the speculative - * read and the write, as shown in the following example: - * - * R1 = 1; R2 = 1; - * CC = R1 == R2; - * IF CC JUMP X; // Always true... - * R0 = [P0]; // If any of these three loads accesses L2 memory from Core - * R1 = [P1]; // B, speculative execution in the pipeline causes the - * R2 = [P2]; // anomaly trigger condition. - * X: - * ... // Any number of instructions... - * [P0] = R0; // This write can be corrupted or lost. - * - * The issue does not occur if the speculative read access is caused by an - * interrupt or exception. - * - * The workaround required depends upon the conditional branch instruction. - * If the evaluated condition is true and the branch is predicted, then the - * workaround is to ensure that the target instruction is not be a load - * instruction, for example: - * - * IF CC JUMP X (BP); - * ... - * X: <load that might be from L2 memory> - * - * If the evaluated condition is false and the branch is not predicted, then - * the workaround is to make sure that none of the three instructions that - * are executed after the conditional JUMP are load instructions, for example: - * - * IF CC JUMP ...; - * <load that might be from L2 memory> - * <load that might be from L2 memory> - * <load that might be from L2 memory> - * - * This problem impacts: - * BF561 - rev 0.4,0.5 - * - */ - -#define WA_05000428 \ - (defined(__SILICON_REVISION__) && \ - defined(__ADSPBF561__) && \ - ((__SILICON_REVISION__ == 0xffff) || \ - (__SILICON_REVISION__ == 0x4) || \ - (__SILICON_REVISION__ == 0x5))) - - -/* 05-00-0443 - IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall -** -** Impacted: -** All parts and revisions other than BF535 based parts. -** -** Used by System Services/Device Drivers. -*/ -#define WA_05000443 \ - (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)) - -#ifdef _MISRA_RULES -#pragma diag(pop) -#endif /* _MISRA_RULES */ - diff --git a/libgloss/bfin/include/sys/excause.h b/libgloss/bfin/include/sys/excause.h deleted file mode 100644 index 2fe9a05e3..000000000 --- a/libgloss/bfin/include/sys/excause.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/************************************************************************ - * - * excause.h - * - * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -/* -** Definitions of constants for the four user-level bits in EXCAUSE, -** the field from SYSSTAT that is set when the EXCPT instruction is -** invoked. -*/ - -#ifndef _EXCAUSE_H -#define _EXCAUSE_H - -/* -** Value 0x0 - exit program. (halt) -** R0 => exit status. -*/ - -#define EX_EXIT_PROG 0x0 - -/* -** Value 0x1 - abnormal exit (abort) -*/ - -#define EX_ABORT_PROG 0x1 - -/* -** Value 0x2 - invoke system service. -** R0 => command. -** R1 => first arg -** R2 => second arg -*/ - -#define EX_SYS_REQ 0x2 - -/* -** Available commands: -*/ - -#define EX_SYSREQ_NONE 0x00 /* Do nothing */ -#define EX_SYSREQ_REG_ISR 0x01 /* Register an interrupt handler. - R1==EVT entry, R2==func ptr - Returns previous entry in R0. */ -#define EX_SYSREQ_RAISE_INT 0x02 /* Cause an interrupt - R1 = int number */ -/* -** Values 0x3 to 0x4 currently undefined. -*/ - -/* -** Value 0x5 - File I/O -** R0 => first arg -** R1 => second arg -** R2 => third arg -** R4 => command -** result => R0 -*/ - -#define EX_FILE_IO 0x5 - -/* -** Available commands: -** XXX stdout/stderr are handled separately for writing. -*/ - -#define EX_FILEIO_OPEN 0x00 /* R0 => dev, R1=> path, R2=>mode */ -#define EX_FILEIO_CLOSE 0x01 /* R0=> fid */ -#define EX_FILEIO_WRITE 0x02 /* R0=>fid, R1=>data, R2=>length */ -#define EX_FILEIO_READ 0x03 /* R0=>fid, R1=>data, R2=>length */ -#define EX_FILEIO_SEEK 0x04 /* R0=>fid, R1=>offset, R2=>mode */ -#define EX_FILEIO_DUP 0x05 /* R0=>fid */ - -/* -** Values 0x6 to 0xF currently undefined. -*/ - -#endif /* _EXCAUSE_H */ diff --git a/libgloss/bfin/include/sys/exception.h b/libgloss/bfin/include/sys/exception.h deleted file mode 100644 index d1a531aa7..000000000 --- a/libgloss/bfin/include/sys/exception.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#pragma once -#ifndef __NO_BUILTIN -#pragma system_header /* exception.h */ -#endif -/************************************************************************ - * - * exception.h - * - * (c) Copyright 2001-2008 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -#ifndef _EXCEPTION_H -#define _EXCEPTION_H - -#ifdef _MISRA_RULES -#pragma diag(push) -#pragma diag(suppress:misra_rule_5_6) -#pragma diag(suppress:misra_rule_5_7) -#pragma diag(suppress:misra_rule_6_3) -#pragma diag(suppress:misra_rule_19_4) -#pragma diag(suppress:misra_rule_19_7) -#pragma diag(suppress:misra_rule_19_10) -#pragma diag(suppress:misra_rule_19_13) -#endif /* _MISRA_RULES */ - - - -/* -** Definitions for user-friendly interrupt handling. -*/ - -/* -** Memory-Mapped Registers (MMRs) - these record what causes address -** exceptions. -*/ - -#define EX_DATA_FAULT_STATUS 0xFFE00008 -#define EX_DATA_FAULT_ADDR 0xFFE0000C -#define EX_CODE_FAULT_STATUS 0xFFE01008 -#define EX_CODE_FAULT_ADDR 0xFFE0100C - -/* -** Event Vector Table -*/ - -#define EX_EVENT_VECTOR_TABLE 0xFFE02000 - -/* -** Meaning of the various bits in EXCAUSE field in SEQSTAT register. -*/ - -#define EX_BITS 0x3F /* All EXCAUSE bits */ -#define EX_TYPE 0x30 /* The bits which define the type */ -#define EX_DEBUG 0x10 /* If set, is a debug exception type */ -#define EX_SYS 0x20 /* If set, is a system exception type */ - /* If neither set, is from EXCPT instr */ - -#define EX_IS_DEBUG_EXCEPTION(E) (((E)&EX_TYPE)==EX_DEBUG) -#define EX_IS_SYSTEM_EXCEPTION(E) (((E)&EX_TYPE)==EX_SYS) -#define EX_IS_USER_EXCEPTION(E) (((E)&EX_TYPE)==0) - -/* -** Service exceptions continue from the instruction after the one -** that raised the exception. -** Error exceptions restart the instruction that raised the exception. -*/ - -#define EX_IS_SERVICE_EXCEPTION(E) (!EX_IS_SYSTEM_EXCEPTION(E)) -#define EX_IS_ERROR_EXCEPTION(E) (EX_IS_SYSTEM_EXCEPTION(E)) - -#define EX_DB_SINGLE_STEP 0x10 /* Processor is single-stepping */ -#define EX_DB_EMTRCOVRFLW 0x11 /* Emulation Trace buffer overflowed */ - -#define EX_SYS_UNDEFINSTR 0x21 /* Undefined instruction */ -#define EX_SYS_ILLINSTRC 0x22 /* Illegal instruction combination */ -#define EX_SYS_DCPLBPROT 0x23 /* Data CPLB Protection violation */ -#define EX_SYS_DALIGN 0x24 /* Data access misaligned address violation */ -#define EX_SYS_UNRECEVT 0x25 /* Unrecoverable event */ -#define EX_SYS_DCPLBMISS 0x26 /* Data access CPLB Miss */ -#define EX_SYS_DCPLBMHIT 0x27 /* Data access CPLB Multiple Hits */ -#define EX_SYS_EMWATCHPT 0x28 /* Emulation watch point match */ -#define EX_SYS_CACCESSEX 0x29 /* Code fetch access exception */ -#define EX_SYS_CALIGN 0x2A /* Attempted misaligned instr cache fetch */ -#define EX_SYS_CCPLBPROT 0x2B /* Code fetch CPLB Protection */ -#define EX_SYS_CCPLBMISS 0x2C /* CPLB miss on an instruction fetch */ -#define EX_SYS_CCPLBMHIT 0x2D /* Code fetch CPLB Multiple Hits */ -#define EX_SYS_ILLUSESUP 0x2E /* Illegal use of Supervisor Resource */ - -/* -** Meaning of the various bits in HWERRCAUSE in SEQSTAT -*/ - -#define EX_HWBITS (0x1F<<14) /* bits 18:14 */ - -#if !defined(__ADSPLPBLACKFIN__) -#define EX_HW_NOMEM1 (0x16<<14) -#define EX_HW_NOMEM2 (0x17<<14) -#else -#define EX_HW_SYSMMR (0x02<<14) -#define EX_HW_EXTMEM (0x03<<14) -#endif -#define EX_HW_DMAHIT (0x01<<14) -#define EX_HW_PERFMON (0x12<<14) -#define EX_HW_RAISE (0x18<<14) - -/* -** Meaning of the bits in DATA_FAULT_STATUS and CODE_FAULT_STATUS -*/ - -#define EX_DATA_FAULT_ILLADDR (1<<19) /* non-existent memory */ -#define EX_DATA_FAULT_DAG (1<<18) /* 0=>DAG0, 1=>DAG1 */ -#define EX_DATA_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */ -#define EX_DATA_FAULT_READWRITE (1<<16) /* 0=>read, 1=>write */ -#define EX_DATA_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */ - -#define EX_CODE_FAULT_ILLADDR (1<<19) /* non-existent memory */ -#define EX_CODE_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */ -#define EX_CODE_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */ - -/* -** The kinds of interrupt that can occur. These are also the -** indices into the Event Vector Table. -*/ - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ik_err=-1, - ik_emulation, - ik_reset, - ik_nmi, - ik_exception, - ik_global_int_enable, - ik_hardware_err, - ik_timer, - ik_ivg7, - ik_ivg8, - ik_ivg9, - ik_ivg10, - ik_ivg11, - ik_ivg12, - ik_ivg13, - ik_ivg14, - ik_ivg15, - num_interrupt_kind -} interrupt_kind; - -/* -** Structure for recording details of an exception or interrupt -** that has occurred. -*/ - -typedef struct { - interrupt_kind kind; /* whether interrupt, exception, etc. */ - int value; /* interrupt number, exception type, etc. */ - void *pc; /* PC at point where exception occurred */ - void *addr; /* if an address faulted, which one. */ - unsigned status; /* if an address faulted, why. */ -} interrupt_info; - -/* -** Macro for defining an interrupt routine -*/ - -typedef void (*ex_handler_fn)(); - -#define EX_HANDLER(KIND,NAME) \ -_Pragma(#KIND) \ -void NAME (void) - -#define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME) - -#define EX_INTERRUPT_HANDLER(NAME) EX_HANDLER(interrupt,NAME) -#define EX_EXCEPTION_HANDLER(NAME) EX_HANDLER(exception,NAME) -#define EX_NMI_HANDLER(NAME) EX_HANDLER(nmi,NAME) -#define EX_REENTRANT_HANDLER(NAME) \ -_Pragma("interrupt_reentrant") \ -EX_HANDLER(interrupt,NAME) - -/* -** A convenience function for setting up the interrupt_info contents. -** Must be called from immediately with the interrupt handler. -*/ - -void get_interrupt_info(interrupt_kind int_kind, interrupt_info *int_info); - -/* -** Diagnostics function for reporting unexpected events. -*/ - -void _ex_report_event(interrupt_info *int_info); - -/* -** Register an interrupt handler within the EVT. -** Return previous value if there was one. -*/ -ex_handler_fn register_handler(interrupt_kind int_kind, ex_handler_fn handler); - -/* -** Some magic values for registering default and null handlers. -*/ - -#define EX_INT_DEFAULT ((ex_handler_fn)-1) -#define EX_INT_IGNORE ((ex_handler_fn)0) - -/* -** Extended function to register an interrupt handler within the EVT. -** Returns the old handler. -** -** If enabled == EX_INT_ALWAYS_ENABLE, install fn (if fn != EX_INT_IGNORE -** and fn != EX_INT_DISABLE), and then enable the interrupt in IMASK then -** return -** -** If fn == EX_INT_IGNORE, disable the interrupt -** If fn == EX_INT_DEFAULT, delete the handler entry in the EVT and disable -** the interrupt in IMASK -** Otherwise, install the new interrupt handler. Then, -** If enabled == EX_INT_DISABLE, disable the interrupt in IMASK -** If enabled == EX_INT_ENABLE, enable the interrupt in IMASK -** otherwise leave the interrupt status alone. -*/ -ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn, - int enable); - -/* Constants for the enabled parameter of register_handler_ex */ -#define EX_INT_DISABLE 0 -#define EX_INT_ENABLE 1 -#define EX_INT_KEEP_IMASK -1 -#define EX_INT_ALWAYS_ENABLE 2 - -/* -** Allow the user to raise exceptions from C. -*/ - -int raise_interrupt(interrupt_kind kind, int which, - int cmd, int arg1, int arg2); - -#ifdef __cplusplus - } /* extern "C" */ -#endif - -#ifdef _MISRA_RULES -#pragma diag(pop) -#endif /* _MISRA_RULES */ - -#endif /* _EXCEPTION_H */ diff --git a/libgloss/bfin/include/sys/mc_typedef.h b/libgloss/bfin/include/sys/mc_typedef.h deleted file mode 100644 index abcd62dd5..000000000 --- a/libgloss/bfin/include/sys/mc_typedef.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#pragma once -#ifndef __NO_BUILTIN -#pragma system_header /* sys/mc_typedef.h */ -#endif -/************************************************************************ - * - * sys/mc_typedef.h - * - * (c) Copyright 2007-2009 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -/* Define testset_t. */ - -#ifndef _SYS_MC_TYPEDEF_H -#define _SYS_MC_TYPEDEF_H - -#if !defined(__ADSPLPBLACKFIN__) - typedef volatile unsigned char testset_t; -#elif defined(__WORKAROUND_TESTSET_ALIGN) || defined(__WORKAROUND_05000412) - /* these workarounds require 32-bit aligned address */ - typedef volatile unsigned int testset_t; -#else - typedef volatile unsigned short testset_t; -#endif - -#endif /* _SYS_MC_TYPEDEF_H */ diff --git a/libgloss/bfin/include/sys/platform.h b/libgloss/bfin/include/sys/platform.h deleted file mode 100644 index b78f8902e..000000000 --- a/libgloss/bfin/include/sys/platform.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#ifndef _PLATFORM_H -#define _PLATFORM_H -/* Generic Wrapper for platform specific header file. - Copyright (C.) 2004, Analog Devices Inc. All Rights Reserved. - */ -#include <sys/_adi_platform.h> -#endif diff --git a/libgloss/bfin/include/sys/pll.h b/libgloss/bfin/include/sys/pll.h deleted file mode 100644 index 7525d04cc..000000000 --- a/libgloss/bfin/include/sys/pll.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/************************************************************************ - * - * pll.h - * - * (c) Copyright 2003-2004 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -#ifndef __ASSEMBLER__ -#pragma once -#pragma system_header -#endif - -#ifndef _PLL_H -#define _PLL_H - -#ifdef _MISRA_RULES -#pragma diag(push) -#pragma diag(suppress:misra_rule_6_3) -#endif /* _MISRA_RULES */ - -#define NO_STARTUP_SET 0 -#define MAX_IN_STARTUP 1 - -#ifndef __ASSEMBLER__ - -enum clkctrl_t { - /* no modification of PLL rates in CRT startup - default */ - no_startup_set=NO_STARTUP_SET, - - /* CRT startup sets PLL rates to suitable maximum values */ - max_in_startup=MAX_IN_STARTUP -}; - -/* -** Define __clk_ctrl to 1 to cause startup to set PLL rates for maximum -** speed performance rates. The default version defined in the runtime- -** libraries defines __clk_ctrl to 0 which disables the feature. -*/ -extern enum clkctrl_t __clk_ctrl; - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(__ADSPLPBLACKFIN__) - -/* Sets SSEL and CSEL bits in PLL_DIV to passed values. -** Returns -1 on failure. -*/ -int pll_set_system_clocks(int _csel, int _ssel); - -/* -** Sets MSEL and DF bits in PLL_CTL and LOCKCNT in PLL_LOCKCNT. -** Returns -1 on failure. -*/ -int pll_set_system_vco(int _msel, int _df, int _lockcnt); - -#endif /* __ADSPLPBLACKFIN__ */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLER__ */ - -#ifdef _MISRA_RULES -#pragma diag(pop) -#endif /* _MISRA_RULES */ - -#endif /* _PLL_H */ - |