diff options
author | Clément Foucault <foucault.clem@gmail.com> | 2020-09-14 02:06:49 +0300 |
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committer | Clément Foucault <foucault.clem@gmail.com> | 2020-09-14 02:10:25 +0300 |
commit | ecfbc5fb55d5035a5ac5f100801559d57ef156e3 (patch) | |
tree | 82f37cca66db05e2046eed08d025d1a4a8ed54a6 /source/blender/draw/engines/workbench | |
parent | ab7608af1bd40548cb79a0312f318a32d2fe8596 (diff) |
Fix T80603 Workbench: Inverted alpha when rendering
This was caused by a left over DRWPass->state modification
that made the subsequent samples redraw without Blending enabled.
This led to incorrect blending.
The fix is to use the new API for pass instancing.
Diffstat (limited to 'source/blender/draw/engines/workbench')
-rw-r--r-- | source/blender/draw/engines/workbench/workbench_private.h | 3 | ||||
-rw-r--r-- | source/blender/draw/engines/workbench/workbench_transparent.c | 23 |
2 files changed, 14 insertions, 12 deletions
diff --git a/source/blender/draw/engines/workbench/workbench_private.h b/source/blender/draw/engines/workbench/workbench_private.h index 8983826f16f..d377f09ac73 100644 --- a/source/blender/draw/engines/workbench/workbench_private.h +++ b/source/blender/draw/engines/workbench/workbench_private.h @@ -131,6 +131,9 @@ typedef struct WORKBENCH_PassList { struct DRWPass *transp_accum_ps; struct DRWPass *transp_accum_infront_ps; + struct DRWPass *transp_depth_infront_ps; + struct DRWPass *transp_depth_ps; + struct DRWPass *shadow_ps[2]; struct DRWPass *merge_infront_ps; diff --git a/source/blender/draw/engines/workbench/workbench_transparent.c b/source/blender/draw/engines/workbench/workbench_transparent.c index 1c8575ddc12..94fcd8b5a9d 100644 --- a/source/blender/draw/engines/workbench/workbench_transparent.c +++ b/source/blender/draw/engines/workbench/workbench_transparent.c @@ -91,16 +91,18 @@ void workbench_transparent_cache_init(WORKBENCH_Data *vedata) { int transp = 1; for (int infront = 0; infront < 2; infront++) { - DRWState state = DRW_STATE_WRITE_COLOR | DRW_STATE_DEPTH_LESS_EQUAL | DRW_STATE_BLEND_OIT; + DRWState state = DRW_STATE_WRITE_COLOR | DRW_STATE_DEPTH_LESS_EQUAL | DRW_STATE_BLEND_OIT | + wpd->cull_state | wpd->clip_state; DRWPass *pass; if (infront) { - DRW_PASS_CREATE(psl->transp_accum_infront_ps, state | wpd->cull_state | wpd->clip_state); - pass = psl->transp_accum_infront_ps; + psl->transp_accum_infront_ps = pass = DRW_pass_create("transp_accum_infront", state); + DRW_PASS_INSTANCE_CREATE( + psl->transp_depth_infront_ps, pass, state | DRW_STATE_WRITE_DEPTH); } else { - DRW_PASS_CREATE(psl->transp_accum_ps, state | wpd->cull_state | wpd->clip_state); - pass = psl->transp_accum_ps; + psl->transp_accum_ps = pass = DRW_pass_create("transp_accum", state); + DRW_PASS_INSTANCE_CREATE(psl->transp_depth_ps, pass, state | DRW_STATE_WRITE_DEPTH); } for (eWORKBENCH_DataType data = 0; data < WORKBENCH_DATATYPE_MAX; data++) { @@ -159,20 +161,17 @@ void workbench_transparent_draw_depth_pass(WORKBENCH_Data *data) const bool do_transparent_depth_pass = psl->outline_ps || wpd->dof_enabled || do_xray_depth_pass; if (do_transparent_depth_pass) { - DRWState state = DRW_STATE_WRITE_COLOR | DRW_STATE_WRITE_DEPTH | DRW_STATE_DEPTH_LESS_EQUAL; - if (!DRW_pass_is_empty(psl->transp_accum_ps)) { + if (!DRW_pass_is_empty(psl->transp_depth_ps)) { GPU_framebuffer_bind(fbl->opaque_fb); /* TODO(fclem) Disable writing to first two buffers. Unnecessary waste of bandwidth. */ - DRW_pass_state_set(psl->transp_accum_ps, state | wpd->cull_state | wpd->clip_state); - DRW_draw_pass(psl->transp_accum_ps); + DRW_draw_pass(psl->transp_depth_ps); } - if (!DRW_pass_is_empty(psl->transp_accum_infront_ps)) { + if (!DRW_pass_is_empty(psl->transp_depth_infront_ps)) { GPU_framebuffer_bind(fbl->opaque_infront_fb); /* TODO(fclem) Disable writing to first two buffers. Unnecessary waste of bandwidth. */ - DRW_pass_state_set(psl->transp_accum_infront_ps, state | wpd->cull_state | wpd->clip_state); - DRW_draw_pass(psl->transp_accum_infront_ps); + DRW_draw_pass(psl->transp_depth_infront_ps); } } } |