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authorAlexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com>2022-12-09 19:19:08 +0300
committerAlexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com>2022-12-09 19:19:08 +0300
commit976b0d39e3e684604394ecf59094e1c1848e433e (patch)
tree06e1017bc907b24aee9fb1323dcc320f371ad318
parent7cdac1c95cc17ccc7ed1512ae796419b8979e70f (diff)
PRG RAM /CE delay test
-rw-r--r--tests.asm4
1 files changed, 4 insertions, 0 deletions
diff --git a/tests.asm b/tests.asm
index ac72301..542d631 100644
--- a/tests.asm
+++ b/tests.asm
@@ -66,6 +66,10 @@ do_tests_again:
inc COPY_DEST_ADDR+1
dex
bne .prg_ram_test_loop
+ ; test for corruption on wrong /CE delay
+ lda #00
+ sta $E000
+ sta $F000
dec <TEST_BANK
bpl .prg_ram_test_loop_bank
lda <TEST_RW