diff options
| author | Alexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com> | 2022-12-06 21:33:11 +0300 |
|---|---|---|
| committer | Alexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com> | 2022-12-06 21:33:42 +0300 |
| commit | d7948d3ea23ae6e26836489b70dcf65678b205b5 (patch) | |
| tree | eb9dbba64be972bfdcc332cece164891c7862fb2 | |
| parent | c4152c650b76bd796a91595f49c9ac188b8c9d08 (diff) | |
Minor refactoring
| -rw-r--r-- | CoolGirl_mappers.vh | 7 | ||||
| -rw-r--r-- | CoolGirl_rev6.x/CoolGirl.qsf | 4 |
2 files changed, 6 insertions, 5 deletions
diff --git a/CoolGirl_mappers.vh b/CoolGirl_mappers.vh index 5aa513f..35ec563 100644 --- a/CoolGirl_mappers.vh +++ b/CoolGirl_mappers.vh @@ -164,8 +164,9 @@ wire cpu_data_out_enabled; wire [7:0] cpu_data_out; assign {cpu_data_out_enabled, cpu_data_out} = (cpu_rw_in && m2) ? // reading? - ((RESET_COMBINATION != 0) && (reset_state != 0)) ? // resetting? - ( + ( + ((RESET_COMBINATION != 0) && (reset_state != 0)) // resetting? + ? ( // resetting // jmp [$FFFC] reset_state == 1 ? {1'b1, 8'h6C} @@ -193,7 +194,7 @@ assign {cpu_data_out_enabled, cpu_data_out} = 9'b00000000 ): 9'b00000000 ) - : 9'b00000000; + ) : 9'b00000000; // Mirroring: 00=vertical, 01=horizontal, 10=1Sa, 11=1Sb assign ppu_ciram_a10 = (ENABLE_MAPPER_118 & (mapper == 6'b010100) & flags[0]) ? chr_addr_mapped[17] : diff --git a/CoolGirl_rev6.x/CoolGirl.qsf b/CoolGirl_rev6.x/CoolGirl.qsf index 53a19bf..21fc88a 100644 --- a/CoolGirl_rev6.x/CoolGirl.qsf +++ b/CoolGirl_rev6.x/CoolGirl.qsf @@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM1270T144C5 set_global_assignment -name TOP_LEVEL_ENTITY CoolGirl
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:53:22 MAY 05, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -50,7 +50,7 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
|