diff options
| author | Alexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com> | 2020-11-27 18:03:42 +0300 |
|---|---|---|
| committer | Alexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com> | 2020-11-27 18:03:42 +0300 |
| commit | 15be92aa5145550a3e02e6520baf1c745e3b6534 (patch) | |
| tree | 2b5ec6fef40e246bb40b549f5b7017edd5b5a88e /CPLD | |
First commit
Diffstat (limited to 'CPLD')
| -rw-r--r-- | CPLD/FamicomDumper.dpf | 20 | ||||
| -rw-r--r-- | CPLD/FamicomDumper.qpf | 30 | ||||
| -rw-r--r-- | CPLD/FamicomDumper.qsf | 75 | ||||
| -rw-r--r-- | CPLD/FamicomDumper.v | 139 |
4 files changed, 264 insertions, 0 deletions
diff --git a/CPLD/FamicomDumper.dpf b/CPLD/FamicomDumper.dpf new file mode 100644 index 0000000..edce5d4 --- /dev/null +++ b/CPLD/FamicomDumper.dpf @@ -0,0 +1,20 @@ +<?xml version="1.0" encoding="UTF-8"?>
+
+<pin_planner>
+ <pin_info>
+ <pin name="led4" source="Pin Planner" >
+ </pin>
+ <pin name="led3" source="Pin Planner" >
+ </pin>
+ <pin name="led2" source="Pin Planner" >
+ </pin>
+ <pin name="led1" source="Pin Planner" >
+ </pin>
+ </pin_info>
+ <buses>
+ </buses>
+ <group_file_association>
+ </group_file_association>
+ <pin_planner_file_specifies>
+ </pin_planner_file_specifies>
+</pin_planner>
diff --git a/CPLD/FamicomDumper.qpf b/CPLD/FamicomDumper.qpf new file mode 100644 index 0000000..571a312 --- /dev/null +++ b/CPLD/FamicomDumper.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 09:20:26 October 29, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "09:20:26 October 29, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "FamicomDumper"
diff --git a/CPLD/FamicomDumper.qsf b/CPLD/FamicomDumper.qsf new file mode 100644 index 0000000..2fc89c3 --- /dev/null +++ b/CPLD/FamicomDumper.qsf @@ -0,0 +1,75 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 09:20:26 October 29, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# FamicomDumper_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX3000A
+set_global_assignment -name DEVICE "EPM3128ATC100-7"
+set_global_assignment -name TOP_LEVEL_ENTITY FamicomDumper
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:20:26 OCTOBER 29, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name VERILOG_FILE FamicomDumper.v
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_75 -to a13
+set_location_assignment PIN_71 -to coolboy_mode
+set_location_assignment PIN_76 -to a15
+set_location_assignment PIN_83 -to nwait
+set_location_assignment PIN_84 -to noe
+set_location_assignment PIN_85 -to nwe
+set_location_assignment PIN_87 -to m2
+set_location_assignment PIN_88 -to ne1
+set_location_assignment PIN_89 -to ne2
+set_location_assignment PIN_90 -to master_clock
+set_location_assignment PIN_92 -to romsel
+set_location_assignment PIN_93 -to cpu_rw
+set_location_assignment PIN_94 -to ppu_rd
+set_location_assignment PIN_96 -to ppu_wr
+set_location_assignment PIN_97 -to na13
+set_location_assignment PIN_98 -to ppu_dir
+set_location_assignment PIN_99 -to ppu_oe
+set_location_assignment PIN_100 -to cpu_dir
+set_location_assignment PIN_6 -to cpu_oe
+set_location_assignment PIN_47 -to coolboy_oe
+set_location_assignment PIN_48 -to coolboy_we
+set_location_assignment PIN_32 -to led_prg_read
+set_location_assignment PIN_31 -to led_prg_write
+set_location_assignment PIN_30 -to led_chr_read
+set_location_assignment PIN_29 -to led_chr_write
\ No newline at end of file diff --git a/CPLD/FamicomDumper.v b/CPLD/FamicomDumper.v new file mode 100644 index 0000000..057515a --- /dev/null +++ b/CPLD/FamicomDumper.v @@ -0,0 +1,139 @@ +module FamicomDumper # (
+ parameter LEDS_TIMER_SIZE = 12
+)
+(
+ input m2,
+ input master_clock,
+ input ne1,
+ input ne2,
+ input nwe,
+ input noe,
+ input a13,
+ input a15,
+ output nwait,
+
+ output romsel,
+ output cpu_rw,
+ output ppu_rd,
+ output ppu_wr,
+ output na13,
+ output cpu_dir,
+ output cpu_oe,
+ output ppu_dir,
+ output ppu_oe,
+
+ input coolboy_mode,
+ output coolboy_oe,
+ output coolboy_we,
+
+ output led_prg_read,
+ output led_prg_write,
+ output led_chr_read,
+ output led_chr_write
+);
+
+assign romsel = !(m2 && a15 && ne1_active);
+assign cpu_rw = reg_cpu_rw;
+assign cpu_oe = !cpu_shifter_enabled;
+assign cpu_dir = !reg_cpu_rw;
+assign ppu_rd = !(!ne2 && !noe);
+assign ppu_wr = !(!ne2 && !nwe);
+assign ppu_oe = !(!ne2 && ne1);
+assign ppu_dir = !(!ne2 && !noe);
+assign na13 = !a13;
+assign nwait = !waiting;
+assign coolboy_oe = !(ne1_active && m2 && a15 && reg_cpu_rw);
+assign coolboy_we = !(ne1_active && m2 && a15 && !reg_cpu_rw);
+
+reg [2:0] stage = 0;
+reg [5:0] wait_timer = 0;
+reg [4:0] neg_m2_timer = 0;
+wire waiting = wait_timer < (nwe ? 3'b111 : 4'b1111);
+reg cpu_shifter_enabled = 0;
+reg reg_cpu_rw = 1;
+
+wire ne1_active = !ne1 && (!noe || !nwe);
+
+reg [1:0] active_led = 0;
+reg [LEDS_TIMER_SIZE:0] led_timer = 0;
+assign led_prg_read = (active_led == 2'b00) && led_on;
+assign led_prg_write = (active_led == 2'b01) && led_on;
+assign led_chr_read = (active_led == 2'b10) && led_on;
+assign led_chr_write = (active_led == 2'b11) && led_on;
+wire led_on = led_timer < ((1 << (LEDS_TIMER_SIZE + 1)) - 1);
+
+always @ (negedge master_clock)
+begin
+ if (m2)
+ begin
+ neg_m2_timer = 0;
+ end else begin
+ neg_m2_timer = neg_m2_timer + 1'b1;
+ end
+
+ // waiting for ne1
+ if (!ne1_active) begin
+ stage = (!m2 && neg_m2_timer < 7) ? 2 : 0;
+ wait_timer = 0;
+ cpu_shifter_enabled = 0;
+ reg_cpu_rw = 1; // read mode
+ end
+ else if (stage == 0) // low M2?
+ begin
+ // waiting for high M2
+ if (m2) stage = 1;
+ end
+ else if (stage == 1) // low M2
+ begin
+ // waiting for low M2
+ if (!m2) stage = 2;
+ end
+ else if (stage == 2) // low M2
+ begin
+ // set direction to writing if need
+ if (!nwe) reg_cpu_rw = 0;
+ // enable shifter
+ cpu_shifter_enabled = 1;
+ // waiting for high M2
+ // actual reading/writing starts here
+ if (m2) stage = 3;
+ end
+ else if (stage == 3) // high M2
+ begin
+ if (ne1_active && waiting)
+ begin
+ wait_timer = wait_timer + 1'b1;
+ end
+ end
+end
+
+always @ (posedge m2)
+begin
+ if (led_on) led_timer = led_timer + 1; // leds timer
+
+ if (!ne1 && !noe)
+ begin
+ active_led = 2'b00;
+ led_timer = 0;
+ end
+
+ if (!ne1 && !nwe)
+ begin
+ active_led = 2'b01;
+ led_timer = 0;
+ end
+
+ if (!ne2 && !noe)
+ begin
+ active_led = 2'b10;
+ led_timer = 0;
+ end
+
+ if (!ne2 && !nwe)
+ begin
+ active_led = 2'b11;
+ led_timer = 0;
+ end
+end
+
+endmodule
\ No newline at end of file |