More FDS stuff

12 files changed, 555 insertions, 275 deletions

diff --git a/STM32/.cproject b/STM32/.cproject
index c83ce54..99a4397 100644
--- a/STM32/.cproject
+++ b/STM32/.cproject
@@ -23,7 +23,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.802816544" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>

 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.323299941" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>

 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1540624207" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>

-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.348107410" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103ZETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/App | ../USB_DEVICE/Target | ../Core/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Drivers/CMSIS/Include ||  ||  || STM32F103xE | USE_HAL_DRIVER ||  || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE ||  ||  || ${workspace_loc:/${ProjName}/STM32F103ZETX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>

+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.348107410" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103ZETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/Target | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Drivers/CMSIS/Include | ../Core/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc | ../USB_DEVICE/App | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc ||  ||  || STM32F103xE | USE_HAL_DRIVER ||  || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE ||  ||  || ${workspace_loc:/${ProjName}/STM32F103ZETX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>

 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1956864674" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>

 							<builder buildPath="${workspace_loc:/STM32}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1575865607" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>

 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.633583979" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">

@@ -105,7 +105,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1878493876" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>

 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.892728556" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>

 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1847660064" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>

-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1207545234" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103ZETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/App | ../USB_DEVICE/Target | ../Core/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Drivers/CMSIS/Include ||  ||  || STM32F103xE | USE_HAL_DRIVER ||  || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE ||  ||  || ${workspace_loc:/${ProjName}/STM32F103ZETX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>

+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1207545234" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103ZETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/Target | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Drivers/CMSIS/Include | ../Core/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc | ../USB_DEVICE/App | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc ||  ||  || STM32F103xE | USE_HAL_DRIVER ||  || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE ||  ||  || ${workspace_loc:/${ProjName}/STM32F103ZETX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>

 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.743968727" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>

 							<builder buildPath="${workspace_loc:/STM32}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1569906200" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>

 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1472380938" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">

@@ -180,4 +180,5 @@
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>

 		</scannerConfigBuildInfo>

 	</storageModule>

+	<storageModule moduleId="refreshScope"/>

 </cproject>

diff --git a/STM32/Core/Inc/comm.h b/STM32/Core/Inc/comm.h
index cff9a36..90e4533 100644
--- a/STM32/Core/Inc/comm.h
+++ b/STM32/Core/Inc/comm.h
@@ -3,8 +3,8 @@
 

 #include <inttypes.h>

 

-#define RECV_BUFFER_SIZE 1024 * 32

-#define SEND_BUFFER_SIZE 512

+#define RECV_BUFFER_SIZE 1024 * 55

+#define SEND_BUFFER_SIZE 1000

 

 #define COMMAND_PRG_STARTED 0

 #define COMMAND_CHR_STARTED 1

@@ -55,6 +55,12 @@
 #define COMMAND_FDS_READ_RESULT_BLOCK 46

 #define COMMAND_FDS_READ_RESULT_END 47

 #define COMMAND_FDS_TIMEOUT 48

+#define COMMAND_FDS_NOT_CONNECTED 49

+#define COMMAND_FDS_BATTERY_LOW 50

+#define COMMAND_FDS_DISK_NOT_INSERTED 51

+#define COMMAND_FDS_END_OF_HEAD 52

+#define COMMAND_FDS_WRITE_REQUEST 53

+#define COMMAND_FDS_WRITE_DONE 54

 

 #define COMMAND_BOOTLOADER 0xFE

 #define COMMAND_DEBUG 0xFF

diff --git a/STM32/Core/Inc/dumper.h b/STM32/Core/Inc/dumper.h
index 168ed42..76ec946 100644
--- a/STM32/Core/Inc/dumper.h
+++ b/STM32/Core/Inc/dumper.h
@@ -1,7 +1,7 @@
 #ifndef _DUMPER_H_

 #define _DUMPER_H_

 

-#define PROTOCOL_VERSION 2

+#define PROTOCOL_VERSION 3

 

 #define FDS_PAUSE_BEFORE_FIRST_BLOCK 300

 #define FDS_PAUSE_BETWEEN_BLOCKS 5

@@ -13,13 +13,14 @@
 void reset(void);

 void read_prg_send(uint16_t address, uint16_t len);

 void read_prg_crc_send(uint16_t address, uint16_t len);

-void write_prg(uint16_t address, uint16_t len, uint8_t* data);

+void write_prg(uint16_t address, uint16_t len, uint8_t *data);

 void read_chr_send(uint16_t address, uint16_t len);

 void read_chr_crc_send(uint16_t address, uint16_t len);

-void write_chr(uint16_t address, uint16_t len, uint8_t* data);

+void write_chr(uint16_t address, uint16_t len, uint8_t *data);

 void erase_flash_sector();

-void write_flash(uint16_t address, uint16_t len, uint8_t* data);

-void read_fds_send(uint8_t start_block, uint8_t block_count);

+void write_flash(uint16_t address, uint16_t len, uint8_t *data);

+void fds_transfer(uint8_t block_read_start, uint8_t block_read_count, uint8_t block_write_count, uint8_t* block_write_ids, uint16_t *write_lengths,

+    uint8_t *write_data);

 void get_mirroring();

 

 #endif

diff --git a/STM32/Core/Inc/led.h b/STM32/Core/Inc/led.h
index b4818cd..ddeda62 100644
--- a/STM32/Core/Inc/led.h
+++ b/STM32/Core/Inc/led.h
@@ -8,6 +8,7 @@ void led_red();;
 void led_yellow();

 void led_blue();

 void led_magenta();

+void led_cyan();

 void led_idle();

 

 #endif

diff --git a/STM32/Core/Src/comm.c b/STM32/Core/Src/comm.c
index da62a8a..f5f2544 100644
--- a/STM32/Core/Src/comm.c
+++ b/STM32/Core/Src/comm.c
@@ -49,7 +49,7 @@ void check_send_buffer()
 

 void comm_start(uint8_t command, uint16_t length)

 {

-  printf("Sending command %02X, length %d\n", command, length);

+  //printf("Sending command %02X, length %d\n", command, length);

   comm_send_crc = 0;

   send_buffer_pos = 0;

   comm_send_pos = 0;

@@ -138,7 +138,7 @@ void comm_proceed(uint8_t data)
       if (!comm_recv_crc)

       {

         comm_recv_done = 1;

-        printf("Received command %02X, length %d\n", comm_recv_command, comm_recv_length);

+        //printf("Received command %02X, length %d\n", comm_recv_command, comm_recv_length);

       } else

       {

         comm_recv_error = 1;

diff --git a/STM32/Core/Src/dumper.c b/STM32/Core/Src/dumper.c
index 7eefb93..56c2b7d 100644
--- a/STM32/Core/Src/dumper.c
+++ b/STM32/Core/Src/dumper.c
@@ -1,3 +1,4 @@
+#include <stdio.h>

 #include "main.h"

 #include "dumper.h"

 #include "comm.h"

@@ -7,6 +8,22 @@
 volatile uint8_t dummy;

 volatile uint16_t page_mask = 0xFFC0;

 

+static void delay_kilo_clock(uint16_t cycles)

+{

+  TIM3->CNT = 0;

+  while (TIM3->CNT < cycles)

+  {

+  }

+}

+

+static void delay_clock(uint16_t cycles)

+{

+  TIM4->CNT = 0;

+  while (TIM4->CNT < cycles)

+  {

+  }

+}

+

 static uint8_t read_prg_once(uint16_t address)

 {

   while (TIM2->CNT > 10)

@@ -114,7 +131,7 @@ void erase_flash_sector()
   uint8_t ff_count = 0;

   while (1)

   {

-    if (HAL_GetTick() >= start_time + 3000) // 3 seconds timeout

+    if (HAL_GetTick() >= start_time + 5000) // 5 seconds timeout

     {

       // timeout

       comm_start(COMMAND_FLASH_ERASE_TIMEOUT, 0);

@@ -180,7 +197,7 @@ void write_flash(uint16_t address, uint16_t len, uint8_t *data)
       // waiting for result

       while (1)

       {

-        if (HAL_GetTick() >= start_time + 1000) // 1 second timeout

+        if (HAL_GetTick() >= start_time + 50) // 50 ms timeout

         {

           // timeout

           comm_start(COMMAND_FLASH_WRITE_TIMEOUT, 0);

@@ -222,245 +239,321 @@ void write_flash(uint16_t address, uint16_t len, uint8_t *data)
   comm_start(COMMAND_PRG_WRITE_DONE, 0);

 }

 

-void read_fds_send(uint8_t start_block, uint8_t block_count)

+uint8_t transfer_fds_byte(uint8_t *output, uint8_t input, uint8_t *end_of_head)

+{

+  uint32_t start_time;

+  start_time = HAL_GetTick();

+  while (!IRQ_FIRED)

+  {

+    // waiting for interrupt

+    // timeout 5 secs

+    if (HAL_GetTick() - start_time >= 5000)

+    {

+      PRG(0x4025) = 0x26; // reset, stop

+      comm_start(COMMAND_FDS_TIMEOUT, 0);

+      return 0;

+    }

+  }

+  if (output)

+    *output = PRG(0x4031);

+  PRG(0x4024) = input; // clear interrupt

+  uint8_t status = PRG(0x4030);

+  if (end_of_head)

+    *end_of_head |= (status >> 6) & 1;

+  start_time = HAL_GetTick();

+  while (IRQ_FIRED)

+  {

+    // is interrupt flag cleared?

+    // timeout 5 secs

+    if (HAL_GetTick() - start_time >= 5000)

+    {

+      PRG(0x4025) = 0x26; // reset, stop

+      comm_start(COMMAND_FDS_TIMEOUT, 0);

+      return 0;

+    }

+  }

+  return 1;

+}

+

+uint8_t read_fds_block_send(uint16_t length, uint8_t send, uint8_t *crc_ok, uint8_t *end_of_head, uint16_t *file_size, uint32_t gap_delay)

 {

+  uint8_t data;

   uint8_t status;

+  uint32_t b;

+

+  PRG(0x4025) = 0x25; // motor on without transfer

+  if (gap_delay > 30000)

+    delay_kilo_clock(gap_delay / 1000);

+  else

+    delay_clock(gap_delay);

+  if (send)

+  {

+    led_green();

+    comm_start(COMMAND_FDS_READ_RESULT_BLOCK, length + 2);

+  }

+  PRG(0x4025) = 0x65; // start transfer

+  PRG(0x4025) = 0xE5; // enable IRQ

+  for (b = 0; b < length; b++)

+  {

+    if (!transfer_fds_byte(&data, 0, end_of_head))

+      return 0;

+    if (file_size)

+    {

+      if (b == 13)

+        *file_size |= data;

+      else if (b == 14)

+        *file_size |= data << 8;

+    }

+    if (send)

+      comm_send_byte(data);

+  }

+  if (!transfer_fds_byte((uint8_t*) &dummy, 0, end_of_head))

+    return 0;

+  PRG(0x4025) = 0xF5; // enable CRC control

+  if (!transfer_fds_byte((uint8_t*) &dummy, 0, end_of_head))

+    return 0;

+  status = PRG(0x4030);

+  *crc_ok &= ((status >> 4) & 1) ^ 1;

+  *end_of_head |= (status >> 6) & 1;

+  if (send)

+  {

+    comm_send_byte(*crc_ok); // CRC check result

+    comm_send_byte(*end_of_head); // end of head meet?

+  }

+  led_cyan();

+  return 1; // success

+}

+

+uint8_t write_fds_block(uint8_t *data, uint16_t length, uint32_t gap_delay)

+{

+  uint8_t end_of_head = 0;

+  uint32_t start_time;

+  led_red();

+  PRG(0x4025) = 0x25;  // motor on without transfer

+  dummy = PRG(0x4032); // check if disk is inserted

+  PRG(0x4025) = 0x21;  // enable writing without transfer

+  if (gap_delay > 30000)

+    delay_kilo_clock(gap_delay / 1000);

+  else

+    delay_clock(gap_delay);

+  PRG(0x4024) = 0x00; // write $00

+  PRG(0x4025) = 0x61; // start transfer

+  PRG(0x4025) = 0xE1; // enable interrupt

+  transfer_fds_byte(0, 0x80, &end_of_head);  // write $80

+  while (length)

+  {

+    if (end_of_head)

+    {

+      PRG(0x4025) = 0x26; // reset, stop

+      comm_start(COMMAND_FDS_END_OF_HEAD, 0);

+      return 0;

+    }

+    if (!transfer_fds_byte(0, *data, &end_of_head))

+    {

+      PRG(0x4025) = 0x26; // reset, stop

+      comm_start(COMMAND_FDS_TIMEOUT, 0);

+      return 0;

+    }

+    data++;

+    length--;

+  }

+  if (!transfer_fds_byte(0, 0xFF, &end_of_head))

+  {

+    PRG(0x4025) = 0x26; // reset, stop

+    comm_start(COMMAND_FDS_TIMEOUT, 0);

+    return 0;

+  }

+  if (end_of_head)

+  {

+    PRG(0x4025) = 0x26; // reset, stop

+    comm_start(COMMAND_FDS_END_OF_HEAD, 0);

+    return 0;

+  }

+  PRG(0x4025) = 0xF1;  // enable CRC control

+  delay_clock(897);

+  start_time = HAL_GetTick();

+  while (1)

+  {

+    uint8_t status = PRG(0x4032);

+    if (!(status & 2))

+      break; // ready

+    // timeout 1 sec

+    if (HAL_GetTick() - start_time >= 1000)

+    {

+      PRG(0x4025) = 0x26; // reset, stop

+      comm_start(COMMAND_FDS_TIMEOUT, 0);

+      return 0;

+    }

+  }

+  //PRG(0x4025) = 0x25;  // disable transfer, IRQ, writing

+  //PRG(0x4025) = 0x26; // reset, stop

+  led_cyan();

+  return 1;

+}

+

+void fds_transfer(uint8_t block_read_start, uint8_t block_read_count, uint8_t block_write_count, uint8_t* block_write_ids, uint16_t *write_lengths,

+    uint8_t *write_data)

+{

+  uint8_t status;

+  uint8_t crc_ok = 1;

   uint8_t end_of_head = 0;

   uint8_t current_block = 0;

-  uint16_t b;

+  uint8_t current_writing_block = 0;

+  uint32_t start_time;

 

   led_magenta();

   PRG(0x4022) = 0x00; // disable IRQ

   PRG(0x4023) = 0x00; // disable registers

   PRG(0x4023) = 0x01; // enable disk registers

-  PRG(0x4025) = 0x2E; // reset

-  // waiting for disk

-  while (1)

+  PRG(0x4025) = 0x26; // reset

+  uint8_t ram_adapter_connected = 1;

+  PRG(0x4026) = 0x00; // Ext. connector

+  PRG(0x0000) = 0xFF; // To prevent open bus read

+  if ((PRG(0x4033) & 0x7F) != 0x00)

+    ram_adapter_connected = 0;

+  PRG(0x4026) = 0xFF; // Ext. connector

+  PRG(0x0000) = 0x00; // To prevent open bus read

+  if ((PRG(0x4033) & 0x7F) != 0x7F)

+    ram_adapter_connected = 0;

+  if (!ram_adapter_connected)

   {

-    status = PRG(0x4032);

-    if (!(status & 1))

-      break; // disk inserted

+    comm_start(COMMAND_FDS_NOT_CONNECTED, 0);

+    return;

+  }

+  status = PRG(0x4032);

+  if (status & 1)

+  {

+    comm_start(COMMAND_FDS_DISK_NOT_INSERTED, 0);

+    return;

   }

-  PRG(0x4025) = 0x2E; // reset

-  HAL_Delay(800); // 916522 cycles

-  PRG(0x4025) = 0x2F; // start motor

-  PRG(0x4025) = 0x2D; // unreset

 

-  HAL_Delay(250); // 268531 cycles

-  PRG(0x4025) = 0x2E; // reset

-  PRG(0x4025) = 0x2F; // start motor

-  PRG(0x4025) = 0x2D; // unreset

+  PRG(0x4025) = 0x26; // reset

+  delay_kilo_clock(916); //HAL_Delay(800); // 916522 cycles

+  PRG(0x4025) = 0x27; // start motor

+  PRG(0x4025) = 0x25; // unreset

+

+  delay_kilo_clock(268); //HAL_Delay(250); // 268531 cycles

+  /*

+   uint8_t ext = PRG(0x4033);

+   if (ext >> 7)

+   {

+   PRG(0x4025) = 0x26; // reset, stop

+   comm_start(COMMAND_FDS_BATTERY_LOW, 0);

+   return;

+   }

+   */

+  PRG(0x4025) = 0x26; // reset

+  PRG(0x4025) = 0x27; // start motor

+  PRG(0x4025) = 0x25; // unreset

 

   // waiting until drive is rewinded

+  start_time = HAL_GetTick();

   while (1)

   {

     status = PRG(0x4032);

     if (!(status & 2))

       break; // ready

+    // timeout 15 secs

+    if (HAL_GetTick() - start_time >= 15000)

+    {

+      PRG(0x4025) = 0x26; // reset, stop

+      comm_start(COMMAND_FDS_TIMEOUT, 0);

+      return;

+    }

   }

 

-  HAL_Delay(FDS_PAUSE_BEFORE_FIRST_BLOCK); // 486974 cycles

+  led_cyan();

 

-  led_green();

-  if (start_block == 0)

-    comm_start(COMMAND_FDS_READ_RESULT_BLOCK, 58);

-  PRG(0x4025) = 0x6D; // start transfer

-  PRG(0x4025) = 0xED; // enable IRQ

-  for (b = 0; b < 56; b++)

+  // disk info block

+  if (block_write_count && (current_block == block_write_ids[current_writing_block]))

   {

-    while (!IRQ_FIRED)

-    {

-      // waiting for interrupt

-    }

-    uint8_t data = PRG(0x4031);

-    //PRG(0x4024) = 0xFF; // clear interrupt

-    // status read also clears interrupt

-    status = PRG(0x4030);

-    end_of_head |= (status >> 6) & 1;

-    if (start_block == 0)

-      comm_send_byte(data);

-    while (IRQ_FIRED)

-    {

-      // is interrupt flag cleared?

-    }

-  }

-  PRG(0x4025) = 0xED; // enable CRC control

-  while (!IRQ_FIRED)

-    ; // waiting for interrupt

-  PRG(0x4031);

-  PRG(0x4024) = 0xFF; // clear interrupt

-  while (IRQ_FIRED)

-    ; // is interrupt flag cleared?

-  status = PRG(0x4030);

-  end_of_head |= (status >> 6) & 1;

-  if (start_block == 0)

+    uint16_t write_length = write_lengths[current_writing_block];

+    if (!write_fds_block(write_data, write_length, 580000))

+      return;

+    write_data += write_length;

+    current_writing_block++;

+    block_write_count--;

+  } else

   {

-    comm_send_byte(((status >> 4) & 1) ^ 1); // CRC check result

-    comm_send_byte(end_of_head); // end of head meet?

+    //HAL_Delay(FDS_PAUSE_BEFORE_FIRST_BLOCK); // 486974 cycles

+    if (!read_fds_block_send(56, (current_block >= block_read_start) && block_read_count, &crc_ok, &end_of_head, 0, 486974))

+      return;

   }

+  if (block_read_count) block_read_count--;

   current_block++;

 

-  // reading file amount block

-  if (!end_of_head && ((start_block + block_count > current_block) || (block_count = 0)))

+  if (crc_ok && !end_of_head && (block_read_count || block_write_count))

   {

-    PRG(0x4025) = 0x2D; // motor on without transfer

-    // waiting until drive is ready

-    while (1)

+    // file amount block

+    if (block_write_count && (current_block == block_write_ids[current_writing_block]))

     {

-      status = PRG(0x4032);

-      if (!(status & 2))

-        break; // ready

-    }

-    HAL_Delay(FDS_PAUSE_BETWEEN_BLOCKS); // 9026 cycles

-    if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-      comm_start(COMMAND_FDS_READ_RESULT_BLOCK, 4);

-    PRG(0x4025) = 0x6D; // start transfer

-    PRG(0x4025) = 0xED; // enable IRQ

-    for (b = 0; b < 2; b++)

+      uint16_t write_length = write_lengths[current_writing_block];

+      if (!write_fds_block(write_data, write_length, 17917))

+        return;

+      write_data += write_length;

+      current_writing_block++;

+      block_write_count--;

+    } else

     {

-      while (!IRQ_FIRED)

-        ; // waiting for interrupt

-      uint8_t data = PRG(0x4031);

-      //PRG(0x4024) = 0xFF; // clear interrupt

-      // status read also clears interrupt

-      status = PRG(0x4030);

-      end_of_head |= (status >> 6) & 1;

-      if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-        comm_send_byte(data);

-      while (IRQ_FIRED)

-      {

-        // is interrupt flag cleared?

-      }

-    }

-    PRG(0x4025) = 0xED; // enable CRC control

-    while (!IRQ_FIRED)

-    {

-      // waiting for interrupt

-    }

-    PRG(0x4031);

-    PRG(0x4024) = 0xFF; // clear interrupt

-    while (IRQ_FIRED)

-      ; // is interrupt flag cleared?

-    status = PRG(0x4030);

-    end_of_head |= (status >> 6) & 1;

-    if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-    {

-      comm_send_byte(((status >> 4) & 1) ^ 1); // CRC check result

-      comm_send_byte(end_of_head); // end of head meet?

+      //delay_clock(9026); //HAL_Delay(FDS_PAUSE_BETWEEN_BLOCKS); // 9026 cycles

+      if (!read_fds_block_send(2, (current_block >= block_read_start) && block_read_count, &crc_ok, &end_of_head, 0, 9026))

+        return;

     }

+    if (block_read_count) block_read_count--;

     current_block++;

   }

 

-  while (!end_of_head && ((start_block + block_count > current_block) || (block_count = 0)))

+  while (crc_ok && !end_of_head && (block_read_count || block_write_count))

   {

-    // reading file header block

+    // file header block

     uint16_t file_size = 0; // size of the next file

-

-    PRG(0x4025) = 0x2D; // motor on without transfer

-    // waiting until drive is ready

-    while (1)

-    {

-      status = PRG(0x4032);

-      if (!(status & 2))

-        break; // ready

-    }

-    HAL_Delay(FDS_PAUSE_BETWEEN_BLOCKS); // 9026 cycles

-    if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-      comm_start(COMMAND_FDS_READ_RESULT_BLOCK, 18);

-    PRG(0x4025) = 0x6D; // start transfer

-    PRG(0x4025) = 0xED; // enable IRQ

-    for (b = 0; b < 16; b++)

+    if (block_write_count && (current_block == block_write_ids[current_writing_block]))

     {

-      while (!IRQ_FIRED)

-        ; // waiting for interrupt

-      uint8_t data = PRG(0x4031);

-      //PRG(0x4024) = 0xFF; // clear interrupt

-      // status read also clears interrupt

-      status = PRG(0x4030);

-      end_of_head |= (status >> 6) & 1;

-      if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-        comm_send_byte(data);

-      if (b == 13)

-        file_size |= data;

-      else if (b == 14)

-        file_size |= data << 8;

-      while (IRQ_FIRED)

-        ; // is interrupt flag cleared?

-    }

-    PRG(0x4025) = 0xED; // enable CRC control

-    while (!IRQ_FIRED)

+      uint16_t write_length = write_lengths[current_writing_block];

+      if (!write_fds_block(write_data, write_length, 17917))

+        return;

+      write_data += write_length;

+      current_writing_block++;

+      block_write_count--;

+    } else

     {

-      // waiting for interrupt

-    }

-    PRG(0x4031);

-    PRG(0x4024) = 0xFF; // clear interrupt

-    while (IRQ_FIRED)

-    {

-      // is interrupt flag cleared?

-    }

-    status = PRG(0x4030);

-    end_of_head |= (status >> 6) & 1;

-    if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-    {

-      comm_send_byte(((status >> 4) & 1) ^ 1); // CRC check result

-      comm_send_byte(end_of_head); // end of head meet?

+      //delay_clock(9026); //HAL_Delay(FDS_PAUSE_BETWEEN_BLOCKS); // 9026 cycles

+      if (!read_fds_block_send(16, (current_block >= block_read_start) && block_read_count, &crc_ok, &end_of_head, &file_size, 9026))

+        return;

     }

+    if (block_read_count) block_read_count--;

     current_block++;

 

-    // reading file data

-    if (!end_of_head && ((start_block + block_count > current_block) || (block_count = 0)))

+    if (crc_ok && !end_of_head && (block_read_count || block_write_count))

     {

-      PRG(0x4025) = 0x2D; // motor on without transfer

-      // waiting until drive is ready

-      while (1)

-      {

-        status = PRG(0x4032);

-        if (!(status & 2))

-          break; // ready

-      }

-      HAL_Delay(FDS_PAUSE_BETWEEN_BLOCKS); // 9026 cycles

-      if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-        comm_start(COMMAND_FDS_READ_RESULT_BLOCK, file_size + 3);

-      PRG(0x4025) = 0x6D; // start transfer

-      PRG(0x4025) = 0xED; // enable IRQ

-      for (b = 0; b < file_size + 1; b++)

+      // file data block

+      if (block_write_count && (current_block == block_write_ids[current_writing_block]))

       {

-        while (!IRQ_FIRED)

-          ; // waiting for interrupt

-        uint8_t data = PRG(0x4031);

-        //PRG(0x4024) = 0xFF; // clear interrupt

-        // status read also clears interrupt

-        status = PRG(0x4030);

-        end_of_head |= (status >> 6) & 1;

-        if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

-          comm_send_byte(data);

-        while (IRQ_FIRED)

-          ; // is interrupt flag cleared?

-      }

-      PRG(0x4025) = 0xED; // enable CRC control

-      while (!IRQ_FIRED)

-      {

-        // waiting for interrupt

-      }

-      PRG(0x4031);

-      PRG(0x4024) = 0xFF; // clear interrupt

-      while (IRQ_FIRED)

-      {

-        // is interrupt flag cleared?

-      }

-      status = PRG(0x4030);

-      end_of_head |= (status >> 6) & 1;

-      if ((current_block >= start_block) && ((current_block < start_block + block_count) || (block_count == 0)))

+        uint16_t write_length = write_lengths[current_writing_block];

+        if (!write_fds_block(write_data, write_length, 17917))

+          return;

+        write_data += write_length;

+        current_writing_block++;

+        block_write_count--;

+      } else

       {

-        comm_send_byte(((status >> 4) & 1) ^ 1); // CRC check result

-        comm_send_byte(end_of_head); // end of head meet?

+        //delay_clock(9026); //HAL_Delay(FDS_PAUSE_BETWEEN_BLOCKS); // 9026 cycles

+        if (!read_fds_block_send(file_size + 1, (current_block >= block_read_start) && block_read_count, &crc_ok, &end_of_head, 0, 9026))

+          return;

       }

+      if (block_read_count) block_read_count--;

       current_block++;

     }

   }

 

   PRG(0x4025) = 0x26; // reset, stop

 

+  HAL_Delay(50);

+  if (current_writing_block && !block_write_count && !block_read_count)

+  {

+    comm_start(COMMAND_FDS_WRITE_DONE, 0);

+    return;

+  }

   comm_start(COMMAND_FDS_READ_RESULT_END, 0);

 }

 

diff --git a/STM32/Core/Src/led.c b/STM32/Core/Src/led.c
index 625e830..544a05a 100644
--- a/STM32/Core/Src/led.c
+++ b/STM32/Core/Src/led.c
@@ -140,6 +140,11 @@ void led_magenta()
   set_led_color(0x80, 0x00, 0x80);

 }

 

+void led_cyan()

+{

+  set_led_color(0x00, 0x80, 0x80);

+}

+

 void led_idle()

 {

   if (idle_timer_start + 5000 < HAL_GetTick())

diff --git a/STM32/Core/Src/main.c b/STM32/Core/Src/main.c
index 12bb26e..e7f2cf0 100644
--- a/STM32/Core/Src/main.c
+++ b/STM32/Core/Src/main.c
@@ -23,6 +23,7 @@
 

 /* Private includes ----------------------------------------------------------*/

 /* USER CODE BEGIN Includes */

+#include <stdio.h>

 #include "dumper.h"

 #include "comm.h"

 #include "led.h"

@@ -45,6 +46,8 @@
 /* Private variables ---------------------------------------------------------*/

 TIM_HandleTypeDef htim1;

 TIM_HandleTypeDef htim2;

+TIM_HandleTypeDef htim3;

+TIM_HandleTypeDef htim4;

 TIM_HandleTypeDef htim5;

 DMA_HandleTypeDef hdma_tim5_ch3_up;

 

@@ -64,6 +67,8 @@ static void MX_FSMC_Init(void);
 static void MX_TIM2_Init(void);

 static void MX_TIM5_Init(void);

 static void MX_TIM1_Init(void);

+static void MX_TIM3_Init(void);

+static void MX_TIM4_Init(void);

 /* USER CODE BEGIN PFP */

 

 /* USER CODE END PFP */

@@ -81,9 +86,9 @@ int _write(int file, char *ptr, int len)
 /* USER CODE END 0 */

 

 /**

-  * @brief  The application entry point.

-  * @retval int

-  */

+ * @brief  The application entry point.

+ * @retval int

+ */

 int main(void)

 {

   /* USER CODE BEGIN 1 */

@@ -114,11 +119,17 @@ int main(void)
   MX_TIM2_Init();

   MX_TIM5_Init();

   MX_TIM1_Init();

+  MX_TIM3_Init();

+  MX_TIM4_Init();

   /* USER CODE BEGIN 2 */

   // Microsecond counter

   HAL_TIM_Base_Start(&htim1);

   // M2 PWM

   HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);

+  // 1000*M2 clock counter (slave of htim2 with /1000 prescaler)

+  HAL_TIM_Base_Start(&htim3);

+  // M2 clock counter (slave of htim2)

+  HAL_TIM_Base_Start(&htim4);

   comm_init();

   printf("Started.\n");

   /* USER CODE END 2 */

@@ -136,15 +147,16 @@ int main(void)
     if (comm_recv_done)

     {

       comm_recv_done = 0;

+      printf("Command: %02X\n", comm_recv_command);

       switch (comm_recv_command)

       {

       case COMMAND_PRG_INIT:

         comm_start(COMMAND_PRG_STARTED, 5);

         comm_send_byte(PROTOCOL_VERSION);

-        comm_send_byte(SEND_BUFFER & 0xFF);

-        comm_send_byte((SEND_BUFFER >> 8) & 0xFF);

-        comm_send_byte(RECV_BUFFER & 0xFF);

-        comm_send_byte((RECV_BUFFER >> 8) & 0xFF);

+        comm_send_byte(0xFF);

+        comm_send_byte(0xFF); // unlimited send buffer

+        comm_send_byte((RECV_BUFFER_SIZE - 4) & 0xFF);

+        comm_send_byte(((RECV_BUFFER_SIZE - 4) >> 8) & 0xFF);

         break;

 

       case COMMAND_PRG_READ_REQUEST:

@@ -207,7 +219,12 @@ int main(void)
         break;

 

       case COMMAND_FDS_READ_REQUEST:

-        read_fds_send(recv_buffer[0], recv_buffer[1]);

+        fds_transfer(recv_buffer[0], recv_buffer[1], 0, 0, 0, 0);

+        break;

+

+      case COMMAND_FDS_WRITE_REQUEST:

+        fds_transfer(0, 0, recv_buffer[0], (uint8_t*) &recv_buffer[1], (uint16_t*) &recv_buffer[1 + recv_buffer[0]],

+            (uint8_t*) &recv_buffer[1 + recv_buffer[0] + recv_buffer[0] * 2]);

         break;

 

       case COMMAND_MIRRORING_REQUEST:

@@ -222,6 +239,7 @@ int main(void)
          */

       }

 

+      printf("Command done\n");

       led_off();

     }

     /* USER CODE END WHILE */

@@ -232,18 +250,18 @@ int main(void)
 }

 

 /**

-  * @brief System Clock Configuration

-  * @retval None

-  */

+ * @brief System Clock Configuration

+ * @retval None

+ */

 void SystemClock_Config(void)

 {

-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};

-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };

+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };

+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };

 

   /** Initializes the RCC Oscillators according to the specified parameters

-  * in the RCC_OscInitTypeDef structure.

-  */

+   * in the RCC_OscInitTypeDef structure.

+   */

   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

   RCC_OscInitStruct.HSEState = RCC_HSE_ON;

   RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;

@@ -256,9 +274,8 @@ void SystemClock_Config(void)
     Error_Handler();

   }

   /** Initializes the CPU, AHB and APB buses clocks

-  */

-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;

+   */

+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;

   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;

@@ -278,10 +295,10 @@ void SystemClock_Config(void)
 }

 

 /**

-  * @brief TIM1 Initialization Function

-  * @param None

-  * @retval None

-  */

+ * @brief TIM1 Initialization Function

+ * @param None

+ * @retval None

+ */

 static void MX_TIM1_Init(void)

 {

 

@@ -289,8 +306,8 @@ static void MX_TIM1_Init(void)
 

   /* USER CODE END TIM1_Init 0 */

 

-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};

-  TIM_MasterConfigTypeDef sMasterConfig = {0};

+  TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };

+  TIM_MasterConfigTypeDef sMasterConfig = { 0 };

 

   /* USER CODE BEGIN TIM1_Init 1 */

 

@@ -324,10 +341,10 @@ static void MX_TIM1_Init(void)
 }

 

 /**

-  * @brief TIM2 Initialization Function

-  * @param None

-  * @retval None

-  */

+ * @brief TIM2 Initialization Function

+ * @param None

+ * @retval None

+ */

 static void MX_TIM2_Init(void)

 {

 

@@ -335,9 +352,9 @@ static void MX_TIM2_Init(void)
 

   /* USER CODE END TIM2_Init 0 */

 

-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};

-  TIM_MasterConfigTypeDef sMasterConfig = {0};

-  TIM_OC_InitTypeDef sConfigOC = {0};

+  TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };

+  TIM_MasterConfigTypeDef sMasterConfig = { 0 };

+  TIM_OC_InitTypeDef sConfigOC = { 0 };

 

   /* USER CODE BEGIN TIM2_Init 1 */

 

@@ -361,7 +378,7 @@ static void MX_TIM2_Init(void)
   {

     Error_Handler();

   }

-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;

+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;

   sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;

   if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)

   {

@@ -383,10 +400,102 @@ static void MX_TIM2_Init(void)
 }

 

 /**

-  * @brief TIM5 Initialization Function

-  * @param None

-  * @retval None

-  */

+ * @brief TIM3 Initialization Function

+ * @param None

+ * @retval None

+ */

+static void MX_TIM3_Init(void)

+{

+

+  /* USER CODE BEGIN TIM3_Init 0 */

+

+  /* USER CODE END TIM3_Init 0 */

+

+  TIM_SlaveConfigTypeDef sSlaveConfig = { 0 };

+  TIM_MasterConfigTypeDef sMasterConfig = { 0 };

+

+  /* USER CODE BEGIN TIM3_Init 1 */

+

+  /* USER CODE END TIM3_Init 1 */

+  htim3.Instance = TIM3;

+  htim3.Init.Prescaler = 999;

+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;

+  htim3.Init.Period = 65535;

+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;

+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;

+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)

+  {

+    Error_Handler();

+  }

+  sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1;

+  sSlaveConfig.InputTrigger = TIM_TS_ITR1;

+  if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)

+  {

+    Error_Handler();

+  }

+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;

+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;

+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)

+  {

+    Error_Handler();

+  }

+  /* USER CODE BEGIN TIM3_Init 2 */

+

+  /* USER CODE END TIM3_Init 2 */

+

+}

+

+/**

+ * @brief TIM4 Initialization Function

+ * @param None

+ * @retval None

+ */

+static void MX_TIM4_Init(void)

+{

+

+  /* USER CODE BEGIN TIM4_Init 0 */

+

+  /* USER CODE END TIM4_Init 0 */

+

+  TIM_SlaveConfigTypeDef sSlaveConfig = { 0 };

+  TIM_MasterConfigTypeDef sMasterConfig = { 0 };

+

+  /* USER CODE BEGIN TIM4_Init 1 */

+

+  /* USER CODE END TIM4_Init 1 */

+  htim4.Instance = TIM4;

+  htim4.Init.Prescaler = 0;

+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;

+  htim4.Init.Period = 65535;

+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;

+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;

+  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)

+  {

+    Error_Handler();

+  }

+  sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1;

+  sSlaveConfig.InputTrigger = TIM_TS_ITR1;

+  if (HAL_TIM_SlaveConfigSynchro(&htim4, &sSlaveConfig) != HAL_OK)

+  {

+    Error_Handler();

+  }

+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;

+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;

+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)

+  {

+    Error_Handler();

+  }

+  /* USER CODE BEGIN TIM4_Init 2 */

+

+  /* USER CODE END TIM4_Init 2 */

+

+}

+

+/**

+ * @brief TIM5 Initialization Function

+ * @param None

+ * @retval None

+ */

 static void MX_TIM5_Init(void)

 {

 

@@ -394,9 +503,9 @@ static void MX_TIM5_Init(void)
 

   /* USER CODE END TIM5_Init 0 */

 

-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};

-  TIM_MasterConfigTypeDef sMasterConfig = {0};

-  TIM_OC_InitTypeDef sConfigOC = {0};

+  TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };

+  TIM_MasterConfigTypeDef sMasterConfig = { 0 };

+  TIM_OC_InitTypeDef sConfigOC = { 0 };

 

   /* USER CODE BEGIN TIM5_Init 1 */

 

@@ -442,10 +551,10 @@ static void MX_TIM5_Init(void)
 }

 

 /**

-  * Enable DMA controller clock

-  * Configure DMA for memory to memory transfers

-  *   hdma_memtomem_dma1_channel1

-  */

+ * Enable DMA controller clock

+ * Configure DMA for memory to memory transfers

+ *   hdma_memtomem_dma1_channel1

+ */

 static void MX_DMA_Init(void)

 {

 

@@ -464,7 +573,7 @@ static void MX_DMA_Init(void)
   hdma_memtomem_dma1_channel1.Init.Priority = DMA_PRIORITY_VERY_HIGH;

   if (HAL_DMA_Init(&hdma_memtomem_dma1_channel1) != HAL_OK)

   {

-    Error_Handler( );

+    Error_Handler();

   }

 

   /* DMA interrupt init */

@@ -478,13 +587,13 @@ static void MX_DMA_Init(void)
 }

 

 /**

-  * @brief GPIO Initialization Function

-  * @param None

-  * @retval None

-  */

+ * @brief GPIO Initialization Function

+ * @param None

+ * @retval None

+ */

 static void MX_GPIO_Init(void)

 {

-  GPIO_InitTypeDef GPIO_InitStruct = {0};

+  GPIO_InitTypeDef GPIO_InitStruct = { 0 };

 

   /* GPIO Ports Clock Enable */

   __HAL_RCC_GPIOF_CLK_ENABLE();

@@ -514,7 +623,7 @@ static void MX_GPIO_Init(void)
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

 

   /*Configure GPIO pins : CIRAM_CE_Pin CIRAM_A10_Pin */

-  GPIO_InitStruct.Pin = CIRAM_CE_Pin|CIRAM_A10_Pin;

+  GPIO_InitStruct.Pin = CIRAM_CE_Pin | CIRAM_A10_Pin;

   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;

   GPIO_InitStruct.Pull = GPIO_NOPULL;

   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

@@ -542,14 +651,14 @@ static void MX_FSMC_Init(void)
 

   /* USER CODE END FSMC_Init 0 */

 

-  FSMC_NORSRAM_TimingTypeDef Timing = {0};

+  FSMC_NORSRAM_TimingTypeDef Timing = { 0 };

 

   /* USER CODE BEGIN FSMC_Init 1 */

 

   /* USER CODE END FSMC_Init 1 */

 

   /** Perform the SRAM1 memory initialization sequence

-  */

+   */

   hsram1.Instance = FSMC_NORSRAM_DEVICE;

   hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;

   /* hsram1.Init */

@@ -578,11 +687,11 @@ static void MX_FSMC_Init(void)
 

   if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)

   {

-    Error_Handler( );

+    Error_Handler();

   }

 

   /** Perform the SRAM2 memory initialization sequence

-  */

+   */

   hsram2.Instance = FSMC_NORSRAM_DEVICE;

   hsram2.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;

   /* hsram2.Init */

@@ -611,11 +720,11 @@ static void MX_FSMC_Init(void)
 

   if (HAL_SRAM_Init(&hsram2, &Timing, NULL) != HAL_OK)

   {

-    Error_Handler( );

+    Error_Handler();

   }

 

   /** Disconnect NADV

-  */

+   */

 

   __HAL_AFIO_FSMCNADV_DISCONNECTED();

 

@@ -629,9 +738,9 @@ static void MX_FSMC_Init(void)
 /* USER CODE END 4 */

 

 /**

-  * @brief  This function is executed in case of error occurrence.

-  * @retval None

-  */

+ * @brief  This function is executed in case of error occurrence.

+ * @retval None

+ */

 void Error_Handler(void)

 {

   /* USER CODE BEGIN Error_Handler_Debug */

diff --git a/STM32/Core/Src/stm32f1xx_hal_msp.c b/STM32/Core/Src/stm32f1xx_hal_msp.c
index 9d6fe12..1011f31 100644
--- a/STM32/Core/Src/stm32f1xx_hal_msp.c
+++ b/STM32/Core/Src/stm32f1xx_hal_msp.c
@@ -114,6 +114,28 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
 

   /* USER CODE END TIM2_MspInit 1 */

   }

+  else if(htim_base->Instance==TIM3)

+  {

+  /* USER CODE BEGIN TIM3_MspInit 0 */

+

+  /* USER CODE END TIM3_MspInit 0 */

+    /* Peripheral clock enable */

+    __HAL_RCC_TIM3_CLK_ENABLE();

+  /* USER CODE BEGIN TIM3_MspInit 1 */

+

+  /* USER CODE END TIM3_MspInit 1 */

+  }

+  else if(htim_base->Instance==TIM4)

+  {

+  /* USER CODE BEGIN TIM4_MspInit 0 */

+

+  /* USER CODE END TIM4_MspInit 0 */

+    /* Peripheral clock enable */

+    __HAL_RCC_TIM4_CLK_ENABLE();

+  /* USER CODE BEGIN TIM4_MspInit 1 */

+

+  /* USER CODE END TIM4_MspInit 1 */

+  }

   else if(htim_base->Instance==TIM5)

   {

   /* USER CODE BEGIN TIM5_MspInit 0 */

@@ -221,6 +243,28 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
 

   /* USER CODE END TIM2_MspDeInit 1 */

   }

+  else if(htim_base->Instance==TIM3)

+  {

+  /* USER CODE BEGIN TIM3_MspDeInit 0 */

+

+  /* USER CODE END TIM3_MspDeInit 0 */

+    /* Peripheral clock disable */

+    __HAL_RCC_TIM3_CLK_DISABLE();

+  /* USER CODE BEGIN TIM3_MspDeInit 1 */

+

+  /* USER CODE END TIM3_MspDeInit 1 */

+  }

+  else if(htim_base->Instance==TIM4)

+  {

+  /* USER CODE BEGIN TIM4_MspDeInit 0 */

+

+  /* USER CODE END TIM4_MspDeInit 0 */

+    /* Peripheral clock disable */

+    __HAL_RCC_TIM4_CLK_DISABLE();

+  /* USER CODE BEGIN TIM4_MspDeInit 1 */

+

+  /* USER CODE END TIM4_MspDeInit 1 */

+  }

   else if(htim_base->Instance==TIM5)

   {

   /* USER CODE BEGIN TIM5_MspDeInit 0 */

diff --git a/STM32/FamicomDumper.ioc b/STM32/FamicomDumper.ioc
index ccb7914..83e2476 100644
--- a/STM32/FamicomDumper.ioc
+++ b/STM32/FamicomDumper.ioc
@@ -38,15 +38,17 @@ KeepUserPlacement=false
 Mcu.Family=STM32F1

 Mcu.IP0=DMA

 Mcu.IP1=FSMC

+Mcu.IP10=USB

+Mcu.IP11=USB_DEVICE

 Mcu.IP2=NVIC

 Mcu.IP3=RCC

 Mcu.IP4=SYS

 Mcu.IP5=TIM1

 Mcu.IP6=TIM2

-Mcu.IP7=TIM5

-Mcu.IP8=USB

-Mcu.IP9=USB_DEVICE

-Mcu.IPNb=10

+Mcu.IP7=TIM3

+Mcu.IP8=TIM4

+Mcu.IP9=TIM5

+Mcu.IPNb=12

 Mcu.Name=STM32F103Z(C-D-E)Tx

 Mcu.Package=LQFP144

 Mcu.Pin0=PF0

@@ -91,14 +93,18 @@ Mcu.Pin43=PE0
 Mcu.Pin44=VP_SYS_VS_Systick

 Mcu.Pin45=VP_TIM1_VS_ClockSourceINT

 Mcu.Pin46=VP_TIM2_VS_ClockSourceINT

-Mcu.Pin47=VP_TIM5_VS_ClockSourceINT

-Mcu.Pin48=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS

+Mcu.Pin47=VP_TIM3_VS_ControllerModeClock

+Mcu.Pin48=VP_TIM3_VS_ClockSourceITR

+Mcu.Pin49=VP_TIM4_VS_ControllerModeClock

 Mcu.Pin5=PF5

+Mcu.Pin50=VP_TIM4_VS_ClockSourceITR

+Mcu.Pin51=VP_TIM5_VS_ClockSourceINT

+Mcu.Pin52=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS

 Mcu.Pin6=OSC_IN

 Mcu.Pin7=OSC_OUT

 Mcu.Pin8=PA0-WKUP

 Mcu.Pin9=PA1

-Mcu.PinsNb=49

+Mcu.PinsNb=53

 Mcu.ThirdPartyNb=0

 Mcu.UserConstants=

 Mcu.UserName=STM32F103ZETx

@@ -214,14 +220,14 @@ ProjectManager.MainLocation=Core/Src
 ProjectManager.NoMain=false

 ProjectManager.PreviousToolchain=STM32CubeIDE

 ProjectManager.ProjectBuild=false

-ProjectManager.ProjectFileName=STM32.ioc

-ProjectManager.ProjectName=STM32

+ProjectManager.ProjectFileName=FamicomDumper.ioc

+ProjectManager.ProjectName=FamicomDumper

 ProjectManager.RegisterCallBack=

 ProjectManager.StackSize=0x400

 ProjectManager.TargetToolchain=STM32CubeIDE

 ProjectManager.ToolChainLocation=

 ProjectManager.UnderRoot=true

-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_FSMC_Init-FSMC-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM5_Init-TIM5-false-HAL-true,8-MX_TIM1_Init-TIM1-false-HAL-true

+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_FSMC_Init-FSMC-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM5_Init-TIM5-false-HAL-true,8-MX_TIM1_Init-TIM1-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true

 RCC.ADCFreqValue=36000000

 RCC.AHBFreq_Value=72000000

 RCC.APB1CLKDivider=RCC_HCLK_DIV2

@@ -336,10 +342,13 @@ SH.S_TIM5_CH3.ConfNb=1
 TIM1.IPParameters=Prescaler

 TIM1.Prescaler=71

 TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1

-TIM2.IPParameters=Channel-PWM Generation1 CH1,Period,Pulse-PWM Generation1 CH1,Prescaler

+TIM2.IPParameters=Channel-PWM Generation1 CH1,Period,Pulse-PWM Generation1 CH1,Prescaler,TIM_MasterOutputTrigger

 TIM2.Period=39

 TIM2.Prescaler=0

 TIM2.Pulse-PWM\ Generation1\ CH1=24

+TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE

+TIM3.IPParameters=Prescaler

+TIM3.Prescaler=999

 TIM5.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3

 TIM5.IPParameters=Channel-PWM Generation3 CH3,Period,Pulse-PWM Generation3 CH3

 TIM5.Period=89

@@ -358,6 +367,14 @@ VP_TIM1_VS_ClockSourceINT.Mode=Internal
 VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT

 VP_TIM2_VS_ClockSourceINT.Mode=Internal

 VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT

+VP_TIM3_VS_ClockSourceITR.Mode=TriggerSource_ITR1

+VP_TIM3_VS_ClockSourceITR.Signal=TIM3_VS_ClockSourceITR

+VP_TIM3_VS_ControllerModeClock.Mode=Clock Mode

+VP_TIM3_VS_ControllerModeClock.Signal=TIM3_VS_ControllerModeClock

+VP_TIM4_VS_ClockSourceITR.Mode=TriggerSource_ITR1

+VP_TIM4_VS_ClockSourceITR.Signal=TIM4_VS_ClockSourceITR

+VP_TIM4_VS_ControllerModeClock.Mode=Clock Mode

+VP_TIM4_VS_ControllerModeClock.Signal=TIM4_VS_ControllerModeClock

 VP_TIM5_VS_ClockSourceINT.Mode=Internal

 VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT

 VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS

diff --git a/STM32/STM32F103ZETX_FLASH.ld b/STM32/STM32F103ZETX_FLASH.ld
index d38bd2f..71d1695 100644
--- a/STM32/STM32F103ZETX_FLASH.ld
+++ b/STM32/STM32F103ZETX_FLASH.ld
@@ -30,8 +30,8 @@ ENTRY(Reset_Handler)
 /* Highest address of the user mode stack */
 _estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
 
-_Min_Heap_Size = 0x200;	/* required amount of heap  */
-_Min_Stack_Size = 0x400;	/* required amount of stack */
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
 
 /* Memories definition */
 MEMORY
diff --git a/STM32/USB_DEVICE/App/usbd_cdc_if.c b/STM32/USB_DEVICE/App/usbd_cdc_if.c
index a360145..e9a164c 100644
--- a/STM32/USB_DEVICE/App/usbd_cdc_if.c
+++ b/STM32/USB_DEVICE/App/usbd_cdc_if.c
@@ -23,7 +23,7 @@
 #include "usbd_cdc_if.h"

 

 /* USER CODE BEGIN INCLUDE */

-

+#include "comm.h"

 /* USER CODE END INCLUDE */

 

 /* Private typedef -----------------------------------------------------------*/

@@ -262,6 +262,9 @@ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
   /* USER CODE BEGIN 6 */

   USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);

   USBD_CDC_ReceivePacket(&hUsbDeviceFS);

+  int l = *Len;

+  for (int i = 0; i < l; i++)

+    comm_proceed(Buf[i]);

   return (USBD_OK);

   /* USER CODE END 6 */

 }