diff options
Diffstat (limited to 'FamicomDumper/Core/Src/stm32f1xx_hal_msp.c')
| -rw-r--r-- | FamicomDumper/Core/Src/stm32f1xx_hal_msp.c | 450 |
1 files changed, 450 insertions, 0 deletions
diff --git a/FamicomDumper/Core/Src/stm32f1xx_hal_msp.c b/FamicomDumper/Core/Src/stm32f1xx_hal_msp.c new file mode 100644 index 0000000..0d611df --- /dev/null +++ b/FamicomDumper/Core/Src/stm32f1xx_hal_msp.c @@ -0,0 +1,450 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : stm32f1xx_hal_msp.c
+ * Description : This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_tim5_ch3_up;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+ /**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_AFIO_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ */
+ __HAL_AFIO_REMAP_SWJ_NOJTAG();
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ if(htim_base->Instance==TIM1)
+ {
+ /* USER CODE BEGIN TIM1_MspInit 0 */
+
+ /* USER CODE END TIM1_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM1_CLK_ENABLE();
+ /* USER CODE BEGIN TIM1_MspInit 1 */
+
+ /* USER CODE END TIM1_MspInit 1 */
+ }
+ else if(htim_base->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspInit 0 */
+
+ /* USER CODE END TIM2_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM2_CLK_ENABLE();
+ /* USER CODE BEGIN TIM2_MspInit 1 */
+
+ /* USER CODE END TIM2_MspInit 1 */
+ }
+ else if(htim_base->Instance==TIM3)
+ {
+ /* USER CODE BEGIN TIM3_MspInit 0 */
+
+ /* USER CODE END TIM3_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM3_CLK_ENABLE();
+ /* USER CODE BEGIN TIM3_MspInit 1 */
+
+ /* USER CODE END TIM3_MspInit 1 */
+ }
+ else if(htim_base->Instance==TIM4)
+ {
+ /* USER CODE BEGIN TIM4_MspInit 0 */
+
+ /* USER CODE END TIM4_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM4_CLK_ENABLE();
+ /* USER CODE BEGIN TIM4_MspInit 1 */
+
+ /* USER CODE END TIM4_MspInit 1 */
+ }
+ else if(htim_base->Instance==TIM5)
+ {
+ /* USER CODE BEGIN TIM5_MspInit 0 */
+
+ /* USER CODE END TIM5_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM5_CLK_ENABLE();
+
+ /* TIM5 DMA Init */
+ /* TIM5_CH3_UP Init */
+ hdma_tim5_ch3_up.Instance = DMA2_Channel2;
+ hdma_tim5_ch3_up.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ hdma_tim5_ch3_up.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_tim5_ch3_up.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_tim5_ch3_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+ hdma_tim5_ch3_up.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ hdma_tim5_ch3_up.Init.Mode = DMA_NORMAL;
+ hdma_tim5_ch3_up.Init.Priority = DMA_PRIORITY_VERY_HIGH;
+ if (HAL_DMA_Init(&hdma_tim5_ch3_up) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Several peripheral DMA handle pointers point to the same DMA handle.
+ Be aware that there is only one channel to perform all the requested DMAs. */
+ __HAL_LINKDMA(htim_base,hdma[TIM_DMA_ID_CC3],hdma_tim5_ch3_up);
+ __HAL_LINKDMA(htim_base,hdma[TIM_DMA_ID_UPDATE],hdma_tim5_ch3_up);
+
+ /* USER CODE BEGIN TIM5_MspInit 1 */
+
+ /* USER CODE END TIM5_MspInit 1 */
+ }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(htim->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+ /* USER CODE END TIM2_MspPostInit 0 */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**TIM2 GPIO Configuration
+ PA0-WKUP ------> TIM2_CH1
+ */
+ GPIO_InitStruct.Pin = M2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(M2_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+ /* USER CODE END TIM2_MspPostInit 1 */
+ }
+ else if(htim->Instance==TIM5)
+ {
+ /* USER CODE BEGIN TIM5_MspPostInit 0 */
+
+ /* USER CODE END TIM5_MspPostInit 0 */
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**TIM5 GPIO Configuration
+ PA2 ------> TIM5_CH3
+ */
+ GPIO_InitStruct.Pin = WS2812_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(WS2812_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM5_MspPostInit 1 */
+
+ /* USER CODE END TIM5_MspPostInit 1 */
+ }
+
+}
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+ if(htim_base->Instance==TIM1)
+ {
+ /* USER CODE BEGIN TIM1_MspDeInit 0 */
+
+ /* USER CODE END TIM1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM1_CLK_DISABLE();
+ /* USER CODE BEGIN TIM1_MspDeInit 1 */
+
+ /* USER CODE END TIM1_MspDeInit 1 */
+ }
+ else if(htim_base->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+ /* USER CODE END TIM2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM2_CLK_DISABLE();
+ /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+ /* USER CODE END TIM2_MspDeInit 1 */
+ }
+ else if(htim_base->Instance==TIM3)
+ {
+ /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+ /* USER CODE END TIM3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM3_CLK_DISABLE();
+ /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+ /* USER CODE END TIM3_MspDeInit 1 */
+ }
+ else if(htim_base->Instance==TIM4)
+ {
+ /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+ /* USER CODE END TIM4_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM4_CLK_DISABLE();
+ /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+ /* USER CODE END TIM4_MspDeInit 1 */
+ }
+ else if(htim_base->Instance==TIM5)
+ {
+ /* USER CODE BEGIN TIM5_MspDeInit 0 */
+
+ /* USER CODE END TIM5_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM5_CLK_DISABLE();
+
+ /* TIM5 DMA DeInit */
+ HAL_DMA_DeInit(htim_base->hdma[TIM_DMA_ID_CC3]);
+ HAL_DMA_DeInit(htim_base->hdma[TIM_DMA_ID_UPDATE]);
+ /* USER CODE BEGIN TIM5_MspDeInit 1 */
+
+ /* USER CODE END TIM5_MspDeInit 1 */
+ }
+
+}
+
+static uint32_t FSMC_Initialized = 0;
+
+static void HAL_FSMC_MspInit(void){
+ /* USER CODE BEGIN FSMC_MspInit 0 */
+
+ /* USER CODE END FSMC_MspInit 0 */
+ GPIO_InitTypeDef GPIO_InitStruct ={0};
+ if (FSMC_Initialized) {
+ return;
+ }
+ FSMC_Initialized = 1;
+
+ /* Peripheral clock enable */
+ __HAL_RCC_FSMC_CLK_ENABLE();
+
+ /** FSMC GPIO Configuration
+ PF0 ------> FSMC_A0
+ PF1 ------> FSMC_A1
+ PF2 ------> FSMC_A2
+ PF3 ------> FSMC_A3
+ PF4 ------> FSMC_A4
+ PF5 ------> FSMC_A5
+ PF12 ------> FSMC_A6
+ PF13 ------> FSMC_A7
+ PF14 ------> FSMC_A8
+ PF15 ------> FSMC_A9
+ PG0 ------> FSMC_A10
+ PG1 ------> FSMC_A11
+ PE7 ------> FSMC_D4
+ PE8 ------> FSMC_D5
+ PE9 ------> FSMC_D6
+ PE10 ------> FSMC_D7
+ PD14 ------> FSMC_D0
+ PD15 ------> FSMC_D1
+ PG2 ------> FSMC_A12
+ PG3 ------> FSMC_A13
+ PG4 ------> FSMC_A14
+ PG5 ------> FSMC_A15
+ PD0 ------> FSMC_D2
+ PD1 ------> FSMC_D3
+ PD4 ------> FSMC_NOE
+ PD5 ------> FSMC_NWE
+ PD6 ------> FSMC_NWAIT
+ PD7 ------> FSMC_NE1
+ PG9 ------> FSMC_NE2
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
+ |GPIO_PIN_14|GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN FSMC_MspInit 1 */
+
+ /* USER CODE END FSMC_MspInit 1 */
+}
+
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
+ /* USER CODE BEGIN SRAM_MspInit 0 */
+
+ /* USER CODE END SRAM_MspInit 0 */
+ HAL_FSMC_MspInit();
+ /* USER CODE BEGIN SRAM_MspInit 1 */
+
+ /* USER CODE END SRAM_MspInit 1 */
+}
+
+static uint32_t FSMC_DeInitialized = 0;
+
+static void HAL_FSMC_MspDeInit(void){
+ /* USER CODE BEGIN FSMC_MspDeInit 0 */
+
+ /* USER CODE END FSMC_MspDeInit 0 */
+ if (FSMC_DeInitialized) {
+ return;
+ }
+ FSMC_DeInitialized = 1;
+ /* Peripheral clock enable */
+ __HAL_RCC_FSMC_CLK_DISABLE();
+
+ /** FSMC GPIO Configuration
+ PF0 ------> FSMC_A0
+ PF1 ------> FSMC_A1
+ PF2 ------> FSMC_A2
+ PF3 ------> FSMC_A3
+ PF4 ------> FSMC_A4
+ PF5 ------> FSMC_A5
+ PF12 ------> FSMC_A6
+ PF13 ------> FSMC_A7
+ PF14 ------> FSMC_A8
+ PF15 ------> FSMC_A9
+ PG0 ------> FSMC_A10
+ PG1 ------> FSMC_A11
+ PE7 ------> FSMC_D4
+ PE8 ------> FSMC_D5
+ PE9 ------> FSMC_D6
+ PE10 ------> FSMC_D7
+ PD14 ------> FSMC_D0
+ PD15 ------> FSMC_D1
+ PG2 ------> FSMC_A12
+ PG3 ------> FSMC_A13
+ PG4 ------> FSMC_A14
+ PG5 ------> FSMC_A15
+ PD0 ------> FSMC_D2
+ PD1 ------> FSMC_D3
+ PD4 ------> FSMC_NOE
+ PD5 ------> FSMC_NWE
+ PD6 ------> FSMC_NWAIT
+ PD7 ------> FSMC_NE1
+ PG9 ------> FSMC_NE2
+ */
+ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
+ |GPIO_PIN_14|GPIO_PIN_15);
+
+ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_9);
+
+ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10);
+
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+
+ /* USER CODE BEGIN FSMC_MspDeInit 1 */
+
+ /* USER CODE END FSMC_MspDeInit 1 */
+}
+
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){
+ /* USER CODE BEGIN SRAM_MspDeInit 0 */
+
+ /* USER CODE END SRAM_MspDeInit 0 */
+ HAL_FSMC_MspDeInit();
+ /* USER CODE BEGIN SRAM_MspDeInit 1 */
+
+ /* USER CODE END SRAM_MspDeInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
|