[FL-1912, FL-1939] Sub-GHz frequency analyzer and add new protocol (#746)

* ToolBox: add manchester-decoder and manchester-encoder
* SubGhz: add new FM config cc1101
* Subghz: add protocol Kia
* SubGhz: fix receiving the last packet Nero Radio
* SubGhz: app protocol CAME Twin (TW2EE/TW4EE)
* SubGhz: add protocol CAME Atomo (AT03EV/ AT04EV)
* F7: sync with F6
* SubGhz: add frequency analyzer
* SubGhz: remove space from file name 
* SubGhz: frequency analyzer add filter and fix view
* [FL-1939] GubGhz: Frequency analyzer redesign
* SubGhz: fix incorrect subghz api call sequence in frequency analyzer worker

Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>

3 files changed, 128 insertions, 13 deletions

diff --git a/firmware/targets/f6/furi-hal/furi-hal-subghz.c b/firmware/targets/f6/furi-hal/furi-hal-subghz.c
index 2d7b1a90..02b91277 100644
--- a/firmware/targets/f6/furi-hal/furi-hal-subghz.c
+++ b/firmware/targets/f6/furi-hal/furi-hal-subghz.c
@@ -132,7 +132,7 @@ static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
     /* End  */
     {0, 0},
 };
-static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
+static const uint8_t furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs[][2] = {
 
     /* GPIO GD0 */
     {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
@@ -146,11 +146,10 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
 
     // // Modem Configuration
     {CC1101_MDMCFG0, 0x00},
-    {CC1101_MDMCFG1, 0x2},
-    {CC1101_MDMCFG2, 0x4}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
+    {CC1101_MDMCFG1, 0x02},
+    {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
     {CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
     {CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
-    //{ CC1101_DEVIATN, 0x14 }, //Deviation 4.760742 kHz
     {CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
 
     /* Main Radio Control State Machine */
@@ -188,6 +187,61 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
     /* End  */
     {0, 0},
 };
+static const uint8_t furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs[][2] = {
+
+    /* GPIO GD0 */
+    {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
+
+    /* Frequency Synthesizer Control */
+    {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
+
+    /* Packet engine */
+    {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
+    {CC1101_PKTCTRL1, 0x04},
+
+    // // Modem Configuration
+    {CC1101_MDMCFG0, 0x00},
+    {CC1101_MDMCFG1, 0x02},
+    {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
+    {CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
+    {CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
+    {CC1101_DEVIATN, 0x14}, //Deviation 4.760742 kHz
+
+    /* Main Radio Control State Machine */
+    {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
+
+    /* Frequency Offset Compensation Configuration */
+    {CC1101_FOCCFG,
+     0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
+
+    /* Automatic Gain Control */
+    {CC1101_AGCCTRL0,
+     0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
+    {CC1101_AGCCTRL1,
+     0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
+    {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
+
+    /* Wake on radio and timeouts control */
+    {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
+
+    /* Frontend configuration */
+    {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
+    {CC1101_FREND1, 0x56},
+
+    /* Frequency Synthesizer Calibration, valid for 433.92 */
+    {CC1101_FSCAL3, 0xE9},
+    {CC1101_FSCAL2, 0x2A},
+    {CC1101_FSCAL1, 0x00},
+    {CC1101_FSCAL0, 0x1F},
+
+    /* Magic f4ckery */
+    {CC1101_TEST2, 0x81}, // FIFOTHR ADC_RETENTION=1 matched value
+    {CC1101_TEST1, 0x35}, // FIFOTHR ADC_RETENTION=1 matched value
+    {CC1101_TEST0, 0x09}, // VCO selection calibration stage is disabled
+
+    /* End  */
+    {0, 0},
+};
 static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
     0x00,
     0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
@@ -282,8 +336,11 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
     } else if(preset == FuriHalSubGhzPresetOok270Async) {
         furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_270khz_async_regs);
         furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
-    } else if(preset == FuriHalSubGhzPreset2FSKAsync) {
-        furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_async_regs);
+    } else if(preset == FuriHalSubGhzPreset2FSKDev238Async) {
+        furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs);
+        furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
+    } else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
+        furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs);
         furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
     } else {
         furi_crash(NULL);
diff --git a/firmware/targets/f7/furi-hal/furi-hal-subghz.c b/firmware/targets/f7/furi-hal/furi-hal-subghz.c
index 2d7b1a90..02b91277 100644
--- a/firmware/targets/f7/furi-hal/furi-hal-subghz.c
+++ b/firmware/targets/f7/furi-hal/furi-hal-subghz.c
@@ -132,7 +132,7 @@ static const uint8_t furi_hal_subghz_preset_ook_650khz_async_regs[][2] = {
     /* End  */
     {0, 0},
 };
-static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
+static const uint8_t furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs[][2] = {
 
     /* GPIO GD0 */
     {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
@@ -146,11 +146,10 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
 
     // // Modem Configuration
     {CC1101_MDMCFG0, 0x00},
-    {CC1101_MDMCFG1, 0x2},
-    {CC1101_MDMCFG2, 0x4}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
+    {CC1101_MDMCFG1, 0x02},
+    {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
     {CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
     {CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
-    //{ CC1101_DEVIATN, 0x14 }, //Deviation 4.760742 kHz
     {CC1101_DEVIATN, 0x04}, //Deviation 2.380371 kHz
 
     /* Main Radio Control State Machine */
@@ -188,6 +187,61 @@ static const uint8_t furi_hal_subghz_preset_2fsk_async_regs[][2] = {
     /* End  */
     {0, 0},
 };
+static const uint8_t furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs[][2] = {
+
+    /* GPIO GD0 */
+    {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input
+
+    /* Frequency Synthesizer Control */
+    {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
+
+    /* Packet engine */
+    {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening
+    {CC1101_PKTCTRL1, 0x04},
+
+    // // Modem Configuration
+    {CC1101_MDMCFG0, 0x00},
+    {CC1101_MDMCFG1, 0x02},
+    {CC1101_MDMCFG2, 0x04}, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
+    {CC1101_MDMCFG3, 0x83}, // Data rate is 4.79794 kBaud
+    {CC1101_MDMCFG4, 0x67}, //Rx BW filter is 270.833333 kHz
+    {CC1101_DEVIATN, 0x14}, //Deviation 4.760742 kHz
+
+    /* Main Radio Control State Machine */
+    {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
+
+    /* Frequency Offset Compensation Configuration */
+    {CC1101_FOCCFG,
+     0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
+
+    /* Automatic Gain Control */
+    {CC1101_AGCCTRL0,
+     0x91}, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
+    {CC1101_AGCCTRL1,
+     0x00}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
+    {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
+
+    /* Wake on radio and timeouts control */
+    {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
+
+    /* Frontend configuration */
+    {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer
+    {CC1101_FREND1, 0x56},
+
+    /* Frequency Synthesizer Calibration, valid for 433.92 */
+    {CC1101_FSCAL3, 0xE9},
+    {CC1101_FSCAL2, 0x2A},
+    {CC1101_FSCAL1, 0x00},
+    {CC1101_FSCAL0, 0x1F},
+
+    /* Magic f4ckery */
+    {CC1101_TEST2, 0x81}, // FIFOTHR ADC_RETENTION=1 matched value
+    {CC1101_TEST1, 0x35}, // FIFOTHR ADC_RETENTION=1 matched value
+    {CC1101_TEST0, 0x09}, // VCO selection calibration stage is disabled
+
+    /* End  */
+    {0, 0},
+};
 static const uint8_t furi_hal_subghz_preset_ook_async_patable[8] = {
     0x00,
     0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
@@ -282,8 +336,11 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
     } else if(preset == FuriHalSubGhzPresetOok270Async) {
         furi_hal_subghz_load_registers(furi_hal_subghz_preset_ook_270khz_async_regs);
         furi_hal_subghz_load_patable(furi_hal_subghz_preset_ook_async_patable);
-    } else if(preset == FuriHalSubGhzPreset2FSKAsync) {
-        furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_async_regs);
+    } else if(preset == FuriHalSubGhzPreset2FSKDev238Async) {
+        furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_dev2_38khz_async_regs);
+        furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
+    } else if(preset == FuriHalSubGhzPreset2FSKDev476Async) {
+        furi_hal_subghz_load_registers(furi_hal_subghz_preset_2fsk_dev4_76khz_async_regs);
         furi_hal_subghz_load_patable(furi_hal_subghz_preset_2fsk_async_patable);
     } else {
         furi_crash(NULL);
diff --git a/firmware/targets/furi-hal-include/furi-hal-subghz.h b/firmware/targets/furi-hal-include/furi-hal-subghz.h
index 334cfd78..97b57e27 100644
--- a/firmware/targets/furi-hal-include/furi-hal-subghz.h
+++ b/firmware/targets/furi-hal-include/furi-hal-subghz.h
@@ -18,7 +18,8 @@ extern "C" {
 typedef enum {
     FuriHalSubGhzPresetOok270Async,     /**< OOK, bandwidth 270kHz, asynchronous */
     FuriHalSubGhzPresetOok650Async,     /**< OOK, bandwidth 650kHz, asynchronous */
-    FuriHalSubGhzPreset2FSKAsync,       /**< FM, asynchronous */
+    FuriHalSubGhzPreset2FSKDev238Async, /**< FM, deviation 2.380371 kHz, asynchronous */
+    FuriHalSubGhzPreset2FSKDev476Async, /**< FM, deviation 4.760742 kHz, asynchronous */
 } FuriHalSubGhzPreset;
 
 /** Switchable Radio Paths */