Updated to FW V1.8.3HEADmaster

14 files changed, 1825 insertions, 383 deletions

diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
index ce68992..9f62fe9 100644
--- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
+++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
@@ -9190,12 +9190,10 @@ typedef struct
 #define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */

 #define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */

 

-/******************  Bit definition for SPI_I2SCFGR register  *****************/

 #define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              

 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */

 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!< I2S mode selection */

 

-

 /******************************************************************************/

 /*                                                                            */

 /*                      Inter-integrated Circuit Interface                    */

@@ -10021,8 +10019,6 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)

-

 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -10182,40 +10178,40 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_IRQn               ADC1_2_IRQn

-#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

-#define TIM9_IRQn               TIM1_BRK_IRQn

 #define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

-#define TIM11_IRQn              TIM1_TRG_COM_IRQn

-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

+#define TIM9_IRQn               TIM1_BRK_IRQn

+#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

+#define TIM11_IRQn              TIM1_TRG_COM_IRQn

 #define TIM10_IRQn              TIM1_UP_IRQn

-#define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

 #define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

+#define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn

 #define CEC_IRQn                USBWakeUp_IRQn

 #define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn

-#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn

+#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

 

 

 /* Aliases for __IRQHandler */

 #define ADC1_IRQHandler               ADC1_2_IRQHandler

-#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

-#define TIM9_IRQHandler               TIM1_BRK_IRQHandler

 #define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

-#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM9_IRQHandler               TIM1_BRK_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

 #define TIM10_IRQHandler              TIM1_UP_IRQHandler

-#define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

+#define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler

 #define CEC_IRQHandler                USBWakeUp_IRQHandler

 #define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler

-#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler

+#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

 

 

 /**

diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
index 516b510..470d78a 100644
--- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
+++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
@@ -90,11 +90,11 @@
 #endif /* USE_HAL_DRIVER */

 

 /**

-  * @brief CMSIS Device version number V4.3.1

+  * @brief CMSIS Device version number V4.3.2

   */

 #define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */

 #define __STM32F1_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */

-#define __STM32F1_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */

+#define __STM32F1_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */

 #define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 

 #define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\

                                        |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\

diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 2063643..43cafcb 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -38,7 +38,6 @@
 #define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

 #define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

 #define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR

-

 /**

   * @}

   */

@@ -236,12 +235,12 @@
 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE

 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE

 

-#if defined(STM32G4)

-#define DAC_CHIPCONNECT_DISABLE       (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)

-#define DAC_CHIPCONNECT_ENABLE        (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)

+#if defined(STM32G4) || defined(STM32H7)

+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL

+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL

 #endif

 

-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)

+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)

 #define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID

 #define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID

 #endif

@@ -306,8 +305,22 @@
 #define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING

 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING

 

+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)

+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI

+#endif

+

 #endif /* STM32L4 */

 

+#if defined(STM32G0)

+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1

+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2

+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM

+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM

+

+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM

+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM

+#endif

+

 #if defined(STM32H7)

 

 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1

@@ -365,6 +378,9 @@
 #define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT

 #define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT

 

+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT

+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT

+

 #endif /* STM32H7 */

 

 /**

@@ -460,7 +476,9 @@
 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2

 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2

 #define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2

-#endif

+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE

+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL

+#endif /* STM32H7 */

 

 /**

   * @}

@@ -564,7 +582,14 @@
 #define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2

 #define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2

 #define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2

-#endif

+

+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \

+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)

+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS

+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS

+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS

+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */

+#endif /* STM32H7 */

 

 #define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1

 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1

@@ -622,6 +647,10 @@
 #define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable

 #define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable

 #define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset

+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A

+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B

+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL

+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL

 #endif /* STM32G4 */

 

 #if defined(STM32H7)

@@ -735,6 +764,66 @@
 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9

 #endif /* STM32H7 */

+

+#if defined(STM32F3)

+/** @brief Constants defining available sources associated to external events.

+  */

+#define HRTIM_EVENTSRC_1              (0x00000000U)

+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)

+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)

+

+/** @brief Constants defining the events that can be selected to configure the

+  *        set/reset crossbar of a timer output

+  */

+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)

+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)

+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)

+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)

+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)

+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)

+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)

+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)

+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)

+

+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)

+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)

+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)

+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)

+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)

+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)

+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)

+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)

+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)

+

+/** @brief Constants defining the event filtering applied to external events

+  *        by a timer

+  */

+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+

+/** @brief Constants defining the DLL calibration periods (in micro seconds)

+  */

+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U

+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)

+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)

+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)

+

+#endif /* STM32F3 */

 /**

   * @}

   */

@@ -874,7 +963,7 @@
 #define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0

 #define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1

 

-#if defined(STM32L1) || defined(STM32L4)

+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)

 #define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID

 #define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID

 #endif

@@ -933,7 +1022,7 @@
 /**

   * @}

   */

-

+  

 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose

   * @{

   */

@@ -965,6 +1054,16 @@
 #define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1

 #define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1

 

+#if defined(STM32H7)

+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X

+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT

+

+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1

+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2

+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3

+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL

+#endif /* STM32H7 */

+

 /**

   * @}

   */

@@ -1358,6 +1457,30 @@
 

 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY

 #define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY

+

+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)

+

+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt

+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End

+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT

+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT

+

+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt

+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End

+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT

+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT

+

+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt

+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End

+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT

+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT

+

+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt

+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End

+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT

+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT

+

+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */

 /**

   * @}

   */

@@ -1380,6 +1503,13 @@
 #endif

 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())

 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)

+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode

+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode

+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode

+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode

+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */

+

 /**

   * @}

   */

@@ -1409,16 +1539,18 @@
 

 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))

 

-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)

+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)

 #define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT

 #define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT

 #define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT

 #define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT

+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */

+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)

 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA

 #define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA

 #define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA

 #define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA

-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */

+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */

 

 #if defined(STM32F4)

 #define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT

@@ -1437,6 +1569,13 @@
 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose

   * @{

   */

+

+#if defined(STM32G0)

+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD

+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD

+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD

+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler

+#endif

 #define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD

 #define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg

 #define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown

@@ -1509,14 +1648,14 @@
 #define HAL_TIM_DMAError                                TIM_DMAError

 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt

 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt

-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)

+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)

 #define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro

 #define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT

 #define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback

 #define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent

 #define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT

 #define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA

-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4  || STM32L0 */

+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */

 /**

   * @}

   */

@@ -3112,9 +3251,8 @@
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK

 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2

 

-#if defined(STM32L4)

+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)

 #define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)

 #else

 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK

 #endif

@@ -3242,7 +3380,7 @@
 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose

   * @{

   */

-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)

+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)

 #else

 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

 #endif

@@ -3350,9 +3488,9 @@
 #define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG

 #define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT

 #define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT

-#define  SDIO_STATIC_FLAGS	        SDMMC_STATIC_FLAGS

-#define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT

-#define  SD_SDIO_SEND_IF_COND	      SD_SDMMC_SEND_IF_COND

+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS

+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT

+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND

 /* alias CMSIS for compatibilities */

 #define  SDIO_IRQn                  SDMMC1_IRQn

 #define  SDIO_IRQHandler            SDMMC1_IRQHandler

@@ -3365,7 +3503,7 @@
 #define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef

 #endif

 

-#if defined(STM32H7)

+#if defined(STM32H7) || defined(STM32L5)

 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback

 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback

 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback

@@ -3606,12 +3744,12 @@
   * @{

   */

 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)

-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT

-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA

-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart

-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT

-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA

-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop

+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT

+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA

+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart

+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT

+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA

+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop

 #endif

 /**

   * @}

@@ -3620,9 +3758,9 @@
 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose

   * @{

   */

-#if defined (STM32L4)

+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)

 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE

-#endif

+#endif /* STM32L4 || STM32F4 || STM32F7 */

 /**

   * @}

   */

diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
index 71f6b8c..6ff1109 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
@@ -28,9 +28,7 @@ extern "C" {
 

 /* Includes ------------------------------------------------------------------*/

 #include "stm32f1xx.h"

-#if defined(USE_HAL_LEGACY)

 #include "Legacy/stm32_hal_legacy.h"

-#endif

 #include <stddef.h>

 

 /* Exported types ------------------------------------------------------------*/

@@ -108,7 +106,14 @@ typedef enum
                                     }while (0U)

 #endif /* USE_RTOS */

 

-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */

+#ifndef __weak

+#define __weak  __attribute__((weak))

+#endif

+#ifndef __packed

+#define __packed  __attribute__((packed))

+#endif

+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

 #ifndef __weak

 #define __weak   __attribute__((weak))

 #endif /* __weak */

@@ -119,7 +124,14 @@ typedef enum
 

 

 /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */

-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */

+#ifndef __ALIGN_BEGIN

+#define __ALIGN_BEGIN

+#endif

+#ifndef __ALIGN_END

+#define __ALIGN_END      __attribute__ ((aligned (4)))

+#endif

+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

 #ifndef __ALIGN_END

 #define __ALIGN_END    __attribute__ ((aligned (4)))

 #endif /* __ALIGN_END */

@@ -131,7 +143,7 @@ typedef enum
 #define __ALIGN_END

 #endif /* __ALIGN_END */

 #ifndef __ALIGN_BEGIN

-#if defined   (__CC_ARM)      /* ARM Compiler */

+#if defined   (__CC_ARM)      /* ARM Compiler V5*/

 #define __ALIGN_BEGIN    __align(4)

 #elif defined (__ICCARM__)    /* IAR Compiler */

 #define __ALIGN_BEGIN

@@ -143,9 +155,9 @@ typedef enum
 /**

   * @brief  __RAM_FUNC definition

   */

-#if defined ( __CC_ARM   )

-/* ARM Compiler

-   ------------

+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))

+/* ARM Compiler V4/V5 and V6

+   --------------------------

    RAM functions are defined using the toolchain options.

    Functions that are executed in RAM should reside in a separate source module.

    Using the 'Options for File' dialog you can simply change the 'Code / Const'

@@ -175,9 +187,9 @@ typedef enum
 /**

   * @brief  __NOINLINE definition

   */

-#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )

-/* ARM & GNUCompiler

-   ----------------

+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )

+/* ARM V4/V5 and V6 & GNU Compiler

+   -------------------------------

 */

 #define __NOINLINE __attribute__ ( (noinline) )

 

diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
index 0bf4ccd..d0d0830 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
@@ -330,11 +330,11 @@ typedef struct
   */

 #define RCC_PERIPHCLK_RTC           0x00000001U

 #define RCC_PERIPHCLK_ADC           0x00000002U

-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\

- || defined(STM32F107xC)

+#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\

+ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)

 #define RCC_PERIPHCLK_I2S2          0x00000004U

 #define RCC_PERIPHCLK_I2S3          0x00000008U

-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\

  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\

  || defined(STM32F105xC) || defined(STM32F107xC)

diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
index 8fcffda..f06ca5c 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
@@ -167,7 +167,7 @@ typedef struct
                                This parameter can be a value of @ref TIM_Encoder_Mode */

 

   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.

-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */

+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

 

   uint32_t IC1Selection;  /*!< Specifies the input.

                                This parameter can be a value of @ref TIM_Input_Capture_Selection */

@@ -179,7 +179,7 @@ typedef struct
                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

 

   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.

-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */

+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

 

   uint32_t IC2Selection;  /*!< Specifies the input.

                               This parameter can be a value of @ref TIM_Input_Capture_Selection */

@@ -295,6 +295,26 @@ typedef enum
 } HAL_TIM_StateTypeDef;

 

 /**

+  * @brief  TIM Channel States definition

+  */

+typedef enum

+{

+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */

+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */

+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */

+} HAL_TIM_ChannelStateTypeDef;

+

+/**

+  * @brief  DMA Burst States definition

+  */

+typedef enum

+{

+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */

+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */

+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */

+} HAL_TIM_DMABurstStateTypeDef;

+

+/**

   * @brief  HAL Active channel structures definition

   */

 typedef enum

@@ -315,13 +335,16 @@ typedef struct __TIM_HandleTypeDef
 typedef struct

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 {

-  TIM_TypeDef                 *Instance;     /*!< Register base address             */

-  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */

-  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */

-  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array

-                                                  This array is accessed by a @ref DMA_Handle_index */

-  HAL_LockTypeDef             Lock;          /*!< Locking object                    */

-  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */

+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */

+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */

+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */

+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array

+                                                             This array is accessed by a @ref DMA_Handle_index */

+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */

+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */

+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */

+  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */

+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */

 

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */

@@ -360,34 +383,34 @@ typedef struct
   */

 typedef enum

 {

-   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */

-  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */

-  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */

-  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */

-  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */

-  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */

-  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */

-  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */

-  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */

-  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */

-  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */

-  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */

-  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */

-  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */

-  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */

-  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */

-  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */

-  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */

-

-  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */

-  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */

-  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */

-  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */

-  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */

-  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */

-  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */

-  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */

-  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */

+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */

+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */

+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */

+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */

+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */

+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */

+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */

+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */

+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */

+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */

+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */

+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */

+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */

+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */

+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */

+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */

+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */

+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */

+

+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */

+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */

+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */

+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */

+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */

+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */

+  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */

+  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */

+  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */

 } HAL_TIM_CallbackIDTypeDef;

 

 /**

@@ -593,6 +616,15 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @}

   */

 

+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity

+  * @{

+  */

+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */

+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */

+/**

+  * @}

+  */

+

 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection

   * @{

   */

@@ -814,7 +846,7 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @{

   */

 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */

-#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 

+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event

                                                                                     (if none of the break inputs BRK and BRK2 is active) */

 /**

   * @}

@@ -984,25 +1016,45 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @retval None

   */

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \

-                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \

-                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \

-                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \

-                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \

-                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \

-                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \

-                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \

-                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \

-                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \

-                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \

-                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \

-                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \

-                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \

-                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \

-                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \

+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \

+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \

+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \

+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \

+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \

+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \

+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \

+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \

+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \

+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \

+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \

+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \

+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \

+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \

+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \

+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \

+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \

                                                      } while(0)

 #else

-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \

+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \

+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \

+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \

+                                                     } while(0)

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

 /**

@@ -1547,6 +1599,9 @@ mode.
 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \

                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))

 

+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \

+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

+

 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \

                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \

                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

@@ -1698,15 +1753,15 @@ mode.
 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \

                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

 

-#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \

-                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \

+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \

                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \

                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \

                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \

@@ -1717,6 +1772,8 @@ mode.
                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \

                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

 

+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

+

 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)

 

 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)

@@ -1742,11 +1799,49 @@ mode.
    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

 

 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \

-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\

    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\

    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\

    ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))

 

+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\

+   (__HANDLE__)->ChannelState[3])

+

+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\

+   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))

+

+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \

+  (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \

+  (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \

+  (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \

+  (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \

+ } while(0)

+

+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\

+   (__HANDLE__)->ChannelNState[3])

+

+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\

+   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))

+

+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \

+  (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__);  \

+  (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__);  \

+  (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__);  \

+  (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__);  \

+ } while(0)

+

 /**

   * @}

   */

@@ -1918,9 +2013,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);

 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

                                               uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);

+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,

+                                                   uint32_t DataLength);

 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);

 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);

+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,

+                                                  uint32_t  DataLength);

 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);

 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);

 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

@@ -1966,6 +2067,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);

 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);

 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);

+

+/* Peripheral Channel state functions  ************************************************/

+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);

+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);

+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);

 /**

   * @}

   */

@@ -1985,7 +2091,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,

                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);

 

-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);

 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);

 void TIM_DMAError(DMA_HandleTypeDef *hdma);

 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);

diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
index 265ca96..6f1b5e5 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
@@ -223,6 +223,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
   */

 /* Extended Peripheral State functions  ***************************************/

 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);

+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);

 /**

   * @}

   */

diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
index ac8c168..31e6d95 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
+++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
@@ -602,6 +602,7 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
 HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);

 HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);

 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);

+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);

 HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);

 HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);

 HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);

@@ -614,6 +615,11 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
 HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);

 HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);

 HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);

+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,

+                                  uint8_t ch_ep_num, uint16_t len);

+

+void             *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);

+

 uint32_t          USB_ReadInterrupts(USB_TypeDef *USBx);

 uint32_t          USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);

 uint32_t          USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);

diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
index ecc59a4..616c155 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
@@ -53,11 +53,11 @@
   * @{

   */

 /**

- * @brief STM32F1xx HAL Driver version number V1.1.5

+ * @brief STM32F1xx HAL Driver version number V1.1.7

    */

 #define __STM32F1xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */

 #define __STM32F1xx_HAL_VERSION_SUB1   (0x01U) /*!< [23:16] sub1 version */

-#define __STM32F1xx_HAL_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */

+#define __STM32F1xx_HAL_VERSION_SUB2   (0x07U) /*!< [15:8]  sub2 version */

 #define __STM32F1xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */

 #define __STM32F1xx_HAL_VERSION         ((__STM32F1xx_HAL_VERSION_MAIN << 24)\

                                         |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\

diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
index 52ead10..cd3563a 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
@@ -486,17 +486,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
   */

 void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)

 {

+  uint32_t odr;

+

   /* Check the parameters */

   assert_param(IS_GPIO_PIN(GPIO_Pin));

 

-  if ((GPIOx->ODR & GPIO_Pin) != 0x00u)

-  {

-    GPIOx->BRR = (uint32_t)GPIO_Pin;

-  }

-  else

-  {

-    GPIOx->BSRR = (uint32_t)GPIO_Pin;

-  }

+  /* get current Ouput Data Register value */

+  odr = GPIOx->ODR;

+

+  /* Set selected pins that were at low level, and reset ones that were high */

+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);

 }

 

 /**

diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
index 4069298..f4e2e78 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
@@ -198,7 +198,7 @@ all interrupt callbacks are set to the corresponding weak functions:
 

 /* Private typedef -----------------------------------------------------------*/

 /* Private define ------------------------------------------------------------*/

-/* Private macro -------------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

 /* Private variables ---------------------------------------------------------*/

 /* Private function prototypes -----------------------------------------------*/

 /** @addtogroup TIM_Private_Functions

@@ -218,6 +218,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);

 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);

 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);

+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);

 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);

 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);

 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,

@@ -303,6 +304,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
   /* Set the Time Base configuration */

   TIM_Base_SetConfig(htim->Instance, &htim->Init);

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Initialize the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -336,6 +344,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIM_Base_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Change the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -388,19 +403,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
   /* Check the parameters */

   assert_param(IS_TIM_INSTANCE(htim->Instance));

 

+  /* Check the TIM state */

+  if (htim->State != HAL_TIM_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

   /* Set the TIM state */

   htim->State = HAL_TIM_STATE_BUSY;

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

 

-  /* Change the TIM state*/

-  htim->State = HAL_TIM_STATE_READY;

-

   /* Return function status */

   return HAL_OK;

 }

@@ -415,13 +440,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
   /* Check the parameters */

   assert_param(IS_TIM_INSTANCE(htim->Instance));

 

-  /* Set the TIM state */

-  htim->State = HAL_TIM_STATE_BUSY;

-

   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the TIM state*/

+  /* Set the TIM state */

   htim->State = HAL_TIM_STATE_READY;

 

   /* Return function status */

@@ -440,12 +462,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
   /* Check the parameters */

   assert_param(IS_TIM_INSTANCE(htim->Instance));

 

+  /* Check the TIM state */

+  if (htim->State != HAL_TIM_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM state */

+  htim->State = HAL_TIM_STATE_BUSY;

+

   /* Enable the TIM Update interrupt */

   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -463,12 +501,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
 {

   /* Check the parameters */

   assert_param(IS_TIM_INSTANCE(htim->Instance));

+

   /* Disable the TIM Update interrupt */

   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);

 

   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM state */

+  htim->State = HAL_TIM_STATE_READY;

+

   /* Return function status */

   return HAL_OK;

 }

@@ -487,6 +529,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
   /* Check the parameters */

   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));

 

+  /* Set the TIM state */

   if (htim->State == HAL_TIM_STATE_BUSY)

   {

     return HAL_BUSY;

@@ -504,7 +547,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
   }

   else

   {

-    /* nothing to do */

+    return HAL_ERROR;

   }

 

   /* Set the DMA Period elapsed callbacks */

@@ -517,6 +560,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
   /* Enable the DMA channel */

   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)

   {

+    /* Return error status */

     return HAL_ERROR;

   }

 

@@ -524,8 +568,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -552,7 +603,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

+  /* Set the TIM state */

   htim->State = HAL_TIM_STATE_READY;

 

   /* Return function status */

@@ -635,6 +686,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
   /* Init the base time for the Output Compare */

   TIM_Base_SetConfig(htim->Instance,  &htim->Init);

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Initialize the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -668,6 +726,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIM_OC_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Change the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -725,6 +790,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM channel state */

+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Output compare channel */

   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

 

@@ -735,8 +809,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   }

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -773,6 +854,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -795,6 +879,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM channel state */

+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -839,8 +932,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   }

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -911,6 +1011,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -935,11 +1038,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM channel state */

+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)

   {

     if ((pData == NULL) && (Length > 0U))

     {

@@ -947,12 +1051,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

     }

   }

   else

   {

-    /* nothing to do */

+    return HAL_ERROR;

   }

 

   switch (Channel)

@@ -969,6 +1073,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

 

@@ -989,6 +1094,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

 

@@ -1009,6 +1115,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 3 DMA request */

@@ -1028,6 +1135,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 4 DMA request */

@@ -1049,8 +1157,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   }

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1125,8 +1240,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

 

   /* Return function status */

   return HAL_OK;

@@ -1208,6 +1323,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
   /* Init the base time for the PWM */

   TIM_Base_SetConfig(htim->Instance, &htim->Init);

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Initialize the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -1241,6 +1363,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIM_PWM_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Change the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -1298,6 +1427,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM channel state */

+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Capture compare channel */

   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

 

@@ -1308,8 +1446,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   }

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1346,8 +1491,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

 

   /* Return function status */

   return HAL_OK;

@@ -1370,6 +1515,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM channel state */

+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -1414,8 +1568,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
   }

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1486,6 +1647,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -1510,11 +1674,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM channel state */

+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)

   {

     if ((pData == NULL) && (Length > 0U))

     {

@@ -1522,12 +1687,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

     }

   }

   else

   {

-    /* nothing to do */

+    return HAL_ERROR;

   }

 

   switch (Channel)

@@ -1544,6 +1709,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

 

@@ -1564,6 +1730,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 2 DMA request */

@@ -1583,6 +1750,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Output Capture/Compare 3 request */

@@ -1602,6 +1770,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 4 DMA request */

@@ -1623,8 +1792,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
   }

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1699,8 +1875,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

 

   /* Return function status */

   return HAL_OK;

@@ -1782,6 +1958,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
   /* Init the base time for the input capture */

   TIM_Base_SetConfig(htim->Instance, &htim->Init);

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Initialize the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -1815,6 +1998,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIM_IC_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Change the TIM channels state */

+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -1868,16 +2058,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

   uint32_t tmpsmcr;

+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);

 

   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM channel state */

+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Input Capture channel */

   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1908,6 +2118,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -1926,10 +2140,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

   uint32_t tmpsmcr;

+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);

 

   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM channel state */

+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -1967,8 +2194,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -2033,6 +2267,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -2053,16 +2291,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)

 {

   uint32_t tmpsmcr;

+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);

 

   /* Check the parameters */

   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM channel state */

+  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)

+      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)

+           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))

   {

     if ((pData == NULL) && (Length > 0U))

     {

@@ -2070,12 +2313,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

     }

   }

   else

   {

-    /* nothing to do */

+    return HAL_ERROR;

   }

 

   switch (Channel)

@@ -2092,6 +2336,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 1 DMA request */

@@ -2111,6 +2356,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 2  DMA request */

@@ -2130,6 +2376,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 3  DMA request */

@@ -2149,6 +2396,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 4  DMA request */

@@ -2164,8 +2412,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -2191,6 +2446,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

 

+  /* Disable the Input Capture channel */

+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -2229,14 +2487,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
       break;

   }

 

-  /* Disable the Input Capture channel */

-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

-

   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

 

   /* Return function status */

   return HAL_OK;

@@ -2273,6 +2529,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
   *         requires a timer reset to avoid unexpected direction

   *         due to DIR bit readonly in center aligned mode.

   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()

+  * @note   When the timer instance is initialized in One Pulse mode, timer

+  *         channels 1 and channel 2 are reserved and cannot be used for other

+  *         purpose.

   * @param  htim TIM One Pulse handle

   * @param  OnePulseMode Select the One pulse mode.

   *         This parameter can be one of the following values:

@@ -2328,6 +2587,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
   /* Configure the OPM Mode */

   htim->Instance->CR1 |= OnePulseMode;

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Initialize the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -2361,6 +2629,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIM_OnePulse_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -2411,9 +2688,29 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
   */

 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)

 {

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

+

   /* Prevent unused argument(s) compilation warning */

   UNUSED(OutputChannel);

 

+  /* Check the TIM channels state */

+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Capture compare and the Input Capture channels

     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)

     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and

@@ -2468,6 +2765,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -2483,9 +2786,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
   */

 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)

 {

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

+

   /* Prevent unused argument(s) compilation warning */

   UNUSED(OutputChannel);

 

+  /* Check the TIM channels state */

+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Capture compare and the Input Capture channels

     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)

     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and

@@ -2551,6 +2874,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -2589,6 +2918,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together

   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource

   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa

+  * @note   When the timer instance is initialized in Encoder mode, timer

+  *         channels 1 and channel 2 are reserved and cannot be used for other

+  *         purpose.

   * @param  htim TIM Encoder Interface handle

   * @param  sConfig TIM Encoder Interface configuration structure

   * @retval HAL status

@@ -2606,15 +2938,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_Ini
   }

 

   /* Check the parameters */

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));

   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));

   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));

   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));

   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));

-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));

-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));

+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));

+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));

   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));

   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));

   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));

@@ -2685,6 +3017,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_Ini
   /* Write to TIMx CCER */

   htim->Instance->CCER = tmpccer;

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -2719,6 +3060,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIM_Encoder_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -2770,8 +3120,58 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
   */

 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

+

   /* Check the parameters */

-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

+

+  /* Set the TIM channel(s) state */

+  if (Channel == TIM_CHANNEL_1)

+  {

+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))

+    {

+      return HAL_ERROR;

+    }

+    else

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+    }

+  }

+  else if (Channel == TIM_CHANNEL_2)

+  {

+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+    {

+      return HAL_ERROR;

+    }

+    else

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+    }

+  }

+  else

+  {

+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+    {

+      return HAL_ERROR;

+    }

+    else

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+    }

+  }

 

   /* Enable the encoder interface channels */

   switch (Channel)

@@ -2815,7 +3215,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

   /* Check the parameters */

-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

 

   /* Disable the Input Capture channels 1 and 2

     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */

@@ -2844,6 +3244,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel(s) state */

+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))

+  {

+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else

+  {

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  }

+

   /* Return function status */

   return HAL_OK;

 }

@@ -2860,8 +3274,58 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
   */

 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

+

   /* Check the parameters */

-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

+

+  /* Set the TIM channel(s) state */

+  if (Channel == TIM_CHANNEL_1)

+  {

+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))

+    {

+      return HAL_ERROR;

+    }

+    else

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+    }

+  }

+  else if (Channel == TIM_CHANNEL_2)

+  {

+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+    {

+      return HAL_ERROR;

+    }

+    else

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+    }

+  }

+  else

+  {

+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+    {

+      return HAL_ERROR;

+    }

+    else

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+    }

+  }

 

   /* Enable the encoder interface channels */

   /* Enable the capture compare Interrupts 1 and/or 2 */

@@ -2911,7 +3375,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

   /* Check the parameters */

-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

 

   /* Disable the Input Capture channels 1 and 2

     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */

@@ -2942,8 +3406,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM channel(s) state */

+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))

+  {

+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else

+  {

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  }

 

   /* Return function status */

   return HAL_OK;

@@ -2965,27 +3440,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,

                                             uint32_t *pData2, uint16_t Length)

 {

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

+

   /* Check the parameters */

-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM channel(s) state */

+  if (Channel == TIM_CHANNEL_1)

   {

-    return HAL_BUSY;

+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)

+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))

+    {

+      return HAL_BUSY;

+    }

+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)

+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))

+    {

+      if ((pData1 == NULL) && (Length > 0U))

+      {

+        return HAL_ERROR;

+      }

+      else

+      {

+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      }

+    }

+    else

+    {

+      return HAL_ERROR;

+    }

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (Channel == TIM_CHANNEL_2)

   {

-    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))

+    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)

+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))

     {

-      return HAL_ERROR;

+      return HAL_BUSY;

+    }

+    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)

+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))

+    {

+      if ((pData2 == NULL) && (Length > 0U))

+      {

+        return HAL_ERROR;

+      }

+      else

+      {

+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+      }

     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      return HAL_ERROR;

     }

   }

   else

   {

-    /* nothing to do */

+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)

+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)

+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)

+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))

+    {

+      return HAL_BUSY;

+    }

+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)

+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)

+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)

+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))

+    {

+      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))

+      {

+        return HAL_ERROR;

+      }

+      else

+      {

+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+      }

+    }

+    else

+    {

+      return HAL_ERROR;

+    }

   }

 

   switch (Channel)

@@ -3002,6 +3545,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Input Capture DMA request */

@@ -3026,6 +3570,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Input Capture  DMA request */

@@ -3051,6 +3596,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

 

@@ -3064,6 +3610,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the Peripheral */

@@ -3083,6 +3630,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
     default:

       break;

   }

+

   /* Return function status */

   return HAL_OK;

 }

@@ -3100,7 +3648,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)

 {

   /* Check the parameters */

-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

 

   /* Disable the Input Capture channels 1 and 2

     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */

@@ -3135,8 +3683,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM channel(s) state */

+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))

+  {

+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else

+  {

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  }

 

   /* Return function status */

   return HAL_OK;

@@ -3390,8 +3949,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
   /* Process Locked */

   __HAL_LOCK(htim);

 

-  htim->State = HAL_TIM_STATE_BUSY;

-

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -3438,8 +3995,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
       break;

   }

 

-  htim->State = HAL_TIM_STATE_READY;

-

   __HAL_UNLOCK(htim);

 

   return HAL_OK;

@@ -3470,8 +4025,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
   /* Process Locked */

   __HAL_LOCK(htim);

 

-  htim->State = HAL_TIM_STATE_BUSY;

-

   if (Channel == TIM_CHANNEL_1)

   {

     /* TI1 Configuration */

@@ -3535,8 +4088,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);

   }

 

-  htim->State = HAL_TIM_STATE_READY;

-

   __HAL_UNLOCK(htim);

 

   return HAL_OK;

@@ -3568,8 +4119,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
   /* Process Locked */

   __HAL_LOCK(htim);

 

-  htim->State = HAL_TIM_STATE_BUSY;

-

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -3644,8 +4193,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
       break;

   }

 

-  htim->State = HAL_TIM_STATE_READY;

-

   __HAL_UNLOCK(htim);

 

   return HAL_OK;

@@ -3809,20 +4356,68 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.

   * @retval HAL status

   */

-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,

-                                              uint32_t *BurstBuffer, uint32_t  BurstLength)

+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)

+{

+  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,

+                                          ((BurstLength) >> 8U) + 1U);

+}

+

+/**

+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral

+  * @param  htim TIM handle

+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write

+  *         This parameter can be one of the following values:

+  *            @arg TIM_DMABASE_CR1

+  *            @arg TIM_DMABASE_CR2

+  *            @arg TIM_DMABASE_SMCR

+  *            @arg TIM_DMABASE_DIER

+  *            @arg TIM_DMABASE_SR

+  *            @arg TIM_DMABASE_EGR

+  *            @arg TIM_DMABASE_CCMR1

+  *            @arg TIM_DMABASE_CCMR2

+  *            @arg TIM_DMABASE_CCER

+  *            @arg TIM_DMABASE_CNT

+  *            @arg TIM_DMABASE_PSC

+  *            @arg TIM_DMABASE_ARR

+  *            @arg TIM_DMABASE_RCR

+  *            @arg TIM_DMABASE_CCR1

+  *            @arg TIM_DMABASE_CCR2

+  *            @arg TIM_DMABASE_CCR3

+  *            @arg TIM_DMABASE_CCR4

+  *            @arg TIM_DMABASE_BDTR

+  * @param  BurstRequestSrc TIM DMA Request sources

+  *         This parameter can be one of the following values:

+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source

+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source

+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source

+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source

+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source

+  *            @arg TIM_DMA_COM: TIM Commutation DMA source

+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source

+  * @param  BurstBuffer The Buffer address.

+  * @param  BurstLength DMA Burst length. This parameter can be one value

+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.

+  * @param  DataLength Data length. This parameter can be one value

+  *         between 1 and 0xFFFF.

+  * @retval HAL status

+  */

+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,

+                                                   uint32_t  BurstLength,  uint32_t  DataLength)

 {

   /* Check the parameters */

   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));

   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));

   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));

   assert_param(IS_TIM_DMA_LENGTH(BurstLength));

+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)

   {

     if ((BurstBuffer == NULL) && (BurstLength > 0U))

     {

@@ -3830,7 +4425,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;

     }

   }

   else

@@ -3849,8 +4444,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3866,8 +4463,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,

-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3883,8 +4481,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,

-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3900,8 +4499,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,

-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3917,8 +4517,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,

-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3934,8 +4535,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,

-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3951,8 +4553,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,

-                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -3960,14 +4563,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
     default:

       break;

   }

-  /* configure the DMA Burst Mode */

-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);

 

+  /* Configure the DMA Burst Mode */

+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);

   /* Enable the TIM DMA Request */

   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);

 

-  htim->State = HAL_TIM_STATE_READY;

-

   /* Return function status */

   return HAL_OK;

 }

@@ -3980,7 +4581,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
   */

 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)

 {

-  HAL_StatusTypeDef status = HAL_OK;

   /* Check the parameters */

   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));

 

@@ -3989,51 +4589,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
   {

     case TIM_DMA_UPDATE:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);

       break;

     }

     case TIM_DMA_CC1:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);

       break;

     }

     case TIM_DMA_CC2:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);

       break;

     }

     case TIM_DMA_CC3:

     {

-      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);

       break;

     }

     case TIM_DMA_CC4:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);

       break;

     }

     case TIM_DMA_COM:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);

       break;

     }

     case TIM_DMA_TRIGGER:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);

       break;

     }

     default:

       break;

   }

 

-  if (HAL_OK == status)

-  {

-    /* Disable the TIM Update DMA request */

-    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);

-  }

+  /* Disable the TIM Update DMA request */

+  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);

+

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

 

   /* Return function status */

-  return status;

+  return HAL_OK;

 }

 

 /**

@@ -4077,17 +4677,65 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)

 {

+  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,

+                                         ((BurstLength) >> 8U) + 1U);

+}

+

+/**

+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory

+  * @param  htim TIM handle

+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read

+  *         This parameter can be one of the following values:

+  *            @arg TIM_DMABASE_CR1

+  *            @arg TIM_DMABASE_CR2

+  *            @arg TIM_DMABASE_SMCR

+  *            @arg TIM_DMABASE_DIER

+  *            @arg TIM_DMABASE_SR

+  *            @arg TIM_DMABASE_EGR

+  *            @arg TIM_DMABASE_CCMR1

+  *            @arg TIM_DMABASE_CCMR2

+  *            @arg TIM_DMABASE_CCER

+  *            @arg TIM_DMABASE_CNT

+  *            @arg TIM_DMABASE_PSC

+  *            @arg TIM_DMABASE_ARR

+  *            @arg TIM_DMABASE_RCR

+  *            @arg TIM_DMABASE_CCR1

+  *            @arg TIM_DMABASE_CCR2

+  *            @arg TIM_DMABASE_CCR3

+  *            @arg TIM_DMABASE_CCR4

+  *            @arg TIM_DMABASE_BDTR

+  * @param  BurstRequestSrc TIM DMA Request sources

+  *         This parameter can be one of the following values:

+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source

+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source

+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source

+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source

+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source

+  *            @arg TIM_DMA_COM: TIM Commutation DMA source

+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source

+  * @param  BurstBuffer The Buffer address.

+  * @param  BurstLength DMA Burst length. This parameter can be one value

+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.

+  * @param  DataLength Data length. This parameter can be one value

+  *         between 1 and 0xFFFF.

+  * @retval HAL status

+  */

+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,

+                                                  uint32_t  BurstLength, uint32_t  DataLength)

+{

   /* Check the parameters */

   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));

   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));

   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));

   assert_param(IS_TIM_DMA_LENGTH(BurstLength));

+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)

   {

     if ((BurstBuffer == NULL) && (BurstLength > 0U))

     {

@@ -4095,7 +4743,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;

     }

   }

   else

@@ -4114,8 +4762,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -4130,15 +4780,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

     }

     case TIM_DMA_CC2:

     {

-      /* Set the DMA capture/compare callbacks */

+      /* Set the DMA capture callbacks */

       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;

       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

 

@@ -4146,8 +4798,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -4162,8 +4816,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -4178,8 +4834,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -4194,8 +4852,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -4210,8 +4870,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;

 

       /* Enable the DMA channel */

-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)

+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,

+                         DataLength) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       break;

@@ -4220,14 +4882,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
       break;

   }

 

-  /* configure the DMA Burst Mode */

+  /* Configure the DMA Burst Mode */

   htim->Instance->DCR = (BurstBaseAddress | BurstLength);

 

   /* Enable the TIM DMA Request */

   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);

 

-  htim->State = HAL_TIM_STATE_READY;

-

   /* Return function status */

   return HAL_OK;

 }

@@ -4240,7 +4900,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
   */

 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)

 {

-  HAL_StatusTypeDef status = HAL_OK;

   /* Check the parameters */

   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));

 

@@ -4249,51 +4908,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
   {

     case TIM_DMA_UPDATE:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);

       break;

     }

     case TIM_DMA_CC1:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);

       break;

     }

     case TIM_DMA_CC2:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);

       break;

     }

     case TIM_DMA_CC3:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);

       break;

     }

     case TIM_DMA_CC4:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);

       break;

     }

     case TIM_DMA_COM:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);

       break;

     }

     case TIM_DMA_TRIGGER:

     {

-      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);

+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);

       break;

     }

     default:

       break;

   }

 

-  if (HAL_OK == status)

-  {

-    /* Disable the TIM Update DMA request */

-    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);

-  }

+  /* Disable the TIM Update DMA request */

+  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);

+

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

 

   /* Return function status */

-  return status;

+  return HAL_OK;

 }

 

 /**

@@ -4599,13 +5258,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_ITR1:

     case TIM_CLOCKSOURCE_ITR2:

     case TIM_CLOCKSOURCE_ITR3:

-    {

-      /* Check whether or not the timer instance supports internal trigger input */

-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

+      {

+        /* Check whether or not the timer instance supports internal trigger input */

+        assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

 

-      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);

-      break;

-    }

+        TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);

+        break;

+      }

 

     default:

       break;

@@ -5536,6 +6195,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
 }

 

 /**

+  * @brief  Return the TIM Encoder Mode handle state.

+  * @param  htim TIM handle

+  * @retval Active channel

+  */

+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)

+{

+  return htim->Channel;

+}

+

+/**

+  * @brief  Return actual state of the TIM channel.

+  * @param  htim TIM handle

+  * @param  Channel TIM Channel

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1

+  *            @arg TIM_CHANNEL_2: TIM Channel 2

+  *            @arg TIM_CHANNEL_3: TIM Channel 3

+  *            @arg TIM_CHANNEL_4: TIM Channel 4

+  *            @arg TIM_CHANNEL_5: TIM Channel 5

+  *            @arg TIM_CHANNEL_6: TIM Channel 6

+  * @retval TIM Channel state

+  */

+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)

+{

+  HAL_TIM_ChannelStateTypeDef channel_state;

+

+  /* Check the parameters */

+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

+

+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);

+

+  return channel_state;

+}

+

+/**

+  * @brief  Return actual state of a DMA burst operation.

+  * @param  htim TIM handle

+  * @retval DMA burst state

+  */

+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)

+{

+  /* Check the parameters */

+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));

+

+  return htim->DMABurstState;

+}

+

+/**

   * @}

   */

 

@@ -5556,13 +6263,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else

+  {

+    htim->State = HAL_TIM_STATE_READY;

+  }

 

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

   htim->ErrorCallback(htim);

 #else

   HAL_TIM_ErrorCallback(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;

 }

 

 /**

@@ -5570,27 +6302,45 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma)
   * @param  hdma pointer to DMA handle.

   * @retval None

   */

-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)

+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)

 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

-

   if (hdma == htim->hdma[TIM_DMA_ID_CC1])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else

   {

@@ -5615,8 +6365,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

-

   if (hdma == htim->hdma[TIM_DMA_ID_CC1])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

@@ -5656,23 +6404,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

-

   if (hdma == htim->hdma[TIM_DMA_ID_CC1])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);

+    }

   }

   else

   {

@@ -5697,8 +6467,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

-

   if (hdma == htim->hdma[TIM_DMA_ID_CC1])

   {

     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

@@ -5738,7 +6506,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

+  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)

+  {

+    htim->State = HAL_TIM_STATE_READY;

+  }

 

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

   htim->PeriodElapsedCallback(htim);

@@ -5756,8 +6527,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

-

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

   htim->PeriodElapsedHalfCpltCallback(htim);

 #else

@@ -5774,7 +6543,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

+  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)

+  {

+    htim->State = HAL_TIM_STATE_READY;

+  }

 

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

   htim->TriggerCallback(htim);

@@ -5792,8 +6564,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
 {

   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

 

-  htim->State = HAL_TIM_STATE_READY;

-

 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

   htim->TriggerHalfCpltCallback(htim);

 #else

@@ -5852,7 +6622,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
 /**

   * @brief  Timer Output Compare 1 configuration

   * @param  TIMx to select the TIM peripheral

-  * @param  OC_Config The ouput configuration structure

+  * @param  OC_Config The output configuration structure

   * @retval None

   */

 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)

@@ -5927,7 +6697,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
 /**

   * @brief  Timer Output Compare 2 configuration

   * @param  TIMx to select the TIM peripheral

-  * @param  OC_Config The ouput configuration structure

+  * @param  OC_Config The output configuration structure

   * @retval None

   */

 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)

@@ -6003,7 +6773,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
 /**

   * @brief  Timer Output Compare 3 configuration

   * @param  TIMx to select the TIM peripheral

-  * @param  OC_Config The ouput configuration structure

+  * @param  OC_Config The output configuration structure

   * @retval None

   */

 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)

@@ -6077,7 +6847,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
 /**

   * @brief  Timer Output Compare 4 configuration

   * @param  TIMx to select the TIM peripheral

-  * @param  OC_Config The ouput configuration structure

+  * @param  OC_Config The output configuration structure

   * @retval None

   */

 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)

@@ -6187,7 +6957,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

 

-      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)

+      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)

       {

         return HAL_ERROR;

       }

@@ -6239,11 +7009,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
     case TIM_TS_ITR1:

     case TIM_TS_ITR2:

     case TIM_TS_ITR3:

-    {

-      /* Check the parameter */

-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

-      break;

-    }

+      {

+        /* Check the parameter */

+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

+        break;

+      }

 

     default:

       break;

diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
index 7d4b5d8..3b2983a 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
@@ -54,7 +54,7 @@
                the commutation event).

 

      (#) Activate the TIM peripheral using one of the start functions:

-           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()

+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()

            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()

            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()

            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().

@@ -90,9 +90,11 @@
 

 /* Private typedef -----------------------------------------------------------*/

 /* Private define ------------------------------------------------------------*/

-/* Private macro -------------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

 /* Private variables ---------------------------------------------------------*/

 /* Private function prototypes -----------------------------------------------*/

+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);

+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);

 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);

 

 /* Exported functions --------------------------------------------------------*/

@@ -123,6 +125,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
   */

 /**

   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.

+  * @note   When the timer instance is initialized in Hall Sensor Interface mode,

+  *         timer channels 1 and channel 2 are reserved and cannot be used for

+  *         other purpose.

   * @param  htim TIM Hall Sensor Interface handle

   * @param  sConfig TIM Hall Sensor configuration structure

   * @retval HAL status

@@ -208,6 +213,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
   htim->Instance->CR2 &= ~TIM_CR2_MMS;

   htim->Instance->CR2 |= TIM_TRGO_OC2REF;

 

+  /* Initialize the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

+

+  /* Initialize the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Initialize the TIM state*/

   htim->State = HAL_TIM_STATE_READY;

 

@@ -241,6 +255,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
   HAL_TIMEx_HallSensor_MspDeInit(htim);

 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

 

+  /* Change the DMA burst operation state */

+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

+

+  /* Change the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

+

   /* Change TIM state */

   htim->State = HAL_TIM_STATE_RESET;

 

@@ -288,17 +311,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)

 {

   uint32_t tmpsmcr;

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

 

   /* Check the parameters */

   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

 

+  /* Check the TIM channels state */

+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Input Capture channel 1

-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */

+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */

   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -324,6 +373,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -336,10 +391,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)

 {

   uint32_t tmpsmcr;

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

 

   /* Check the parameters */

   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

 

+  /* Check the TIM channels state */

+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the capture compare Interrupts 1 event */

   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);

 

@@ -348,8 +422,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -378,6 +459,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channels state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -392,29 +479,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)

 {

   uint32_t tmpsmcr;

+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);

+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

 

   /* Check the parameters */

   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM channel state */

+  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)

+      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)

+           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))

   {

-    if (((uint32_t)pData == 0U) && (Length > 0U))

+    if ((pData == NULL) && (Length > 0U))

     {

       return HAL_ERROR;

     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);

     }

   }

   else

   {

-    /* nothing to do */

+    return HAL_ERROR;

   }

+

   /* Enable the Input Capture channel 1

     (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */

   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);

@@ -428,14 +522,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
   /* Enable the DMA channel for Capture 1*/

   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)

   {

+    /* Return error status */

     return HAL_ERROR;

   }

   /* Enable the capture compare 1 Interrupt */

   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -463,9 +565,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);

 

   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);

+

   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM channel state */

+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -512,6 +619,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM complementary channel state */

+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the Capture compare channel N */

   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

 

@@ -519,8 +635,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   __HAL_TIM_MOE_ENABLE(htim);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -554,6 +677,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -576,6 +702,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM complementary channel state */

+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -614,8 +749,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
   __HAL_TIM_MOE_ENABLE(htim);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -684,6 +826,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -708,24 +853,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM complementary channel state */

+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)

   {

-    if (((uint32_t)pData == 0U) && (Length > 0U))

+    if ((pData == NULL) && (Length > 0U))

     {

       return HAL_ERROR;

     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

     }

   }

   else

   {

-    /* nothing to do  */

+    return HAL_ERROR;

   }

 

   switch (Channel)

@@ -733,15 +879,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
     case TIM_CHANNEL_1:

     {

       /* Set the DMA compare callbacks */

-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;

+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;

       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

 

       /* Set the DMA error callback */

-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;

+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;

 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Output Compare DMA request */

@@ -752,15 +899,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
     case TIM_CHANNEL_2:

     {

       /* Set the DMA compare callbacks */

-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;

+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;

       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

 

       /* Set the DMA error callback */

-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;

+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;

 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Output Compare DMA request */

@@ -771,15 +919,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
     case TIM_CHANNEL_3:

     {

       /* Set the DMA compare callbacks */

-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;

+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;

       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

 

       /* Set the DMA error callback */

-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;

+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;

 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Output Compare DMA request */

@@ -798,8 +947,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
   __HAL_TIM_MOE_ENABLE(htim);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -863,8 +1019,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

 

   /* Return function status */

   return HAL_OK;

@@ -921,6 +1077,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM complementary channel state */

+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the complementary PWM output  */

   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

 

@@ -928,8 +1093,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
   __HAL_TIM_MOE_ENABLE(htim);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -962,6 +1134,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -984,6 +1159,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

 

+  /* Check the TIM complementary channel state */

+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

@@ -1021,8 +1205,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
   __HAL_TIM_MOE_ENABLE(htim);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1092,6 +1283,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -1116,39 +1310,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

 

-  if (htim->State == HAL_TIM_STATE_BUSY)

+  /* Set the TIM complementary channel state */

+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)

   {

     return HAL_BUSY;

   }

-  else if (htim->State == HAL_TIM_STATE_READY)

+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)

   {

-    if (((uint32_t)pData == 0U) && (Length > 0U))

+    if ((pData == NULL) && (Length > 0U))

     {

       return HAL_ERROR;

     }

     else

     {

-      htim->State = HAL_TIM_STATE_BUSY;

+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

     }

   }

   else

   {

-    /* nothing to do */

+    return HAL_ERROR;

   }

+

   switch (Channel)

   {

     case TIM_CHANNEL_1:

     {

       /* Set the DMA compare callbacks */

-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;

+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;

       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

 

       /* Set the DMA error callback */

-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;

+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;

 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 1 DMA request */

@@ -1159,15 +1356,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
     case TIM_CHANNEL_2:

     {

       /* Set the DMA compare callbacks */

-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;

+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;

       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

 

       /* Set the DMA error callback */

-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;

+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;

 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 2 DMA request */

@@ -1178,15 +1376,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
     case TIM_CHANNEL_3:

     {

       /* Set the DMA compare callbacks */

-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;

+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;

       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

 

       /* Set the DMA error callback */

-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;

+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;

 

       /* Enable the DMA channel */

       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)

       {

+        /* Return error status */

         return HAL_ERROR;

       }

       /* Enable the TIM Capture/Compare 3 DMA request */

@@ -1205,8 +1404,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
   __HAL_TIM_MOE_ENABLE(htim);

 

   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */

-  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

-  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;

+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))

+    {

+      __HAL_TIM_ENABLE(htim);

+    }

+  }

+  else

   {

     __HAL_TIM_ENABLE(htim);

   }

@@ -1270,8 +1476,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

-  /* Change the htim state */

-  htim->State = HAL_TIM_STATE_READY;

+  /* Set the TIM complementary channel state */

+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

 

   /* Return function status */

   return HAL_OK;

@@ -1311,11 +1517,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
   */

 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)

 {

+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;

+  HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);

+  HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);

+

   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

 

-  /* Enable the complementary One Pulse output */

+  /* Check the TIM channels state */

+  if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

+  /* Enable the complementary One Pulse output channel and the Input Capture channel */

   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);

+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);

 

   /* Enable the Main Output */

   __HAL_TIM_MOE_ENABLE(htim);

@@ -1336,12 +1558,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
   */

 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)

 {

+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;

 

   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

 

-  /* Disable the complementary One Pulse output */

+  /* Disable the complementary One Pulse output channel and the Input Capture channel */

   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);

+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);

 

   /* Disable the Main Output */

   __HAL_TIM_MOE_DISABLE(htim);

@@ -1349,6 +1573,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM  channels state */

+  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -1365,17 +1593,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
   */

 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)

 {

+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;

+  HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);

+  HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);

+

   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

 

+  /* Check the TIM channels state */

+  if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)

+      || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))

+  {

+    return HAL_ERROR;

+  }

+

+  /* Set the TIM channels state */

+  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);

+  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);

+

   /* Enable the TIM Capture/Compare 1 interrupt */

   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);

 

   /* Enable the TIM Capture/Compare 2 interrupt */

   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);

 

-  /* Enable the complementary One Pulse output */

+  /* Enable the complementary One Pulse output channel and the Input Capture channel */

   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);

+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);

 

   /* Enable the Main Output */

   __HAL_TIM_MOE_ENABLE(htim);

@@ -1396,6 +1640,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
   */

 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)

 {

+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;

+

   /* Check the parameters */

   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

 

@@ -1405,8 +1651,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
   /* Disable the TIM Capture/Compare 2 interrupt */

   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);

 

-  /* Disable the complementary One Pulse output */

+  /* Disable the complementary One Pulse output channel and the Input Capture channel */

   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);

+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);

 

   /* Disable the Main Output */

   __HAL_TIM_MOE_DISABLE(htim);

@@ -1414,6 +1661,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
   /* Disable the Peripheral */

   __HAL_TIM_DISABLE(htim);

 

+  /* Set the TIM  channels state */

+  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);

+  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);

+

   /* Return function status */

   return HAL_OK;

 }

@@ -1633,7 +1884,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
   uint32_t tmpsmcr;

 

   /* Check the parameters */

-  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));

+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));

   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));

   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

 

@@ -1654,16 +1905,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
   /* Select the TRGO source */

   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;

 

-  /* Reset the MSM Bit */

-  tmpsmcr &= ~TIM_SMCR_MSM;

-  /* Set master mode */

-  tmpsmcr |= sMasterConfig->MasterSlaveMode;

-

   /* Update TIMx CR2 */

   htim->Instance->CR2 = tmpcr2;

 

-  /* Update TIMx SMCR */

-  htim->Instance->SMCR = tmpsmcr;

+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))

+  {

+    /* Reset the MSM Bit */

+    tmpsmcr &= ~TIM_SMCR_MSM;

+    /* Set master mode */

+    tmpsmcr |= sMasterConfig->MasterSlaveMode;

+

+    /* Update TIMx SMCR */

+    htim->Instance->SMCR = tmpsmcr;

+  }

 

   /* Change the htim state */

   htim->State = HAL_TIM_STATE_READY;

@@ -1733,6 +1987,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
   */

 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)

 {

+  /* Prevent unused argument(s) compilation warning */

+  UNUSED(htim);

+  UNUSED(Remap);

 

   return HAL_OK;

 }

@@ -1830,6 +2087,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
 }

 

 /**

+  * @brief  Return actual state of the TIM complementary channel.

+  * @param  htim TIM handle

+  * @param  ChannelN TIM Complementary channel

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1

+  *            @arg TIM_CHANNEL_2: TIM Channel 2

+  *            @arg TIM_CHANNEL_3: TIM Channel 3

+  * @retval TIM Complementary channel state

+  */

+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)

+{

+  HAL_TIM_ChannelStateTypeDef channel_state;

+

+  /* Check the parameters */

+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));

+

+  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);

+

+  return channel_state;

+}

+/**

   * @}

   */

 

@@ -1882,6 +2160,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
 

 

 /**

+  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).

+  * @param  hdma pointer to DMA handle.

+  * @retval None

+  */

+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)

+{

+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

+

+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+    }

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+    }

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

+    }

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

+

+    if (hdma->Init.Mode == DMA_NORMAL)

+    {

+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);

+    }

+  }

+  else

+  {

+    /* nothing to do */

+  }

+

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+  htim->PWM_PulseFinishedCallback(htim);

+#else

+  HAL_TIM_PWM_PulseFinishedCallback(htim);

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;

+}

+

+/**

+  * @brief  TIM DMA error callback (complementary channel)

+  * @param  hdma pointer to DMA handle.

+  * @retval None

+  */

+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)

+{

+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

+

+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])

+  {

+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);

+  }

+  else

+  {

+    /* nothing to do */

+  }

+

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+  htim->ErrorCallback(htim);

+#else

+  HAL_TIM_ErrorCallback(htim);

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;

+}

+

+/**

   * @brief  Enables or disables the TIM Capture Compare Channel xN.

   * @param  TIMx to select the TIM peripheral

   * @param  Channel specifies the TIM Channel

diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
index 1230036..9d34ff9 100644
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
+++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
@@ -1895,6 +1895,46 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
 }

 

 /**

+  * @brief  USB_FlushTxFifo : Flush a Tx FIFO

+  * @param  USBx : Selected device

+  * @param  num : FIFO number

+  *         This parameter can be a value from 1 to 15

+            15 means Flush all Tx FIFOs

+  * @retval HAL status

+  */

+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)

+{

+  /* Prevent unused argument(s) compilation warning */

+  UNUSED(USBx);

+  UNUSED(num);

+

+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used

+              only by USB OTG FS peripheral.

+            - This function is added to ensure compatibility across platforms.

+   */

+

+  return HAL_OK;

+}

+

+/**

+  * @brief  USB_FlushRxFifo : Flush Rx FIFO

+  * @param  USBx : Selected device

+  * @retval HAL status

+  */

+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)

+{

+  /* Prevent unused argument(s) compilation warning */

+  UNUSED(USBx);

+

+  /* NOTE : - This function is not required by USB Device FS peripheral, it is used

+              only by USB OTG FS peripheral.

+            - This function is added to ensure compatibility across platforms.

+   */

+

+  return HAL_OK;

+}

+

+/**

   * @brief  Activate and configure an endpoint

   * @param  USBx Selected device

   * @param  ep pointer to endpoint structure

diff --git a/nessmd2usb.ioc b/nessmd2usb.ioc
index 20e8916..570052d 100644
--- a/nessmd2usb.ioc
+++ b/nessmd2usb.ioc
@@ -61,8 +61,8 @@ Mcu.PinsNb=32
 Mcu.ThirdPartyNb=0

 Mcu.UserConstants=

 Mcu.UserName=STM32F103C8Tx

-MxCube.Version=6.0.1

-MxDb.Version=DB.6.0.0

+MxCube.Version=6.1.0

+MxDb.Version=DB.6.0.10

 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false

 NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true

 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false

@@ -197,7 +197,7 @@ PD0-OSC_IN.Signal=RCC_OSC_IN
 PD1-OSC_OUT.Mode=HSE-External-Oscillator

 PD1-OSC_OUT.Signal=RCC_OSC_OUT

 PinOutPanel.RotationAngle=0

-ProjectManager.AskForMigrate=true

+ProjectManager.AskForMigrate=false

 ProjectManager.BackupPrevious=false

 ProjectManager.CompilerOptimize=6

 ProjectManager.ComputerToolchain=false

@@ -206,7 +206,7 @@ ProjectManager.CustomerFirmwarePackage=
 ProjectManager.DefaultFWLocation=true

 ProjectManager.DeletePrevious=true

 ProjectManager.DeviceId=STM32F103C8Tx

-ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.1

+ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.3

 ProjectManager.FreePins=false

 ProjectManager.HalAssertFull=false

 ProjectManager.HeapSize=0x200