diff options
| author | madmonkey <madfkingmonkey@gmail.com> | 2018-07-26 02:07:39 +0300 |
|---|---|---|
| committer | madmonkey <madfkingmonkey@gmail.com> | 2018-07-26 02:08:32 +0300 |
| commit | 8a2777b41a5af447d35f43b36df0c2910b7136c9 (patch) | |
| tree | 75d05a74cd9ea0cc9c6f3feb324627fff67948cc | |
| parent | 9f53fdde860f03c64b78091dea3b1055652965a0 (diff) | |
sound fix
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | drivers/dma/sunxi-dma.c | 10 | ||||
| -rw-r--r-- | sound/soc/sunxi/i2s0/sunxi-i2s0.c | 9 |
3 files changed, 15 insertions, 6 deletions
@@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 4 SUBLEVEL = 113 -EXTRAVERSION = .22-madmonkey +EXTRAVERSION = .23-madmonkey NAME = Saber-toothed Squirrel # *DOCUMENTATION* diff --git a/drivers/dma/sunxi-dma.c b/drivers/dma/sunxi-dma.c index 615c14fc..2b5801cc 100644 --- a/drivers/dma/sunxi-dma.c +++ b/drivers/dma/sunxi-dma.c @@ -417,6 +417,9 @@ static int sunxi_terminate_all(struct sunxi_chan *ch) writel(CHAN_STOP, sdev->base + DMA_ENABLE(chan_num)); writel(CHAN_RESUME, sdev->base + DMA_PAUSE(chan_num)); + while(readl(sdev->base + DMA_STAT) & (1 << chan_num)) + cpu_relax(); + if (ch->cyclic) { ch->cyclic = false; if (ch->desc) { @@ -855,12 +858,17 @@ struct dma_async_tx_descriptor *sunxi_prep_dma_cyclic( struct dma_chan *chan, dma_addr_t phy; unsigned int periods = buf_len / period_len; unsigned int i; + unsigned long lock_flags; /* * Not allow duplicate prep dma on cyclic channel. */ - if (schan->desc && schan->cyclic) + spin_lock_irqsave(&schan->vc.lock, lock_flags); + if (schan->desc && schan->cyclic) { + spin_unlock_irqrestore(&schan->vc.lock, lock_flags); return NULL; + } + spin_unlock_irqrestore(&schan->vc.lock, lock_flags); txd = kzalloc(sizeof(*txd), GFP_NOWAIT); if (!txd) { diff --git a/sound/soc/sunxi/i2s0/sunxi-i2s0.c b/sound/soc/sunxi/i2s0/sunxi-i2s0.c index b9f028e7..d94b8b29 100644 --- a/sound/soc/sunxi/i2s0/sunxi-i2s0.c +++ b/sound/soc/sunxi/i2s0/sunxi-i2s0.c @@ -90,10 +90,6 @@ static struct sunxi_dma_params sunxi_i2s0_pcm_stereo_in = { static void sunxi_snd_txctrl_i2s0(struct snd_pcm_substream *substream, int on) { u32 reg_val; - /*for test*/ -// reg_val = readl(sunxi_i2s0.regs + SUNXI_I2S0CTL); -// reg_val |= SUNXI_I2S0CTL_LOOP; -// writel(reg_val, sunxi_i2s0.regs + SUNXI_I2S0CTL); reg_val = readl(sunxi_i2s0.regs + SUNXI_TXCHSEL); reg_val &= ~0x7; @@ -167,6 +163,11 @@ static void sunxi_snd_txctrl_i2s0(struct snd_pcm_substream *substream, int on) reg_val = readl(sunxi_i2s0.regs + SUNXI_I2S0INT); reg_val &= ~SUNXI_I2S0INT_TXDRQEN; writel(reg_val, sunxi_i2s0.regs + SUNXI_I2S0INT); + + /* Give the DMA engine some time to complete any pending + * DRQ. This ensures that the following start trigger will + * be the only code changing the FIFO state. */ + udelay(10); } } |