diff options
| author | Alexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com> | 2022-10-10 17:41:13 +0300 |
|---|---|---|
| committer | Alexey 'Cluster' Avdyukhin <clusterrr@clusterrr.com> | 2022-10-10 17:41:13 +0300 |
| commit | a4a6e7865cf48f2a63971781c6a43faa17f6ae77 (patch) | |
| tree | 701a5076d7938b54bb01f4e71c036b29a98d0c10 | |
| parent | fb1a19cac417e7020e9de1b8af26e78fb7ca1077 (diff) | |
Nintenso Switch compatibility
37 files changed, 2922 insertions, 929 deletions
@@ -17,17 +17,20 @@ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1488400450" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1488400450." name="/" resourcePath="">
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.483172604" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
- <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.555321986" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.260247374" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1921623235" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32F103RETx" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1325752801" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2010177888" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.815559788" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.905944704" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103RETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/Target | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../USB_DEVICE/App | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc || || || STM32F103xE | USE_HAL_DRIVER || || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE || || || ${workspace_loc:/${ProjName}/STM32F103RETX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || " valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.555321986" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.260247374" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" useByScannerDiscovery="false" value="7-2018-q2-update" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1921623235" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F103RETx" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1325752801" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2010177888" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.815559788" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.905944704" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103RETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/Target | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../USB_DEVICE/App | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc || || || STM32F103xE | USE_HAL_DRIVER || || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE || || || ${workspace_loc:/${ProjName}/STM32F103RETX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1134078102" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/wii2usb}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1642864635" managedBuildOn="true" name="Gnu Make Builder.Debug" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1565764526" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.849336850" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.270451112" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="DEBUG"/>
+ </option>
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.633382474" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
</tool>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1746601837" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
@@ -101,13 +104,13 @@ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.462458863" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.462458863." name="/" resourcePath="">
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.788322645" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
- <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1103916973" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.971118038" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.859165887" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32F103RETx" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1336789470" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.229555079" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.372104909" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
- <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1139585481" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103RETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/Target | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../USB_DEVICE/App | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc || || || STM32F103xE | USE_HAL_DRIVER || || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE || || || ${workspace_loc:/${ProjName}/STM32F103RETX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || " valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1103916973" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.971118038" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" useByScannerDiscovery="false" value="7-2018-q2-update" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.859165887" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F103RETx" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1336789470" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.229555079" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.372104909" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+ <option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1139585481" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32F103RETx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../USB_DEVICE/Target | ../Drivers/CMSIS/Device/ST/STM32F1xx/Include | ../Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc | ../Drivers/CMSIS/Include | ../Core/Inc | ../USB_DEVICE/App | ../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy | ../Drivers/STM32F1xx_HAL_Driver/Inc | ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc || || || STM32F103xE | USE_HAL_DRIVER || || Drivers | Core/Startup | Middlewares | Core | USB_DEVICE || || || ${workspace_loc:/${ProjName}/STM32F103RETX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.649647478" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/wii2usb}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1735656434" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1866486032" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -183,4 +186,5 @@ <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
-</cproject>
+ <storageModule moduleId="refreshScope"/>
+</cproject>
\ No newline at end of file @@ -1,37 +1,37 @@ [PreviousLibFiles]
-LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pcd.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pcd_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usb.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_core.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_def.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Inc\usbd_customhid.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pcd.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pcd_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_usb.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Src\usbd_customhid.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pcd.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pcd_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usb.h;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_def.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_rcc_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_gpio_ex.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_flash_ex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_i2c.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_hal_tim_ex.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_core.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_def.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Inc\usbd_customhid.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xe.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
[PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;USB_DEVICE\App\usb_device.c;USB_DEVICE\Target\usbd_conf.c;USB_DEVICE\App\usbd_desc.c;USB_DEVICE\App\usbd_custom_hid_if.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c;Core\Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c;Core\Src/system_stm32f1xx.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c;
+SourceFiles=Core\Src\main.c;USB_DEVICE\App\usb_device.c;USB_DEVICE\Target\usbd_conf.c;USB_DEVICE\App\usbd_desc.c;USB_DEVICE\App\usbd_custom_hid_if.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pcd.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pcd_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_usb.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Src\usbd_customhid.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pcd.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pcd_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_usb.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_i2c.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_tim_ex.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Src\usbd_customhid.c;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Core\Src\system_stm32f1xx.c;;;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Src\usbd_customhid.c;
HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USB_Device_Library\Core\Inc;Middlewares\ST\STM32_USB_Device_Library\Class\CustomHID\Inc;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;USB_DEVICE\App;USB_DEVICE\Target;Core\Inc;
CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
[PreviousGenFiles]
AdvancedFolderStructure=true
HeaderFileListSize=7
-HeaderFiles#0=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App/usb_device.h
-HeaderFiles#1=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/Target/usbd_conf.h
-HeaderFiles#2=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App/usbd_desc.h
-HeaderFiles#3=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App/usbd_custom_hid_if.h
-HeaderFiles#4=F:/Projects/STM32/wii2usb/wii2usb/Core/Inc/stm32f1xx_it.h
-HeaderFiles#5=F:/Projects/STM32/wii2usb/wii2usb/Core/Inc/stm32f1xx_hal_conf.h
-HeaderFiles#6=F:/Projects/STM32/wii2usb/wii2usb/Core/Inc/main.h
+HeaderFiles#0=..\USB_DEVICE\App\usb_device.h
+HeaderFiles#1=..\USB_DEVICE\Target\usbd_conf.h
+HeaderFiles#2=..\USB_DEVICE\App\usbd_desc.h
+HeaderFiles#3=..\USB_DEVICE\App\usbd_custom_hid_if.h
+HeaderFiles#4=..\Core\Inc\stm32f1xx_it.h
+HeaderFiles#5=..\Core\Inc\stm32f1xx_hal_conf.h
+HeaderFiles#6=..\Core\Inc\main.h
HeaderFolderListSize=3
-HeaderPath#0=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App
-HeaderPath#1=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/Target
-HeaderPath#2=F:/Projects/STM32/wii2usb/wii2usb/Core/Inc
+HeaderPath#0=..\USB_DEVICE\App
+HeaderPath#1=..\USB_DEVICE\Target
+HeaderPath#2=..\Core\Inc
HeaderFiles=;
SourceFileListSize=7
-SourceFiles#0=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App/usb_device.c
-SourceFiles#1=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/Target/usbd_conf.c
-SourceFiles#2=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App/usbd_desc.c
-SourceFiles#3=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App/usbd_custom_hid_if.c
-SourceFiles#4=F:/Projects/STM32/wii2usb/wii2usb/Core/Src/stm32f1xx_it.c
-SourceFiles#5=F:/Projects/STM32/wii2usb/wii2usb/Core/Src/stm32f1xx_hal_msp.c
-SourceFiles#6=F:/Projects/STM32/wii2usb/wii2usb/Core/Src/main.c
+SourceFiles#0=..\USB_DEVICE\App\usb_device.c
+SourceFiles#1=..\USB_DEVICE\Target\usbd_conf.c
+SourceFiles#2=..\USB_DEVICE\App\usbd_desc.c
+SourceFiles#3=..\USB_DEVICE\App\usbd_custom_hid_if.c
+SourceFiles#4=..\Core\Src\stm32f1xx_it.c
+SourceFiles#5=..\Core\Src\stm32f1xx_hal_msp.c
+SourceFiles#6=..\Core\Src\main.c
SourceFolderListSize=3
-SourcePath#0=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/App
-SourcePath#1=F:/Projects/STM32/wii2usb/wii2usb/USB_DEVICE/Target
-SourcePath#2=F:/Projects/STM32/wii2usb/wii2usb/Core/Src
+SourcePath#0=..\USB_DEVICE\App
+SourcePath#1=..\USB_DEVICE\Target
+SourcePath#2=..\Core\Src
SourceFiles=;
diff --git a/Core/Inc/main.h b/Core/Inc/main.h index 3bda995..b5c18ec 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -39,14 +39,40 @@ extern "C" { /* USER CODE BEGIN ET */
typedef struct __attribute__((packed))
{
- int8_t x;
- int8_t y;
- int8_t z;
- int8_t rx;
- int8_t ry;
- int8_t rz;
- uint8_t hat_switch;
- uint16_t buttons;
+ // 0
+ unsigned int Y : 1;
+ unsigned int B : 1;
+ unsigned int A : 1;
+ unsigned int X : 1;
+ unsigned int L : 1;
+ unsigned int R : 1;
+ unsigned int ZL : 1;
+ unsigned int ZR : 1;
+ // 1
+ unsigned int minus : 1;
+ unsigned int plus : 1;
+ unsigned int lclick : 1;
+ unsigned int rclick : 1;
+ unsigned int home : 1;
+ unsigned int capture : 1;
+ unsigned int : 2; // unused bits
+ // 2
+ unsigned int hat_switch : 4;
+ unsigned int : 4; // unused bits
+ // 3
+ uint8_t LX : 8;
+ // 4
+ uint8_t LY : 8;
+ // 5
+ uint8_t RX : 8;
+ // 6
+ uint8_t RY : 8;
+ // 7
+ unsigned int : 8; // unknown
+ // 8
+ //uint8_t ExtraX : 8; // for nunchuck
+ // 9
+ //uint8_t ExtraY : 8; // for nunchuck
} USB_JoystickReport_Data_t;
/* USER CODE END ET */
@@ -83,5 +109,3 @@ void Error_Handler(void); #endif
#endif /* __MAIN_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Core/Inc/stm32f1xx_hal_conf.h b/Core/Inc/stm32f1xx_hal_conf.h index b3a4f0d..ffdeb3b 100644 --- a/Core/Inc/stm32f1xx_hal_conf.h +++ b/Core/Inc/stm32f1xx_hal_conf.h @@ -1,3 +1,4 @@ +/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_hal_conf.h
@@ -5,16 +6,16 @@ ******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
+/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CONF_H
@@ -388,4 +389,3 @@ void assert_failed(uint8_t* file, uint32_t line); #endif /* __STM32F1xx_HAL_CONF_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Core/Inc/stm32f1xx_it.h b/Core/Inc/stm32f1xx_it.h index df49c30..a603caf 100644 --- a/Core/Inc/stm32f1xx_it.h +++ b/Core/Inc/stm32f1xx_it.h @@ -66,5 +66,3 @@ void USB_LP_CAN1_RX0_IRQHandler(void); #endif
#endif /* __STM32F1xx_IT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Core/Src/main.c b/Core/Src/main.c index 142754d..8ed9b03 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -136,40 +136,39 @@ int main(void) wii_accessory_data.button_r, wii_accessory_data.button_zl,
wii_accessory_data.button_zr, wii_accessory_data.wtf);
#endif
-
- joystick_data.x = wii_accessory_data.jx;
- joystick_data.y = wii_accessory_data.jy;
- if (wii_accessory_data.data_format == 0) // Nunchuck
+ memset(&joystick_data, 0, sizeof(joystick_data));
+ joystick_data.LX = 0x80 + wii_accessory_data.jx;
+ joystick_data.LY = 0x80 + wii_accessory_data.jy;
+ if (wii_accessory_data.data_format == 0)
{
- // Accelerometer
- joystick_data.rx = wii_accessory_data.acc_x;
- joystick_data.ry = wii_accessory_data.acc_y;
- joystick_data.rz = wii_accessory_data.acc_z;
+ // Nunchuck
+ // Accelerometers
+ joystick_data.RX = 0x80 + wii_accessory_data.acc_x;
+ joystick_data.RY = 0x80 + wii_accessory_data.acc_y;
+ //joystick_data.ExtraX = 0x80 + wii_accessory_data.acc_z;
} else {
- joystick_data.z = wii_accessory_data.rx;
- joystick_data.rx = wii_accessory_data.ry;
+ joystick_data.RX = 0x80 + wii_accessory_data.rx;
+ joystick_data.RY = 0x80 + wii_accessory_data.ry;
// Unsigned for trigger analog buttons
- joystick_data.ry = wii_accessory_data.tl - 128;
- joystick_data.rz = wii_accessory_data.tr - 128;
+ //joystick_data.ExtraX = wii_accessory_data.tl;
+ //joystick_data.ExtraY = wii_accessory_data.tr;
}
- joystick_data.buttons = (wii_accessory_data.button_a << 0)
- | (wii_accessory_data.button_b << 1)
- | (wii_accessory_data.button_x << 2)
- | (wii_accessory_data.button_y << 3)
- | (wii_accessory_data.button_select << 4)
- | (wii_accessory_data.button_start << 5)
- | (wii_accessory_data.button_home << 6)
- | (wii_accessory_data.button_l << 7)
- | (wii_accessory_data.button_r << 8)
- | (wii_accessory_data.button_zl << 9)
- | (wii_accessory_data.button_zr << 10);
+ joystick_data.A = wii_accessory_data.button_a;
+ joystick_data.B = wii_accessory_data.button_b;
+ joystick_data.X = wii_accessory_data.button_x;
+ joystick_data.Y = wii_accessory_data.button_y;
+ joystick_data.L = wii_accessory_data.button_l;
+ joystick_data.R = wii_accessory_data.button_r;
+ joystick_data.ZL = wii_accessory_data.button_zl;
+ joystick_data.ZR = wii_accessory_data.button_zr;
+ joystick_data.minus = wii_accessory_data.button_select;
+ joystick_data.plus = wii_accessory_data.button_start;
+
if (wii_accessory_data.dpad_up && wii_accessory_data.dpad_right)
joystick_data.hat_switch = 1;
- else if (wii_accessory_data.dpad_right
- && wii_accessory_data.dpad_down)
+ else if (wii_accessory_data.dpad_right && wii_accessory_data.dpad_down)
joystick_data.hat_switch = 3;
- else if (wii_accessory_data.dpad_down
- && wii_accessory_data.dpad_left)
+ else if (wii_accessory_data.dpad_down && wii_accessory_data.dpad_left)
joystick_data.hat_switch = 5;
else if (wii_accessory_data.dpad_left && wii_accessory_data.dpad_up)
joystick_data.hat_switch = 7;
@@ -249,6 +248,7 @@ void SystemClock_Config(void) {
Error_Handler();
}
+
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
@@ -368,5 +368,3 @@ void assert_failed(uint8_t *file, uint32_t line) /* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Core/Src/stm32f1xx_hal_msp.c b/Core/Src/stm32f1xx_hal_msp.c index 8815c3b..2cf6142 100644 --- a/Core/Src/stm32f1xx_hal_msp.c +++ b/Core/Src/stm32f1xx_hal_msp.c @@ -149,5 +149,3 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN 1 */
/* USER CODE END 1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Core/Src/stm32f1xx_it.c b/Core/Src/stm32f1xx_it.c index 4ee9689..a11b485 100644 --- a/Core/Src/stm32f1xx_it.c +++ b/Core/Src/stm32f1xx_it.c @@ -214,4 +214,3 @@ void USB_LP_CAN1_RX0_IRQHandler(void) /* USER CODE BEGIN 1 */
/* USER CODE END 1 */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h index ed22a14..cb5e86f 100644 --- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h @@ -904,7 +904,15 @@ typedef struct /** @addtogroup Exported_constants
* @{
*/
-
+
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -10583,7 +10591,6 @@ typedef struct #define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
@@ -11484,8 +11491,6 @@ typedef struct ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
@@ -11693,20 +11698,20 @@ typedef struct /* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
-#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
-#define TIM12_IRQn TIM8_BRK_IRQn
#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn
-#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn
#define TIM13_IRQn TIM8_UP_IRQn
#define CEC_IRQn USBWakeUp_IRQn
@@ -11720,20 +11725,20 @@ typedef struct /* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
-#define TIM12_IRQHandler TIM8_BRK_IRQHandler
#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler
-#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler
#define TIM13_IRQHandler TIM8_UP_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h index 516b510..61ff830 100644 --- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h @@ -90,11 +90,11 @@ #endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V4.3.1
+ * @brief CMSIS Device version number V4.3.3
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F1_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
@@ -191,6 +191,61 @@ typedef enum #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
/**
* @}
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 2063643..412525a 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -236,12 +235,12 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4)
-#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
-#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -306,8 +305,22 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
#endif /* STM32L4 */
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -365,6 +378,9 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
#endif /* STM32H7 */
/**
@@ -460,7 +476,9 @@ #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -564,7 +582,14 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@@ -622,6 +647,10 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@@ -735,6 +764,66 @@ #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+ * set/reset crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
/**
* @}
*/
@@ -874,7 +963,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -933,7 +1022,7 @@ /**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -965,6 +1054,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -1358,6 +1457,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1380,6 +1503,13 @@ #endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
/**
* @}
*/
@@ -1409,16 +1539,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1437,6 +1569,13 @@ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1509,14 +1648,14 @@ #define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@@ -3112,9 +3251,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3242,7 +3380,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3350,9 +3488,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@@ -3365,7 +3503,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3606,12 +3744,12 @@ * @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
@@ -3620,9 +3758,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32L4)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif
+#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h index 71f6b8c..6ff1109 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -28,9 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
-#if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
-#endif
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
@@ -108,7 +106,14 @@ typedef enum }while (0U)
#endif /* USE_RTOS */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@@ -119,7 +124,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@@ -131,7 +143,7 @@ typedef enum #define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
-#if defined (__CC_ARM) /* ARM Compiler */
+#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@@ -143,9 +155,9 @@ typedef enum /**
* @brief __RAM_FUNC definition
*/
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+ --------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@@ -175,9 +187,9 @@ typedef enum /**
* @brief __NOINLINE definition
*/
-#if defined ( __CC_ARM ) || defined ( __GNUC__ )
-/* ARM & GNUCompiler
- ----------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+/* ARM V4/V5 and V6 & GNU Compiler
+ -------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h index 5d3b049..e42e8c0 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h @@ -217,19 +217,19 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (GPIOG)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h index 6a3ebcf..454572d 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h @@ -85,7 +85,7 @@ typedef struct * 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
- * b5 Peripheral initilisation status
+ * b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h index e44d97d..5798449 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h @@ -198,16 +198,20 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
+ ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
@@ -224,8 +228,11 @@ typedef struct #if defined (USB)
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
+ &= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
@@ -457,27 +464,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #if defined (USB_OTG_FS)
#ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
#ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_NAK */
#ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NAKM */
#ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_STPKTRX */
#ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NYETM */
#endif /* defined (USB_OTG_FS) */
/* Private macros ------------------------------------------------------------*/
@@ -490,7 +497,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
+ (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
@@ -505,7 +513,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
+ & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -794,8 +804,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+
/**
* @brief sets address of the tx/rx buffer.
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h index 0bf4ccd..d0d0830 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -330,11 +330,11 @@ typedef struct */
#define RCC_PERIPHCLK_RTC 0x00000001U
#define RCC_PERIPHCLK_ADC 0x00000002U
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
+#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
+ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PERIPHCLK_I2S2 0x00000004U
#define RCC_PERIPHCLK_I2S3 0x00000008U
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h index 8fcffda..999f62e 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -65,8 +65,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
@@ -167,7 +169,7 @@ typedef struct This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -179,7 +181,7 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -218,7 +220,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ This parameter must be 0: When OCRef clear feature is used with ETR source,
+ ETR prescaler must be off */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;
@@ -264,22 +267,22 @@ typedef struct */
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the break input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
} TIM_BreakDeadTimeConfigTypeDef;
/**
@@ -295,6 +298,26 @@ typedef enum } HAL_TIM_StateTypeDef;
/**
+ * @brief TIM Channel States definition
+ */
+typedef enum
+{
+ HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
+ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
+ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+ * @brief DMA Burst States definition
+ */
+typedef enum
+{
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
* @brief HAL Active channel structures definition
*/
typedef enum
@@ -315,13 +338,16 @@ typedef struct __TIM_HandleTypeDef typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@@ -360,34 +386,34 @@ typedef struct */
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
- ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@@ -593,13 +619,20 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @}
*/
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
@@ -814,8 +847,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
- (if none of the break inputs BRK and BRK2 is active) */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
@@ -922,24 +954,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@@ -984,25 +1016,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ } while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@@ -1039,7 +1091,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+ * disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
@@ -1200,8 +1253,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+ * or Encoder mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
@@ -1275,7 +1328,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+ * function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -1547,6 +1601,9 @@ mode. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@@ -1698,15 +1755,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@@ -1717,6 +1774,8 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@@ -1742,11 +1801,53 @@ mode. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+ (__HANDLE__)->ChannelState[3])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
+ } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+ (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelNState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
+
/**
* @}
*/
@@ -1918,9 +2019,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -1966,6 +2073,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@@ -1985,7 +2097,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h index 265ca96..6f1b5e5 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -223,6 +223,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); */
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h index ac8c168..3d75775 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h @@ -94,14 +94,15 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -131,7 +132,7 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
+ This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
@@ -168,15 +169,16 @@ typedef struct uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint8_t speed; /*!< USB Host Channel speed.
+ This parameter can be any value of @ref HCD_Device_Speed:
+ (HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
+ This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
@@ -186,6 +188,8 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
+
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
@@ -225,12 +229,13 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -467,12 +472,19 @@ typedef struct #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ + USB_OTG_HOST_CHANNEL_BASE\
+ + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
@@ -602,18 +614,28 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
+
+#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+#endif
+
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len);
+
+void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
+
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c index ecc59a4..f4824ab 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -53,11 +53,11 @@ * @{
*/
/**
- * @brief STM32F1xx HAL Driver version number V1.1.5
+ * @brief STM32F1xx HAL Driver version number V1.1.8
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c index 44daaff..60030e8 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c @@ -276,6 +276,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
+ /* Get default Trigger and GPIOSel configuration */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
@@ -284,10 +288,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT {
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
- else
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- }
/* Get falling configuration */
/* Check if configuration of selected line is enable */
@@ -304,16 +304,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = AFIO->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
- else
- {
- pExtiConfig->GPIOSel = 0x00u;
- }
- }
- else
- {
- /* No Trigger selected */
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
@@ -485,6 +475,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
+ /* Prevent unused argument compilation warning */
+ UNUSED(Edge);
+
/* Compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
@@ -512,6 +505,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
+ /* Prevent unused argument compilation warning */
+ UNUSED(Edge);
+
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index 52ead10..cd3563a 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -486,17 +486,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
+ uint32_t odr;
+
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
- {
- GPIOx->BRR = (uint32_t)GPIO_Pin;
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin;
- }
+ /* get current Ouput Data Register value */
+ odr = GPIOx->ODR;
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c index 2dd34dd..009cd65 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c @@ -90,7 +90,7 @@ [..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
@@ -109,7 +109,7 @@ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
@@ -119,7 +119,7 @@ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
- (+) Differents sequential I2C interfaces are listed below:
+ (+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
@@ -1760,9 +1760,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->Devaddress = DevAddress;
- /* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1772,6 +1769,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
return HAL_OK;
}
else
@@ -1840,11 +1840,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->Devaddress = DevAddress;
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1856,6 +1851,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
return HAL_OK;
}
else
@@ -2051,30 +2052,41 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- if (dmaxferstatus == HAL_OK)
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ }
+ else
{
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -2084,6 +2096,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Enable DMA Request */
SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
else
{
@@ -2190,18 +2208,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -2241,12 +2276,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D }
else
{
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2256,6 +2285,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
return HAL_OK;
@@ -2308,18 +2343,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -2403,18 +2455,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -3128,18 +3197,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -3147,16 +3233,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Abort the ongoing DMA */
- dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
+ dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
/* Prevent unused argument(s) compilation and MISRA warning */
UNUSED(dmaxferstatus);
- /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
- if (hi2c->hdmatx != NULL)
- {
- hi2c->hdmatx->XferCpltCallback = NULL;
- }
+ /* Set the unused I2C DMA transfer complete callback to NULL */
+ hi2c->hdmatx->XferCpltCallback = NULL;
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
@@ -3292,18 +3375,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -3316,11 +3416,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Prevent unused argument(s) compilation and MISRA warning */
UNUSED(dmaxferstatus);
- /* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
- if (hi2c->hdmarx != NULL)
- {
- hi2c->hdmarx->XferCpltCallback = NULL;
- }
+ /* Set the unused I2C DMA transfer complete callback to NULL */
+ hi2c->hdmarx->XferCpltCallback = NULL;
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
@@ -3711,18 +3808,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -4035,20 +4149,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
}
}
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
/* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
@@ -4298,18 +4427,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -4521,18 +4667,35 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
if (dmaxferstatus == HAL_OK)
{
@@ -4763,13 +4926,16 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* BTF set -------------------------------------------------------------*/
else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
- if (CurrentMode == HAL_I2C_MODE_MASTER)
+ if (CurrentState == HAL_I2C_STATE_BUSY_TX)
{
I2C_MasterTransmit_BTF(hi2c);
}
else /* HAL_I2C_MODE_MEM */
{
- I2C_MemoryTransmit_TXE_BTF(hi2c);
+ if (CurrentMode == HAL_I2C_MODE_MEM)
+ {
+ I2C_MemoryTransmit_TXE_BTF(hi2c);
+ }
}
}
else
@@ -5326,13 +5492,25 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
+ HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->MasterTxCpltCallback(hi2c);
+ hi2c->MasterTxCpltCallback(hi2c);
#else
- HAL_I2C_MasterTxCpltCallback(hi2c);
+ HAL_I2C_MasterTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
}
}
}
@@ -5385,6 +5563,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) {
/* Generate Restart */
hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ hi2c->EventCount++;
}
else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
{
@@ -5732,13 +5912,11 @@ static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) /* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
- if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
+ if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
+ || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
{
- if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
- {
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- }
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
}
}
@@ -6059,7 +6237,7 @@ static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) else
{
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -7397,7 +7575,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) }
/**
- * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c index 7a3657a..d019fad 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c @@ -723,7 +723,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, /**
* @brief Unregister the USB PCD Iso OUT incomplete Callback
- * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * USB PCD Iso OUT incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -797,7 +798,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, /**
* @brief Unregister the USB PCD Iso IN incomplete Callback
- * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * USB PCD Iso IN incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -903,9 +905,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) {
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t i, ep_intr, epint, epnum;
- uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
+ uint32_t i;
+ uint32_t ep_intr;
+ uint32_t epint;
+ uint32_t epnum;
+ uint32_t fifoemptymsk;
+ uint32_t temp;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -2169,8 +2175,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+ {
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
}
}
}
@@ -2257,9 +2266,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- /* Manage all non bulk transaction or Bulk Single Buffer Transaction */
- if ((ep->type != EP_TYPE_BULK) ||
- ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
+ /* Manage all non bulk/isoc transaction Bulk Single Buffer Transaction */
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_CTRL) ||
+ ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
{
/* multi-packet on the NON control IN endpoint */
TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
@@ -2291,7 +2300,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) (void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
- /* bulk in double buffer enable in case of transferLen> Ep_Mps */
+ /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
@@ -2415,6 +2424,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */
if (ep->xfer_len == 0U)
{
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2485,6 +2497,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */
if (ep->xfer_len == 0U)
{
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2492,7 +2507,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- /*need to Free USB Buff*/
+ /* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c index 4719727..e6e1b4d 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c @@ -110,11 +110,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
{
+ FlagStatus pwrclkchanged = RESET;
+
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
- FlagStatus pwrclkchanged = RESET;
-
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c index 4069298..b32c0bd 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -198,7 +198,7 @@ all interrupt callbacks are set to the corresponding weak functions: /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup TIM_Private_Functions
@@ -218,6 +218,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
@@ -303,6 +304,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -336,6 +344,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -388,19 +403,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
- /* Change the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -415,13 +440,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the TIM state*/
+ /* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
/* Return function status */
@@ -440,12 +462,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -463,12 +501,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) {
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
@@ -487,6 +529,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ /* Set the TIM state */
if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
@@ -504,7 +547,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat }
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
/* Set the DMA Period elapsed callbacks */
@@ -515,8 +558,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -524,8 +569,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -552,7 +604,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
+ /* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
/* Return function status */
@@ -635,6 +687,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -668,6 +727,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -725,6 +791,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -735,8 +810,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) }
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -773,6 +855,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -795,6 +880,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -839,8 +933,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) }
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -911,6 +1012,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -935,11 +1039,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -947,12 +1052,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel }
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -967,8 +1072,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -987,8 +1094,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1007,8 +1116,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1026,8 +1137,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1049,8 +1162,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel }
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1125,8 +1245,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1208,6 +1328,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -1241,6 +1368,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1298,6 +1432,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -1308,8 +1451,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) }
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1346,8 +1496,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1370,6 +1520,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1414,8 +1573,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel }
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1486,6 +1652,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1510,11 +1679,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1522,12 +1692,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe }
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -1542,8 +1712,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1562,8 +1734,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1581,8 +1755,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Capture/Compare 3 request */
@@ -1600,8 +1776,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1623,8 +1801,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe }
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1699,8 +1884,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1782,6 +1967,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -1815,6 +2007,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1868,16 +2067,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1908,6 +2127,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1926,10 +2149,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1967,8 +2203,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2033,6 +2276,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2053,16 +2300,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2070,12 +2322,30 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel }
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
}
switch (Channel)
@@ -2090,8 +2360,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -2109,8 +2381,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -2128,8 +2402,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -2147,8 +2423,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2160,16 +2438,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break;
}
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -2191,6 +2459,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2229,14 +2500,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -2273,6 +2542,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction
* due to DIR bit readonly in center aligned mode.
* Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @note When the timer instance is initialized in One Pulse mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
* @param htim TIM One Pulse handle
* @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
@@ -2328,6 +2600,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -2361,6 +2642,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2402,23 +2692,44 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /**
* @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2438,11 +2749,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /**
* @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2454,7 +2766,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -2468,29 +2780,56 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2516,11 +2855,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2538,7 +2878,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -2551,6 +2891,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2589,6 +2935,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
* Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
* using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @note When the timer instance is initialized in Encoder mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
@@ -2606,15 +2955,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini }
/* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -2685,6 +3034,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -2719,6 +3077,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2770,8 +3137,58 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
/* Enable the encoder interface channels */
switch (Channel)
@@ -2815,7 +3232,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2844,6 +3261,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2860,8 +3291,58 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@@ -2911,7 +3392,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2942,8 +3423,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
return HAL_OK;
@@ -2965,27 +3457,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
{
- return HAL_BUSY;
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData1 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (Channel == TIM_CHANNEL_2)
{
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
- return HAL_ERROR;
+ return HAL_BUSY;
+ }
+ else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData2 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ return HAL_ERROR;
}
}
else
{
- /* nothing to do */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
switch (Channel)
@@ -3000,8 +3560,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3024,8 +3586,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3049,8 +3613,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -3062,8 +3628,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the Peripheral */
@@ -3083,6 +3651,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch default:
break;
}
+
/* Return function status */
return HAL_OK;
}
@@ -3100,7 +3669,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -3135,8 +3704,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
return HAL_OK;
@@ -3390,8 +3970,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3438,8 +4016,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break;
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3470,8 +4046,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
if (Channel == TIM_CHANNEL_1)
{
/* TI1 Configuration */
@@ -3535,8 +4109,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3568,8 +4140,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3644,8 +4214,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break;
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3809,20 +4377,68 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -3830,7 +4446,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t }
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -3849,8 +4465,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3866,8 +4484,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3883,8 +4502,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3900,8 +4520,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3917,8 +4538,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3934,8 +4556,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3951,8 +4574,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -3960,14 +4584,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t default:
break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -3980,7 +4602,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -3989,51 +4610,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B {
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -4077,17 +4698,65 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
+ return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4095,7 +4764,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B }
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4114,8 +4783,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4130,15 +4801,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
}
case TIM_DMA_CC2:
{
- /* Set the DMA capture/compare callbacks */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
@@ -4146,8 +4819,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4162,8 +4837,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4178,8 +4855,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4194,8 +4873,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4210,8 +4891,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4220,14 +4903,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B break;
}
- /* configure the DMA Burst Mode */
+ /* Configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4240,7 +4921,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B */
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4249,51 +4929,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu {
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -4599,13 +5279,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1:
case TIM_CLOCKSOURCE_ITR2:
case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
break;
@@ -5264,111 +5944,138 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID)
{
case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
break;
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
break;
case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
break;
case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
break;
case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
break;
case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
break;
case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
break;
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
break;
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
break;
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
break;
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
break;
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
break;
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
break;
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
break;
case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ /* Legacy weak Period Elapsed Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
break;
case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ /* Legacy weak Period Elapsed half complete Callback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
break;
case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ /* Legacy weak Trigger Callback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
break;
case HAL_TIM_TRIGGER_HALF_CB_ID :
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ /* Legacy weak Trigger half complete Callback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
break;
case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ /* Legacy weak IC Capture Callback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
break;
case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ /* Legacy weak IC Capture half complete Callback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
break;
case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ /* Legacy weak OC Delay Elapsed Callback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
break;
case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ /* Legacy weak PWM Pulse Finished Callback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
break;
case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ /* Legacy weak PWM Pulse Finished half complete Callback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
break;
case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ /* Legacy weak Error Callback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
break;
case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ /* Legacy weak Commutation Callback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
break;
case HAL_TIM_COMMUTATION_HALF_CB_ID :
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ /* Legacy weak Commutation half complete Callback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
break;
case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ /* Legacy weak Break Callback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
break;
default :
@@ -5382,59 +6089,73 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID)
{
case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
break;
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
break;
case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
break;
case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
break;
case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
break;
case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
break;
case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
break;
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
break;
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
break;
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
break;
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
break;
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
break;
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
break;
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
break;
default :
@@ -5536,6 +6257,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) }
/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM handle
+ * @retval Active channel
+ */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+ return htim->Channel;
+}
+
+/**
+ * @brief Return actual state of the TIM channel.
+ * @param htim TIM handle
+ * @param Channel TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval TIM Channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+ return channel_state;
+}
+
+/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
* @}
*/
@@ -5556,13 +6325,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
@@ -5570,27 +6364,45 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else
{
@@ -5615,8 +6427,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -5656,23 +6466,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else
{
@@ -5697,8 +6529,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -5738,7 +6568,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
@@ -5756,8 +6589,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedHalfCpltCallback(htim);
#else
@@ -5774,7 +6605,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
@@ -5792,8 +6626,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) {
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerHalfCpltCallback(htim);
#else
@@ -5852,7 +6684,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /**
* @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -5927,7 +6759,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /**
* @brief Timer Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6003,7 +6835,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /**
* @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6077,7 +6909,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /**
* @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6187,7 +7019,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
{
return HAL_ERROR;
}
@@ -6239,11 +7071,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1:
case TIM_TS_ITR2:
case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
break;
@@ -6620,19 +7452,19 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim)
{
/* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c index 7d4b5d8..f15cbbb 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -54,10 +54,13 @@ the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+ HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+ HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+ HAL_TIMEx_HallSensor_Start_IT().
@endverbatim
******************************************************************************
@@ -90,9 +93,11 @@ /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
@@ -123,6 +128,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */
/**
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @note When the timer instance is initialized in Hall Sensor Interface mode,
+ * timer channels 1 and channel 2 are reserved and cannot be used for
+ * other purpose.
* @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
@@ -208,6 +216,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -241,6 +258,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -288,17 +314,44 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -318,12 +371,19 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -336,20 +396,47 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -369,7 +456,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts event */
@@ -378,6 +466,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -392,31 +486,39 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
+
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callbacks */
@@ -428,14 +530,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -455,7 +565,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
@@ -463,9 +574,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -512,6 +628,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@@ -519,8 +644,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -554,6 +686,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -576,6 +711,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -614,8 +758,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -684,6 +835,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -708,24 +862,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -733,15 +888,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -752,15 +909,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -771,15 +930,17 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -798,8 +959,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -863,8 +1031,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -921,6 +1089,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@@ -928,8 +1105,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -962,6 +1146,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -984,6 +1171,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1021,8 +1217,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1092,6 +1295,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1116,39 +1322,43 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -1159,15 +1369,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1178,15 +1390,17 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1205,8 +1419,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1270,8 +1491,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1302,8 +1523,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1311,11 +1534,33 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
- /* Enable the complementary One Pulse output */
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1327,8 +1572,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1336,12 +1583,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
- /* Disable the complementary One Pulse output */
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1349,6 +1598,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1356,8 +1611,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1365,17 +1622,39 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- /* Enable the complementary One Pulse output */
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1387,8 +1666,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1396,6 +1677,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@@ -1405,8 +1688,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- /* Disable the complementary One Pulse output */
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1414,6 +1698,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1633,7 +1923,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@@ -1654,16 +1944,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@@ -1733,6 +2026,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+ UNUSED(Remap);
return HAL_OK;
}
@@ -1830,6 +2126,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) }
/**
+ * @brief Return actual state of the TIM complementary channel.
+ * @param htim TIM handle
+ * @param ChannelN TIM Complementary channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @retval TIM Complementary channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+ channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+ return channel_state;
+}
+/**
* @}
*/
@@ -1882,6 +2199,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) /**
+ * @brief TIM DMA Delay Pulse complete callback (complementary channel).
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback (complementary channel)
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c index 1230036..1de2d5c 100644 --- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c @@ -83,33 +83,15 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c {
HAL_StatusTypeDef ret;
- if (cfg.phy_itface == USB_OTG_ULPI_PHY)
- {
- USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
- /* Init The ULPI Interface */
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+ /* Select FS Embedded PHY */
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
- /* Select vbus source */
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
- if (cfg.use_external_vbus == 1U)
- {
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
- }
- /* Reset after a PHY select */
- ret = USB_CoreReset(USBx);
- }
- else /* FS interface (embedded Phy) */
- {
- /* Select FS Embedded PHY */
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+ /* Reset after a PHY select */
+ ret = USB_CoreReset(USBx);
- /* Reset after a PHY select */
- ret = USB_CoreReset(USBx);
-
- /* Activate the USB Transceiver */
- USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
- }
+ /* Activate the USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
return ret;
}
@@ -229,21 +211,39 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) */
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
{
+ uint32_t ms = 0U;
+
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
if (mode == USB_HOST_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
}
else if (mode == USB_DEVICE_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
}
else
{
return HAL_ERROR;
}
- HAL_Delay(50U);
+
+ if (ms == 50U)
+ {
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -438,7 +438,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @param USBx Selected device
* @retval speed device speed
* This parameter can be one of these values:
- * @arg PCD_SPEED_FULL: Full speed mode
+ * @arg USBD_FS_SPEED: Full speed mode
*/
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@@ -652,7 +652,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
+ (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
if (ep->type == EP_TYPE_ISOC)
@@ -810,14 +812,18 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t *pSrc = (uint32_t *)src;
- uint32_t count32b, i;
+ uint8_t *pSrc = src;
+ uint32_t count32b;
+ uint32_t i;
count32b = ((uint32_t)len + 3U) / 4U;
for (i = 0U; i < count32b; i++)
{
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
pSrc++;
+ pSrc++;
+ pSrc++;
+ pSrc++;
}
return HAL_OK;
@@ -833,14 +839,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t *pDest = (uint32_t *)dest;
+ uint8_t *pDest = dest;
+ uint32_t pData;
uint32_t i;
- uint32_t count32b = ((uint32_t)len + 3U) / 4U;
+ uint32_t count32b = (uint32_t)len >> 2U;
+ uint16_t remaining_bytes = len % 4U;
for (i = 0U; i < count32b; i++)
{
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
pDest++;
+ pDest++;
+ pDest++;
+ pDest++;
+ }
+
+ /* When Number of data is not word aligned, read the remaining byte */
+ if (remaining_bytes != 0U)
+ {
+ i = 0U;
+ __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
+
+ do
+ {
+ *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
+ i++;
+ pDest++;
+ remaining_bytes--;
+ } while (remaining_bytes != 0U);
}
return ((void *)pDest);
@@ -1072,7 +1098,9 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t tmpreg, msk, emp;
+ uint32_t tmpreg;
+ uint32_t msk;
+ uint32_t emp;
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
@@ -1131,9 +1159,9 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) */
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
{
- UNUSED(psetup);
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ UNUSED(psetup);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
{
@@ -1217,11 +1245,6 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx_HC(i)->HCINTMSK = 0U;
}
- /* Enable VBUS driving */
- (void)USB_DriveVbus(USBx, 1U);
-
- HAL_Delay(200U);
-
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@@ -1380,7 +1403,7 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) * @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param mps Max Packet Size
- * This parameter can be a value from 0 to32K
+ * This parameter can be a value from 0 to 32K
* @retval HAL state
*/
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
@@ -1389,7 +1412,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, {
HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t HCcharEpDir, HCcharLowSpeed;
+ uint32_t HCcharEpDir;
+ uint32_t HCcharLowSpeed;
+ uint32_t HostCoreSpeed;
/* Clear old interrupt conditions for this host channel. */
USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
@@ -1461,7 +1486,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, HCcharEpDir = 0U;
}
- if (speed == HPRT0_PRTSPD_LOW_SPEED)
+ HostCoreSpeed = USB_GetHostSpeed(USBx);
+
+ /* LS device plugged to HUB */
+ if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
{
HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
}
@@ -1493,7 +1521,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe {
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)hc->ch_num;
- static __IO uint32_t tmpreg = 0U;
+ __IO uint32_t tmpreg;
uint8_t is_oddframe;
uint16_t len_words;
uint16_t num_packets;
@@ -1507,20 +1535,29 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if (num_packets > max_hc_pkt_count)
{
num_packets = max_hc_pkt_count;
- hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
}
}
else
{
num_packets = 1U;
}
+
+ /*
+ * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+ * max_packet size.
+ */
if (hc->ep_is_in != 0U)
{
- hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ else
+ {
+ hc->XferSize = hc->xfer_len;
}
/* Initialize the HCTSIZn register */
- USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
+ USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
(((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
(((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
@@ -1610,28 +1647,38 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) uint32_t hcnum = (uint32_t)hc_num;
uint32_t count = 0U;
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+ uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+
+ if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
+ (ChannelEna == 0U))
+ {
+ return HAL_OK;
+ }
/* Check for space in the request queue to issue the halt. */
if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
- if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+ if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
{
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
+ if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
{
- if (++count > 1000U)
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+ do
{
- break;
- }
- } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
- else
- {
- USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ if (++count > 1000U)
+ {
+ break;
+ }
+ } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ else
+ {
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
}
}
else
@@ -1736,8 +1783,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) USBx_HOST->HAINT = 0xFFFFFFFFU;
USBx->GINTSTS = 0xFFFFFFFFU;
- (void)USB_EnableGlobalInt(USBx);
-
return HAL_OK;
}
@@ -1895,6 +1940,47 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) }
/**
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx : Selected device
+ * @param num : FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+#if defined (HAL_PCD_MODULE_ENABLED)
+/**
* @brief Activate and configure an endpoint
* @param USBx Selected device
* @param ep pointer to endpoint structure
@@ -2185,22 +2271,73 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* manage isochronous double buffer IN mode */
else
{
- /* Write the data to the USB endpoint */
+ /* enable double buffer */
+ PCD_SET_EP_DBUF(USBx, ep->num);
+
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ if (len > 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
- }
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ if (len > 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
}
}
@@ -2326,6 +2463,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) return HAL_OK;
}
+#endif
/**
* @brief USB_StopDevice Stop the usb device mode
diff --git a/USB_DEVICE/App/usb_device.c b/USB_DEVICE/App/usb_device.c index eafa541..e18fe02 100644 --- a/USB_DEVICE/App/usb_device.c +++ b/USB_DEVICE/App/usb_device.c @@ -99,4 +99,3 @@ void MX_USB_DEVICE_Init(void) * @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/USB_DEVICE/App/usb_device.h b/USB_DEVICE/App/usb_device.h index 12523f1..082a1e3 100644 --- a/USB_DEVICE/App/usb_device.h +++ b/USB_DEVICE/App/usb_device.h @@ -100,5 +100,3 @@ void MX_USB_DEVICE_Init(void); #endif
#endif /* __USB_DEVICE__H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/USB_DEVICE/App/usbd_custom_hid_if.c b/USB_DEVICE/App/usbd_custom_hid_if.c index 7b4bf78..28ac455 100644 --- a/USB_DEVICE/App/usbd_custom_hid_if.c +++ b/USB_DEVICE/App/usbd_custom_hid_if.c @@ -92,6 +92,7 @@ __ALIGN_BEGIN static uint8_t CUSTOM_HID_ReportDesc_FS[USBD_CUSTOM_HID_REPORT_DESC_SIZE] __ALIGN_END =
{
/* USER CODE BEGIN 0 */
+ /*
0x05, 0x01, // USAGE_PAGE (Generic Desktop)
0x09, 0x05, // USAGE (Game Pad)
0xa1, 0x01, // COLLECTION (Application)
@@ -132,6 +133,53 @@ __ALIGN_BEGIN static uint8_t CUSTOM_HID_ReportDesc_FS[USBD_CUSTOM_HID_REPORT_DES 0x75, 0x01, // REPORT_SIZE (1)
0x81, 0x01, // INPUT (Cnst,Ary,Abs)
0xc0,
+ */
+ 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */
+ 0x09, 0x05, /* USAGE (Gamepad) */
+ 0xa1, 0x01, /* COLLECTION (Application) */
+ 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
+ 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
+ 0x35, 0x00, /* PHYSICAL_MINIMUM (0) */
+ 0x45, 0x01, /* PHYSICAL_MAXIMUM (1) */
+ 0x75, 0x01, /* REPORT_SIZE (1) */
+ 0x95, 0x0e, /* REPORT_COUNT (14) */
+ 0x05, 0x09, /* USAGE_PAGE (Buttons) */
+ 0x19, 0x01, /* USAGE_MINIMUM (Button 1) */
+ 0x29, 0x0e, /* USAGE_MAXIMUM (Button 14) */
+ 0x81, 0x02, /* INPUT (Data,Var,Abs) */
+ 0x95, 0x02, /* REPORT_COUNT (2) */
+ 0x81, 0x01, /* INPUT (Data,Var,Abs) */
+ 0x05, 0x01, /* USAGE_PAGE (Generic Desktop Ctr) */
+ 0x25, 0x07, /* LOGICAL_MAXIMUM (7) */
+ 0x46, 0x3b, 0x01, /* PHYSICAL_MAXIMUM (315) */
+ 0x75, 0x04, /* REPORT_SIZE (4) */
+ 0x95, 0x01, /* REPORT_COUNT (1) */
+ 0x65, 0x14, /* UNIT (20) */
+ 0x09, 0x39, /* USAGE (Hat Switch) */
+ 0x81, 0x42, /* INPUT (Data,Var,Abs) */
+ 0x65, 0x00, /* UNIT (0) */
+ 0x95, 0x01, /* REPORT_COUNT (1) */
+ 0x81, 0x01, /* INPUT (Data,Var,Abs) */
+ 0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */
+ 0x46, 0xff, 0x00, /* PHYSICAL_MAXIMUM (255) */
+ 0x09, 0x30, /* USAGE (Direction-X) */
+ 0x09, 0x31, /* USAGE (Direction-Y) */
+ 0x09, 0x32, /* USAGE (Direction-Z) */
+ 0x09, 0x35, /* USAGE (Rotate-Z) */
+ 0x75, 0x08, /* REPORT_SIZE (8) */
+ 0x95, 0x04, /* REPORT_COUNT (4) */
+ 0x81, 0x02, /* INPUT (Data,Var,Abs) */
+ 0x75, 0x08, /* REPORT_SIZE (8) */
+ 0x95, 0x01, /* REPORT_COUNT (1) */
+ 0x81, 0x01, /* INPUT (Data,Var,Abs) */
+ // extra, for nunchuck
+ //0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */
+ //0x46, 0xff, 0x00, /* PHYSICAL_MAXIMUM (255) */
+ //0x09, 0x33, /* USAGE (Rx) */
+ //0x09, 0x34, /* USAGE (Ry) */
+ //0x75, 0x08, /* REPORT_SIZE (8) */
+ //0x95, 0x02, /* REPORT_COUNT (2) */
+ //0x81, 0x02, /* INPUT (Data,Var,Abs) */
/* USER CODE END 0 */
0xC0 /* END_COLLECTION */
};
@@ -250,5 +298,3 @@ static int8_t USBD_CUSTOM_HID_SendReport_FS(uint8_t *report, uint16_t len) * @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/USB_DEVICE/App/usbd_custom_hid_if.h b/USB_DEVICE/App/usbd_custom_hid_if.h index 7c497e5..9370ef2 100644 --- a/USB_DEVICE/App/usbd_custom_hid_if.h +++ b/USB_DEVICE/App/usbd_custom_hid_if.h @@ -126,4 +126,3 @@ extern USBD_CUSTOM_HID_ItfTypeDef USBD_CustomHID_fops_FS; #endif /* __USBD_CUSTOM_HID_IF_H__ */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/USB_DEVICE/App/usbd_desc.c b/USB_DEVICE/App/usbd_desc.c index f875aac..3434edd 100644 --- a/USB_DEVICE/App/usbd_desc.c +++ b/USB_DEVICE/App/usbd_desc.c @@ -63,10 +63,10 @@ * @{
*/
-#define USBD_VID 5511
+#define USBD_VID 0x0f0d
#define USBD_LANGID_STRING 1033
#define USBD_MANUFACTURER_STRING "Cluster"
-#define USBD_PID_FS 22352
+#define USBD_PID_FS 0x00c1
#define USBD_PRODUCT_STRING_FS "Wii Accessory"
#define USBD_CONFIGURATION_STRING_FS "Custom HID Config"
#define USBD_INTERFACE_STRING_FS "Custom HID Interface"
@@ -182,7 +182,7 @@ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = #pragma data_alignment=4
#endif /* defined ( __ICCARM__ ) */
-/** USB lang indentifier descriptor. */
+/** USB lang identifier descriptor. */
__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
{
USB_LEN_LANGID_STR_DESC,
@@ -391,4 +391,3 @@ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) * @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/USB_DEVICE/App/usbd_desc.h b/USB_DEVICE/App/usbd_desc.h index 0ce33b5..5b09f2f 100644 --- a/USB_DEVICE/App/usbd_desc.h +++ b/USB_DEVICE/App/usbd_desc.h @@ -142,4 +142,3 @@ extern USBD_DescriptorsTypeDef FS_Desc; #endif /* __USBD_DESC__C__ */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/USB_DEVICE/Target/usbd_conf.c b/USB_DEVICE/Target/usbd_conf.c index 745aef6..afd6fc1 100644 --- a/USB_DEVICE/Target/usbd_conf.c +++ b/USB_DEVICE/Target/usbd_conf.c @@ -562,10 +562,10 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_a }
/**
- * @brief Returns the last transfered packet size.
+ * @brief Returns the last transferred packet size.
* @param pdev: Device handle
* @param ep_addr: Endpoint number
- * @retval Recived Data Size
+ * @retval Received Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
@@ -630,7 +630,7 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) }
/**
- * @brief Retuns the USB status depending on the HAL status:
+ * @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
@@ -658,5 +658,3 @@ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) }
return usb_status;
}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/USB_DEVICE/Target/usbd_conf.h b/USB_DEVICE/Target/usbd_conf.h index 6b62ced..f1b757f 100644 --- a/USB_DEVICE/Target/usbd_conf.h +++ b/USB_DEVICE/Target/usbd_conf.h @@ -75,7 +75,7 @@ /*---------- -----------*/
#define USBD_CUSTOMHID_OUTREPORT_BUF_SIZE 16
/*---------- -----------*/
-#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 81
+#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 80
/*---------- -----------*/
#define CUSTOM_HID_FS_BINTERVAL 1
@@ -178,4 +178,3 @@ void USBD_static_free(void *p); #endif /* __USBD_CONF__H__ */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/wii2usb.ioc b/wii2usb.ioc index 5853d0b..57ce89f 100644 --- a/wii2usb.ioc +++ b/wii2usb.ioc @@ -1,6 +1,7 @@ #MicroXplorer Configuration settings - do not modify
File.Version=6
KeepUserPlacement=false
+Mcu.CPN=STM32F103RET6
Mcu.Family=STM32F1
Mcu.IP0=I2C1
Mcu.IP1=NVIC
@@ -29,20 +30,20 @@ Mcu.PinsNb=14 Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F103RETx
-MxCube.Version=6.0.1
-MxDb.Version=DB.6.0.0
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+MxCube.Version=6.6.1
+MxDb.Version=DB.6.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-NVIC.USB_LP_CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
+NVIC.USB_LP_CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=LED_WII
PA10.Locked=true
@@ -65,8 +66,12 @@ PB5.GPIOParameters=GPIO_Label PB5.GPIO_Label=DTCT
PB5.Locked=true
PB5.Signal=GPIO_Input
+PB6.GPIOParameters=GPIO_Pu
+PB6.GPIO_Pu=GPIO_PULLUP
PB6.Mode=I2C
PB6.Signal=I2C1_SCL
+PB7.GPIOParameters=GPIO_Pu
+PB7.GPIO_Pu=GPIO_PULLUP
PB7.Mode=I2C
PB7.Signal=I2C1_SDA
PD0-OSC_IN.Mode=HSE-External-Oscillator
@@ -83,7 +88,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F103RETx
-ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.1
+ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
@@ -134,12 +139,12 @@ USB_DEVICE.CLASS_NAME_FS=CUSTOM_HID USB_DEVICE.CUSTOM_HID_FS_BINTERVAL=1
USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS,PID_CUSTOMHID_FS,MANUFACTURER_STRING,PRODUCT_STRING_CUSTOMHID_FS,USBD_CUSTOM_HID_REPORT_DESC_SIZE,USBD_CUSTOMHID_OUTREPORT_BUF_SIZE,CUSTOM_HID_FS_BINTERVAL,USBD_DEBUG_LEVEL,VID
USB_DEVICE.MANUFACTURER_STRING=Cluster
-USB_DEVICE.PID_CUSTOMHID_FS=22352
+USB_DEVICE.PID_CUSTOMHID_FS=0x00c1
USB_DEVICE.PRODUCT_STRING_CUSTOMHID_FS=Wii Accessory
USB_DEVICE.USBD_CUSTOMHID_OUTREPORT_BUF_SIZE=16
-USB_DEVICE.USBD_CUSTOM_HID_REPORT_DESC_SIZE=81
+USB_DEVICE.USBD_CUSTOM_HID_REPORT_DESC_SIZE=80
USB_DEVICE.USBD_DEBUG_LEVEL=3
-USB_DEVICE.VID=5511
+USB_DEVICE.VID=0x0f0d
USB_DEVICE.VirtualMode=CustomHid
USB_DEVICE.VirtualModeFS=Custom_Hid_FS
VP_SYS_VS_Systick.Mode=SysTick
|