diff options
author | David Crocker <dcrocker@eschertech.com> | 2020-09-07 17:51:44 +0300 |
---|---|---|
committer | David Crocker <dcrocker@eschertech.com> | 2020-09-07 17:51:44 +0300 |
commit | 78593ec1d7141949f7597590bd12bf12e12619ca (patch) | |
tree | 01988c1cbec7244641461671ec0441de84a7734b /src/Hardware/ExceptionHandlers.cpp | |
parent | 7b485e5189f943cbab6d8bf32339b03ee8ccc0ca (diff) |
Fixes, mostly for software resets
Reduced stack length in software reset data to 27 words because we can't
print more
Avoid some unaligned accesses to CAN data etc.
Add dwell time before M122 P100x operations that cause a reset, so allow
the HTTP response to be sent back to DWC, otherwise it will retry
Fixed issue with NVM not getting initialised after a firmware upgrade
Binary parser only pads arrays out if exactly one value was given
Diffstat (limited to 'src/Hardware/ExceptionHandlers.cpp')
-rw-r--r-- | src/Hardware/ExceptionHandlers.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/Hardware/ExceptionHandlers.cpp b/src/Hardware/ExceptionHandlers.cpp index 4eff7345..e53009ff 100644 --- a/src/Hardware/ExceptionHandlers.cpp +++ b/src/Hardware/ExceptionHandlers.cpp @@ -23,11 +23,6 @@ void SoftwareReset(uint16_t reason, const uint32_t *stk) noexcept Cache::Disable(); -#if USE_MPU - //TODO set the flash memory to strongly-ordered or device instead - ARM_MPU_Disable(); // disable the MPU -#endif - if (reason == (uint16_t)SoftwareResetReason::erase) { #if SAME5x @@ -98,6 +93,7 @@ void HardFault_Handler() noexcept " mrsne r0, psp \n" " ldr r2, handler_hf_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_hf_address_const: .word hardFaultDispatcher \n" ); } @@ -121,6 +117,7 @@ void MemManage_Handler() noexcept " mrsne r0, psp \n" " ldr r2, handler_mf_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_mf_address_const: .word memManageDispatcher \n" ); } @@ -150,6 +147,7 @@ void WDT_Handler() noexcept " mrsne r0, psp \n" " ldr r2, handler_wdt_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_wdt_address_const: .word wdtFaultDispatcher \n" ); } @@ -172,6 +170,7 @@ void OtherFault_Handler() noexcept " mrsne r0, psp \n" " ldr r2, handler_oflt_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_oflt_address_const: .word otherFaultDispatcher \n" ); } @@ -199,6 +198,7 @@ void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName) noexce " mov r0, sp \n" " ldr r2, handler_sovf_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_sovf_address_const: .word stackOverflowDispatcher \n" ); } @@ -221,6 +221,7 @@ void vAssertCalled(uint32_t line, const char *file) noexcept " mov r0, sp \n" " ldr r2, handler_asrt_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_asrt_address_const: .word assertCalledDispatcher \n" ); } @@ -240,6 +241,7 @@ void vApplicationMallocFailedHook() noexcept " mov r0, sp \n" " ldr r2, handler_amf_address_const \n" " bx r2 \n" + " .align 2 \n" /* make the 2 LSBs zero at the next instruction */ " handler_amf_address_const: .word applicationMallocFailedCalledDispatcher \n" ); } |