diff options
| author | David Crocker <dcrocker@eschertech.com> | 2022-05-18 18:19:55 +0300 |
|---|---|---|
| committer | David Crocker <dcrocker@eschertech.com> | 2022-05-18 18:19:55 +0300 |
| commit | a63451632e48388da8cfe5b0861a6a0461cc9d02 (patch) | |
| tree | 2ab1248cda6dfc6c86b9f2c02ad11c9766435566 /src/Hardware | |
| parent | 32b9f715fdca487125cd77a57c458512929c78a2 (diff) | |
Added build configuration for FMDC v0.3
Diffstat (limited to 'src/Hardware')
| -rw-r--r-- | src/Hardware/SAME5x/Devices.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/Hardware/SAME5x/Devices.cpp b/src/Hardware/SAME5x/Devices.cpp index 30d4dbbd..689dc8b4 100644 --- a/src/Hardware/SAME5x/Devices.cpp +++ b/src/Hardware/SAME5x/Devices.cpp @@ -122,16 +122,16 @@ static void UsbInit() noexcept static void SdhcInit() noexcept { // Set up SDHC clock -#if defined(DUET3MINI_V04) +#if defined(DUET3MINI_V04) || defined(FMDC_V02) // Using SDHC 1 hri_mclk_set_AHBMASK_SDHC1_bit(MCLK); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, GCLK_PCHCTRL_GEN(GclkNum90MHz) | GCLK_PCHCTRL_CHEN); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, GCLK_PCHCTRL_GEN(GclkNum31KHz) | GCLK_PCHCTRL_CHEN); -#elif defined(FMDC_V02) - // Using SDHC 1 on v0.2 board - hri_mclk_set_AHBMASK_SDHC1_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, GCLK_PCHCTRL_GEN(GclkNum90MHz) | GCLK_PCHCTRL_CHEN); - hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, GCLK_PCHCTRL_GEN(GclkNum31KHz) | GCLK_PCHCTRL_CHEN); +#elif defined(FMDC_V03) + // Using SDHC 0 on v0.3 board + hri_mclk_set_AHBMASK_SDHC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, GCLK_PCHCTRL_GEN(GclkNum90MHz) | GCLK_PCHCTRL_CHEN); + hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, GCLK_PCHCTRL_GEN(GclkNum31KHz) | GCLK_PCHCTRL_CHEN); #else # error Unknown board #endif |