diff options
| author | David Crocker <dcrocker@eschertech.com> | 2019-11-14 00:33:15 +0300 |
|---|---|---|
| committer | David Crocker <dcrocker@eschertech.com> | 2019-11-14 00:33:15 +0300 |
| commit | 0bd7e4618f0df71f271cc031604eb4d33f69cd8b (patch) | |
| tree | ba5a3b233fb6dc0f0c74d231ef4f3d71807d5da1 /src/Tasks.cpp | |
| parent | 54259da8a68b184f8c1bd5b91338aa71fa5492f4 (diff) | |
Refactor StepTimer and step interrupts
SoftTimer class renamed StepTimer. We now use instances of StepTimer to schedule step interrupts. This means we only need a single compare match interrupt from the step timer TC. In turn this allows us to chain two 16-bit timers together on the SAM4S and SAME70 so we no longer need to keep the upper 16 bits in software or use the overflow interrupt.
Diffstat (limited to 'src/Tasks.cpp')
| -rw-r--r-- | src/Tasks.cpp | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/src/Tasks.cpp b/src/Tasks.cpp index ae7c7af5..5591e129 100644 --- a/src/Tasks.cpp +++ b/src/Tasks.cpp @@ -176,7 +176,6 @@ extern "C" [[noreturn]] void AppMain() SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; #if SAME70 && USE_MPU - // Set up the MPU so that we can have a non-cacheable RAM region, and so that we can trap accesses to non-existent memory // Where regions overlap, the region with the highest region number takes priority constexpr ARM_MPU_Region_t regionTable[] = @@ -186,7 +185,7 @@ extern "C" [[noreturn]] void AppMain() ARM_MPU_RBAR(0, IFLASH_ADDR), ARM_MPU_RASR_EX(0u, ARM_MPU_AP_RO, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_WB_WRA, ARM_MPU_CACHEP_WB_WRA, 1u), 0u, ARM_MPU_REGION_SIZE_1MB) }, - // First 256kb RAM, read-write, cacheable, execute disabled. Parts of this are is overridden later. + // First 256kb RAM, read-write, cacheable, execute disabled. Parts of this are overridden later. { ARM_MPU_RBAR(1, IRAM_ADDR), ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_WB_WRA, ARM_MPU_CACHEP_WB_WRA, 1u), 0u, ARM_MPU_REGION_SIZE_256KB) @@ -255,9 +254,8 @@ extern "C" [[noreturn]] void AppMain() pinMode(LED3, OUTPUT_LOW); pinMode(LED4, OUTPUT_LOW); #else - // When doing a software reset, we disable the NRST input (User reset) to prevent the negative-going pulse that gets generated on it - // being held in the capacitor and changing the reset reason from Software to User. So enable it again here. We hope that the reset signal - // will have gone away by now. + // When doing a software reset, we disable the NRST input (User reset) to prevent the negative-going pulse that gets generated on it being held + // in the capacitor and changing the reset reason from Software to User. So enable it again here. We hope that the reset signal will have gone away by now. # ifndef RSTC_MR_KEY_PASSWD // Definition of RSTC_MR_KEY_PASSWD is missing in the SAM3X ASF files # define RSTC_MR_KEY_PASSWD (0xA5u << 24) @@ -275,8 +273,15 @@ extern "C" [[noreturn]] void AppMain() EnableCache(); #endif - // Add the FreeRTOS internal tasks to the task list - idleTask.AddToList(); +#if SAM4S + efc_enable_cloe(EFC0); // enable code loop optimisation +#endif + +#if SAM4E || SAME70 + efc_enable_cloe(EFC); // enable code loop optimisation +#endif + + idleTask.AddToList(); // add the FreeRTOS internal tasks to the task list #if configUSE_TIMERS timerTask.AddToList(); @@ -285,7 +290,7 @@ extern "C" [[noreturn]] void AppMain() // Create the startup task mainTask.Create(MainTask, "MAIN", nullptr, TaskPriority::SpinPriority); vTaskStartScheduler(); // doesn't return - for (;;) { } // kep gcc happy + for (;;) { } // keep gcc happy } extern "C" [[noreturn]] void MainTask(void *pvParameters) |