diff options
| author | David Crocker <dcrocker@eschertech.com> | 2022-04-29 14:34:40 +0300 |
|---|---|---|
| committer | David Crocker <dcrocker@eschertech.com> | 2022-04-29 14:34:40 +0300 |
| commit | d4ad8377decb4b59708eb4af07d3e79e5a4bc15f (patch) | |
| tree | 4cfe450d6956c556b07c3cb9e88e206341df0a33 /src | |
| parent | e4794741e9afa7ad26b91f6e3dc96ef5dab6db72 (diff) | |
Got SDHC working in FMDC build
Diffstat (limited to 'src')
| -rw-r--r-- | src/Config/Pins_FMDC.h | 2 | ||||
| -rw-r--r-- | src/Hardware/SAME5x/Devices.cpp | 8 | ||||
| -rw-r--r-- | src/Libraries/sd_mmc/conf_sd_mmc.h | 4 |
3 files changed, 5 insertions, 9 deletions
diff --git a/src/Config/Pins_FMDC.h b/src/Config/Pins_FMDC.h index f496338e..747756a8 100644 --- a/src/Config/Pins_FMDC.h +++ b/src/Config/Pins_FMDC.h @@ -29,7 +29,7 @@ constexpr uint32_t IAP_IMAGE_START = 0x20028000; #define HAS_SBC_INTERFACE 0 #define HAS_MASS_STORAGE 1 -#define HAS_HIGH_SPEED_SD 0//1 +#define HAS_HIGH_SPEED_SD 1 //#define HAS_CPU_TEMP_SENSOR 0 // according to the SAME5x errata doc, the temperature sensors don't work in revision A or D chips (revision D is latest as at 2020-06-28) #define HAS_CPU_TEMP_SENSOR 1 // enable this as an experiment - it may be better than nothing diff --git a/src/Hardware/SAME5x/Devices.cpp b/src/Hardware/SAME5x/Devices.cpp index aeb7f6a1..30d4dbbd 100644 --- a/src/Hardware/SAME5x/Devices.cpp +++ b/src/Hardware/SAME5x/Devices.cpp @@ -128,10 +128,10 @@ static void SdhcInit() noexcept hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, GCLK_PCHCTRL_GEN(GclkNum90MHz) | GCLK_PCHCTRL_CHEN); hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, GCLK_PCHCTRL_GEN(GclkNum31KHz) | GCLK_PCHCTRL_CHEN); #elif defined(FMDC_V02) - // Using SDHC 0 - hri_mclk_set_AHBMASK_SDHC0_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, GCLK_PCHCTRL_GEN(GclkNum90MHz) | GCLK_PCHCTRL_CHEN); - hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, GCLK_PCHCTRL_GEN(GclkNum31KHz) | GCLK_PCHCTRL_CHEN); + // Using SDHC 1 on v0.2 board + hri_mclk_set_AHBMASK_SDHC1_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, GCLK_PCHCTRL_GEN(GclkNum90MHz) | GCLK_PCHCTRL_CHEN); + hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, GCLK_PCHCTRL_GEN(GclkNum31KHz) | GCLK_PCHCTRL_CHEN); #else # error Unknown board #endif diff --git a/src/Libraries/sd_mmc/conf_sd_mmc.h b/src/Libraries/sd_mmc/conf_sd_mmc.h index c506b42b..e25c8321 100644 --- a/src/Libraries/sd_mmc/conf_sd_mmc.h +++ b/src/Libraries/sd_mmc/conf_sd_mmc.h @@ -55,12 +55,8 @@ // SD card configuration for Duet and Duet WiFi #define SD_MMC_ENABLE -#ifdef FMDC_V02 -#define SD_MMC_HSMCI_MEM_CNT 0 // TEMP disable SDHC -#else #define SD_MMC_HSMCI_MEM_CNT 1 // Number of HSMCI card slots supported #define SD_MMC_HSMCI_SLOT_0_SIZE 4 // HSMCI bus width -#endif #ifdef PCCB # define SD_MMC_SPI_MEM_CNT 0 // Number of SPI card slots supported |