diff options
| author | Rémi Denis-Courmont <remi@remlab.net> | 2022-09-26 17:52:49 +0300 |
|---|---|---|
| committer | Lynne <dev@lynne.ee> | 2022-09-27 14:19:52 +0300 |
| commit | 09f907999f6ff4204d5848e5fd01e1143cb76d9c (patch) | |
| tree | 9e76801e91ecaf0af8eb0d6c50f1bde71905ca18 /libavcodec/riscv | |
| parent | 15c3a0bd6ec1383e26ca6a41ea8daa95dc0e1736 (diff) | |
lavc/aacpsdsp: RISC-V V hybrid_analysis_ileave
Diffstat (limited to 'libavcodec/riscv')
| -rw-r--r-- | libavcodec/riscv/aacpsdsp_init.c | 5 | ||||
| -rw-r--r-- | libavcodec/riscv/aacpsdsp_rvv.S | 35 |
2 files changed, 40 insertions, 0 deletions
diff --git a/libavcodec/riscv/aacpsdsp_init.c b/libavcodec/riscv/aacpsdsp_init.c index 09f16f1041..1d36f89f6e 100644 --- a/libavcodec/riscv/aacpsdsp_init.c +++ b/libavcodec/riscv/aacpsdsp_init.c @@ -29,6 +29,8 @@ void ff_ps_mul_pair_single_rvv(float (*dst)[2], float (*src0)[2], float *src1, int n); void ff_ps_hybrid_analysis_rvv(float (*out)[2], float (*in)[2], const float (*filter)[8][2], ptrdiff_t, int n); +void ff_ps_hybrid_analysis_ileave_rvv(float (*out)[32][2], float L[2][38][64], + int i, int len); av_cold void ff_psdsp_init_riscv(PSDSPContext *c) { @@ -40,5 +42,8 @@ av_cold void ff_psdsp_init_riscv(PSDSPContext *c) c->mul_pair_single = ff_ps_mul_pair_single_rvv; c->hybrid_analysis = ff_ps_hybrid_analysis_rvv; } + + if (flags & AV_CPU_FLAG_RVV_I32) + c->hybrid_analysis_ileave = ff_ps_hybrid_analysis_ileave_rvv; #endif } diff --git a/libavcodec/riscv/aacpsdsp_rvv.S b/libavcodec/riscv/aacpsdsp_rvv.S index 65e5e0be4f..c9cc15e73d 100644 --- a/libavcodec/riscv/aacpsdsp_rvv.S +++ b/libavcodec/riscv/aacpsdsp_rvv.S @@ -149,3 +149,38 @@ func ff_ps_hybrid_analysis_rvv, zve32f .purgem input .purgem filter endfunc + +func ff_ps_hybrid_analysis_ileave_rvv, zve32x /* no needs for zve32f here */ + slli t0, a2, 5 + 1 + 2 // ctz(32 * 2 * 4) + sh2add a1, a2, a1 + add a0, a0, t0 + addi a2, a2, -64 + li t1, 38 * 64 * 4 + li t6, 64 * 4 // (uint8_t *)L[x][j+1][i] - L[x][j][i] + add a4, a1, t1 // &L[1] + beqz a2, 3f +1: + mv t0, a0 + mv t1, a1 + mv t3, a3 + mv t4, a4 + addi a2, a2, 1 +2: + vsetvli t5, t3, e32, m1, ta, ma + vlse32.v v16, (t1), t6 + sub t3, t3, t5 + vlse32.v v17, (t4), t6 + mul t2, t5, t6 + vsseg2e32.v v16, (t0) + sh3add t0, t5, t0 + add t1, t1, t2 + add t4, t4, t2 + bnez t3, 2b + + add a0, a0, 32 * 2 * 4 + add a1, a1, 4 + add a4, a4, 4 + bnez a2, 1b +3: + ret +endfunc |