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| author | Rémi Denis-Courmont <remi@remlab.net> | 2022-09-26 17:52:25 +0300 |
|---|---|---|
| committer | Lynne <dev@lynne.ee> | 2022-09-27 14:19:52 +0300 |
| commit | 0c0a3deb1826638915775daa7cefb891a300060b (patch) | |
| tree | d3a0dfdf84e60d72174d5399e8c3fe89b17c0352 /tests | |
| parent | 1edac8eb468cb9a769ded6197dbce515b71b137e (diff) | |
lavu/cpu: CPU flags for the RISC-V Vector extension
RVV defines a total of 12 different extensions, including:
- 5 different instruction subsets:
- Zve32x: 8-, 16- and 32-bit integers,
- Zve32f: Zve32x plus single precision floats,
- Zve64x: Zve32x plus 64-bit integers,
- Zve64f: Zve32f plus Zve64x,
- Zve64d: Zve64f plus double precision floats.
- 6 different vector lengths:
- Zvl32b (embedded only),
- Zvl64b (embedded only),
- Zvl128b,
- Zvl256b,
- Zvl512b,
- Zvl1024b,
- and the V extension proper: equivalent to Zve64f and Zvl128b.
In total, there are 6 different possible sets of supported instructions
(including the empty set), but for convenience we allocate one bit for
each type sets: up-to-32-bit ints (RVV_I32), floats (RVV_F32),
64-bit ints (RVV_I64) and doubles (RVV_F64).
Whence the vector size is needed, it can be retrieved by reading the
unprivileged read-only vlenb CSR. This should probably be a separate
helper macro if needed at a later point.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/checkasm/checkasm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index e1135a84ac..90dd7e4634 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -236,6 +236,10 @@ static const struct { { "RVI", "rvi", AV_CPU_FLAG_RVI }, { "RVF", "rvf", AV_CPU_FLAG_RVF }, { "RVD", "rvd", AV_CPU_FLAG_RVD }, + { "RVVi32", "rvv_i32", AV_CPU_FLAG_RVV_I32 }, + { "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 }, + { "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 }, + { "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 }, #elif ARCH_MIPS { "MMI", "mmi", AV_CPU_FLAG_MMI }, { "MSA", "msa", AV_CPU_FLAG_MSA }, |