diff options
| author | Rémi Denis-Courmont <remi@remlab.net> | 2022-09-26 17:52:21 +0300 |
|---|---|---|
| committer | Lynne <dev@lynne.ee> | 2022-09-27 14:19:52 +0300 |
| commit | b95e2fbd85e93b58d019ad0e3da64a72ee7cc3d5 (patch) | |
| tree | ccf3b030be7df33cf5312936bb017469a3522e68 /tests | |
| parent | 179830108dbeb1c6b73105ae2234cf04874728b4 (diff) | |
lavu/cpu: detect RISC-V base extensions
This introduces compile-time and run-time CPU detection on RISC-V. In
practice, I doubt that FFmpeg will ever see a RISC-V CPU without all of
I, F and D extensions, and if it does, it probably won't have run-time
detection. So the flags are essentially always set.
But as things stand, checkasm wants them that way. Compare the ARMV8
flag on AArch64. We are nowhere near running short on CPU flag bits.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/checkasm/checkasm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/checkasm/checkasm.c b/tests/checkasm/checkasm.c index 8fd9bba0b0..e1135a84ac 100644 --- a/tests/checkasm/checkasm.c +++ b/tests/checkasm/checkasm.c @@ -232,6 +232,10 @@ static const struct { { "ALTIVEC", "altivec", AV_CPU_FLAG_ALTIVEC }, { "VSX", "vsx", AV_CPU_FLAG_VSX }, { "POWER8", "power8", AV_CPU_FLAG_POWER8 }, +#elif ARCH_RISCV + { "RVI", "rvi", AV_CPU_FLAG_RVI }, + { "RVF", "rvf", AV_CPU_FLAG_RVF }, + { "RVD", "rvd", AV_CPU_FLAG_RVD }, #elif ARCH_MIPS { "MMI", "mmi", AV_CPU_FLAG_MMI }, { "MSA", "msa", AV_CPU_FLAG_MSA }, |