Clockless_rmt_esp32 support for new ESP32 variants

* Tested on ESPC3 hardware, not yet tested on ESPS3 or H2

2 files changed, 113 insertions, 6 deletions

diff --git a/src/platforms/esp/32/clockless_rmt_esp32.cpp b/src/platforms/esp/32/clockless_rmt_esp32.cpp
index 90ca046f..a3a87572 100644
--- a/src/platforms/esp/32/clockless_rmt_esp32.cpp
+++ b/src/platforms/esp/32/clockless_rmt_esp32.cpp
@@ -240,7 +240,11 @@ void IRAM_ATTR ESP32RMTController::startOnChannel(int channel)
     gOnChannel[channel] = this;
 
     // -- Assign the pin to this channel
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 4, 0)
+    rmt_set_gpio(mRMT_channel, RMT_MODE_TX, mPin, false);
+#else
     rmt_set_pin(mRMT_channel, RMT_MODE_TX, mPin);
+#endif
 
     if (FASTLED_RMT_BUILTIN_DRIVER) {
         // -- Use the built-in RMT driver to send all the data in one shot
@@ -275,11 +279,46 @@ void IRAM_ATTR ESP32RMTController::tx_start()
 {
     // rmt_tx_start(mRMT_channel, true);
     // Inline the code for rmt_tx_start, so it can be placed in IRAM
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+    // rmt_ll_tx_reset_pointer(&RMT, mRMT_channel)
+    RMT.tx_conf[mRMT_channel].mem_rd_rst = 1;
+    RMT.tx_conf[mRMT_channel].mem_rd_rst = 0;
+    RMT.tx_conf[mRMT_channel].mem_rst = 1;
+    RMT.tx_conf[mRMT_channel].mem_rst = 0;
+    // rmt_ll_clear_tx_end_interrupt(&RMT, mRMT_channel)
+    RMT.int_clr.val = (1 << (mRMT_channel));
+    // rmt_ll_enable_tx_end_interrupt(&RMT, mRMT_channel, true)
+    RMT.int_ena.val |= (1 << mRMT_channel);
+    // rmt_ll_tx_start(&RMT, mRMT_channel)
+    RMT.tx_conf[mRMT_channel].conf_update = 1;
+    RMT.tx_conf[mRMT_channel].tx_start = 1;
+#elif CONFIG_IDF_TARGET_ESP32S3
+    // rmt_ll_tx_reset_pointer(&RMT, mRMT_channel)
+    RMT.chnconf0[mRMT_channel].mem_rd_rst_n = 1;
+    RMT.chnconf0[mRMT_channel].mem_rd_rst_n = 0;
+    RMT.chnconf0[mRMT_channel].apb_mem_rst_n = 1;
+    RMT.chnconf0[mRMT_channel].apb_mem_rst_n = 0;
+    // rmt_ll_clear_tx_end_interrupt(&RMT, mRMT_channel)
+    RMT.int_clr.val = (1 << (mRMT_channel));
+    // rmt_ll_enable_tx_end_interrupt(&RMT, mRMT_channel, true)
+    RMT.int_ena.val |= (1 << mRMT_channel);
+    // rmt_ll_tx_start(&RMT, mRMT_channel)
+    RMT.chnconf0[mRMT_channel].conf_update_n = 1;
+    RMT.chnconf0[mRMT_channel].tx_start_n = 1;
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+    // rmt_ll_tx_reset_pointer(&RMT, mRMT_channel)
     RMT.conf_ch[mRMT_channel].conf1.mem_rd_rst = 1;
     RMT.conf_ch[mRMT_channel].conf1.mem_rd_rst = 0;
+    // rmt_ll_clear_tx_end_interrupt(&RMT, mRMT_channel)
+    RMT.int_clr.val = (1 << (mRMT_channel * 3));
+    // rmt_ll_enable_tx_end_interrupt(&RMT, mRMT_channel, true)
     RMT.int_ena.val &= ~(1 << (mRMT_channel * 3));
     RMT.int_ena.val |= (1 << (mRMT_channel * 3));
+    // rmt_ll_tx_start(&RMT, mRMT_channel)
     RMT.conf_ch[mRMT_channel].conf1.tx_start = 1;
+#else
+    #error Not yet implemented for unknown ESP32 target
+#endif
     mLastFill = __clock_cycles();
 }
 
@@ -299,10 +338,51 @@ void IRAM_ATTR ESP32RMTController::doneOnChannel(rmt_channel_t channel, void * a
 
     // -- Turn off the interrupts
     // rmt_set_tx_intr_en(channel, false);
-    // Inline the code for rmt_tx_stop, so it can be placed in IRAM
+
+    // Inline the code for rmt_set_tx_intr_en(channel, false) and rmt_tx_stop, so it can be placed in IRAM
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+    // rmt_ll_enable_tx_end_interrupt(&RMT, channel)
+    RMT.int_ena.val &= ~(1 << channel);
+    // rmt_ll_tx_stop(&RMT, channel)
+    RMT.tx_conf[channel].tx_stop = 1;
+    RMT.tx_conf[channel].conf_update = 1;
+    // rmt_ll_tx_reset_pointer(&RMT, channel)
+    RMT.tx_conf[channel].mem_rd_rst = 1;
+    RMT.tx_conf[channel].mem_rd_rst = 0;
+    RMT.tx_conf[channel].mem_rst = 1;
+    RMT.tx_conf[channel].mem_rst = 0;
+#elif CONFIG_IDF_TARGET_ESP32S3
+    // rmt_ll_enable_tx_end_interrupt(&RMT, channel)
+    RMT.int_ena.val &= ~(1 << channel);
+    // rmt_ll_tx_stop(&RMT, channel)
+    RMT.chnconf0[channel].tx_stop_n = 1;
+    RMT.chnconf0[channel].conf_update_n = 1;
+    // rmt_ll_tx_reset_pointer(&RMT, channel)
+    RMT.chnconf0[channel].mem_rd_rst_n = 1;
+    RMT.chnconf0[channel].mem_rd_rst_n = 0;
+    RMT.chnconf0[channel].apb_mem_rst_n = 1;
+    RMT.chnconf0[channel].apb_mem_rst_n = 0;
+#elif CONFIG_IDF_TARGET_ESP32S2
+    // rmt_ll_enable_tx_end_interrupt(&RMT, channel)
+    RMT.int_ena.val &= ~(1 << (channel * 3));
+    // rmt_ll_tx_stop(&RMT, channel)
+    RMT.conf_ch[channel].conf1.tx_stop = 1;
+    // rmt_ll_tx_reset_pointer(&RMT, channel)
+    RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
+    RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
+#elif CONFIG_IDF_TARGET_ESP32
+    // rmt_ll_enable_tx_end_interrupt(&RMT, channel)
     RMT.int_ena.val &= ~(1 << (channel * 3));
+    // rmt_ll_tx_stop(&RMT, channel)
+    RMT.conf_ch[channel].conf1.tx_start = 0;
     RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
     RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
+    // rmt_ll_tx_reset_pointer(&RMT, channel)
+    // RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
+    // RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
+#else
+    #error Not yet implemented for unknown ESP32 target
+#endif
 
     gOnChannel[channel] = NULL;
     gNumDone++;
@@ -337,11 +417,17 @@ void IRAM_ATTR ESP32RMTController::interruptHandler(void *arg)
     uint8_t channel;
 
     for (channel = 0; channel < gMaxChannel; channel++) {
+        #if CONFIG_IDF_TARGET_ESP32S2
         int tx_done_bit = channel * 3;
-        #ifdef CONFIG_IDF_TARGET_ESP32S2
         int tx_next_bit = channel + 12;
-        #else
+        #elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+        int tx_done_bit = channel;
+        int tx_next_bit = channel + 8;
+        #elif CONFIG_IDF_TARGET_ESP32
+        int tx_done_bit = channel * 3;
         int tx_next_bit = channel + 24;
+        #else
+        #error Not yet implemented for unknown ESP32 target
         #endif
 
         ESP32RMTController * pController = gOnChannel[channel];
diff --git a/src/platforms/esp/32/clockless_rmt_esp32.h b/src/platforms/esp/32/clockless_rmt_esp32.h
index 73bcefbc..5f522d97 100644
--- a/src/platforms/esp/32/clockless_rmt_esp32.h
+++ b/src/platforms/esp/32/clockless_rmt_esp32.h
@@ -136,7 +136,11 @@ extern void spi_flash_op_unlock(void);
 
 __attribute__ ((always_inline)) inline static uint32_t __clock_cycles() {
   uint32_t cyc;
+#ifdef FASTLED_XTENSA
   __asm__ __volatile__ ("rsr %0,ccount":"=a" (cyc));
+#else
+  cyc = cpu_hal_get_cycle_count();
+#endif
   return cyc;
 }
 
@@ -164,11 +168,23 @@ __attribute__ ((always_inline)) inline static uint32_t __clock_cycles() {
 #define FASTLED_RMT_MEM_BLOCKS 2
 #endif
 
-#define MAX_PULSES         (64 * FASTLED_RMT_MEM_BLOCKS) /* One block has a 64 "pulse" buffer */
+// 64 for ESP32, ESP32S2
+// 48 for ESP32S3, ESP32C3, ESP32H2
+#ifndef FASTLED_RMT_MEM_WORDS_PER_CHANNEL
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 4, 0)
+#define FASTLED_RMT_MEM_WORDS_PER_CHANNEL SOC_RMT_MEM_WORDS_PER_CHANNEL
+#else
+// ESP32 value (only chip variant supported on older IDF)
+#define FASTLED_RMT_MEM_WORDS_PER_CHANNEL 64 
+#endif 
+#endif
+
+#define MAX_PULSES (FASTLED_RMT_MEM_WORDS_PER_CHANNEL * FASTLED_RMT_MEM_BLOCKS)
 #define PULSES_PER_FILL    (MAX_PULSES / 2)              /* Half of the channel buffer */
 
 // -- Convert ESP32 CPU cycles to RMT device cycles, taking into account the divider
-#define F_CPU_RMT                   (  80000000L)
+// RMT Clock is typically APB CLK, which is 80MHz on most devices, but 40MHz on ESP32-H2
+#define F_CPU_RMT                   (  APB_CLK_FREQ )
 #define RMT_CYCLES_PER_SEC          (F_CPU_RMT/DIVIDER)
 #define RMT_CYCLES_PER_ESP_CYCLE    (F_CPU / RMT_CYCLES_PER_SEC)
 #define ESP_TO_RMT_CYCLES(n)        ((n) / (RMT_CYCLES_PER_ESP_CYCLE))
@@ -188,14 +204,19 @@ __attribute__ ((always_inline)) inline static uint32_t __clock_cycles() {
 #define FASTLED_RMT_MAX_CONTROLLERS 32
 #endif
 
-// -- Max RMT channel (default to 8 on ESP32 and 4 on ESP32-S2)
+// -- Max RMT TX channel
 #ifndef FASTLED_RMT_MAX_CHANNELS
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 4, 0)
+// 8 for (ESP32)  4 for (ESP32S2, ESP32S3)  2 for (ESP32C3, ESP32H2)
+#define FASTLED_RMT_MAX_CHANNELS SOC_RMT_TX_CANDIDATES_PER_GROUP
+#else
 #ifdef CONFIG_IDF_TARGET_ESP32S2
 #define FASTLED_RMT_MAX_CHANNELS 4
 #else
 #define FASTLED_RMT_MAX_CHANNELS 8
 #endif
 #endif
+#endif
 
 class ESP32RMTController
 {