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name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></td></tr> +<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Setup information of a single MPU Region. <a href="structARM__MPU__Region__t.html#details">More...</a><br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:gab4bfac6284dc050dc6fa6aeb8e954c2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gab4bfac6284dc050dc6fa6aeb8e954c2c">ARM_MPU_ATTR_DEVICE</a>   ( 0U )</td></tr> +<tr class="memdesc:gab4bfac6284dc050dc6fa6aeb8e954c2c"><td class="mdescLeft"> </td><td class="mdescRight">Attribute for device memory (outer only) <a href="#gab4bfac6284dc050dc6fa6aeb8e954c2c">More...</a><br/></td></tr> +<tr class="separator:gab4bfac6284dc050dc6fa6aeb8e954c2c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga03266f9660485693eb1baec6ba255ab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga03266f9660485693eb1baec6ba255ab2">ARM_MPU_ATTR_NON_CACHEABLE</a>   ( 4U )</td></tr> +<tr class="memdesc:ga03266f9660485693eb1baec6ba255ab2"><td class="mdescLeft"> </td><td class="mdescRight">Attribute for non-cacheable, normal memory. <a href="#ga03266f9660485693eb1baec6ba255ab2">More...</a><br/></td></tr> +<tr class="separator:ga03266f9660485693eb1baec6ba255ab2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac2f1c567950e3785d75773362b525390"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a>(NT, WB, RA, WA)</td></tr> +<tr class="memdesc:gac2f1c567950e3785d75773362b525390"><td class="mdescLeft"> </td><td class="mdescRight">Attribute for normal memory (outer and inner) <a href="#gac2f1c567950e3785d75773362b525390">More...</a><br/></td></tr> +<tr class="separator:gac2f1c567950e3785d75773362b525390"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabfa9ae279357044cf5b74e77af22a686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gabfa9ae279357044cf5b74e77af22a686">ARM_MPU_ATTR_DEVICE_nGnRnE</a></td></tr> +<tr class="memdesc:gabfa9ae279357044cf5b74e77af22a686"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. <a href="#gabfa9ae279357044cf5b74e77af22a686">More...</a><br/></td></tr> +<tr class="separator:gabfa9ae279357044cf5b74e77af22a686"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6e08ae44fab85e03fea96ae6a5fcdfb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga6e08ae44fab85e03fea96ae6a5fcdfb0">ARM_MPU_ATTR_DEVICE_nGnRE</a></td></tr> +<tr class="memdesc:ga6e08ae44fab85e03fea96ae6a5fcdfb0"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. <a href="#ga6e08ae44fab85e03fea96ae6a5fcdfb0">More...</a><br/></td></tr> +<tr class="separator:ga6e08ae44fab85e03fea96ae6a5fcdfb0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gadcc9977aabb4dc7177d30cbbac1b53d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gadcc9977aabb4dc7177d30cbbac1b53d1">ARM_MPU_ATTR_DEVICE_nGRE</a></td></tr> +<tr class="memdesc:gadcc9977aabb4dc7177d30cbbac1b53d1"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. <a href="#gadcc9977aabb4dc7177d30cbbac1b53d1">More...</a><br/></td></tr> +<tr class="separator:gadcc9977aabb4dc7177d30cbbac1b53d1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga496bcd6a2bbd038d8935049fec9d0fda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga496bcd6a2bbd038d8935049fec9d0fda">ARM_MPU_ATTR_DEVICE_GRE</a></td></tr> +<tr class="memdesc:ga496bcd6a2bbd038d8935049fec9d0fda"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type Gathering, Re-ordering, Early Write Acknowledgement. <a href="#ga496bcd6a2bbd038d8935049fec9d0fda">More...</a><br/></td></tr> +<tr class="separator:ga496bcd6a2bbd038d8935049fec9d0fda"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga2c465cc9429b8233bcb9cd7cbef0e54c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga2c465cc9429b8233bcb9cd7cbef0e54c">ARM_MPU_ATTR</a>(O, I)</td></tr> +<tr class="memdesc:ga2c465cc9429b8233bcb9cd7cbef0e54c"><td class="mdescLeft"> </td><td class="mdescRight">Memory Attribute. <a href="#ga2c465cc9429b8233bcb9cd7cbef0e54c">More...</a><br/></td></tr> +<tr class="separator:ga2c465cc9429b8233bcb9cd7cbef0e54c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3d0f688198289f72264f73cf72a742e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a></td></tr> +<tr class="memdesc:ga3d0f688198289f72264f73cf72a742e8"><td class="mdescLeft"> </td><td class="mdescRight">Normal memory non-shareable. <a href="#ga3d0f688198289f72264f73cf72a742e8">More...</a><br/></td></tr> +<tr class="separator:ga3d0f688198289f72264f73cf72a742e8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac4fddbdb9e1350bce6906de33c1fd500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac4fddbdb9e1350bce6906de33c1fd500">ARM_MPU_SH_OUTER</a></td></tr> +<tr class="memdesc:gac4fddbdb9e1350bce6906de33c1fd500"><td class="mdescLeft"> </td><td class="mdescRight">Normal memory outer shareable. <a href="#gac4fddbdb9e1350bce6906de33c1fd500">More...</a><br/></td></tr> +<tr class="separator:gac4fddbdb9e1350bce6906de33c1fd500"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga73c70127f24f34781ad463cbe51d8f6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga73c70127f24f34781ad463cbe51d8f6b">ARM_MPU_SH_INNER</a></td></tr> +<tr class="memdesc:ga73c70127f24f34781ad463cbe51d8f6b"><td class="mdescLeft"> </td><td class="mdescRight">Normal memory inner shareable. <a href="#ga73c70127f24f34781ad463cbe51d8f6b">More...</a><br/></td></tr> +<tr class="separator:ga73c70127f24f34781ad463cbe51d8f6b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga81b2aa3fb55cdd5feadff02da10d391b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga81b2aa3fb55cdd5feadff02da10d391b">ARM_MPU_AP_</a>(RO, NP)</td></tr> +<tr class="memdesc:ga81b2aa3fb55cdd5feadff02da10d391b"><td class="mdescLeft"> </td><td class="mdescRight">Memory access permissions. <a href="#ga81b2aa3fb55cdd5feadff02da10d391b">More...</a><br/></td></tr> +<tr class="separator:ga81b2aa3fb55cdd5feadff02da10d391b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafe39c2f98058bcac7e7e0501e64e7a9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gafe39c2f98058bcac7e7e0501e64e7a9d">ARM_MPU_RBAR</a>(BASE, SH, RO, NP, XN)</td></tr> +<tr class="memdesc:gafe39c2f98058bcac7e7e0501e64e7a9d"><td class="mdescLeft"> </td><td class="mdescRight">Region Base Address Register value. <a href="#gafe39c2f98058bcac7e7e0501e64e7a9d">More...</a><br/></td></tr> +<tr class="separator:gafe39c2f98058bcac7e7e0501e64e7a9d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaeaaa071276ba7956944e6c3dc05d677e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(LIMIT, IDX)</td></tr> +<tr class="memdesc:gaeaaa071276ba7956944e6c3dc05d677e"><td class="mdescLeft"> </td><td class="mdescRight">Region Limit Address Register value. <a href="#gaeaaa071276ba7956944e6c3dc05d677e">More...</a><br/></td></tr> +<tr class="separator:gaeaaa071276ba7956944e6c3dc05d677e"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga5a3f40314553baccdeea551f86d9a997"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga5a3f40314553baccdeea551f86d9a997">ARM_MPU_Enable</a> (uint32_t MPU_Control)</td></tr> +<tr class="separator:ga5a3f40314553baccdeea551f86d9a997"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga61814eba4652a0fdfb76bbe222086327"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga61814eba4652a0fdfb76bbe222086327">ARM_MPU_Disable</a> (void)</td></tr> +<tr class="separator:ga61814eba4652a0fdfb76bbe222086327"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5866c75d6deb9148a1e9af6337eec50a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga5866c75d6deb9148a1e9af6337eec50a">ARM_MPU_Enable_NS</a> (uint32_t MPU_Control)</td></tr> +<tr class="separator:ga5866c75d6deb9148a1e9af6337eec50a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga389f9b6049d176bc83f9964d3259b712"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga389f9b6049d176bc83f9964d3259b712">ARM_MPU_Disable_NS</a> (void)</td></tr> +<tr class="separator:ga389f9b6049d176bc83f9964d3259b712"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1799413f08a157d636a1491371c15ce2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga1799413f08a157d636a1491371c15ce2">ARM_MPU_SetMemAttrEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint8_t idx, uint8_t attr)</td></tr> +<tr class="separator:ga1799413f08a157d636a1491371c15ce2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab5b3c0a53d19c09a5550f1d9071ae65c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gab5b3c0a53d19c09a5550f1d9071ae65c">ARM_MPU_SetMemAttr</a> (uint8_t idx, uint8_t attr)</td></tr> +<tr class="separator:gab5b3c0a53d19c09a5550f1d9071ae65c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5100a150a755902af2455a455a329ef9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga5100a150a755902af2455a455a329ef9">ARM_MPU_SetMemAttr_NS</a> (uint8_t idx, uint8_t attr)</td></tr> +<tr class="separator:ga5100a150a755902af2455a455a329ef9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga01fa1151c9ec0ba5de76f908c0999316"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga01fa1151c9ec0ba5de76f908c0999316">ARM_MPU_ClrRegionEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint32_t rnr)</td></tr> +<tr class="separator:ga01fa1151c9ec0ba5de76f908c0999316"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a> (uint32_t rnr)</td></tr> +<tr class="separator:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac526bc5bfcf048ce57a44c0c0cdadbe4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac526bc5bfcf048ce57a44c0c0cdadbe4">ARM_MPU_ClrRegion_NS</a> (uint32_t rnr)</td></tr> +<tr class="separator:gac526bc5bfcf048ce57a44c0c0cdadbe4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3d50ba8546252bea959e45c8fdf16993"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga3d50ba8546252bea959e45c8fdf16993">ARM_MPU_SetRegionEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)</td></tr> +<tr class="separator:ga3d50ba8546252bea959e45c8fdf16993"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6d7f220015c070c0e469948c1775ee3d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga6d7f220015c070c0e469948c1775ee3d">ARM_MPU_SetRegion</a> (uint32_t rnr, uint32_t rbar, uint32_t rlar)</td></tr> +<tr class="separator:ga6d7f220015c070c0e469948c1775ee3d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7566931ca9bb9f22d213a67ec5f8c745"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga7566931ca9bb9f22d213a67ec5f8c745">ARM_MPU_SetRegion_NS</a> (uint32_t rnr, uint32_t rbar, uint32_t rlar)</td></tr> +<tr class="separator:ga7566931ca9bb9f22d213a67ec5f8c745"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac1a949403bf84eecaf407003fb553ae7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac1a949403bf84eecaf407003fb553ae7">ARM_MPU_OrderedMemcpy</a> (volatile uint32_t *dst, const uint32_t *<a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> src, uint32_t len)</td></tr> +<tr class="separator:gac1a949403bf84eecaf407003fb553ae7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab6094419f2abd678f1f3b121cd115049"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gab6094419f2abd678f1f3b121cd115049">ARM_MPU_LoadEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint32_t rnr, <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const *table, uint32_t cnt)</td></tr> +<tr class="separator:gab6094419f2abd678f1f3b121cd115049"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaca76614e3091c7324aa9d60e634621bf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gaca76614e3091c7324aa9d60e634621bf">ARM_MPU_Load</a> (uint32_t rnr, <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const *table, uint32_t cnt)</td></tr> +<tr class="separator:gaca76614e3091c7324aa9d60e634621bf"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7f8c6e09be98067d613e4df1832c543d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga7f8c6e09be98067d613e4df1832c543d">ARM_MPU_Load_NS</a> (uint32_t rnr, <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const *table, uint32_t cnt)</td></tr> +<tr class="separator:ga7f8c6e09be98067d613e4df1832c543d"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.</p> +<p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keywordtype">void</span> main() </div> +<div class="line">{</div> +<div class="line"> <span class="comment">// Set Region 0 using Attr 0</span></div> +<div class="line"> <a class="code" href="group__mpu8__functions.html#gab5b3c0a53d19c09a5550f1d9071ae65c">ARM_MPU_SetMemAttr</a>(0UL, <a class="code" href="group__mpu8__functions.html#ga2c465cc9429b8233bcb9cd7cbef0e54c">ARM_MPU_ATTR</a>( <span class="comment">/* Normal memory */</span></div> +<div class="line"> <a class="code" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a>(0UL, 1UL, 1UL, 1UL), <span class="comment">/* Outer Write-Back transient with read and write allocate */</span></div> +<div class="line"> <a class="code" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a>(0UL, 0UL, 1UL, 1UL) <span class="comment">/* Inner Write-Through transient with read and write allocate */</span></div> +<div class="line"> ));</div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>(0UL,</div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x08000000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), <span class="comment">/* Non-shareable, read/write, non-privileged, execute-never */</span></div> +<div class="line"> <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x080FFFFFUL, 0UL) <span class="comment">/* 1MB memory block using Attr 0 */</span></div> +<div class="line"> );</div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a>(0);</div> +<div class="line"> </div> +<div class="line"> <span class="comment">// Execute application code that is access protected by the MPU</span></div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a>();</div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga81b2aa3fb55cdd5feadff02da10d391b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_AP_</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">RO, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">NP </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">RO</td><td>Read-Only: Set to 1 for read-only memory. </td></tr> + <tr><td class="paramname">NP</td><td>Non-Privileged: Set to 1 for non-privileged memory. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga2c465cc9429b8233bcb9cd7cbef0e54c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">O, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">I </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">O</td><td>Outer memory attributes </td></tr> + <tr><td class="paramname">I</td><td>O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gab4bfac6284dc050dc6fa6aeb8e954c2c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_DEVICE   ( 0U )</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga496bcd6a2bbd038d8935049fec9d0fda"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_DEVICE_GRE</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga6e08ae44fab85e03fea96ae6a5fcdfb0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_DEVICE_nGnRE</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gabfa9ae279357044cf5b74e77af22a686"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_DEVICE_nGnRnE</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gadcc9977aabb4dc7177d30cbbac1b53d1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_DEVICE_nGRE</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gac2f1c567950e3785d75773362b525390"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_MEMORY_</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">NT, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">WB, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">RA, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">WA </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">NT</td><td>Non-Transient: Set to 1 for non-transient data. </td></tr> + <tr><td class="paramname">WB</td><td>Write-Back: Set to 1 to use write-back update policy. </td></tr> + <tr><td class="paramname">RA</td><td>Read Allocation: Set to 1 to use cache allocation on read miss. </td></tr> + <tr><td class="paramname">WA</td><td>Write Allocation: Set to 1 to use cache allocation on write miss. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga03266f9660485693eb1baec6ba255ab2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gafe39c2f98058bcac7e7e0501e64e7a9d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RBAR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">BASE, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">SH, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">RO, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">NP, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">XN </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">BASE</td><td>The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. </td></tr> + <tr><td class="paramname">SH</td><td>Defines the Shareability domain for this memory region. </td></tr> + <tr><td class="paramname">RO</td><td>Read-Only: Set to 1 for a read-only memory region. </td></tr> + <tr><td class="paramname">NP</td><td>Non-Privileged: Set to 1 for a non-privileged memory region. </td></tr> + <tr><td class="paramname">XN</td><td>eXecute Never: Set to 1 for a non-executable memory region. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gaeaaa071276ba7956944e6c3dc05d677e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RLAR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">LIMIT, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IDX </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">LIMIT</td><td>The limit address bits [31:5] for this memory region. The value is one extended. </td></tr> + <tr><td class="paramname">IDX</td><td>The attribute index to be associated with this memory region. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga73c70127f24f34781ad463cbe51d8f6b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_SH_INNER</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga3d0f688198289f72264f73cf72a742e8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_SH_NON</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gac4fddbdb9e1350bce6906de33c1fd500"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_SH_OUTER</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga9dcb0afddf4ac351f33f3c7a5169c62c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear and disable the given MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gac526bc5bfcf048ce57a44c0c0cdadbe4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear and disable the given Non-secure MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga01fa1151c9ec0ba5de76f908c0999316"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegionEx </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td> + <td class="paramname"><em>mpu</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear and disable the given MPU region of the given MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">mpu</td><td>Pointer to MPU to be used. </td></tr> + <tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga61814eba4652a0fdfb76bbe222086327"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable the MPU. </p> + +</div> +</div> +<a class="anchor" id="ga389f9b6049d176bc83f9964d3259b712"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable the Non-secure MPU. </p> + +</div> +</div> +<a class="anchor" id="ga5a3f40314553baccdeea551f86d9a997"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Enable </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>MPU_Control</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable the MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">MPU_Control</td><td>Default access permissions for unconfigured regions. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga5866c75d6deb9148a1e9af6337eec50a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> ARM_MPU_Enable_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>MPU_Control</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enable the Non-secure MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">MPU_Control</td><td>Default access permissions for unconfigured regions. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gaca76614e3091c7324aa9d60e634621bf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const * </td> + <td class="paramname"><em>table</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>cnt</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Load the given number of MPU regions from a table. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>First region number to be configured. </td></tr> + <tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr> + <tr><td class="paramname">cnt</td><td>Amount of regions to be configured.</td></tr> + </table> + </dd> +</dl> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> mpuTable[1][4] = {</div> +<div class="line"> {</div> +<div class="line"> <span class="comment">// BASE SH RO NP XN LIMIT ATTR </span></div> +<div class="line"> { .<a class="code" href="structARM__MPU__Region__t.html#afe7a7721aa08988d915670efa432cdd2">RBAR</a> = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x08000000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 0UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x080FFFFFUL, 0UL) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x20000000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x20007FFFUL, 0UL) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x40020000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x40021FFFUL, 1UL) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x40022000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x40022FFFUL, 1UL) }</div> +<div class="line"> }</div> +<div class="line">};</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> UpdateMpu(uint32_t idx)</div> +<div class="line">{</div> +<div class="line"> <a class="code" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a>(0, mpuTable[idx], 4);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga7f8c6e09be98067d613e4df1832c543d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const * </td> + <td class="paramname"><em>table</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>cnt</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Load the given number of MPU regions from a table to the Non-secure MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>First region number to be configured. </td></tr> + <tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr> + <tr><td class="paramname">cnt</td><td>Amount of regions to be configured. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gab6094419f2abd678f1f3b121cd115049"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_LoadEx </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td> + <td class="paramname"><em>mpu</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const * </td> + <td class="paramname"><em>table</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>cnt</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Load the given number of MPU regions from a table to the given MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">mpu</td><td>Pointer to the MPU registers to be used. </td></tr> + <tr><td class="paramname">rnr</td><td>First region number to be configured. </td></tr> + <tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr> + <tr><td class="paramname">cnt</td><td>Amount of regions to be configured. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gac1a949403bf84eecaf407003fb553ae7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_OrderedMemcpy </td> + <td>(</td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>dst</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t *<a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> </td> + <td class="paramname"><em>src</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>len</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Memcopy with strictly ordered memory access, e.g. for register targets. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">dst</td><td>Destination data is copied to. </td></tr> + <tr><td class="paramname">src</td><td>Source data is copied from. </td></tr> + <tr><td class="paramname">len</td><td>Amount of data words to be copied. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gab5b3c0a53d19c09a5550f1d9071ae65c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetMemAttr </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>idx</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>attr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set the memory attribute encoding. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">idx</td><td>The attribute index to be set [0-7] </td></tr> + <tr><td class="paramname">attr</td><td>The attribute value to be set. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga5100a150a755902af2455a455a329ef9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetMemAttr_NS </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>idx</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>attr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set the memory attribute encoding to the Non-secure MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">idx</td><td>The attribute index to be set [0-7] </td></tr> + <tr><td class="paramname">attr</td><td>The attribute value to be set. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga1799413f08a157d636a1491371c15ce2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetMemAttrEx </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td> + <td class="paramname"><em>mpu</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>idx</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>attr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Set the memory attribute encoding to the given MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">mpu</td><td>Pointer to the MPU to be configured. </td></tr> + <tr><td class="paramname">idx</td><td>The attribute index to be set [0-7] </td></tr> + <tr><td class="paramname">attr</td><td>The attribute value to be set. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga6d7f220015c070c0e469948c1775ee3d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rlar</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure the given MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr> + <tr><td class="paramname">rbar</td><td>Value for RBAR register. </td></tr> + <tr><td class="paramname">rlar</td><td>Value for RLAR register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga7566931ca9bb9f22d213a67ec5f8c745"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rlar</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure the given Non-secure MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr> + <tr><td class="paramname">rbar</td><td>Value for RBAR register. </td></tr> + <tr><td class="paramname">rlar</td><td>Value for RLAR register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga3d50ba8546252bea959e45c8fdf16993"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegionEx </td> + <td>(</td> + <td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td> + <td class="paramname"><em>mpu</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rlar</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure the given MPU region of the given MPU. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">mpu</td><td>Pointer to MPU to be used. </td></tr> + <tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr> + <tr><td class="paramname">rbar</td><td>Value for RBAR register. </td></tr> + <tr><td class="paramname">rlar</td><td>Value for RLAR register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |