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Diffstat (limited to 'Drivers/CMSIS/docs/RTOS2/html/pHardwareRequirements.html')
| -rw-r--r-- | Drivers/CMSIS/docs/RTOS2/html/pHardwareRequirements.html | 33 |
1 files changed, 17 insertions, 16 deletions
diff --git a/Drivers/CMSIS/docs/RTOS2/html/pHardwareRequirements.html b/Drivers/CMSIS/docs/RTOS2/html/pHardwareRequirements.html index fac09bb1c..275e23d36 100644 --- a/Drivers/CMSIS/docs/RTOS2/html/pHardwareRequirements.html +++ b/Drivers/CMSIS/docs/RTOS2/html/pHardwareRequirements.html @@ -114,7 +114,7 @@ $(document).ready(function(){initNavTree('pHardwareRequirements.html','');}); <div class="textblock"><p>The following section lists the hardware requirements for RTX v5 on the various supported target processors:</p> <h1><a class="anchor" id="tpProcessor"></a> Processor Requirements</h1> -<p>RTX assumes a fully function-able processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.</p> +<p>RTX assumes a fully functionable processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.</p> <h2><a class="anchor" id="tpCortexM0_M0P_M23"></a> Cortex-M0/M0+/M23 target processor</h2> <table class="doxtable"> @@ -131,7 +131,7 @@ Cortex-M0/M0+/M23 target processor</h2> <tr> <td align="left">Interrupt Control </td><td align="left">The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register. </td></tr> </table> -<p>The interface files to the processor hardware are:</p> +<p>The RTX implements interfaces to the processor hardware in following files:</p> <ul> <li><b>irq_cm0.s</b> defines exception handlers for Cortex-M0/M0+</li> <li><b>irq_armv8mbl_common.s</b> defines exception handlers for Cortex-M23</li> @@ -139,37 +139,38 @@ Cortex-M0/M0+/M23 target processor</h2> <li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the SysTick timer.</li> </ul> <dl class="section note"><dt>Note</dt><dd><ul> -<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used to configure the SysTick timer.</li> +<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used by RTX to configure the SysTick timer.</li> </ul> </dd></dl> -<h2><a class="anchor" id="tpCortexM3_M4_M7_M33"></a> -Cortex-M3/M4/M7/M33 target processor</h2> +<h2><a class="anchor" id="tpCortexM3_M4_M7_M33_M35P"></a> +Cortex-M3/M4/M7/M33/M35P target processor</h2> +<p>RTX assumes a fully function-able processor and uses the following hardware features:</p> <table class="doxtable"> <tr> -<th align="left">Hardware Requirement </th><th align="left">Description </th></tr> +<th align="left">Hardware Item </th><th align="left">Requirement Description </th></tr> <tr> -<td align="left">SysTick timer </td><td align="left">The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> </td></tr> +<td align="left">SysTick timer </td><td align="left">The <b>SysTick</b> timer shall be available in the processor. </td></tr> <tr> -<td align="left">Exception Handler </td><td align="left">RTX implements exception handlers for SVC, PendSV, and SysTick interrupt </td></tr> +<td align="left">System Exceptions </td><td align="left">The RTX requires <b>SVC</b>, <b>PendSV</b>, and <b>SysTick</b> exceptions and implements corresponding exception handlers. </td></tr> <tr> -<td align="left">Core Registers </td><td align="left">The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK, BASEPRI </td></tr> +<td align="left">Core Registers </td><td align="left">The RTX uses <b>CONTROL</b>, <b>IPSR</b> , <b>PRIMASK</b> and <b>BASEPRI</b> core registers for reading processor status. </td></tr> <tr> -<td align="left">System Control Block (SBC) </td><td align="left">To control and setup the processor exceptions including PendSV and SVC </td></tr> +<td align="left">System Control Block (SCB) </td><td align="left">The RTX uses <b>SCB</b> registers to control and setup the processor system exceptions including PendSV and SVC. </td></tr> <tr> -<td align="left">NVIC Interface </td><td align="left">The CMSIS-Core function NVIC_GetPriorityGrouping to setup interrupt priorities. </td></tr> +<td align="left">NVIC Interface </td><td align="left">CMSIS-Core function <b>NVIC_GetPriorityGrouping</b> is used by the RTX to setup interrupt priorities. </td></tr> <tr> -<td align="left">LDREX, STREX instruction </td><td align="left">Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions. </td></tr> +<td align="left">LDREX, STREX instructions </td><td align="left">Exclusive access instructions <b>LDREX</b> and <b>STREX</b> are used to implement atomic execution without disabling interrupts. </td></tr> </table> <p>The interface files to the processor hardware are:</p> <ul> <li><b>irq_cm3.s</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7 without floating point unit.</li> <li><b>irq_cm4f.s</b> defines exception handlers for Cortex-M4/M7 with floating point unit.</li> -<li><b>irq_armv8mml_common.s</b> defines exception handlers for Cortex-M33</li> +<li><b>irq_armv8mml_common.s</b> defines exception handlers for Cortex-M33/M35P</li> <li><b>rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li> <li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the SysTick timer.</li> </ul> <dl class="section note"><dt>Note</dt><dd><ul> -<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used to configure the SysTick timer.</li> +<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used by RTX to configure the SysTick timer.</li> </ul> </dd></dl> <h2><a class="anchor" id="tpCortexA5_A7_A9"></a> @@ -196,7 +197,7 @@ Cortex-A5/A7/A9 target processor</h2> <li><b>irq_ctrl.h</b> is the <a href="../../Core_A/html/group__irq__ctrl__gr.html" class="el">IRQ Controller API</a> that defines the interface functions to the interrupt controller.</li> </ul> <dl class="section note"><dt>Note</dt><dd><ul> -<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used to configure the timer peripheral.</li> +<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used by RTX to configure the timer peripheral.</li> </ul> </dd></dl> <h1><a class="anchor" id="rMemory"></a> @@ -209,7 +210,7 @@ Memory Requirements</h1> <div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> <ul> <li class="navelem"><a class="el" href="index.html">index</a></li><li class="navelem"><a class="el" href="rtx5_impl.html">RTX v5 Implementation</a></li><li class="navelem"><a class="el" href="technicalData5.html">Technical Data</a></li> - <li class="footer">Generated on Wed Aug 1 2018 17:12:45 for CMSIS-RTOS2 by Arm Ltd. All rights reserved. + <li class="footer">Generated on Wed Jul 10 2019 15:21:04 for CMSIS-RTOS2 Version 2.1.3 by Arm Ltd. All rights reserved. <!-- <a href="http://www.doxygen.org/index.html"> <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 |