diff options
Diffstat (limited to 'Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h')
| -rw-r--r-- | Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h | 96 |
1 files changed, 69 insertions, 27 deletions
diff --git a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h index 852c3a0e2..4c8a15af1 100644 --- a/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h +++ b/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h @@ -90,10 +90,12 @@ extern "C" { #endif #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF -#define LL_PWR_SCR_C802AF PWR_SCR_C802AF #define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF #define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF +#if defined(PWR_CR3_E802A) +#define LL_PWR_SCR_C802AF PWR_SCR_C802AF #define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF +#endif #define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) #define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF @@ -145,9 +147,12 @@ extern "C" { /* Radio (BLE or 802.15.4) flags */ #define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */ -#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */ + #define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */ +#if defined(PWR_CR3_E802A) +#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */ #define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */ +#endif #define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */ #define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */ @@ -179,7 +184,9 @@ extern "C" { */ #define LL_PWR_MODE_STOP0 (0x000000000U) #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0) +#if defined(PWR_SUPPORT_STOP2) #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1) +#endif #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) /** @@ -521,9 +528,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) @@ -537,9 +546,11 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx */ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) { @@ -557,7 +568,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) { /* Unlock bit FPDR */ - WRITE_REG(PWR->CR1, 0x0000C1B0U); + WRITE_REG(PWR->CR1, 0x0000C1B0UL); /* Update bit FPDR */ MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode); @@ -640,7 +651,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V * - * (*) Not available on devices STM32WB50xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) @@ -656,7 +667,7 @@ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V * - * (*) Not available on devices STM32WB50xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) @@ -672,7 +683,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) * @arg @ref LL_PWR_PVM_VDDA_1_62V * - * (*) Not available on devices STM32WB50xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) @@ -808,7 +819,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) } /** - * @brief Enable SRAM2 content retention in Standby mode + * @brief Enable SRAM2a content retention in Standby mode + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention * @retval None */ @@ -818,7 +831,9 @@ __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) } /** - * @brief Disable SRAM2 content retention in Standby mode + * @brief Disable SRAM2a content retention in Standby mode + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention * @retval None */ @@ -829,6 +844,8 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) /** * @brief Check if SRAM2 content retention in Standby mode is enabled + * @note On devices STM32WB15xx, STM32WB10xx, retention is extended + * to SRAM1, SRAM2a and SRAM2b. * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention * @retval State of bit (1 or 0). */ @@ -851,7 +868,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) @@ -873,7 +890,7 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) @@ -895,7 +912,7 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) @@ -972,7 +989,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) @@ -994,7 +1011,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) @@ -1016,7 +1033,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) @@ -1323,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown * @retval None */ __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode) @@ -1345,7 +1362,7 @@ __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown */ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) { @@ -1366,7 +1383,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) * requested operating mode can differ from effective low power mode. * - dependency on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown * - dependency on BOR level: * - bypass mode if supply voltage drops below BOR level * @note This functions check flags of SMPS operating modes step down @@ -1380,7 +1397,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) * * (1) SMPS operating mode step down or open depends on system low-power mode: * - step down mode if system low power mode is run, LP run or stop0, - * - open mode if system low power mode is stop1, stop2, standby or shutdown + * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown */ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void) { @@ -1637,9 +1654,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void) * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) @@ -1653,9 +1672,11 @@ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode) * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP0 * @arg @ref LL_PWR_MODE_STOP1 - * @arg @ref LL_PWR_MODE_STOP2 + * @arg @ref LL_PWR_MODE_STOP2 (*) * @arg @ref LL_PWR_MODE_STANDBY * @arg @ref LL_PWR_MODE_SHUTDOWN + * + * (*) Not available on devices STM32WB15xx, STM32WB10xx */ __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void) { @@ -1673,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void) __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) { /* Unlock bit FPDR */ - WRITE_REG(PWR->C2CR1, 0x0000C1B0U); + WRITE_REG(PWR->C2CR1, 0x0000C1B0UL); /* Update bit FPDR */ MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode); @@ -1761,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin) @@ -1783,7 +1804,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin) @@ -1805,7 +1826,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin) * @arg @ref LL_PWR_WAKEUP_PIN4 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) * - * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx + * (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx * @retval None */ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) @@ -1874,6 +1895,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE(void) return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Wakeup 802.15.4 controller from its sleep mode * @note This bit is automatically reset when 802.15.4 controller @@ -1896,6 +1918,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void) { return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL); } +#endif /** * @} @@ -2179,6 +2202,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU(void) return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Get 802.15.4 wakeup interrupt flag * @rmtoll SR1 802WUF LL_PWR_IsActiveFlag_802WU @@ -2188,6 +2212,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL); } +#endif /** * @brief Get BLE end of activity interrupt flag @@ -2199,6 +2224,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA(void) return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Get 802.15.4 end of activity interrupt flag * @rmtoll SR1 802AF LL_PWR_IsActiveFlag_802A @@ -2208,6 +2234,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL); } +#endif /** * @brief Get critical radio phase end of activity interrupt flag @@ -2239,6 +2266,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_BLEWU(void) WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF); } +#if defined(PWR_CR3_E802A) /** * @brief Clear 802.15.4 wakeup interrupt flag * @rmtoll SCR 802WU LL_PWR_ClearFlag_802WU @@ -2248,6 +2276,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void) { WRITE_REG(PWR->SCR, PWR_SCR_C802WUF); } +#endif /** * @brief Clear BLE end of activity interrupt flag @@ -2259,6 +2288,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_BLEA(void) WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF); } +#if defined(PWR_CR3_E802A) /** * @brief Clear 802.15.4 end of activity interrupt flag * @rmtoll SCR 802AF LL_PWR_ClearFlag_802A @@ -2268,6 +2298,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802A(void) { WRITE_REG(PWR->SCR, PWR_SCR_C802AF); } +#endif /** * @brief Clear critical radio phase end of activity interrupt flag @@ -2461,6 +2492,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_BLEA(void) SET_BIT(PWR->CR3, PWR_CR3_EBLEA); } +#if defined(PWR_CR3_E802A) /** * @brief Enable 802.15.4 end of activity interrupt for CPU1 * @rmtoll CR3 E802A LL_PWR_EnableIT_802A @@ -2470,7 +2502,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_802A(void) { SET_BIT(PWR->CR3, PWR_CR3_E802A); } - +#endif /** * @brief Disable BLE end of activity interrupt for CPU1 @@ -2482,6 +2514,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_BLEA(void) CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA); } +#if defined(PWR_CR3_E802A) /** * @brief Disable 802.15.4 end of activity interrupt for CPU1 * @rmtoll CR3 E802A LL_PWR_DisableIT_802A @@ -2491,6 +2524,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_802A(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_E802A); } +#endif /** * @brief Check if BLE end of activity interrupt is enabled for CPU1 @@ -2502,6 +2536,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA(void) return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Check if 802.15.4 end of activity interrupt is enabled for CPU1 * @rmtoll CR3 E802A LL_PWR_IsEnabledIT_802A @@ -2511,6 +2546,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL); } +#endif /** * @brief Enable critical radio phase end of activity interrupt for CPU1 @@ -2598,6 +2634,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU(void) SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); } +#if defined(PWR_CR3_E802A) /** * @brief Enable 802.15.4 host wakeup interrupt for CPU2 * @rmtoll C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU @@ -2607,6 +2644,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void) { SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); } +#endif /** * @brief Disable BLE host wakeup interrupt for CPU2 @@ -2618,6 +2656,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU(void) CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP); } +#if defined(PWR_CR3_E802A) /** * @brief Disable 802.15.4 host wakeup interrupt for CPU2 * @rmtoll C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU @@ -2627,6 +2666,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void) { CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); } +#endif /** * @brief Check if BLE host wakeup interrupt is enabled for CPU2 @@ -2638,6 +2678,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU(void) return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL); } +#if defined(PWR_CR3_E802A) /** * @brief Check if 802.15.4 host wakeup interrupt is enabled for CPU2 * @rmtoll C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU @@ -2647,6 +2688,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void) { return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL); } +#endif /** * @} |