diff options
Diffstat (limited to 'Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h')
| -rw-r--r-- | Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h | 35 |
1 files changed, 9 insertions, 26 deletions
diff --git a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h index 7fcd60664..76fb9c3e6 100644 --- a/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h +++ b/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_DataThroughput/Core/Inc/hw_conf.h @@ -1,17 +1,16 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** - * @file hw_conf.h - * @author MCD Application Team - * @brief Configuration of hardware interface - ****************************************************************************** + * File Name : hw_conf.h + * Description : Hardware configuration file for STM32WPAN Middleware. + ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2019 STMicroelectronics. + * <h2><center>© Copyright (c) 2021 STMicroelectronics. * All rights reserved.</center></h2> * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: * www.st.com/SLA0044 * @@ -200,23 +199,15 @@ #define CFG_HW_LPUART1_RX_SPEED GPIO_SPEED_FREQ_VERY_HIGH #define CFG_HW_LPUART1_RX_ALTERNATE GPIO_AF8_LPUART1 -#define CFG_HW_LPUART1_CTS_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define CFG_HW_LPUART1_CTS_PORT GPIOA -#define CFG_HW_LPUART1_CTS_PIN GPIO_PIN_6 -#define CFG_HW_LPUART1_CTS_MODE GPIO_MODE_AF_PP -#define CFG_HW_LPUART1_CTS_PULL GPIO_PULLDOWN -#define CFG_HW_LPUART1_CTS_SPEED GPIO_SPEED_FREQ_VERY_HIGH -#define CFG_HW_LPUART1_CTS_ALTERNATE GPIO_AF8_LPUART1 - #define CFG_HW_LPUART1_DMA_TX_PREEMPTPRIORITY 0x0F #define CFG_HW_LPUART1_DMA_TX_SUBPRIORITY 0 #define CFG_HW_LPUART1_DMAMUX_CLK_ENABLE __HAL_RCC_DMAMUX1_CLK_ENABLE #define CFG_HW_LPUART1_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE #define CFG_HW_LPUART1_TX_DMA_REQ DMA_REQUEST_LPUART1_TX -#define CFG_HW_LPUART1_TX_DMA_CHANNEL DMA1_Channel4 -#define CFG_HW_LPUART1_TX_DMA_IRQn DMA1_Channel4_IRQn -#define CFG_HW_LPUART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler +#define CFG_HW_LPUART1_TX_DMA_CHANNEL DMA1_Channel3 +#define CFG_HW_LPUART1_TX_DMA_IRQn DMA1_Channel3_IRQn +#define CFG_HW_LPUART1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler /** * UART1 @@ -252,14 +243,6 @@ #define CFG_HW_USART1_RX_SPEED GPIO_SPEED_FREQ_VERY_HIGH #define CFG_HW_USART1_RX_ALTERNATE GPIO_AF7_USART1 -#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define CFG_HW_USART1_CTS_PORT GPIOA -#define CFG_HW_USART1_CTS_PIN GPIO_PIN_11 -#define CFG_HW_USART1_CTS_MODE GPIO_MODE_AF_PP -#define CFG_HW_USART1_CTS_PULL GPIO_PULLDOWN -#define CFG_HW_USART1_CTS_SPEED GPIO_SPEED_FREQ_VERY_HIGH -#define CFG_HW_USART1_CTS_ALTERNATE GPIO_AF7_USART1 - #define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY 0x0F #define CFG_HW_USART1_DMA_TX_SUBPRIORITY 0 |